1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mm-clock.h> 6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h> 10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h> 11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h> 12 #include <dt-bindings/thermal/thermal.h>
13 13
14 #include "imx8mm-pinfunc.h" 14 #include "imx8mm-pinfunc.h"
15 15
16 / { 16 / {
17 interrupt-parent = <&gic>; 17 interrupt-parent = <&gic>;
18 #address-cells = <2>; 18 #address-cells = <2>;
19 #size-cells = <2>; 19 #size-cells = <2>;
20 20
21 aliases { 21 aliases {
22 ethernet0 = &fec1; 22 ethernet0 = &fec1;
23 gpio0 = &gpio1; 23 gpio0 = &gpio1;
24 gpio1 = &gpio2; 24 gpio1 = &gpio2;
25 gpio2 = &gpio3; 25 gpio2 = &gpio3;
26 gpio3 = &gpio4; 26 gpio3 = &gpio4;
27 gpio4 = &gpio5; 27 gpio4 = &gpio5;
28 i2c0 = &i2c1; 28 i2c0 = &i2c1;
29 i2c1 = &i2c2; 29 i2c1 = &i2c2;
30 i2c2 = &i2c3; 30 i2c2 = &i2c3;
31 i2c3 = &i2c4; 31 i2c3 = &i2c4;
32 mmc0 = &usdhc1; 32 mmc0 = &usdhc1;
33 mmc1 = &usdhc2; 33 mmc1 = &usdhc2;
34 mmc2 = &usdhc3; 34 mmc2 = &usdhc3;
35 serial0 = &uart1; 35 serial0 = &uart1;
36 serial1 = &uart2; 36 serial1 = &uart2;
37 serial2 = &uart3; 37 serial2 = &uart3;
38 serial3 = &uart4; 38 serial3 = &uart4;
39 spi0 = &ecspi1; 39 spi0 = &ecspi1;
40 spi1 = &ecspi2; 40 spi1 = &ecspi2;
41 spi2 = &ecspi3; 41 spi2 = &ecspi3;
42 }; 42 };
43 43
44 cpus { 44 cpus {
45 #address-cells = <1>; 45 #address-cells = <1>;
46 #size-cells = <0>; 46 #size-cells = <0>;
47 47
48 idle-states { 48 idle-states {
49 entry-method = "psci"; 49 entry-method = "psci";
50 50
51 cpu_pd_wait: cpu-pd-wa 51 cpu_pd_wait: cpu-pd-wait {
52 compatible = " 52 compatible = "arm,idle-state";
53 arm,psci-suspe 53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-st 54 local-timer-stop;
55 entry-latency- 55 entry-latency-us = <1000>;
56 exit-latency-u 56 exit-latency-us = <700>;
57 min-residency- 57 min-residency-us = <2700>;
58 }; 58 };
59 }; 59 };
60 60
61 A53_0: cpu@0 { 61 A53_0: cpu@0 {
62 device_type = "cpu"; 62 device_type = "cpu";
63 compatible = "arm,cort 63 compatible = "arm,cortex-a53";
64 reg = <0x0>; 64 reg = <0x0>;
65 clock-latency = <61036 65 clock-latency = <61036>; /* two CLK32 periods */
66 clocks = <&clk IMX8MM_ 66 clocks = <&clk IMX8MM_CLK_ARM>;
67 enable-method = "psci" 67 enable-method = "psci";
68 i-cache-size = <0x8000 68 i-cache-size = <0x8000>;
69 i-cache-line-size = <6 69 i-cache-line-size = <64>;
70 i-cache-sets = <256>; 70 i-cache-sets = <256>;
71 d-cache-size = <0x8000 71 d-cache-size = <0x8000>;
72 d-cache-line-size = <6 72 d-cache-line-size = <64>;
73 d-cache-sets = <128>; 73 d-cache-sets = <128>;
74 next-level-cache = <&A 74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = 75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_sp 76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "sp 77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cp 78 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>; 79 #cooling-cells = <2>;
80 }; 80 };
81 81
82 A53_1: cpu@1 { 82 A53_1: cpu@1 {
83 device_type = "cpu"; 83 device_type = "cpu";
84 compatible = "arm,cort 84 compatible = "arm,cortex-a53";
85 reg = <0x1>; 85 reg = <0x1>;
86 clock-latency = <61036 86 clock-latency = <61036>; /* two CLK32 periods */
87 clocks = <&clk IMX8MM_ 87 clocks = <&clk IMX8MM_CLK_ARM>;
88 enable-method = "psci" 88 enable-method = "psci";
89 i-cache-size = <0x8000 89 i-cache-size = <0x8000>;
90 i-cache-line-size = <6 90 i-cache-line-size = <64>;
91 i-cache-sets = <256>; 91 i-cache-sets = <256>;
92 d-cache-size = <0x8000 92 d-cache-size = <0x8000>;
93 d-cache-line-size = <6 93 d-cache-line-size = <64>;
94 d-cache-sets = <128>; 94 d-cache-sets = <128>;
95 next-level-cache = <&A 95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = 96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cp 97 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>; 98 #cooling-cells = <2>;
99 }; 99 };
100 100
101 A53_2: cpu@2 { 101 A53_2: cpu@2 {
102 device_type = "cpu"; 102 device_type = "cpu";
103 compatible = "arm,cort 103 compatible = "arm,cortex-a53";
104 reg = <0x2>; 104 reg = <0x2>;
105 clock-latency = <61036 105 clock-latency = <61036>; /* two CLK32 periods */
106 clocks = <&clk IMX8MM_ 106 clocks = <&clk IMX8MM_CLK_ARM>;
107 enable-method = "psci" 107 enable-method = "psci";
108 i-cache-size = <0x8000 108 i-cache-size = <0x8000>;
109 i-cache-line-size = <6 109 i-cache-line-size = <64>;
110 i-cache-sets = <256>; 110 i-cache-sets = <256>;
111 d-cache-size = <0x8000 111 d-cache-size = <0x8000>;
112 d-cache-line-size = <6 112 d-cache-line-size = <64>;
113 d-cache-sets = <128>; 113 d-cache-sets = <128>;
114 next-level-cache = <&A 114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = 115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cp 116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>; 117 #cooling-cells = <2>;
118 }; 118 };
119 119
120 A53_3: cpu@3 { 120 A53_3: cpu@3 {
121 device_type = "cpu"; 121 device_type = "cpu";
122 compatible = "arm,cort 122 compatible = "arm,cortex-a53";
123 reg = <0x3>; 123 reg = <0x3>;
124 clock-latency = <61036 124 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MM_ 125 clocks = <&clk IMX8MM_CLK_ARM>;
126 enable-method = "psci" 126 enable-method = "psci";
127 i-cache-size = <0x8000 127 i-cache-size = <0x8000>;
128 i-cache-line-size = <6 128 i-cache-line-size = <64>;
129 i-cache-sets = <256>; 129 i-cache-sets = <256>;
130 d-cache-size = <0x8000 130 d-cache-size = <0x8000>;
131 d-cache-line-size = <6 131 d-cache-line-size = <64>;
132 d-cache-sets = <128>; 132 d-cache-sets = <128>;
133 next-level-cache = <&A 133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = 134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cp 135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>; 136 #cooling-cells = <2>;
137 }; 137 };
138 138
139 A53_L2: l2-cache0 { 139 A53_L2: l2-cache0 {
140 compatible = "cache"; 140 compatible = "cache";
141 cache-level = <2>; 141 cache-level = <2>;
142 cache-unified; <<
143 cache-size = <0x80000> 142 cache-size = <0x80000>;
144 cache-line-size = <64> 143 cache-line-size = <64>;
145 cache-sets = <512>; 144 cache-sets = <512>;
146 }; 145 };
147 }; 146 };
148 147
149 a53_opp_table: opp-table { 148 a53_opp_table: opp-table {
150 compatible = "operating-points 149 compatible = "operating-points-v2";
151 opp-shared; 150 opp-shared;
152 151
153 opp-1200000000 { 152 opp-1200000000 {
154 opp-hz = /bits/ 64 <12 153 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <85000 154 opp-microvolt = <850000>;
156 opp-supported-hw = <0x 155 opp-supported-hw = <0xe>, <0x7>;
157 clock-latency-ns = <15 156 clock-latency-ns = <150000>;
158 opp-suspend; 157 opp-suspend;
159 }; 158 };
160 159
161 opp-1600000000 { 160 opp-1600000000 {
162 opp-hz = /bits/ 64 <16 161 opp-hz = /bits/ 64 <1600000000>;
163 opp-microvolt = <95000 162 opp-microvolt = <950000>;
164 opp-supported-hw = <0x 163 opp-supported-hw = <0xc>, <0x7>;
165 clock-latency-ns = <15 164 clock-latency-ns = <150000>;
166 opp-suspend; 165 opp-suspend;
167 }; 166 };
168 167
169 opp-1800000000 { 168 opp-1800000000 {
170 opp-hz = /bits/ 64 <18 169 opp-hz = /bits/ 64 <1800000000>;
171 opp-microvolt = <10000 170 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x 171 opp-supported-hw = <0x8>, <0x3>;
173 clock-latency-ns = <15 172 clock-latency-ns = <150000>;
174 opp-suspend; 173 opp-suspend;
175 }; 174 };
176 }; 175 };
177 176
178 osc_32k: clock-osc-32k { 177 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock"; 178 compatible = "fixed-clock";
180 #clock-cells = <0>; 179 #clock-cells = <0>;
181 clock-frequency = <32768>; 180 clock-frequency = <32768>;
182 clock-output-names = "osc_32k" 181 clock-output-names = "osc_32k";
183 }; 182 };
184 183
185 osc_24m: clock-osc-24m { 184 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock"; 185 compatible = "fixed-clock";
187 #clock-cells = <0>; 186 #clock-cells = <0>;
188 clock-frequency = <24000000>; 187 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m" 188 clock-output-names = "osc_24m";
190 }; 189 };
191 190
192 clk_ext1: clock-ext1 { 191 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock"; 192 compatible = "fixed-clock";
194 #clock-cells = <0>; 193 #clock-cells = <0>;
195 clock-frequency = <133000000>; 194 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1 195 clock-output-names = "clk_ext1";
197 }; 196 };
198 197
199 clk_ext2: clock-ext2 { 198 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock"; 199 compatible = "fixed-clock";
201 #clock-cells = <0>; 200 #clock-cells = <0>;
202 clock-frequency = <133000000>; 201 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2 202 clock-output-names = "clk_ext2";
204 }; 203 };
205 204
206 clk_ext3: clock-ext3 { 205 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock"; 206 compatible = "fixed-clock";
208 #clock-cells = <0>; 207 #clock-cells = <0>;
209 clock-frequency = <133000000>; 208 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3 209 clock-output-names = "clk_ext3";
211 }; 210 };
212 211
213 clk_ext4: clock-ext4 { 212 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock"; 213 compatible = "fixed-clock";
215 #clock-cells = <0>; 214 #clock-cells = <0>;
216 clock-frequency = <133000000>; !! 215 clock-frequency= <133000000>;
217 clock-output-names = "clk_ext4 216 clock-output-names = "clk_ext4";
218 }; 217 };
219 218
220 psci { 219 psci {
221 compatible = "arm,psci-1.0"; 220 compatible = "arm,psci-1.0";
222 method = "smc"; 221 method = "smc";
223 }; 222 };
224 223
225 pmu { 224 pmu {
226 compatible = "arm,cortex-a53-p 225 compatible = "arm,cortex-a53-pmu";
227 interrupts = <GIC_PPI 7 226 interrupts = <GIC_PPI 7
228 (GIC_CPU_MASK_SIM 227 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
229 }; 228 };
230 229
231 timer { 230 timer {
232 compatible = "arm,armv8-timer" 231 compatible = "arm,armv8-timer";
233 interrupts = <GIC_PPI 13 (GIC_ 232 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
234 <GIC_PPI 14 (GIC_ 233 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
235 <GIC_PPI 11 (GIC_ 234 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
236 <GIC_PPI 10 (GIC_ 235 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
237 clock-frequency = <8000000>; 236 clock-frequency = <8000000>;
238 arm,no-tick-in-suspend; 237 arm,no-tick-in-suspend;
239 }; 238 };
240 239
241 thermal-zones { 240 thermal-zones {
242 cpu-thermal { 241 cpu-thermal {
243 polling-delay-passive 242 polling-delay-passive = <250>;
244 polling-delay = <2000> 243 polling-delay = <2000>;
245 thermal-sensors = <&tm 244 thermal-sensors = <&tmu>;
246 trips { 245 trips {
247 cpu_alert0: tr 246 cpu_alert0: trip0 {
248 temper 247 temperature = <85000>;
249 hyster 248 hysteresis = <2000>;
250 type = 249 type = "passive";
251 }; 250 };
252 251
253 cpu_crit0: tri 252 cpu_crit0: trip1 {
254 temper 253 temperature = <95000>;
255 hyster 254 hysteresis = <2000>;
256 type = 255 type = "critical";
257 }; 256 };
258 }; 257 };
259 258
260 cooling-maps { 259 cooling-maps {
261 map0 { 260 map0 {
262 trip = 261 trip = <&cpu_alert0>;
263 coolin 262 cooling-device =
264 263 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
265 264 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
266 265 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
267 266 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
268 }; 267 };
269 }; 268 };
270 }; 269 };
271 }; 270 };
272 271
273 usbphynop1: usbphynop1 { 272 usbphynop1: usbphynop1 {
274 #phy-cells = <0>; 273 #phy-cells = <0>;
275 compatible = "usb-nop-xceiv"; 274 compatible = "usb-nop-xceiv";
276 clocks = <&clk IMX8MM_CLK_USB_ 275 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277 assigned-clocks = <&clk IMX8MM 276 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
278 assigned-clock-parents = <&clk 277 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
279 clock-names = "main_clk"; 278 clock-names = "main_clk";
280 power-domains = <&pgc_otg1>; <<
281 }; 279 };
282 280
283 usbphynop2: usbphynop2 { 281 usbphynop2: usbphynop2 {
284 #phy-cells = <0>; 282 #phy-cells = <0>;
285 compatible = "usb-nop-xceiv"; 283 compatible = "usb-nop-xceiv";
286 clocks = <&clk IMX8MM_CLK_USB_ 284 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
287 assigned-clocks = <&clk IMX8MM 285 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
288 assigned-clock-parents = <&clk 286 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
289 clock-names = "main_clk"; 287 clock-names = "main_clk";
290 power-domains = <&pgc_otg2>; <<
291 }; 288 };
292 289
293 soc: soc@0 { !! 290 soc@0 {
294 compatible = "fsl,imx8mm-soc", 291 compatible = "fsl,imx8mm-soc", "simple-bus";
295 #address-cells = <1>; 292 #address-cells = <1>;
296 #size-cells = <1>; 293 #size-cells = <1>;
297 ranges = <0x0 0x0 0x0 0x3e0000 294 ranges = <0x0 0x0 0x0 0x3e000000>;
298 dma-ranges = <0x40000000 0x0 0 295 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
299 nvmem-cells = <&imx8mm_uid>; 296 nvmem-cells = <&imx8mm_uid>;
300 nvmem-cell-names = "soc_unique 297 nvmem-cell-names = "soc_unique_id";
301 298
302 aips1: bus@30000000 { 299 aips1: bus@30000000 {
303 compatible = "fsl,aips 300 compatible = "fsl,aips-bus", "simple-bus";
304 reg = <0x30000000 0x40 301 reg = <0x30000000 0x400000>;
305 #address-cells = <1>; 302 #address-cells = <1>;
306 #size-cells = <1>; 303 #size-cells = <1>;
307 ranges = <0x30000000 0 304 ranges = <0x30000000 0x30000000 0x400000>;
308 305
309 spba2: spba-bus@300000 306 spba2: spba-bus@30000000 {
310 compatible = " 307 compatible = "fsl,spba-bus", "simple-bus";
311 #address-cells 308 #address-cells = <1>;
312 #size-cells = 309 #size-cells = <1>;
313 reg = <0x30000 310 reg = <0x30000000 0x100000>;
314 ranges; 311 ranges;
315 312
316 sai1: sai@3001 313 sai1: sai@30010000 {
317 #sound 314 #sound-dai-cells = <0>;
318 compat 315 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
319 reg = 316 reg = <0x30010000 0x10000>;
320 interr 317 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
321 clocks 318 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
322 319 <&clk IMX8MM_CLK_SAI1_ROOT>,
323 320 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
324 clock- 321 clock-names = "bus", "mclk1", "mclk2", "mclk3";
325 dmas = 322 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
326 dma-na 323 dma-names = "rx", "tx";
327 status 324 status = "disabled";
328 }; 325 };
329 326
330 sai2: sai@3002 327 sai2: sai@30020000 {
331 #sound 328 #sound-dai-cells = <0>;
332 compat 329 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
333 reg = 330 reg = <0x30020000 0x10000>;
334 interr 331 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
335 clocks 332 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
336 333 <&clk IMX8MM_CLK_SAI2_ROOT>,
337 334 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
338 clock- 335 clock-names = "bus", "mclk1", "mclk2", "mclk3";
339 dmas = 336 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
340 dma-na 337 dma-names = "rx", "tx";
341 status 338 status = "disabled";
342 }; 339 };
343 340
344 sai3: sai@3003 341 sai3: sai@30030000 {
345 #sound 342 #sound-dai-cells = <0>;
346 compat 343 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
347 reg = 344 reg = <0x30030000 0x10000>;
348 interr 345 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
349 clocks 346 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
350 347 <&clk IMX8MM_CLK_SAI3_ROOT>,
351 348 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
352 clock- 349 clock-names = "bus", "mclk1", "mclk2", "mclk3";
353 dmas = 350 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
354 dma-na 351 dma-names = "rx", "tx";
355 status 352 status = "disabled";
356 }; 353 };
357 354
358 sai5: sai@3005 355 sai5: sai@30050000 {
359 #sound 356 #sound-dai-cells = <0>;
360 compat 357 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
361 reg = 358 reg = <0x30050000 0x10000>;
362 interr 359 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
363 clocks 360 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
364 361 <&clk IMX8MM_CLK_SAI5_ROOT>,
365 362 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
366 clock- 363 clock-names = "bus", "mclk1", "mclk2", "mclk3";
367 dmas = 364 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
368 dma-na 365 dma-names = "rx", "tx";
369 status 366 status = "disabled";
370 }; 367 };
371 368
372 sai6: sai@3006 369 sai6: sai@30060000 {
373 #sound 370 #sound-dai-cells = <0>;
374 compat 371 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
375 reg = 372 reg = <0x30060000 0x10000>;
376 interr 373 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
377 clocks 374 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
378 375 <&clk IMX8MM_CLK_SAI6_ROOT>,
379 376 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
380 clock- 377 clock-names = "bus", "mclk1", "mclk2", "mclk3";
381 dmas = 378 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
382 dma-na 379 dma-names = "rx", "tx";
383 status 380 status = "disabled";
384 }; 381 };
385 382
386 micfil: audio- 383 micfil: audio-controller@30080000 {
387 compat 384 compatible = "fsl,imx8mm-micfil";
388 reg = 385 reg = <0x30080000 0x10000>;
389 interr 386 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
390 387 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
391 388 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
392 389 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
393 clocks 390 clocks = <&clk IMX8MM_CLK_PDM_IPG>,
394 391 <&clk IMX8MM_CLK_PDM_ROOT>,
395 392 <&clk IMX8MM_AUDIO_PLL1_OUT>,
396 393 <&clk IMX8MM_AUDIO_PLL2_OUT>,
397 394 <&clk IMX8MM_CLK_EXT3>;
398 clock- 395 clock-names = "ipg_clk", "ipg_clk_app",
399 396 "pll8k", "pll11k", "clkext3";
400 dmas = 397 dmas = <&sdma2 24 25 0x80000000>;
401 dma-na 398 dma-names = "rx";
402 #sound <<
403 status 399 status = "disabled";
404 }; 400 };
405 401
406 spdif1: spdif@ 402 spdif1: spdif@30090000 {
407 compat 403 compatible = "fsl,imx35-spdif";
408 reg = 404 reg = <0x30090000 0x10000>;
409 interr 405 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
410 clocks 406 clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, /* core */
411 407 <&clk IMX8MM_CLK_24M>, /* rxtx0 */
412 408 <&clk IMX8MM_CLK_SPDIF1>, /* rxtx1 */
413 409 <&clk IMX8MM_CLK_DUMMY>, /* rxtx2 */
414 410 <&clk IMX8MM_CLK_DUMMY>, /* rxtx3 */
415 411 <&clk IMX8MM_CLK_DUMMY>, /* rxtx4 */
416 412 <&clk IMX8MM_CLK_AUDIO_AHB>, /* rxtx5 */
417 413 <&clk IMX8MM_CLK_DUMMY>, /* rxtx6 */
418 414 <&clk IMX8MM_CLK_DUMMY>, /* rxtx7 */
419 415 <&clk IMX8MM_CLK_DUMMY>; /* spba */
420 clock- 416 clock-names = "core", "rxtx0",
421 417 "rxtx1", "rxtx2",
422 418 "rxtx3", "rxtx4",
423 419 "rxtx5", "rxtx6",
424 420 "rxtx7", "spba";
425 dmas = 421 dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
426 dma-na 422 dma-names = "rx", "tx";
427 status 423 status = "disabled";
428 }; 424 };
429 }; 425 };
430 426
431 gpio1: gpio@30200000 { 427 gpio1: gpio@30200000 {
432 compatible = " 428 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
433 reg = <0x30200 429 reg = <0x30200000 0x10000>;
434 interrupts = < 430 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
435 < 431 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clk 432 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
437 gpio-controlle 433 gpio-controller;
438 #gpio-cells = 434 #gpio-cells = <2>;
439 interrupt-cont 435 interrupt-controller;
440 #interrupt-cel 436 #interrupt-cells = <2>;
441 gpio-ranges = 437 gpio-ranges = <&iomuxc 0 10 30>;
442 }; 438 };
443 439
444 gpio2: gpio@30210000 { 440 gpio2: gpio@30210000 {
445 compatible = " 441 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
446 reg = <0x30210 442 reg = <0x30210000 0x10000>;
447 interrupts = < 443 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
448 < 444 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clk 445 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
450 gpio-controlle 446 gpio-controller;
451 #gpio-cells = 447 #gpio-cells = <2>;
452 interrupt-cont 448 interrupt-controller;
453 #interrupt-cel 449 #interrupt-cells = <2>;
454 gpio-ranges = 450 gpio-ranges = <&iomuxc 0 40 21>;
455 }; 451 };
456 452
457 gpio3: gpio@30220000 { 453 gpio3: gpio@30220000 {
458 compatible = " 454 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
459 reg = <0x30220 455 reg = <0x30220000 0x10000>;
460 interrupts = < 456 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
461 < 457 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clk 458 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
463 gpio-controlle 459 gpio-controller;
464 #gpio-cells = 460 #gpio-cells = <2>;
465 interrupt-cont 461 interrupt-controller;
466 #interrupt-cel 462 #interrupt-cells = <2>;
467 gpio-ranges = 463 gpio-ranges = <&iomuxc 0 61 26>;
468 }; 464 };
469 465
470 gpio4: gpio@30230000 { 466 gpio4: gpio@30230000 {
471 compatible = " 467 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
472 reg = <0x30230 468 reg = <0x30230000 0x10000>;
473 interrupts = < 469 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
474 < 470 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk 471 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
476 gpio-controlle 472 gpio-controller;
477 #gpio-cells = 473 #gpio-cells = <2>;
478 interrupt-cont 474 interrupt-controller;
479 #interrupt-cel 475 #interrupt-cells = <2>;
480 gpio-ranges = 476 gpio-ranges = <&iomuxc 0 87 32>;
481 }; 477 };
482 478
483 gpio5: gpio@30240000 { 479 gpio5: gpio@30240000 {
484 compatible = " 480 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
485 reg = <0x30240 481 reg = <0x30240000 0x10000>;
486 interrupts = < 482 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
487 < 483 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clk 484 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
489 gpio-controlle 485 gpio-controller;
490 #gpio-cells = 486 #gpio-cells = <2>;
491 interrupt-cont 487 interrupt-controller;
492 #interrupt-cel 488 #interrupt-cells = <2>;
493 gpio-ranges = 489 gpio-ranges = <&iomuxc 0 119 30>;
494 }; 490 };
495 491
496 tmu: tmu@30260000 { 492 tmu: tmu@30260000 {
497 compatible = " 493 compatible = "fsl,imx8mm-tmu";
498 reg = <0x30260 494 reg = <0x30260000 0x10000>;
499 clocks = <&clk 495 clocks = <&clk IMX8MM_CLK_TMU_ROOT>;
500 nvmem-cells = <<
501 nvmem-cell-nam <<
502 #thermal-senso 496 #thermal-sensor-cells = <0>;
503 }; 497 };
504 498
505 wdog1: watchdog@302800 499 wdog1: watchdog@30280000 {
506 compatible = " 500 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
507 reg = <0x30280 501 reg = <0x30280000 0x10000>;
508 interrupts = < 502 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clk 503 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
510 status = "disa 504 status = "disabled";
511 }; 505 };
512 506
513 wdog2: watchdog@302900 507 wdog2: watchdog@30290000 {
514 compatible = " 508 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
515 reg = <0x30290 509 reg = <0x30290000 0x10000>;
516 interrupts = < 510 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clk 511 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
518 status = "disa 512 status = "disabled";
519 }; 513 };
520 514
521 wdog3: watchdog@302a00 515 wdog3: watchdog@302a0000 {
522 compatible = " 516 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
523 reg = <0x302a0 517 reg = <0x302a0000 0x10000>;
524 interrupts = < 518 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clk 519 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
526 status = "disa 520 status = "disabled";
527 }; 521 };
528 522
529 sdma2: dma-controller@ 523 sdma2: dma-controller@302c0000 {
530 compatible = " 524 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
531 reg = <0x302c0 525 reg = <0x302c0000 0x10000>;
532 interrupts = < 526 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&clk 527 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
534 <&clk 528 <&clk IMX8MM_CLK_SDMA2_ROOT>;
535 clock-names = 529 clock-names = "ipg", "ahb";
536 #dma-cells = < 530 #dma-cells = <3>;
537 fsl,sdma-ram-s 531 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
538 }; 532 };
539 533
540 sdma3: dma-controller@ 534 sdma3: dma-controller@302b0000 {
541 compatible = " 535 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
542 reg = <0x302b0 536 reg = <0x302b0000 0x10000>;
543 interrupts = < 537 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clk 538 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
545 <&clk IMX8MM_ 539 <&clk IMX8MM_CLK_SDMA3_ROOT>;
546 clock-names = 540 clock-names = "ipg", "ahb";
547 #dma-cells = < 541 #dma-cells = <3>;
548 fsl,sdma-ram-s 542 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
549 }; 543 };
550 544
551 iomuxc: pinctrl@303300 545 iomuxc: pinctrl@30330000 {
552 compatible = " 546 compatible = "fsl,imx8mm-iomuxc";
553 reg = <0x30330 547 reg = <0x30330000 0x10000>;
554 }; 548 };
555 549
556 gpr: syscon@30340000 { !! 550 gpr: iomuxc-gpr@30340000 {
557 compatible = " !! 551 compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
558 reg = <0x30340 552 reg = <0x30340000 0x10000>;
559 }; 553 };
560 554
561 ocotp: efuse@30350000 555 ocotp: efuse@30350000 {
562 compatible = " 556 compatible = "fsl,imx8mm-ocotp", "syscon";
563 reg = <0x30350 557 reg = <0x30350000 0x10000>;
564 clocks = <&clk 558 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
565 /* For nvmem s 559 /* For nvmem subnodes */
566 #address-cells 560 #address-cells = <1>;
567 #size-cells = 561 #size-cells = <1>;
568 562
569 /* !! 563 imx8mm_uid: unique-id@410 {
570 * The registe <<
571 * Fusemap Des <<
572 * Assuming <<
573 * reg = <AD <<
574 * then <<
575 * Fuse Addr <<
576 * Note that i <<
577 * each subseq <<
578 * +0x10 in Fu <<
579 * reg = <0x4 <<
580 * 0x420). <<
581 */ <<
582 imx8mm_uid: un <<
583 reg = 564 reg = <0x4 0x8>;
584 }; 565 };
585 566
586 cpu_speed_grad !! 567 cpu_speed_grade: speed-grade@10 {
587 reg = 568 reg = <0x10 4>;
588 }; 569 };
589 570
590 tmu_calib: cal !! 571 fec_mac_address: mac-address@90 {
591 reg = <<
592 }; <<
593 <<
594 fec_mac_addres <<
595 reg = 572 reg = <0x90 6>;
596 }; 573 };
597 }; 574 };
598 575
599 anatop: clock-controll !! 576 anatop: anatop@30360000 {
600 compatible = " !! 577 compatible = "fsl,imx8mm-anatop", "syscon";
601 reg = <0x30360 578 reg = <0x30360000 0x10000>;
602 #clock-cells = <<
603 }; 579 };
604 580
605 snvs: snvs@30370000 { 581 snvs: snvs@30370000 {
606 compatible = " 582 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
607 reg = <0x30370 583 reg = <0x30370000 0x10000>;
608 584
609 snvs_rtc: snvs 585 snvs_rtc: snvs-rtc-lp {
610 compat 586 compatible = "fsl,sec-v4.0-mon-rtc-lp";
611 regmap 587 regmap = <&snvs>;
612 offset 588 offset = <0x34>;
613 interr 589 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
614 590 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
615 clocks 591 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
616 clock- 592 clock-names = "snvs-rtc";
617 }; 593 };
618 594
619 snvs_pwrkey: s 595 snvs_pwrkey: snvs-powerkey {
620 compat 596 compatible = "fsl,sec-v4.0-pwrkey";
621 regmap 597 regmap = <&snvs>;
622 interr 598 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
623 clocks 599 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
624 clock- 600 clock-names = "snvs-pwrkey";
625 linux, 601 linux,keycode = <KEY_POWER>;
626 wakeup 602 wakeup-source;
627 status 603 status = "disabled";
628 }; 604 };
629 <<
630 snvs_lpgpr: sn <<
631 compat <<
632 <<
633 }; <<
634 }; 605 };
635 606
636 clk: clock-controller@ 607 clk: clock-controller@30380000 {
637 compatible = " 608 compatible = "fsl,imx8mm-ccm";
638 reg = <0x30380 609 reg = <0x30380000 0x10000>;
639 interrupts = < <<
640 < <<
641 #clock-cells = 610 #clock-cells = <1>;
642 clocks = <&osc 611 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
643 <&clk 612 <&clk_ext3>, <&clk_ext4>;
644 clock-names = 613 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
645 614 "clk_ext3", "clk_ext4";
646 assigned-clock 615 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
647 616 <&clk IMX8MM_CLK_A53_CORE>,
648 617 <&clk IMX8MM_CLK_NOC>,
649 618 <&clk IMX8MM_CLK_AUDIO_AHB>,
650 619 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
651 620 <&clk IMX8MM_SYS_PLL3>,
>> 621 <&clk IMX8MM_VIDEO_PLL1>,
652 622 <&clk IMX8MM_AUDIO_PLL1>;
653 assigned-clock 623 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
654 624 <&clk IMX8MM_ARM_PLL_OUT>,
655 625 <&clk IMX8MM_SYS_PLL3_OUT>,
656 626 <&clk IMX8MM_SYS_PLL1_800M>;
657 assigned-clock 627 assigned-clock-rates = <0>, <0>, <0>,
658 628 <400000000>,
659 629 <400000000>,
660 630 <750000000>,
>> 631 <594000000>,
661 632 <393216000>;
662 }; 633 };
663 634
664 src: reset-controller@ 635 src: reset-controller@30390000 {
665 compatible = " 636 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
666 reg = <0x30390 637 reg = <0x30390000 0x10000>;
667 interrupts = < 638 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
668 #reset-cells = 639 #reset-cells = <1>;
669 }; 640 };
670 641
671 gpc: gpc@303a0000 { 642 gpc: gpc@303a0000 {
672 compatible = " 643 compatible = "fsl,imx8mm-gpc";
673 reg = <0x303a0 644 reg = <0x303a0000 0x10000>;
674 interrupts = < 645 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
675 interrupt-pare 646 interrupt-parent = <&gic>;
676 interrupt-cont 647 interrupt-controller;
677 #interrupt-cel 648 #interrupt-cells = <3>;
678 649
679 pgc { 650 pgc {
680 #addre 651 #address-cells = <1>;
681 #size- 652 #size-cells = <0>;
682 653
683 pgc_hs 654 pgc_hsiomix: power-domain@0 {
684 655 #power-domain-cells = <0>;
685 656 reg = <IMX8MM_POWER_DOMAIN_HSIOMIX>;
686 657 clocks = <&clk IMX8MM_CLK_USB_BUS>;
687 658 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
688 659 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
689 }; 660 };
690 661
691 pgc_pc 662 pgc_pcie: power-domain@1 {
692 663 #power-domain-cells = <0>;
693 664 reg = <IMX8MM_POWER_DOMAIN_PCIE>;
694 665 power-domains = <&pgc_hsiomix>;
695 666 clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>;
696 }; 667 };
697 668
698 pgc_ot 669 pgc_otg1: power-domain@2 {
699 670 #power-domain-cells = <0>;
700 671 reg = <IMX8MM_POWER_DOMAIN_OTG1>;
>> 672 power-domains = <&pgc_hsiomix>;
701 }; 673 };
702 674
703 pgc_ot 675 pgc_otg2: power-domain@3 {
704 676 #power-domain-cells = <0>;
705 677 reg = <IMX8MM_POWER_DOMAIN_OTG2>;
>> 678 power-domains = <&pgc_hsiomix>;
706 }; 679 };
707 680
708 pgc_gp 681 pgc_gpumix: power-domain@4 {
709 682 #power-domain-cells = <0>;
710 683 reg = <IMX8MM_POWER_DOMAIN_GPUMIX>;
711 684 clocks = <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
712 685 <&clk IMX8MM_CLK_GPU_AHB>;
713 686 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
714 687 <&clk IMX8MM_CLK_GPU_AHB>;
715 688 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
716 689 <&clk IMX8MM_SYS_PLL1_800M>;
717 690 assigned-clock-rates = <800000000>, <400000000>;
718 }; 691 };
719 692
720 pgc_gp 693 pgc_gpu: power-domain@5 {
721 694 #power-domain-cells = <0>;
722 695 reg = <IMX8MM_POWER_DOMAIN_GPU>;
723 696 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
724 697 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
725 698 <&clk IMX8MM_CLK_GPU2D_ROOT>,
726 699 <&clk IMX8MM_CLK_GPU3D_ROOT>;
727 700 resets = <&src IMX8MQ_RESET_GPU_RESET>;
728 701 power-domains = <&pgc_gpumix>;
729 }; 702 };
730 703
731 pgc_vp 704 pgc_vpumix: power-domain@6 {
732 705 #power-domain-cells = <0>;
733 706 reg = <IMX8MM_POWER_DOMAIN_VPUMIX>;
734 707 clocks = <&clk IMX8MM_CLK_VPU_DEC_ROOT>;
735 708 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
736 709 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
737 }; 710 };
738 711
739 pgc_vp 712 pgc_vpu_g1: power-domain@7 {
740 713 #power-domain-cells = <0>;
741 714 reg = <IMX8MM_POWER_DOMAIN_VPUG1>;
742 }; 715 };
743 716
744 pgc_vp 717 pgc_vpu_g2: power-domain@8 {
745 718 #power-domain-cells = <0>;
746 719 reg = <IMX8MM_POWER_DOMAIN_VPUG2>;
747 }; 720 };
748 721
749 pgc_vp 722 pgc_vpu_h1: power-domain@9 {
750 723 #power-domain-cells = <0>;
751 724 reg = <IMX8MM_POWER_DOMAIN_VPUH1>;
752 }; 725 };
753 726
754 pgc_di 727 pgc_dispmix: power-domain@10 {
755 728 #power-domain-cells = <0>;
756 729 reg = <IMX8MM_POWER_DOMAIN_DISPMIX>;
757 730 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
758 731 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
759 732 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
760 733 <&clk IMX8MM_CLK_DISP_APB>;
761 734 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
762 735 <&clk IMX8MM_SYS_PLL1_800M>;
763 736 assigned-clock-rates = <500000000>, <200000000>;
764 }; 737 };
765 738
766 pgc_mi 739 pgc_mipi: power-domain@11 {
767 740 #power-domain-cells = <0>;
768 741 reg = <IMX8MM_POWER_DOMAIN_MIPI>;
769 }; 742 };
770 }; 743 };
771 }; 744 };
772 }; 745 };
773 746
774 aips2: bus@30400000 { 747 aips2: bus@30400000 {
775 compatible = "fsl,aips 748 compatible = "fsl,aips-bus", "simple-bus";
776 reg = <0x30400000 0x40 749 reg = <0x30400000 0x400000>;
777 #address-cells = <1>; 750 #address-cells = <1>;
778 #size-cells = <1>; 751 #size-cells = <1>;
779 ranges = <0x30400000 0 752 ranges = <0x30400000 0x30400000 0x400000>;
780 753
781 pwm1: pwm@30660000 { 754 pwm1: pwm@30660000 {
782 compatible = " 755 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
783 reg = <0x30660 756 reg = <0x30660000 0x10000>;
784 interrupts = < 757 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clk 758 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
786 <&clk 759 <&clk IMX8MM_CLK_PWM1_ROOT>;
787 clock-names = 760 clock-names = "ipg", "per";
788 #pwm-cells = < 761 #pwm-cells = <3>;
789 status = "disa 762 status = "disabled";
790 }; 763 };
791 764
792 pwm2: pwm@30670000 { 765 pwm2: pwm@30670000 {
793 compatible = " 766 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
794 reg = <0x30670 767 reg = <0x30670000 0x10000>;
795 interrupts = < 768 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clk 769 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
797 <&clk 770 <&clk IMX8MM_CLK_PWM2_ROOT>;
798 clock-names = 771 clock-names = "ipg", "per";
799 #pwm-cells = < 772 #pwm-cells = <3>;
800 status = "disa 773 status = "disabled";
801 }; 774 };
802 775
803 pwm3: pwm@30680000 { 776 pwm3: pwm@30680000 {
804 compatible = " 777 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
805 reg = <0x30680 778 reg = <0x30680000 0x10000>;
806 interrupts = < 779 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clk 780 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
808 <&clk 781 <&clk IMX8MM_CLK_PWM3_ROOT>;
809 clock-names = 782 clock-names = "ipg", "per";
810 #pwm-cells = < 783 #pwm-cells = <3>;
811 status = "disa 784 status = "disabled";
812 }; 785 };
813 786
814 pwm4: pwm@30690000 { 787 pwm4: pwm@30690000 {
815 compatible = " 788 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
816 reg = <0x30690 789 reg = <0x30690000 0x10000>;
817 interrupts = < 790 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clk 791 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
819 <&clk 792 <&clk IMX8MM_CLK_PWM4_ROOT>;
820 clock-names = 793 clock-names = "ipg", "per";
821 #pwm-cells = < 794 #pwm-cells = <3>;
822 status = "disa 795 status = "disabled";
823 }; 796 };
824 797
825 system_counter: timer@ 798 system_counter: timer@306a0000 {
826 compatible = " 799 compatible = "nxp,sysctr-timer";
827 reg = <0x306a0 800 reg = <0x306a0000 0x20000>;
828 interrupts = < 801 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&osc 802 clocks = <&osc_24m>;
830 clock-names = 803 clock-names = "per";
831 }; 804 };
832 }; 805 };
833 806
834 aips3: bus@30800000 { 807 aips3: bus@30800000 {
835 compatible = "fsl,aips 808 compatible = "fsl,aips-bus", "simple-bus";
836 reg = <0x30800000 0x40 809 reg = <0x30800000 0x400000>;
837 #address-cells = <1>; 810 #address-cells = <1>;
838 #size-cells = <1>; 811 #size-cells = <1>;
839 ranges = <0x30800000 0 812 ranges = <0x30800000 0x30800000 0x400000>,
840 <0x8000000 0x 813 <0x8000000 0x8000000 0x10000000>;
841 814
842 spba1: spba-bus@308000 815 spba1: spba-bus@30800000 {
843 compatible = " 816 compatible = "fsl,spba-bus", "simple-bus";
844 #address-cells 817 #address-cells = <1>;
845 #size-cells = 818 #size-cells = <1>;
846 reg = <0x30800 819 reg = <0x30800000 0x100000>;
847 ranges; 820 ranges;
848 821
849 ecspi1: spi@30 822 ecspi1: spi@30820000 {
850 compat 823 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
851 #addre 824 #address-cells = <1>;
852 #size- 825 #size-cells = <0>;
853 reg = 826 reg = <0x30820000 0x10000>;
854 interr 827 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
855 clocks 828 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
856 829 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
857 clock- 830 clock-names = "ipg", "per";
858 dmas = 831 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
859 dma-na 832 dma-names = "rx", "tx";
860 status 833 status = "disabled";
861 }; 834 };
862 835
863 ecspi2: spi@30 836 ecspi2: spi@30830000 {
864 compat 837 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
865 #addre 838 #address-cells = <1>;
866 #size- 839 #size-cells = <0>;
867 reg = 840 reg = <0x30830000 0x10000>;
868 interr 841 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
869 clocks 842 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
870 843 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
871 clock- 844 clock-names = "ipg", "per";
872 dmas = 845 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
873 dma-na 846 dma-names = "rx", "tx";
874 status 847 status = "disabled";
875 }; 848 };
876 849
877 ecspi3: spi@30 850 ecspi3: spi@30840000 {
878 compat 851 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
879 #addre 852 #address-cells = <1>;
880 #size- 853 #size-cells = <0>;
881 reg = 854 reg = <0x30840000 0x10000>;
882 interr 855 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
883 clocks 856 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
884 857 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
885 clock- 858 clock-names = "ipg", "per";
886 dmas = 859 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
887 dma-na 860 dma-names = "rx", "tx";
888 status 861 status = "disabled";
889 }; 862 };
890 863
891 uart1: serial@ 864 uart1: serial@30860000 {
892 compat 865 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
893 reg = 866 reg = <0x30860000 0x10000>;
894 interr 867 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
895 clocks 868 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
896 869 <&clk IMX8MM_CLK_UART1_ROOT>;
897 clock- 870 clock-names = "ipg", "per";
898 dmas = 871 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
899 dma-na 872 dma-names = "rx", "tx";
900 status 873 status = "disabled";
901 }; 874 };
902 875
903 uart3: serial@ 876 uart3: serial@30880000 {
904 compat 877 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
905 reg = 878 reg = <0x30880000 0x10000>;
906 interr 879 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
907 clocks 880 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
908 881 <&clk IMX8MM_CLK_UART3_ROOT>;
909 clock- 882 clock-names = "ipg", "per";
910 dmas = 883 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
911 dma-na 884 dma-names = "rx", "tx";
912 status 885 status = "disabled";
913 }; 886 };
914 887
915 uart2: serial@ 888 uart2: serial@30890000 {
916 compat 889 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
917 reg = 890 reg = <0x30890000 0x10000>;
918 interr 891 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
919 clocks 892 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
920 893 <&clk IMX8MM_CLK_UART2_ROOT>;
921 clock- 894 clock-names = "ipg", "per";
922 status 895 status = "disabled";
923 }; 896 };
924 }; 897 };
925 898
926 crypto: crypto@3090000 899 crypto: crypto@30900000 {
927 compatible = " 900 compatible = "fsl,sec-v4.0";
928 #address-cells 901 #address-cells = <1>;
929 #size-cells = 902 #size-cells = <1>;
930 reg = <0x30900 903 reg = <0x30900000 0x40000>;
931 ranges = <0 0x 904 ranges = <0 0x30900000 0x40000>;
932 interrupts = < 905 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&clk 906 clocks = <&clk IMX8MM_CLK_AHB>,
934 <&clk 907 <&clk IMX8MM_CLK_IPG_ROOT>;
935 clock-names = 908 clock-names = "aclk", "ipg";
936 909
937 sec_jr0: jr@10 910 sec_jr0: jr@1000 {
938 compat 911 compatible = "fsl,sec-v4.0-job-ring";
939 reg = 912 reg = <0x1000 0x1000>;
940 interr 913 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
941 status <<
942 }; 914 };
943 915
944 sec_jr1: jr@20 916 sec_jr1: jr@2000 {
945 compat 917 compatible = "fsl,sec-v4.0-job-ring";
946 reg = 918 reg = <0x2000 0x1000>;
947 interr 919 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
948 }; 920 };
949 921
950 sec_jr2: jr@30 922 sec_jr2: jr@3000 {
951 compat 923 compatible = "fsl,sec-v4.0-job-ring";
952 reg = 924 reg = <0x3000 0x1000>;
953 interr 925 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
954 }; 926 };
955 }; 927 };
956 928
957 i2c1: i2c@30a20000 { 929 i2c1: i2c@30a20000 {
958 compatible = " 930 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
959 #address-cells 931 #address-cells = <1>;
960 #size-cells = 932 #size-cells = <0>;
961 reg = <0x30a20 933 reg = <0x30a20000 0x10000>;
962 interrupts = < 934 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clk 935 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
964 status = "disa 936 status = "disabled";
965 }; 937 };
966 938
967 i2c2: i2c@30a30000 { 939 i2c2: i2c@30a30000 {
968 compatible = " 940 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
969 #address-cells 941 #address-cells = <1>;
970 #size-cells = 942 #size-cells = <0>;
971 reg = <0x30a30 943 reg = <0x30a30000 0x10000>;
972 interrupts = < 944 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clk 945 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
974 status = "disa 946 status = "disabled";
975 }; 947 };
976 948
977 i2c3: i2c@30a40000 { 949 i2c3: i2c@30a40000 {
978 #address-cells 950 #address-cells = <1>;
979 #size-cells = 951 #size-cells = <0>;
980 compatible = " 952 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
981 reg = <0x30a40 953 reg = <0x30a40000 0x10000>;
982 interrupts = < 954 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&clk 955 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
984 status = "disa 956 status = "disabled";
985 }; 957 };
986 958
987 i2c4: i2c@30a50000 { 959 i2c4: i2c@30a50000 {
988 compatible = " 960 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
989 #address-cells 961 #address-cells = <1>;
990 #size-cells = 962 #size-cells = <0>;
991 reg = <0x30a50 963 reg = <0x30a50000 0x10000>;
992 interrupts = < 964 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&clk 965 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
994 status = "disa 966 status = "disabled";
995 }; 967 };
996 968
997 uart4: serial@30a60000 969 uart4: serial@30a60000 {
998 compatible = " 970 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
999 reg = <0x30a60 971 reg = <0x30a60000 0x10000>;
1000 interrupts = 972 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&cl 973 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
1002 <&cl 974 <&clk IMX8MM_CLK_UART4_ROOT>;
1003 clock-names = 975 clock-names = "ipg", "per";
1004 dmas = <&sdma 976 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1005 dma-names = " 977 dma-names = "rx", "tx";
1006 status = "dis 978 status = "disabled";
1007 }; 979 };
1008 980
1009 mu: mailbox@30aa0000 981 mu: mailbox@30aa0000 {
1010 compatible = 982 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
1011 reg = <0x30aa 983 reg = <0x30aa0000 0x10000>;
1012 interrupts = 984 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1013 clocks = <&cl 985 clocks = <&clk IMX8MM_CLK_MU_ROOT>;
1014 #mbox-cells = 986 #mbox-cells = <2>;
1015 }; 987 };
1016 988
1017 usdhc1: mmc@30b40000 989 usdhc1: mmc@30b40000 {
1018 compatible = 990 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1019 reg = <0x30b4 991 reg = <0x30b40000 0x10000>;
1020 interrupts = 992 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&cl 993 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1022 <&cl 994 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1023 <&cl 995 <&clk IMX8MM_CLK_USDHC1_ROOT>;
1024 clock-names = 996 clock-names = "ipg", "ahb", "per";
1025 fsl,tuning-st 997 fsl,tuning-start-tap = <20>;
1026 fsl,tuning-st !! 998 fsl,tuning-step= <2>;
1027 bus-width = < 999 bus-width = <4>;
1028 status = "dis 1000 status = "disabled";
1029 }; 1001 };
1030 1002
1031 usdhc2: mmc@30b50000 1003 usdhc2: mmc@30b50000 {
1032 compatible = 1004 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1033 reg = <0x30b5 1005 reg = <0x30b50000 0x10000>;
1034 interrupts = 1006 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&cl 1007 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1036 <&cl 1008 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1037 <&cl 1009 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1038 clock-names = 1010 clock-names = "ipg", "ahb", "per";
1039 fsl,tuning-st 1011 fsl,tuning-start-tap = <20>;
1040 fsl,tuning-st !! 1012 fsl,tuning-step= <2>;
1041 bus-width = < 1013 bus-width = <4>;
1042 status = "dis 1014 status = "disabled";
1043 }; 1015 };
1044 1016
1045 usdhc3: mmc@30b60000 1017 usdhc3: mmc@30b60000 {
1046 compatible = 1018 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1047 reg = <0x30b6 1019 reg = <0x30b60000 0x10000>;
1048 interrupts = 1020 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&cl 1021 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1050 <&cl 1022 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1051 <&cl 1023 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1052 clock-names = 1024 clock-names = "ipg", "ahb", "per";
1053 fsl,tuning-st 1025 fsl,tuning-start-tap = <20>;
1054 fsl,tuning-st !! 1026 fsl,tuning-step= <2>;
1055 bus-width = < 1027 bus-width = <4>;
1056 status = "dis 1028 status = "disabled";
1057 }; 1029 };
1058 1030
1059 flexspi: spi@30bb0000 1031 flexspi: spi@30bb0000 {
1060 #address-cell 1032 #address-cells = <1>;
1061 #size-cells = 1033 #size-cells = <0>;
1062 compatible = 1034 compatible = "nxp,imx8mm-fspi";
1063 reg = <0x30bb 1035 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1064 reg-names = " 1036 reg-names = "fspi_base", "fspi_mmap";
1065 interrupts = 1037 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1066 clocks = <&cl 1038 clocks = <&clk IMX8MM_CLK_QSPI_ROOT>,
1067 <&cl 1039 <&clk IMX8MM_CLK_QSPI_ROOT>;
1068 clock-names = 1040 clock-names = "fspi_en", "fspi";
1069 status = "dis 1041 status = "disabled";
1070 }; 1042 };
1071 1043
1072 sdma1: dma-controller 1044 sdma1: dma-controller@30bd0000 {
1073 compatible = 1045 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1074 reg = <0x30bd 1046 reg = <0x30bd0000 0x10000>;
1075 interrupts = 1047 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&cl 1048 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1077 <&cl 1049 <&clk IMX8MM_CLK_AHB>;
1078 clock-names = 1050 clock-names = "ipg", "ahb";
1079 #dma-cells = 1051 #dma-cells = <3>;
1080 fsl,sdma-ram- 1052 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1081 }; 1053 };
1082 1054
1083 fec1: ethernet@30be00 1055 fec1: ethernet@30be0000 {
1084 compatible = 1056 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1085 reg = <0x30be 1057 reg = <0x30be0000 0x10000>;
1086 interrupts = 1058 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1087 1059 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1088 1060 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1089 1061 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1090 clocks = <&cl 1062 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1091 <&cl 1063 <&clk IMX8MM_CLK_ENET1_ROOT>,
1092 <&cl 1064 <&clk IMX8MM_CLK_ENET_TIMER>,
1093 <&cl 1065 <&clk IMX8MM_CLK_ENET_REF>,
1094 <&cl 1066 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1095 clock-names = 1067 clock-names = "ipg", "ahb", "ptp",
1096 1068 "enet_clk_ref", "enet_out";
1097 assigned-cloc 1069 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1098 1070 <&clk IMX8MM_CLK_ENET_TIMER>,
1099 1071 <&clk IMX8MM_CLK_ENET_REF>,
1100 1072 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1101 assigned-cloc 1073 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1102 1074 <&clk IMX8MM_SYS_PLL2_100M>,
1103 1075 <&clk IMX8MM_SYS_PLL2_125M>,
1104 1076 <&clk IMX8MM_SYS_PLL2_50M>;
1105 assigned-cloc 1077 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1106 fsl,num-tx-qu 1078 fsl,num-tx-queues = <3>;
1107 fsl,num-rx-qu 1079 fsl,num-rx-queues = <3>;
1108 nvmem-cells = 1080 nvmem-cells = <&fec_mac_address>;
1109 nvmem-cell-na 1081 nvmem-cell-names = "mac-address";
1110 fsl,stop-mode 1082 fsl,stop-mode = <&gpr 0x10 3>;
1111 status = "dis 1083 status = "disabled";
1112 }; 1084 };
1113 1085
1114 }; 1086 };
1115 1087
1116 aips4: bus@32c00000 { 1088 aips4: bus@32c00000 {
1117 compatible = "fsl,aip 1089 compatible = "fsl,aips-bus", "simple-bus";
1118 reg = <0x32c00000 0x4 1090 reg = <0x32c00000 0x400000>;
1119 #address-cells = <1>; 1091 #address-cells = <1>;
1120 #size-cells = <1>; 1092 #size-cells = <1>;
1121 ranges = <0x32c00000 1093 ranges = <0x32c00000 0x32c00000 0x400000>;
1122 1094
1123 lcdif: lcdif@32e00000 <<
1124 compatible = <<
1125 reg = <0x32e0 <<
1126 clocks = <&cl <<
1127 <&cl <<
1128 <&cl <<
1129 clock-names = <<
1130 assigned-cloc <<
1131 <<
1132 <<
1133 assigned-cloc <<
1134 <<
1135 <<
1136 assigned-cloc <<
1137 interrupts = <<
1138 power-domains <<
1139 status = "dis <<
1140 <<
1141 port { <<
1142 lcdif <<
1143 <<
1144 }; <<
1145 }; <<
1146 }; <<
1147 <<
1148 mipi_dsi: dsi@32e1000 <<
1149 compatible = <<
1150 reg = <0x32e1 <<
1151 clocks = <&cl <<
1152 <&cl <<
1153 clock-names = <<
1154 assigned-cloc <<
1155 assigned-cloc <<
1156 interrupts = <<
1157 power-domains <<
1158 status = "dis <<
1159 <<
1160 ports { <<
1161 #addr <<
1162 #size <<
1163 <<
1164 port@ <<
1165 <<
1166 <<
1167 <<
1168 <<
1169 <<
1170 }; <<
1171 <<
1172 port@ <<
1173 <<
1174 <<
1175 <<
1176 <<
1177 }; <<
1178 }; <<
1179 }; <<
1180 <<
1181 csi: csi@32e20000 { 1095 csi: csi@32e20000 {
1182 compatible = 1096 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1183 reg = <0x32e2 1097 reg = <0x32e20000 0x1000>;
1184 interrupts = 1098 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1185 clocks = <&cl 1099 clocks = <&clk IMX8MM_CLK_CSI1_ROOT>;
1186 clock-names = 1100 clock-names = "mclk";
1187 power-domains 1101 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1188 status = "dis 1102 status = "disabled";
1189 1103
1190 port { 1104 port {
1191 csi_i 1105 csi_in: endpoint {
1192 1106 remote-endpoint = <&imx8mm_mipi_csi_out>;
1193 }; 1107 };
1194 }; 1108 };
1195 }; 1109 };
1196 1110
1197 disp_blk_ctrl: blk-ct 1111 disp_blk_ctrl: blk-ctrl@32e28000 {
1198 compatible = 1112 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1199 reg = <0x32e2 1113 reg = <0x32e28000 0x100>;
1200 power-domains 1114 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1201 1115 <&pgc_dispmix>, <&pgc_mipi>,
1202 1116 <&pgc_mipi>;
1203 power-domain- 1117 power-domain-names = "bus", "csi-bridge",
1204 1118 "lcdif", "mipi-dsi",
1205 1119 "mipi-csi";
1206 clocks = <&cl 1120 clocks = <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1207 <&cl 1121 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1208 <&cl 1122 <&clk IMX8MM_CLK_CSI1_ROOT>,
1209 <&cl 1123 <&clk IMX8MM_CLK_DISP_AXI_ROOT>,
1210 <&cl 1124 <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1211 <&cl 1125 <&clk IMX8MM_CLK_DISP_ROOT>,
1212 <&cl 1126 <&clk IMX8MM_CLK_DSI_CORE>,
1213 <&cl 1127 <&clk IMX8MM_CLK_DSI_PHY_REF>,
1214 <&cl 1128 <&clk IMX8MM_CLK_CSI1_CORE>,
1215 <&cl 1129 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1216 clock-names = 1130 clock-names = "csi-bridge-axi","csi-bridge-apb",
1217 1131 "csi-bridge-core", "lcdif-axi",
1218 1132 "lcdif-apb", "lcdif-pix",
1219 1133 "dsi-pclk", "dsi-ref",
1220 1134 "csi-aclk", "csi-pclk";
1221 #power-domain 1135 #power-domain-cells = <1>;
1222 }; 1136 };
1223 1137
1224 mipi_csi: mipi-csi@32 1138 mipi_csi: mipi-csi@32e30000 {
1225 compatible = 1139 compatible = "fsl,imx8mm-mipi-csi2";
1226 reg = <0x32e3 1140 reg = <0x32e30000 0x1000>;
1227 interrupts = 1141 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1228 assigned-cloc !! 1142 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>,
1229 assigned-cloc !! 1143 <&clk IMX8MM_CLK_CSI1_PHY_REF>;
1230 !! 1144 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
>> 1145 <&clk IMX8MM_SYS_PLL2_1000M>;
1231 clock-frequen 1146 clock-frequency = <333000000>;
1232 clocks = <&cl 1147 clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
1233 <&cl 1148 <&clk IMX8MM_CLK_CSI1_ROOT>,
1234 <&cl 1149 <&clk IMX8MM_CLK_CSI1_PHY_REF>,
1235 <&cl 1150 <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
1236 clock-names = 1151 clock-names = "pclk", "wrap", "phy", "axi";
1237 power-domains 1152 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1238 status = "dis 1153 status = "disabled";
1239 1154
1240 ports { 1155 ports {
1241 #addr 1156 #address-cells = <1>;
1242 #size 1157 #size-cells = <0>;
1243 1158
1244 port@ 1159 port@0 {
1245 1160 reg = <0>;
1246 }; 1161 };
1247 1162
1248 port@ 1163 port@1 {
1249 1164 reg = <1>;
1250 1165
1251 1166 imx8mm_mipi_csi_out: endpoint {
1252 1167 remote-endpoint = <&csi_in>;
1253 1168 };
1254 }; 1169 };
1255 }; 1170 };
1256 }; 1171 };
1257 1172
1258 usbotg1: usb@32e40000 1173 usbotg1: usb@32e40000 {
1259 compatible = !! 1174 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1260 reg = <0x32e4 1175 reg = <0x32e40000 0x200>;
1261 interrupts = 1176 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cl 1177 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
>> 1178 clock-names = "usb1_ctrl_root_clk";
1263 assigned-cloc 1179 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1264 assigned-cloc 1180 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1265 phys = <&usbp 1181 phys = <&usbphynop1>;
1266 fsl,usbmisc = 1182 fsl,usbmisc = <&usbmisc1 0>;
1267 power-domains !! 1183 power-domains = <&pgc_otg1>;
1268 status = "dis 1184 status = "disabled";
1269 }; 1185 };
1270 1186
1271 usbmisc1: usbmisc@32e 1187 usbmisc1: usbmisc@32e40200 {
1272 compatible = !! 1188 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1273 <<
1274 #index-cells 1189 #index-cells = <1>;
1275 reg = <0x32e4 1190 reg = <0x32e40200 0x200>;
1276 }; 1191 };
1277 1192
1278 usbotg2: usb@32e50000 1193 usbotg2: usb@32e50000 {
1279 compatible = !! 1194 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1280 reg = <0x32e5 1195 reg = <0x32e50000 0x200>;
1281 interrupts = 1196 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1282 clocks = <&cl 1197 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
>> 1198 clock-names = "usb1_ctrl_root_clk";
1283 assigned-cloc 1199 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1284 assigned-cloc 1200 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1285 phys = <&usbp 1201 phys = <&usbphynop2>;
1286 fsl,usbmisc = 1202 fsl,usbmisc = <&usbmisc2 0>;
1287 power-domains !! 1203 power-domains = <&pgc_otg2>;
1288 status = "dis 1204 status = "disabled";
1289 }; 1205 };
1290 1206
1291 usbmisc2: usbmisc@32e 1207 usbmisc2: usbmisc@32e50200 {
1292 compatible = !! 1208 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1293 <<
1294 #index-cells 1209 #index-cells = <1>;
1295 reg = <0x32e5 1210 reg = <0x32e50200 0x200>;
1296 }; 1211 };
1297 1212
1298 pcie_phy: pcie-phy@32 1213 pcie_phy: pcie-phy@32f00000 {
1299 compatible = 1214 compatible = "fsl,imx8mm-pcie-phy";
1300 reg = <0x32f0 1215 reg = <0x32f00000 0x10000>;
1301 clocks = <&cl 1216 clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1302 clock-names = 1217 clock-names = "ref";
1303 assigned-cloc 1218 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1304 assigned-cloc 1219 assigned-clock-rates = <100000000>;
1305 assigned-cloc 1220 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1306 resets = <&sr 1221 resets = <&src IMX8MQ_RESET_PCIEPHY>;
1307 reset-names = 1222 reset-names = "pciephy";
1308 #phy-cells = 1223 #phy-cells = <0>;
1309 status = "dis 1224 status = "disabled";
1310 }; 1225 };
1311 }; 1226 };
1312 1227
1313 dma_apbh: dma-controller@3300 1228 dma_apbh: dma-controller@33000000 {
1314 compatible = "fsl,imx 1229 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1315 reg = <0x33000000 0x2 1230 reg = <0x33000000 0x2000>;
1316 interrupts = <GIC_SPI 1231 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 1232 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 1233 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 1234 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> 1235 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1320 #dma-cells = <1>; 1236 #dma-cells = <1>;
1321 dma-channels = <4>; 1237 dma-channels = <4>;
1322 clocks = <&clk IMX8MM 1238 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1323 }; 1239 };
1324 1240
1325 gpmi: nand-controller@3300200 !! 1241 gpmi: nand-controller@33002000{
1326 compatible = "fsl,imx 1242 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1327 #address-cells = <1>; 1243 #address-cells = <1>;
1328 #size-cells = <0>; !! 1244 #size-cells = <1>;
1329 reg = <0x33002000 0x2 1245 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1330 reg-names = "gpmi-nan 1246 reg-names = "gpmi-nand", "bch";
1331 interrupts = <GIC_SPI 1247 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1332 interrupt-names = "bc 1248 interrupt-names = "bch";
1333 clocks = <&clk IMX8MM 1249 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1334 <&clk IMX8MM 1250 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1335 clock-names = "gpmi_i 1251 clock-names = "gpmi_io", "gpmi_bch_apb";
1336 dmas = <&dma_apbh 0>; 1252 dmas = <&dma_apbh 0>;
1337 dma-names = "rx-tx"; 1253 dma-names = "rx-tx";
1338 status = "disabled"; 1254 status = "disabled";
1339 }; 1255 };
1340 1256
1341 pcie0: pcie@33800000 { 1257 pcie0: pcie@33800000 {
1342 compatible = "fsl,imx 1258 compatible = "fsl,imx8mm-pcie";
1343 reg = <0x33800000 0x4 1259 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
1344 reg-names = "dbi", "c 1260 reg-names = "dbi", "config";
1345 #address-cells = <3>; 1261 #address-cells = <3>;
1346 #size-cells = <2>; 1262 #size-cells = <2>;
1347 device_type = "pci"; 1263 device_type = "pci";
1348 bus-range = <0x00 0xf 1264 bus-range = <0x00 0xff>;
1349 ranges = <0x81000000 !! 1265 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
1350 <0x82000000 !! 1266 0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1351 num-lanes = <1>; 1267 num-lanes = <1>;
1352 num-viewport = <4>; 1268 num-viewport = <4>;
1353 interrupts = <GIC_SPI 1269 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1354 interrupt-names = "ms 1270 interrupt-names = "msi";
1355 #interrupt-cells = <1 1271 #interrupt-cells = <1>;
1356 interrupt-map-mask = 1272 interrupt-map-mask = <0 0 0 0x7>;
1357 interrupt-map = <0 0 1273 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1358 <0 0 1274 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
1359 <0 0 1275 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
1360 <0 0 1276 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1361 fsl,max-link-speed = 1277 fsl,max-link-speed = <2>;
1362 linux,pci-domain = <0 1278 linux,pci-domain = <0>;
1363 clocks = <&clk IMX8MM <<
1364 <&clk IMX8MM <<
1365 <&clk IMX8MM <<
1366 clock-names = "pcie", <<
1367 power-domains = <&pgc <<
1368 resets = <&src IMX8MQ <<
1369 <&src IMX8MQ <<
1370 reset-names = "apps", <<
1371 phys = <&pcie_phy>; <<
1372 phy-names = "pcie-phy <<
1373 status = "disabled"; <<
1374 }; <<
1375 <<
1376 pcie0_ep: pcie-ep@33800000 { <<
1377 compatible = "fsl,imx <<
1378 reg = <0x33800000 0x4 <<
1379 <0x18000000 0x8 <<
1380 reg-names = "dbi", "a <<
1381 num-lanes = <1>; <<
1382 interrupts = <GIC_SPI <<
1383 interrupt-names = "dm <<
1384 fsl,max-link-speed = <<
1385 clocks = <&clk IMX8MM <<
1386 <&clk IMX8MM <<
1387 <&clk IMX8MM <<
1388 clock-names = "pcie", <<
1389 power-domains = <&pgc 1279 power-domains = <&pgc_pcie>;
1390 resets = <&src IMX8MQ 1280 resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
1391 <&src IMX8MQ 1281 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
1392 reset-names = "apps", 1282 reset-names = "apps", "turnoff";
1393 phys = <&pcie_phy>; 1283 phys = <&pcie_phy>;
1394 phy-names = "pcie-phy 1284 phy-names = "pcie-phy";
1395 num-ib-windows = <4>; <<
1396 num-ob-windows = <4>; <<
1397 status = "disabled"; 1285 status = "disabled";
1398 }; 1286 };
1399 1287
1400 gpu_3d: gpu@38000000 { 1288 gpu_3d: gpu@38000000 {
1401 compatible = "vivante 1289 compatible = "vivante,gc";
1402 reg = <0x38000000 0x8 1290 reg = <0x38000000 0x8000>;
1403 interrupts = <GIC_SPI 1291 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1404 clocks = <&clk IMX8MM 1292 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1405 <&clk IMX8MM 1293 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1406 <&clk IMX8MM 1294 <&clk IMX8MM_CLK_GPU3D_ROOT>,
1407 <&clk IMX8MM 1295 <&clk IMX8MM_CLK_GPU3D_ROOT>;
1408 clock-names = "reg", 1296 clock-names = "reg", "bus", "core", "shader";
1409 assigned-clocks = <&c 1297 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1410 <&c 1298 <&clk IMX8MM_GPU_PLL_OUT>;
1411 assigned-clock-parent 1299 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1412 assigned-clock-rates !! 1300 assigned-clock-rates = <0>, <1000000000>;
1413 power-domains = <&pgc 1301 power-domains = <&pgc_gpu>;
1414 }; 1302 };
1415 1303
1416 gpu_2d: gpu@38008000 { 1304 gpu_2d: gpu@38008000 {
1417 compatible = "vivante 1305 compatible = "vivante,gc";
1418 reg = <0x38008000 0x8 1306 reg = <0x38008000 0x8000>;
1419 interrupts = <GIC_SPI 1307 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
1420 clocks = <&clk IMX8MM 1308 clocks = <&clk IMX8MM_CLK_GPU_AHB>,
1421 <&clk IMX8MM 1309 <&clk IMX8MM_CLK_GPU_BUS_ROOT>,
1422 <&clk IMX8MM 1310 <&clk IMX8MM_CLK_GPU2D_ROOT>;
1423 clock-names = "reg", 1311 clock-names = "reg", "bus", "core";
1424 assigned-clocks = <&c 1312 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1425 <&c 1313 <&clk IMX8MM_GPU_PLL_OUT>;
1426 assigned-clock-parent 1314 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1427 assigned-clock-rates !! 1315 assigned-clock-rates = <0>, <1000000000>;
1428 power-domains = <&pgc 1316 power-domains = <&pgc_gpu>;
1429 }; 1317 };
1430 1318
1431 vpu_g1: video-codec@38300000 1319 vpu_g1: video-codec@38300000 {
1432 compatible = "nxp,imx 1320 compatible = "nxp,imx8mm-vpu-g1";
1433 reg = <0x38300000 0x1 1321 reg = <0x38300000 0x10000>;
1434 interrupts = <GIC_SPI 1322 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1435 clocks = <&clk IMX8MM 1323 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>;
1436 power-domains = <&vpu 1324 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1437 }; 1325 };
1438 1326
1439 vpu_g2: video-codec@38310000 1327 vpu_g2: video-codec@38310000 {
1440 compatible = "nxp,imx 1328 compatible = "nxp,imx8mq-vpu-g2";
1441 reg = <0x38310000 0x1 1329 reg = <0x38310000 0x10000>;
1442 interrupts = <GIC_SPI 1330 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1443 clocks = <&clk IMX8MM 1331 clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>;
1444 power-domains = <&vpu 1332 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1445 }; 1333 };
1446 1334
1447 vpu_blk_ctrl: blk-ctrl@383300 1335 vpu_blk_ctrl: blk-ctrl@38330000 {
1448 compatible = "fsl,imx 1336 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1449 reg = <0x38330000 0x1 1337 reg = <0x38330000 0x100>;
1450 power-domains = <&pgc 1338 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1451 <&pgc 1339 <&pgc_vpu_g2>, <&pgc_vpu_h1>;
1452 power-domain-names = 1340 power-domain-names = "bus", "g1", "g2", "h1";
1453 clocks = <&clk IMX8MM 1341 clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>,
1454 <&clk IMX8MM 1342 <&clk IMX8MM_CLK_VPU_G2_ROOT>,
1455 <&clk IMX8MM 1343 <&clk IMX8MM_CLK_VPU_H1_ROOT>;
1456 clock-names = "g1", " 1344 clock-names = "g1", "g2", "h1";
1457 assigned-clocks = <&c 1345 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1458 <&c 1346 <&clk IMX8MM_CLK_VPU_G2>;
1459 assigned-clock-parent 1347 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1460 1348 <&clk IMX8MM_VPU_PLL_OUT>;
1461 assigned-clock-rates 1349 assigned-clock-rates = <600000000>,
1462 1350 <600000000>;
1463 #power-domain-cells = 1351 #power-domain-cells = <1>;
1464 }; 1352 };
1465 1353
1466 gic: interrupt-controller@388 1354 gic: interrupt-controller@38800000 {
1467 compatible = "arm,gic 1355 compatible = "arm,gic-v3";
1468 reg = <0x38800000 0x1 1356 reg = <0x38800000 0x10000>, /* GIC Dist */
1469 <0x38880000 0xc 1357 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1470 #interrupt-cells = <3 1358 #interrupt-cells = <3>;
1471 interrupt-controller; 1359 interrupt-controller;
1472 interrupts = <GIC_PPI 1360 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1473 }; 1361 };
1474 1362
1475 ddrc: memory-controller@3d400 1363 ddrc: memory-controller@3d400000 {
1476 compatible = "fsl,imx 1364 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1477 reg = <0x3d400000 0x4 1365 reg = <0x3d400000 0x400000>;
1478 clock-names = "core", 1366 clock-names = "core", "pll", "alt", "apb";
1479 clocks = <&clk IMX8MM 1367 clocks = <&clk IMX8MM_CLK_DRAM_CORE>,
1480 <&clk IMX8MM 1368 <&clk IMX8MM_DRAM_PLL>,
1481 <&clk IMX8MM 1369 <&clk IMX8MM_CLK_DRAM_ALT>,
1482 <&clk IMX8MM 1370 <&clk IMX8MM_CLK_DRAM_APB>;
1483 }; 1371 };
1484 1372
1485 ddr-pmu@3d800000 { 1373 ddr-pmu@3d800000 {
1486 compatible = "fsl,imx 1374 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1487 reg = <0x3d800000 0x4 1375 reg = <0x3d800000 0x400000>;
1488 interrupts = <GIC_SPI 1376 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1489 }; 1377 };
1490 }; 1378 };
1491 }; 1379 };
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