1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mm-clock.h> 6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h> <<
11 #include <dt-bindings/reset/imx8mq-reset.h> <<
12 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/thermal/thermal.h>
13 11
14 #include "imx8mm-pinfunc.h" 12 #include "imx8mm-pinfunc.h"
15 13
16 / { 14 / {
>> 15 compatible = "fsl,imx8mm";
17 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
18 #address-cells = <2>; 17 #address-cells = <2>;
19 #size-cells = <2>; 18 #size-cells = <2>;
20 19
21 aliases { 20 aliases {
22 ethernet0 = &fec1; 21 ethernet0 = &fec1;
23 gpio0 = &gpio1; <<
24 gpio1 = &gpio2; <<
25 gpio2 = &gpio3; <<
26 gpio3 = &gpio4; <<
27 gpio4 = &gpio5; <<
28 i2c0 = &i2c1; 22 i2c0 = &i2c1;
29 i2c1 = &i2c2; 23 i2c1 = &i2c2;
30 i2c2 = &i2c3; 24 i2c2 = &i2c3;
31 i2c3 = &i2c4; 25 i2c3 = &i2c4;
32 mmc0 = &usdhc1; <<
33 mmc1 = &usdhc2; <<
34 mmc2 = &usdhc3; <<
35 serial0 = &uart1; 26 serial0 = &uart1;
36 serial1 = &uart2; 27 serial1 = &uart2;
37 serial2 = &uart3; 28 serial2 = &uart3;
38 serial3 = &uart4; 29 serial3 = &uart4;
39 spi0 = &ecspi1; 30 spi0 = &ecspi1;
40 spi1 = &ecspi2; 31 spi1 = &ecspi2;
41 spi2 = &ecspi3; 32 spi2 = &ecspi3;
>> 33 mmc0 = &usdhc1;
>> 34 mmc1 = &usdhc2;
>> 35 mmc2 = &usdhc3;
>> 36 gpio0 = &gpio1;
>> 37 gpio1 = &gpio2;
>> 38 gpio2 = &gpio3;
>> 39 gpio3 = &gpio4;
>> 40 gpio4 = &gpio5;
42 }; 41 };
43 42
44 cpus { 43 cpus {
45 #address-cells = <1>; 44 #address-cells = <1>;
46 #size-cells = <0>; 45 #size-cells = <0>;
47 46
48 idle-states { 47 idle-states {
49 entry-method = "psci"; 48 entry-method = "psci";
50 49
51 cpu_pd_wait: cpu-pd-wa 50 cpu_pd_wait: cpu-pd-wait {
52 compatible = " 51 compatible = "arm,idle-state";
53 arm,psci-suspe 52 arm,psci-suspend-param = <0x0010033>;
54 local-timer-st 53 local-timer-stop;
55 entry-latency- 54 entry-latency-us = <1000>;
56 exit-latency-u 55 exit-latency-us = <700>;
57 min-residency- 56 min-residency-us = <2700>;
58 }; 57 };
59 }; 58 };
60 59
61 A53_0: cpu@0 { 60 A53_0: cpu@0 {
62 device_type = "cpu"; 61 device_type = "cpu";
63 compatible = "arm,cort 62 compatible = "arm,cortex-a53";
64 reg = <0x0>; 63 reg = <0x0>;
65 clock-latency = <61036 64 clock-latency = <61036>; /* two CLK32 periods */
66 clocks = <&clk IMX8MM_ 65 clocks = <&clk IMX8MM_CLK_ARM>;
67 enable-method = "psci" 66 enable-method = "psci";
68 i-cache-size = <0x8000 <<
69 i-cache-line-size = <6 <<
70 i-cache-sets = <256>; <<
71 d-cache-size = <0x8000 <<
72 d-cache-line-size = <6 <<
73 d-cache-sets = <128>; <<
74 next-level-cache = <&A 67 next-level-cache = <&A53_L2>;
75 operating-points-v2 = 68 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_sp 69 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "sp 70 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cp 71 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>; <<
80 }; 72 };
81 73
82 A53_1: cpu@1 { 74 A53_1: cpu@1 {
83 device_type = "cpu"; 75 device_type = "cpu";
84 compatible = "arm,cort 76 compatible = "arm,cortex-a53";
85 reg = <0x1>; 77 reg = <0x1>;
86 clock-latency = <61036 78 clock-latency = <61036>; /* two CLK32 periods */
87 clocks = <&clk IMX8MM_ 79 clocks = <&clk IMX8MM_CLK_ARM>;
88 enable-method = "psci" 80 enable-method = "psci";
89 i-cache-size = <0x8000 <<
90 i-cache-line-size = <6 <<
91 i-cache-sets = <256>; <<
92 d-cache-size = <0x8000 <<
93 d-cache-line-size = <6 <<
94 d-cache-sets = <128>; <<
95 next-level-cache = <&A 81 next-level-cache = <&A53_L2>;
96 operating-points-v2 = 82 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cp 83 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>; <<
99 }; 84 };
100 85
101 A53_2: cpu@2 { 86 A53_2: cpu@2 {
102 device_type = "cpu"; 87 device_type = "cpu";
103 compatible = "arm,cort 88 compatible = "arm,cortex-a53";
104 reg = <0x2>; 89 reg = <0x2>;
105 clock-latency = <61036 90 clock-latency = <61036>; /* two CLK32 periods */
106 clocks = <&clk IMX8MM_ 91 clocks = <&clk IMX8MM_CLK_ARM>;
107 enable-method = "psci" 92 enable-method = "psci";
108 i-cache-size = <0x8000 <<
109 i-cache-line-size = <6 <<
110 i-cache-sets = <256>; <<
111 d-cache-size = <0x8000 <<
112 d-cache-line-size = <6 <<
113 d-cache-sets = <128>; <<
114 next-level-cache = <&A 93 next-level-cache = <&A53_L2>;
115 operating-points-v2 = 94 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cp 95 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>; <<
118 }; 96 };
119 97
120 A53_3: cpu@3 { 98 A53_3: cpu@3 {
121 device_type = "cpu"; 99 device_type = "cpu";
122 compatible = "arm,cort 100 compatible = "arm,cortex-a53";
123 reg = <0x3>; 101 reg = <0x3>;
124 clock-latency = <61036 102 clock-latency = <61036>; /* two CLK32 periods */
125 clocks = <&clk IMX8MM_ 103 clocks = <&clk IMX8MM_CLK_ARM>;
126 enable-method = "psci" 104 enable-method = "psci";
127 i-cache-size = <0x8000 <<
128 i-cache-line-size = <6 <<
129 i-cache-sets = <256>; <<
130 d-cache-size = <0x8000 <<
131 d-cache-line-size = <6 <<
132 d-cache-sets = <128>; <<
133 next-level-cache = <&A 105 next-level-cache = <&A53_L2>;
134 operating-points-v2 = 106 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cp 107 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>; <<
137 }; 108 };
138 109
139 A53_L2: l2-cache0 { 110 A53_L2: l2-cache0 {
140 compatible = "cache"; 111 compatible = "cache";
141 cache-level = <2>; <<
142 cache-unified; <<
143 cache-size = <0x80000> <<
144 cache-line-size = <64> <<
145 cache-sets = <512>; <<
146 }; 112 };
147 }; 113 };
148 114
149 a53_opp_table: opp-table { 115 a53_opp_table: opp-table {
150 compatible = "operating-points 116 compatible = "operating-points-v2";
151 opp-shared; 117 opp-shared;
152 118
153 opp-1200000000 { 119 opp-1200000000 {
154 opp-hz = /bits/ 64 <12 120 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <85000 121 opp-microvolt = <850000>;
156 opp-supported-hw = <0x 122 opp-supported-hw = <0xe>, <0x7>;
157 clock-latency-ns = <15 123 clock-latency-ns = <150000>;
158 opp-suspend; 124 opp-suspend;
159 }; 125 };
160 126
161 opp-1600000000 { 127 opp-1600000000 {
162 opp-hz = /bits/ 64 <16 128 opp-hz = /bits/ 64 <1600000000>;
163 opp-microvolt = <95000 129 opp-microvolt = <950000>;
164 opp-supported-hw = <0x 130 opp-supported-hw = <0xc>, <0x7>;
165 clock-latency-ns = <15 131 clock-latency-ns = <150000>;
166 opp-suspend; 132 opp-suspend;
167 }; 133 };
168 134
169 opp-1800000000 { 135 opp-1800000000 {
170 opp-hz = /bits/ 64 <18 136 opp-hz = /bits/ 64 <1800000000>;
171 opp-microvolt = <10000 137 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x 138 opp-supported-hw = <0x8>, <0x3>;
173 clock-latency-ns = <15 139 clock-latency-ns = <150000>;
174 opp-suspend; 140 opp-suspend;
175 }; 141 };
176 }; 142 };
177 143
>> 144 memory@40000000 {
>> 145 device_type = "memory";
>> 146 reg = <0x0 0x40000000 0 0x80000000>;
>> 147 };
>> 148
178 osc_32k: clock-osc-32k { 149 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock"; 150 compatible = "fixed-clock";
180 #clock-cells = <0>; 151 #clock-cells = <0>;
181 clock-frequency = <32768>; 152 clock-frequency = <32768>;
182 clock-output-names = "osc_32k" 153 clock-output-names = "osc_32k";
183 }; 154 };
184 155
185 osc_24m: clock-osc-24m { 156 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock"; 157 compatible = "fixed-clock";
187 #clock-cells = <0>; 158 #clock-cells = <0>;
188 clock-frequency = <24000000>; 159 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m" 160 clock-output-names = "osc_24m";
190 }; 161 };
191 162
192 clk_ext1: clock-ext1 { 163 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock"; 164 compatible = "fixed-clock";
194 #clock-cells = <0>; 165 #clock-cells = <0>;
195 clock-frequency = <133000000>; 166 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1 167 clock-output-names = "clk_ext1";
197 }; 168 };
198 169
199 clk_ext2: clock-ext2 { 170 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock"; 171 compatible = "fixed-clock";
201 #clock-cells = <0>; 172 #clock-cells = <0>;
202 clock-frequency = <133000000>; 173 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2 174 clock-output-names = "clk_ext2";
204 }; 175 };
205 176
206 clk_ext3: clock-ext3 { 177 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock"; 178 compatible = "fixed-clock";
208 #clock-cells = <0>; 179 #clock-cells = <0>;
209 clock-frequency = <133000000>; 180 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3 181 clock-output-names = "clk_ext3";
211 }; 182 };
212 183
213 clk_ext4: clock-ext4 { 184 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock"; 185 compatible = "fixed-clock";
215 #clock-cells = <0>; 186 #clock-cells = <0>;
216 clock-frequency = <133000000>; !! 187 clock-frequency= <133000000>;
217 clock-output-names = "clk_ext4 188 clock-output-names = "clk_ext4";
218 }; 189 };
219 190
220 psci { 191 psci {
221 compatible = "arm,psci-1.0"; 192 compatible = "arm,psci-1.0";
222 method = "smc"; 193 method = "smc";
223 }; 194 };
224 195
225 pmu { 196 pmu {
226 compatible = "arm,cortex-a53-p !! 197 compatible = "arm,armv8-pmuv3";
227 interrupts = <GIC_PPI 7 198 interrupts = <GIC_PPI 7
228 (GIC_CPU_MASK_SIM !! 199 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>;
>> 200 interrupt-affinity = <&A53_0>, <&A53_1>, <&A53_2>, <&A53_3>;
229 }; 201 };
230 202
231 timer { 203 timer {
232 compatible = "arm,armv8-timer" 204 compatible = "arm,armv8-timer";
233 interrupts = <GIC_PPI 13 (GIC_ !! 205 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
234 <GIC_PPI 14 (GIC_ !! 206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
235 <GIC_PPI 11 (GIC_ !! 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
236 <GIC_PPI 10 (GIC_ !! 208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
237 clock-frequency = <8000000>; 209 clock-frequency = <8000000>;
238 arm,no-tick-in-suspend; 210 arm,no-tick-in-suspend;
239 }; 211 };
240 212
241 thermal-zones { <<
242 cpu-thermal { <<
243 polling-delay-passive <<
244 polling-delay = <2000> <<
245 thermal-sensors = <&tm <<
246 trips { <<
247 cpu_alert0: tr <<
248 temper <<
249 hyster <<
250 type = <<
251 }; <<
252 <<
253 cpu_crit0: tri <<
254 temper <<
255 hyster <<
256 type = <<
257 }; <<
258 }; <<
259 <<
260 cooling-maps { <<
261 map0 { <<
262 trip = <<
263 coolin <<
264 <<
265 <<
266 <<
267 <<
268 }; <<
269 }; <<
270 }; <<
271 }; <<
272 <<
273 usbphynop1: usbphynop1 { 213 usbphynop1: usbphynop1 {
274 #phy-cells = <0>; <<
275 compatible = "usb-nop-xceiv"; 214 compatible = "usb-nop-xceiv";
276 clocks = <&clk IMX8MM_CLK_USB_ 215 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
277 assigned-clocks = <&clk IMX8MM 216 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
278 assigned-clock-parents = <&clk 217 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
279 clock-names = "main_clk"; 218 clock-names = "main_clk";
280 power-domains = <&pgc_otg1>; <<
281 }; 219 };
282 220
283 usbphynop2: usbphynop2 { 221 usbphynop2: usbphynop2 {
284 #phy-cells = <0>; <<
285 compatible = "usb-nop-xceiv"; 222 compatible = "usb-nop-xceiv";
286 clocks = <&clk IMX8MM_CLK_USB_ 223 clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
287 assigned-clocks = <&clk IMX8MM 224 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
288 assigned-clock-parents = <&clk 225 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
289 clock-names = "main_clk"; 226 clock-names = "main_clk";
290 power-domains = <&pgc_otg2>; <<
291 }; 227 };
292 228
293 soc: soc@0 { !! 229 soc@0 {
294 compatible = "fsl,imx8mm-soc", !! 230 compatible = "simple-bus";
295 #address-cells = <1>; 231 #address-cells = <1>;
296 #size-cells = <1>; 232 #size-cells = <1>;
297 ranges = <0x0 0x0 0x0 0x3e0000 233 ranges = <0x0 0x0 0x0 0x3e000000>;
298 dma-ranges = <0x40000000 0x0 0 <<
299 nvmem-cells = <&imx8mm_uid>; <<
300 nvmem-cell-names = "soc_unique <<
301 234
302 aips1: bus@30000000 { 235 aips1: bus@30000000 {
303 compatible = "fsl,aips 236 compatible = "fsl,aips-bus", "simple-bus";
304 reg = <0x30000000 0x40 <<
305 #address-cells = <1>; 237 #address-cells = <1>;
306 #size-cells = <1>; 238 #size-cells = <1>;
307 ranges = <0x30000000 0 239 ranges = <0x30000000 0x30000000 0x400000>;
308 240
309 spba2: spba-bus@300000 !! 241 sai1: sai@30010000 {
310 compatible = " !! 242 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
311 #address-cells !! 243 reg = <0x30010000 0x10000>;
312 #size-cells = !! 244 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
313 reg = <0x30000 !! 245 clocks = <&clk IMX8MM_CLK_SAI1_IPG>,
314 ranges; !! 246 <&clk IMX8MM_CLK_SAI1_ROOT>,
315 !! 247 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
316 sai1: sai@3001 !! 248 clock-names = "bus", "mclk1", "mclk2", "mclk3";
317 #sound !! 249 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
318 compat !! 250 dma-names = "rx", "tx";
319 reg = !! 251 status = "disabled";
320 interr !! 252 };
321 clocks <<
322 <<
323 <<
324 clock- <<
325 dmas = <<
326 dma-na <<
327 status <<
328 }; <<
329 <<
330 sai2: sai@3002 <<
331 #sound <<
332 compat <<
333 reg = <<
334 interr <<
335 clocks <<
336 <<
337 <<
338 clock- <<
339 dmas = <<
340 dma-na <<
341 status <<
342 }; <<
343 <<
344 sai3: sai@3003 <<
345 #sound <<
346 compat <<
347 reg = <<
348 interr <<
349 clocks <<
350 <<
351 <<
352 clock- <<
353 dmas = <<
354 dma-na <<
355 status <<
356 }; <<
357 253
358 sai5: sai@3005 !! 254 sai2: sai@30020000 {
359 #sound !! 255 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
360 compat !! 256 reg = <0x30020000 0x10000>;
361 reg = !! 257 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
362 interr !! 258 clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
363 clocks !! 259 <&clk IMX8MM_CLK_SAI2_ROOT>,
364 !! 260 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
365 !! 261 clock-names = "bus", "mclk1", "mclk2", "mclk3";
366 clock- !! 262 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
367 dmas = !! 263 dma-names = "rx", "tx";
368 dma-na !! 264 status = "disabled";
369 status !! 265 };
370 }; <<
371 266
372 sai6: sai@3006 !! 267 sai3: sai@30030000 {
373 #sound !! 268 #sound-dai-cells = <0>;
374 compat !! 269 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
375 reg = !! 270 reg = <0x30030000 0x10000>;
376 interr !! 271 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
377 clocks !! 272 clocks = <&clk IMX8MM_CLK_SAI3_IPG>,
378 !! 273 <&clk IMX8MM_CLK_SAI3_ROOT>,
379 !! 274 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
380 clock- !! 275 clock-names = "bus", "mclk1", "mclk2", "mclk3";
381 dmas = !! 276 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
382 dma-na !! 277 dma-names = "rx", "tx";
383 status !! 278 status = "disabled";
384 }; !! 279 };
385 280
386 micfil: audio- !! 281 sai5: sai@30050000 {
387 compat !! 282 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
388 reg = !! 283 reg = <0x30050000 0x10000>;
389 interr !! 284 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
390 !! 285 clocks = <&clk IMX8MM_CLK_SAI5_IPG>,
391 !! 286 <&clk IMX8MM_CLK_SAI5_ROOT>,
392 !! 287 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
393 clocks !! 288 clock-names = "bus", "mclk1", "mclk2", "mclk3";
394 !! 289 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
395 !! 290 dma-names = "rx", "tx";
396 !! 291 status = "disabled";
397 !! 292 };
398 clock- <<
399 <<
400 dmas = <<
401 dma-na <<
402 #sound <<
403 status <<
404 }; <<
405 293
406 spdif1: spdif@ !! 294 sai6: sai@30060000 {
407 compat !! 295 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
408 reg = !! 296 reg = <0x30060000 0x10000>;
409 interr !! 297 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
410 clocks !! 298 clocks = <&clk IMX8MM_CLK_SAI6_IPG>,
411 !! 299 <&clk IMX8MM_CLK_SAI6_ROOT>,
412 !! 300 <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
413 !! 301 clock-names = "bus", "mclk1", "mclk2", "mclk3";
414 !! 302 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
415 !! 303 dma-names = "rx", "tx";
416 !! 304 status = "disabled";
417 <<
418 <<
419 <<
420 clock- <<
421 <<
422 <<
423 <<
424 <<
425 dmas = <<
426 dma-na <<
427 status <<
428 }; <<
429 }; 305 };
430 306
431 gpio1: gpio@30200000 { 307 gpio1: gpio@30200000 {
432 compatible = " 308 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
433 reg = <0x30200 309 reg = <0x30200000 0x10000>;
434 interrupts = < 310 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
435 < 311 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&clk 312 clocks = <&clk IMX8MM_CLK_GPIO1_ROOT>;
437 gpio-controlle 313 gpio-controller;
438 #gpio-cells = 314 #gpio-cells = <2>;
439 interrupt-cont 315 interrupt-controller;
440 #interrupt-cel 316 #interrupt-cells = <2>;
441 gpio-ranges = 317 gpio-ranges = <&iomuxc 0 10 30>;
442 }; 318 };
443 319
444 gpio2: gpio@30210000 { 320 gpio2: gpio@30210000 {
445 compatible = " 321 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
446 reg = <0x30210 322 reg = <0x30210000 0x10000>;
447 interrupts = < 323 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
448 < 324 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
449 clocks = <&clk 325 clocks = <&clk IMX8MM_CLK_GPIO2_ROOT>;
450 gpio-controlle 326 gpio-controller;
451 #gpio-cells = 327 #gpio-cells = <2>;
452 interrupt-cont 328 interrupt-controller;
453 #interrupt-cel 329 #interrupt-cells = <2>;
454 gpio-ranges = 330 gpio-ranges = <&iomuxc 0 40 21>;
455 }; 331 };
456 332
457 gpio3: gpio@30220000 { 333 gpio3: gpio@30220000 {
458 compatible = " 334 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
459 reg = <0x30220 335 reg = <0x30220000 0x10000>;
460 interrupts = < 336 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
461 < 337 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
462 clocks = <&clk 338 clocks = <&clk IMX8MM_CLK_GPIO3_ROOT>;
463 gpio-controlle 339 gpio-controller;
464 #gpio-cells = 340 #gpio-cells = <2>;
465 interrupt-cont 341 interrupt-controller;
466 #interrupt-cel 342 #interrupt-cells = <2>;
467 gpio-ranges = 343 gpio-ranges = <&iomuxc 0 61 26>;
468 }; 344 };
469 345
470 gpio4: gpio@30230000 { 346 gpio4: gpio@30230000 {
471 compatible = " 347 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
472 reg = <0x30230 348 reg = <0x30230000 0x10000>;
473 interrupts = < 349 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
474 < 350 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&clk 351 clocks = <&clk IMX8MM_CLK_GPIO4_ROOT>;
476 gpio-controlle 352 gpio-controller;
477 #gpio-cells = 353 #gpio-cells = <2>;
478 interrupt-cont 354 interrupt-controller;
479 #interrupt-cel 355 #interrupt-cells = <2>;
480 gpio-ranges = 356 gpio-ranges = <&iomuxc 0 87 32>;
481 }; 357 };
482 358
483 gpio5: gpio@30240000 { 359 gpio5: gpio@30240000 {
484 compatible = " 360 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
485 reg = <0x30240 361 reg = <0x30240000 0x10000>;
486 interrupts = < 362 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
487 < 363 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
488 clocks = <&clk 364 clocks = <&clk IMX8MM_CLK_GPIO5_ROOT>;
489 gpio-controlle 365 gpio-controller;
490 #gpio-cells = 366 #gpio-cells = <2>;
491 interrupt-cont 367 interrupt-controller;
492 #interrupt-cel 368 #interrupt-cells = <2>;
493 gpio-ranges = 369 gpio-ranges = <&iomuxc 0 119 30>;
494 }; 370 };
495 371
496 tmu: tmu@30260000 { <<
497 compatible = " <<
498 reg = <0x30260 <<
499 clocks = <&clk <<
500 nvmem-cells = <<
501 nvmem-cell-nam <<
502 #thermal-senso <<
503 }; <<
504 <<
505 wdog1: watchdog@302800 372 wdog1: watchdog@30280000 {
506 compatible = " 373 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
507 reg = <0x30280 374 reg = <0x30280000 0x10000>;
508 interrupts = < 375 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
509 clocks = <&clk 376 clocks = <&clk IMX8MM_CLK_WDOG1_ROOT>;
510 status = "disa 377 status = "disabled";
511 }; 378 };
512 379
513 wdog2: watchdog@302900 380 wdog2: watchdog@30290000 {
514 compatible = " 381 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
515 reg = <0x30290 382 reg = <0x30290000 0x10000>;
516 interrupts = < 383 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&clk 384 clocks = <&clk IMX8MM_CLK_WDOG2_ROOT>;
518 status = "disa 385 status = "disabled";
519 }; 386 };
520 387
521 wdog3: watchdog@302a00 388 wdog3: watchdog@302a0000 {
522 compatible = " 389 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
523 reg = <0x302a0 390 reg = <0x302a0000 0x10000>;
524 interrupts = < 391 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&clk 392 clocks = <&clk IMX8MM_CLK_WDOG3_ROOT>;
526 status = "disa 393 status = "disabled";
527 }; 394 };
528 395
529 sdma2: dma-controller@ 396 sdma2: dma-controller@302c0000 {
530 compatible = " 397 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
531 reg = <0x302c0 398 reg = <0x302c0000 0x10000>;
532 interrupts = < 399 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&clk 400 clocks = <&clk IMX8MM_CLK_SDMA2_ROOT>,
534 <&clk 401 <&clk IMX8MM_CLK_SDMA2_ROOT>;
535 clock-names = 402 clock-names = "ipg", "ahb";
536 #dma-cells = < 403 #dma-cells = <3>;
537 fsl,sdma-ram-s 404 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
538 }; 405 };
539 406
540 sdma3: dma-controller@ 407 sdma3: dma-controller@302b0000 {
541 compatible = " 408 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
542 reg = <0x302b0 409 reg = <0x302b0000 0x10000>;
543 interrupts = < 410 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&clk 411 clocks = <&clk IMX8MM_CLK_SDMA3_ROOT>,
545 <&clk IMX8MM_ 412 <&clk IMX8MM_CLK_SDMA3_ROOT>;
546 clock-names = 413 clock-names = "ipg", "ahb";
547 #dma-cells = < 414 #dma-cells = <3>;
548 fsl,sdma-ram-s 415 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
549 }; 416 };
550 417
551 iomuxc: pinctrl@303300 418 iomuxc: pinctrl@30330000 {
552 compatible = " 419 compatible = "fsl,imx8mm-iomuxc";
553 reg = <0x30330 420 reg = <0x30330000 0x10000>;
554 }; 421 };
555 422
556 gpr: syscon@30340000 { !! 423 gpr: iomuxc-gpr@30340000 {
557 compatible = " 424 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
558 reg = <0x30340 425 reg = <0x30340000 0x10000>;
559 }; 426 };
560 427
561 ocotp: efuse@30350000 !! 428 ocotp: ocotp-ctrl@30350000 {
562 compatible = " !! 429 compatible = "fsl,imx8mm-ocotp", "fsl,imx7d-ocotp", "syscon";
563 reg = <0x30350 430 reg = <0x30350000 0x10000>;
564 clocks = <&clk 431 clocks = <&clk IMX8MM_CLK_OCOTP_ROOT>;
565 /* For nvmem s 432 /* For nvmem subnodes */
566 #address-cells 433 #address-cells = <1>;
567 #size-cells = 434 #size-cells = <1>;
568 435
569 /* !! 436 cpu_speed_grade: speed-grade@10 {
570 * The registe <<
571 * Fusemap Des <<
572 * Assuming <<
573 * reg = <AD <<
574 * then <<
575 * Fuse Addr <<
576 * Note that i <<
577 * each subseq <<
578 * +0x10 in Fu <<
579 * reg = <0x4 <<
580 * 0x420). <<
581 */ <<
582 imx8mm_uid: un <<
583 reg = <<
584 }; <<
585 <<
586 cpu_speed_grad <<
587 reg = 437 reg = <0x10 4>;
588 }; 438 };
589 <<
590 tmu_calib: cal <<
591 reg = <<
592 }; <<
593 <<
594 fec_mac_addres <<
595 reg = <<
596 }; <<
597 }; 439 };
598 440
599 anatop: clock-controll !! 441 anatop: anatop@30360000 {
600 compatible = " !! 442 compatible = "fsl,imx8mm-anatop", "syscon", "simple-bus";
601 reg = <0x30360 443 reg = <0x30360000 0x10000>;
602 #clock-cells = <<
603 }; 444 };
604 445
605 snvs: snvs@30370000 { 446 snvs: snvs@30370000 {
606 compatible = " 447 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
607 reg = <0x30370 448 reg = <0x30370000 0x10000>;
608 449
609 snvs_rtc: snvs 450 snvs_rtc: snvs-rtc-lp {
610 compat 451 compatible = "fsl,sec-v4.0-mon-rtc-lp";
611 regmap 452 regmap = <&snvs>;
612 offset 453 offset = <0x34>;
613 interr 454 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
614 455 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
615 clocks 456 clocks = <&clk IMX8MM_CLK_SNVS_ROOT>;
616 clock- 457 clock-names = "snvs-rtc";
617 }; 458 };
618 459
619 snvs_pwrkey: s 460 snvs_pwrkey: snvs-powerkey {
620 compat 461 compatible = "fsl,sec-v4.0-pwrkey";
621 regmap 462 regmap = <&snvs>;
622 interr 463 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
623 clocks <<
624 clock- <<
625 linux, 464 linux,keycode = <KEY_POWER>;
626 wakeup 465 wakeup-source;
627 status 466 status = "disabled";
628 }; 467 };
629 <<
630 snvs_lpgpr: sn <<
631 compat <<
632 <<
633 }; <<
634 }; 468 };
635 469
636 clk: clock-controller@ 470 clk: clock-controller@30380000 {
637 compatible = " 471 compatible = "fsl,imx8mm-ccm";
638 reg = <0x30380 472 reg = <0x30380000 0x10000>;
639 interrupts = < <<
640 < <<
641 #clock-cells = 473 #clock-cells = <1>;
642 clocks = <&osc 474 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
643 <&clk 475 <&clk_ext3>, <&clk_ext4>;
644 clock-names = 476 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
645 477 "clk_ext3", "clk_ext4";
646 assigned-clock !! 478 assigned-clocks = <&clk IMX8MM_CLK_NOC>,
647 <<
648 <<
649 479 <&clk IMX8MM_CLK_AUDIO_AHB>,
650 480 <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>,
651 481 <&clk IMX8MM_SYS_PLL3>,
652 !! 482 <&clk IMX8MM_VIDEO_PLL1>,
653 assigned-clock !! 483 <&clk IMX8MM_AUDIO_PLL1>,
654 !! 484 <&clk IMX8MM_AUDIO_PLL2>;
655 !! 485 assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>,
656 486 <&clk IMX8MM_SYS_PLL1_800M>;
657 assigned-clock !! 487 assigned-clock-rates = <0>,
658 488 <400000000>,
659 489 <400000000>,
660 490 <750000000>,
661 !! 491 <594000000>,
>> 492 <393216000>,
>> 493 <361267200>;
662 }; 494 };
663 495
664 src: reset-controller@ 496 src: reset-controller@30390000 {
665 compatible = " 497 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
666 reg = <0x30390 498 reg = <0x30390000 0x10000>;
667 interrupts = < 499 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
668 #reset-cells = 500 #reset-cells = <1>;
669 }; 501 };
670 <<
671 gpc: gpc@303a0000 { <<
672 compatible = " <<
673 reg = <0x303a0 <<
674 interrupts = < <<
675 interrupt-pare <<
676 interrupt-cont <<
677 #interrupt-cel <<
678 <<
679 pgc { <<
680 #addre <<
681 #size- <<
682 <<
683 pgc_hs <<
684 <<
685 <<
686 <<
687 <<
688 <<
689 }; <<
690 <<
691 pgc_pc <<
692 <<
693 <<
694 <<
695 <<
696 }; <<
697 <<
698 pgc_ot <<
699 <<
700 <<
701 }; <<
702 <<
703 pgc_ot <<
704 <<
705 <<
706 }; <<
707 <<
708 pgc_gp <<
709 <<
710 <<
711 <<
712 <<
713 <<
714 <<
715 <<
716 <<
717 <<
718 }; <<
719 <<
720 pgc_gp <<
721 <<
722 <<
723 <<
724 <<
725 <<
726 <<
727 <<
728 <<
729 }; <<
730 <<
731 pgc_vp <<
732 <<
733 <<
734 <<
735 <<
736 <<
737 }; <<
738 <<
739 pgc_vp <<
740 <<
741 <<
742 }; <<
743 <<
744 pgc_vp <<
745 <<
746 <<
747 }; <<
748 <<
749 pgc_vp <<
750 <<
751 <<
752 }; <<
753 <<
754 pgc_di <<
755 <<
756 <<
757 <<
758 <<
759 <<
760 <<
761 <<
762 <<
763 <<
764 }; <<
765 <<
766 pgc_mi <<
767 <<
768 <<
769 }; <<
770 }; <<
771 }; <<
772 }; 502 };
773 503
774 aips2: bus@30400000 { 504 aips2: bus@30400000 {
775 compatible = "fsl,aips 505 compatible = "fsl,aips-bus", "simple-bus";
776 reg = <0x30400000 0x40 <<
777 #address-cells = <1>; 506 #address-cells = <1>;
778 #size-cells = <1>; 507 #size-cells = <1>;
779 ranges = <0x30400000 0 508 ranges = <0x30400000 0x30400000 0x400000>;
780 509
781 pwm1: pwm@30660000 { 510 pwm1: pwm@30660000 {
782 compatible = " 511 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
783 reg = <0x30660 512 reg = <0x30660000 0x10000>;
784 interrupts = < 513 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&clk 514 clocks = <&clk IMX8MM_CLK_PWM1_ROOT>,
786 <&clk 515 <&clk IMX8MM_CLK_PWM1_ROOT>;
787 clock-names = 516 clock-names = "ipg", "per";
788 #pwm-cells = < !! 517 #pwm-cells = <2>;
789 status = "disa 518 status = "disabled";
790 }; 519 };
791 520
792 pwm2: pwm@30670000 { 521 pwm2: pwm@30670000 {
793 compatible = " 522 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
794 reg = <0x30670 523 reg = <0x30670000 0x10000>;
795 interrupts = < 524 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&clk 525 clocks = <&clk IMX8MM_CLK_PWM2_ROOT>,
797 <&clk 526 <&clk IMX8MM_CLK_PWM2_ROOT>;
798 clock-names = 527 clock-names = "ipg", "per";
799 #pwm-cells = < !! 528 #pwm-cells = <2>;
800 status = "disa 529 status = "disabled";
801 }; 530 };
802 531
803 pwm3: pwm@30680000 { 532 pwm3: pwm@30680000 {
804 compatible = " 533 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
805 reg = <0x30680 534 reg = <0x30680000 0x10000>;
806 interrupts = < 535 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
807 clocks = <&clk 536 clocks = <&clk IMX8MM_CLK_PWM3_ROOT>,
808 <&clk 537 <&clk IMX8MM_CLK_PWM3_ROOT>;
809 clock-names = 538 clock-names = "ipg", "per";
810 #pwm-cells = < !! 539 #pwm-cells = <2>;
811 status = "disa 540 status = "disabled";
812 }; 541 };
813 542
814 pwm4: pwm@30690000 { 543 pwm4: pwm@30690000 {
815 compatible = " 544 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
816 reg = <0x30690 545 reg = <0x30690000 0x10000>;
817 interrupts = < 546 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
818 clocks = <&clk 547 clocks = <&clk IMX8MM_CLK_PWM4_ROOT>,
819 <&clk 548 <&clk IMX8MM_CLK_PWM4_ROOT>;
820 clock-names = 549 clock-names = "ipg", "per";
821 #pwm-cells = < !! 550 #pwm-cells = <2>;
822 status = "disa 551 status = "disabled";
823 }; 552 };
824 553
825 system_counter: timer@ 554 system_counter: timer@306a0000 {
826 compatible = " 555 compatible = "nxp,sysctr-timer";
827 reg = <0x306a0 556 reg = <0x306a0000 0x20000>;
828 interrupts = < 557 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&osc 558 clocks = <&osc_24m>;
830 clock-names = 559 clock-names = "per";
831 }; 560 };
832 }; 561 };
833 562
834 aips3: bus@30800000 { 563 aips3: bus@30800000 {
835 compatible = "fsl,aips 564 compatible = "fsl,aips-bus", "simple-bus";
836 reg = <0x30800000 0x40 <<
837 #address-cells = <1>; 565 #address-cells = <1>;
838 #size-cells = <1>; 566 #size-cells = <1>;
839 ranges = <0x30800000 0 !! 567 ranges = <0x30800000 0x30800000 0x400000>;
840 <0x8000000 0x <<
841 568
842 spba1: spba-bus@308000 !! 569 ecspi1: spi@30820000 {
843 compatible = " !! 570 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
844 #address-cells 571 #address-cells = <1>;
845 #size-cells = !! 572 #size-cells = <0>;
846 reg = <0x30800 !! 573 reg = <0x30820000 0x10000>;
847 ranges; !! 574 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
848 !! 575 clocks = <&clk IMX8MM_CLK_ECSPI1_ROOT>,
849 ecspi1: spi@30 !! 576 <&clk IMX8MM_CLK_ECSPI1_ROOT>;
850 compat !! 577 clock-names = "ipg", "per";
851 #addre !! 578 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
852 #size- !! 579 dma-names = "rx", "tx";
853 reg = !! 580 status = "disabled";
854 interr !! 581 };
855 clocks <<
856 <<
857 clock- <<
858 dmas = <<
859 dma-na <<
860 status <<
861 }; <<
862 <<
863 ecspi2: spi@30 <<
864 compat <<
865 #addre <<
866 #size- <<
867 reg = <<
868 interr <<
869 clocks <<
870 <<
871 clock- <<
872 dmas = <<
873 dma-na <<
874 status <<
875 }; <<
876 <<
877 ecspi3: spi@30 <<
878 compat <<
879 #addre <<
880 #size- <<
881 reg = <<
882 interr <<
883 clocks <<
884 <<
885 clock- <<
886 dmas = <<
887 dma-na <<
888 status <<
889 }; <<
890 <<
891 uart1: serial@ <<
892 compat <<
893 reg = <<
894 interr <<
895 clocks <<
896 <<
897 clock- <<
898 dmas = <<
899 dma-na <<
900 status <<
901 }; <<
902 <<
903 uart3: serial@ <<
904 compat <<
905 reg = <<
906 interr <<
907 clocks <<
908 <<
909 clock- <<
910 dmas = <<
911 dma-na <<
912 status <<
913 }; <<
914 582
915 uart2: serial@ !! 583 ecspi2: spi@30830000 {
916 compat !! 584 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
917 reg = !! 585 #address-cells = <1>;
918 interr !! 586 #size-cells = <0>;
919 clocks !! 587 reg = <0x30830000 0x10000>;
920 !! 588 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
921 clock- !! 589 clocks = <&clk IMX8MM_CLK_ECSPI2_ROOT>,
922 status !! 590 <&clk IMX8MM_CLK_ECSPI2_ROOT>;
923 }; !! 591 clock-names = "ipg", "per";
>> 592 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
>> 593 dma-names = "rx", "tx";
>> 594 status = "disabled";
924 }; 595 };
925 596
926 crypto: crypto@3090000 !! 597 ecspi3: spi@30840000 {
927 compatible = " !! 598 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
928 #address-cells 599 #address-cells = <1>;
929 #size-cells = !! 600 #size-cells = <0>;
930 reg = <0x30900 !! 601 reg = <0x30840000 0x10000>;
931 ranges = <0 0x !! 602 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
932 interrupts = < !! 603 clocks = <&clk IMX8MM_CLK_ECSPI3_ROOT>,
933 clocks = <&clk !! 604 <&clk IMX8MM_CLK_ECSPI3_ROOT>;
934 <&clk !! 605 clock-names = "ipg", "per";
935 clock-names = !! 606 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
936 !! 607 dma-names = "rx", "tx";
937 sec_jr0: jr@10 !! 608 status = "disabled";
938 compat !! 609 };
939 reg = <<
940 interr <<
941 status <<
942 }; <<
943 610
944 sec_jr1: jr@20 !! 611 uart1: serial@30860000 {
945 compat !! 612 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
946 reg = !! 613 reg = <0x30860000 0x10000>;
947 interr !! 614 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
948 }; !! 615 clocks = <&clk IMX8MM_CLK_UART1_ROOT>,
>> 616 <&clk IMX8MM_CLK_UART1_ROOT>;
>> 617 clock-names = "ipg", "per";
>> 618 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
>> 619 dma-names = "rx", "tx";
>> 620 status = "disabled";
>> 621 };
949 622
950 sec_jr2: jr@30 !! 623 uart3: serial@30880000 {
951 compat !! 624 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
952 reg = !! 625 reg = <0x30880000 0x10000>;
953 interr !! 626 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
954 }; !! 627 clocks = <&clk IMX8MM_CLK_UART3_ROOT>,
>> 628 <&clk IMX8MM_CLK_UART3_ROOT>;
>> 629 clock-names = "ipg", "per";
>> 630 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
>> 631 dma-names = "rx", "tx";
>> 632 status = "disabled";
>> 633 };
>> 634
>> 635 uart2: serial@30890000 {
>> 636 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
>> 637 reg = <0x30890000 0x10000>;
>> 638 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>> 639 clocks = <&clk IMX8MM_CLK_UART2_ROOT>,
>> 640 <&clk IMX8MM_CLK_UART2_ROOT>;
>> 641 clock-names = "ipg", "per";
>> 642 status = "disabled";
955 }; 643 };
956 644
957 i2c1: i2c@30a20000 { 645 i2c1: i2c@30a20000 {
958 compatible = " 646 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
959 #address-cells 647 #address-cells = <1>;
960 #size-cells = 648 #size-cells = <0>;
961 reg = <0x30a20 649 reg = <0x30a20000 0x10000>;
962 interrupts = < 650 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
963 clocks = <&clk 651 clocks = <&clk IMX8MM_CLK_I2C1_ROOT>;
964 status = "disa 652 status = "disabled";
965 }; 653 };
966 654
967 i2c2: i2c@30a30000 { 655 i2c2: i2c@30a30000 {
968 compatible = " 656 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
969 #address-cells 657 #address-cells = <1>;
970 #size-cells = 658 #size-cells = <0>;
971 reg = <0x30a30 659 reg = <0x30a30000 0x10000>;
972 interrupts = < 660 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
973 clocks = <&clk 661 clocks = <&clk IMX8MM_CLK_I2C2_ROOT>;
974 status = "disa 662 status = "disabled";
975 }; 663 };
976 664
977 i2c3: i2c@30a40000 { 665 i2c3: i2c@30a40000 {
978 #address-cells 666 #address-cells = <1>;
979 #size-cells = 667 #size-cells = <0>;
980 compatible = " 668 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
981 reg = <0x30a40 669 reg = <0x30a40000 0x10000>;
982 interrupts = < 670 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
983 clocks = <&clk 671 clocks = <&clk IMX8MM_CLK_I2C3_ROOT>;
984 status = "disa 672 status = "disabled";
985 }; 673 };
986 674
987 i2c4: i2c@30a50000 { 675 i2c4: i2c@30a50000 {
988 compatible = " 676 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
989 #address-cells 677 #address-cells = <1>;
990 #size-cells = 678 #size-cells = <0>;
991 reg = <0x30a50 679 reg = <0x30a50000 0x10000>;
992 interrupts = < 680 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
993 clocks = <&clk 681 clocks = <&clk IMX8MM_CLK_I2C4_ROOT>;
994 status = "disa 682 status = "disabled";
995 }; 683 };
996 684
997 uart4: serial@30a60000 685 uart4: serial@30a60000 {
998 compatible = " 686 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
999 reg = <0x30a60 687 reg = <0x30a60000 0x10000>;
1000 interrupts = 688 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1001 clocks = <&cl 689 clocks = <&clk IMX8MM_CLK_UART4_ROOT>,
1002 <&cl 690 <&clk IMX8MM_CLK_UART4_ROOT>;
1003 clock-names = 691 clock-names = "ipg", "per";
1004 dmas = <&sdma 692 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1005 dma-names = " 693 dma-names = "rx", "tx";
1006 status = "dis 694 status = "disabled";
1007 }; 695 };
1008 696
1009 mu: mailbox@30aa0000 <<
1010 compatible = <<
1011 reg = <0x30aa <<
1012 interrupts = <<
1013 clocks = <&cl <<
1014 #mbox-cells = <<
1015 }; <<
1016 <<
1017 usdhc1: mmc@30b40000 697 usdhc1: mmc@30b40000 {
1018 compatible = 698 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1019 reg = <0x30b4 699 reg = <0x30b40000 0x10000>;
1020 interrupts = 700 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&cl 701 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1022 <&cl 702 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1023 <&cl 703 <&clk IMX8MM_CLK_USDHC1_ROOT>;
1024 clock-names = 704 clock-names = "ipg", "ahb", "per";
>> 705 assigned-clocks = <&clk IMX8MM_CLK_USDHC1>;
>> 706 assigned-clock-rates = <400000000>;
1025 fsl,tuning-st 707 fsl,tuning-start-tap = <20>;
1026 fsl,tuning-st !! 708 fsl,tuning-step= <2>;
1027 bus-width = < 709 bus-width = <4>;
1028 status = "dis 710 status = "disabled";
1029 }; 711 };
1030 712
1031 usdhc2: mmc@30b50000 713 usdhc2: mmc@30b50000 {
1032 compatible = 714 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1033 reg = <0x30b5 715 reg = <0x30b50000 0x10000>;
1034 interrupts = 716 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1035 clocks = <&cl 717 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1036 <&cl 718 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1037 <&cl 719 <&clk IMX8MM_CLK_USDHC2_ROOT>;
1038 clock-names = 720 clock-names = "ipg", "ahb", "per";
1039 fsl,tuning-st 721 fsl,tuning-start-tap = <20>;
1040 fsl,tuning-st !! 722 fsl,tuning-step= <2>;
1041 bus-width = < 723 bus-width = <4>;
1042 status = "dis 724 status = "disabled";
1043 }; 725 };
1044 726
1045 usdhc3: mmc@30b60000 727 usdhc3: mmc@30b60000 {
1046 compatible = 728 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1047 reg = <0x30b6 729 reg = <0x30b60000 0x10000>;
1048 interrupts = 730 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1049 clocks = <&cl 731 clocks = <&clk IMX8MM_CLK_IPG_ROOT>,
1050 <&cl 732 <&clk IMX8MM_CLK_NAND_USDHC_BUS>,
1051 <&cl 733 <&clk IMX8MM_CLK_USDHC3_ROOT>;
1052 clock-names = 734 clock-names = "ipg", "ahb", "per";
>> 735 assigned-clocks = <&clk IMX8MM_CLK_USDHC3_ROOT>;
>> 736 assigned-clock-rates = <400000000>;
1053 fsl,tuning-st 737 fsl,tuning-start-tap = <20>;
1054 fsl,tuning-st !! 738 fsl,tuning-step= <2>;
1055 bus-width = < 739 bus-width = <4>;
1056 status = "dis 740 status = "disabled";
1057 }; 741 };
1058 742
1059 flexspi: spi@30bb0000 <<
1060 #address-cell <<
1061 #size-cells = <<
1062 compatible = <<
1063 reg = <0x30bb <<
1064 reg-names = " <<
1065 interrupts = <<
1066 clocks = <&cl <<
1067 <&cl <<
1068 clock-names = <<
1069 status = "dis <<
1070 }; <<
1071 <<
1072 sdma1: dma-controller 743 sdma1: dma-controller@30bd0000 {
1073 compatible = 744 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1074 reg = <0x30bd 745 reg = <0x30bd0000 0x10000>;
1075 interrupts = 746 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1076 clocks = <&cl 747 clocks = <&clk IMX8MM_CLK_SDMA1_ROOT>,
1077 <&cl 748 <&clk IMX8MM_CLK_AHB>;
1078 clock-names = 749 clock-names = "ipg", "ahb";
1079 #dma-cells = 750 #dma-cells = <3>;
1080 fsl,sdma-ram- 751 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1081 }; 752 };
1082 753
1083 fec1: ethernet@30be00 754 fec1: ethernet@30be0000 {
1084 compatible = !! 755 compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
1085 reg = <0x30be 756 reg = <0x30be0000 0x10000>;
1086 interrupts = 757 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1087 758 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1088 !! 759 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1089 <<
1090 clocks = <&cl 760 clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
1091 <&cl 761 <&clk IMX8MM_CLK_ENET1_ROOT>,
1092 <&cl 762 <&clk IMX8MM_CLK_ENET_TIMER>,
1093 <&cl 763 <&clk IMX8MM_CLK_ENET_REF>,
1094 <&cl 764 <&clk IMX8MM_CLK_ENET_PHY_REF>;
1095 clock-names = 765 clock-names = "ipg", "ahb", "ptp",
1096 766 "enet_clk_ref", "enet_out";
1097 assigned-cloc 767 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1098 768 <&clk IMX8MM_CLK_ENET_TIMER>,
1099 769 <&clk IMX8MM_CLK_ENET_REF>,
1100 !! 770 <&clk IMX8MM_CLK_ENET_TIMER>;
1101 assigned-cloc 771 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1102 772 <&clk IMX8MM_SYS_PLL2_100M>,
1103 !! 773 <&clk IMX8MM_SYS_PLL2_125M>;
1104 !! 774 assigned-clock-rates = <0>, <0>, <125000000>, <100000000>;
1105 assigned-cloc <<
1106 fsl,num-tx-qu 775 fsl,num-tx-queues = <3>;
1107 fsl,num-rx-qu 776 fsl,num-rx-queues = <3>;
1108 nvmem-cells = <<
1109 nvmem-cell-na <<
1110 fsl,stop-mode <<
1111 status = "dis 777 status = "disabled";
1112 }; 778 };
1113 779
1114 }; 780 };
1115 781
1116 aips4: bus@32c00000 { 782 aips4: bus@32c00000 {
1117 compatible = "fsl,aip 783 compatible = "fsl,aips-bus", "simple-bus";
1118 reg = <0x32c00000 0x4 <<
1119 #address-cells = <1>; 784 #address-cells = <1>;
1120 #size-cells = <1>; 785 #size-cells = <1>;
1121 ranges = <0x32c00000 786 ranges = <0x32c00000 0x32c00000 0x400000>;
1122 787
1123 lcdif: lcdif@32e00000 <<
1124 compatible = <<
1125 reg = <0x32e0 <<
1126 clocks = <&cl <<
1127 <&cl <<
1128 <&cl <<
1129 clock-names = <<
1130 assigned-cloc <<
1131 <<
1132 <<
1133 assigned-cloc <<
1134 <<
1135 <<
1136 assigned-cloc <<
1137 interrupts = <<
1138 power-domains <<
1139 status = "dis <<
1140 <<
1141 port { <<
1142 lcdif <<
1143 <<
1144 }; <<
1145 }; <<
1146 }; <<
1147 <<
1148 mipi_dsi: dsi@32e1000 <<
1149 compatible = <<
1150 reg = <0x32e1 <<
1151 clocks = <&cl <<
1152 <&cl <<
1153 clock-names = <<
1154 assigned-cloc <<
1155 assigned-cloc <<
1156 interrupts = <<
1157 power-domains <<
1158 status = "dis <<
1159 <<
1160 ports { <<
1161 #addr <<
1162 #size <<
1163 <<
1164 port@ <<
1165 <<
1166 <<
1167 <<
1168 <<
1169 <<
1170 }; <<
1171 <<
1172 port@ <<
1173 <<
1174 <<
1175 <<
1176 <<
1177 }; <<
1178 }; <<
1179 }; <<
1180 <<
1181 csi: csi@32e20000 { <<
1182 compatible = <<
1183 reg = <0x32e2 <<
1184 interrupts = <<
1185 clocks = <&cl <<
1186 clock-names = <<
1187 power-domains <<
1188 status = "dis <<
1189 <<
1190 port { <<
1191 csi_i <<
1192 <<
1193 }; <<
1194 }; <<
1195 }; <<
1196 <<
1197 disp_blk_ctrl: blk-ct <<
1198 compatible = <<
1199 reg = <0x32e2 <<
1200 power-domains <<
1201 <<
1202 <<
1203 power-domain- <<
1204 <<
1205 <<
1206 clocks = <&cl <<
1207 <&cl <<
1208 <&cl <<
1209 <&cl <<
1210 <&cl <<
1211 <&cl <<
1212 <&cl <<
1213 <&cl <<
1214 <&cl <<
1215 <&cl <<
1216 clock-names = <<
1217 <<
1218 <<
1219 <<
1220 <<
1221 #power-domain <<
1222 }; <<
1223 <<
1224 mipi_csi: mipi-csi@32 <<
1225 compatible = <<
1226 reg = <0x32e3 <<
1227 interrupts = <<
1228 assigned-cloc <<
1229 assigned-cloc <<
1230 <<
1231 clock-frequen <<
1232 clocks = <&cl <<
1233 <&cl <<
1234 <&cl <<
1235 <&cl <<
1236 clock-names = <<
1237 power-domains <<
1238 status = "dis <<
1239 <<
1240 ports { <<
1241 #addr <<
1242 #size <<
1243 <<
1244 port@ <<
1245 <<
1246 }; <<
1247 <<
1248 port@ <<
1249 <<
1250 <<
1251 <<
1252 <<
1253 <<
1254 }; <<
1255 }; <<
1256 }; <<
1257 <<
1258 usbotg1: usb@32e40000 788 usbotg1: usb@32e40000 {
1259 compatible = !! 789 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1260 reg = <0x32e4 790 reg = <0x32e40000 0x200>;
1261 interrupts = 791 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
1262 clocks = <&cl 792 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
>> 793 clock-names = "usb1_ctrl_root_clk";
1263 assigned-cloc 794 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1264 assigned-cloc 795 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1265 phys = <&usbp !! 796 fsl,usbphy = <&usbphynop1>;
1266 fsl,usbmisc = 797 fsl,usbmisc = <&usbmisc1 0>;
1267 power-domains <<
1268 status = "dis 798 status = "disabled";
1269 }; 799 };
1270 800
1271 usbmisc1: usbmisc@32e 801 usbmisc1: usbmisc@32e40200 {
1272 compatible = !! 802 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1273 <<
1274 #index-cells 803 #index-cells = <1>;
1275 reg = <0x32e4 804 reg = <0x32e40200 0x200>;
1276 }; 805 };
1277 806
1278 usbotg2: usb@32e50000 807 usbotg2: usb@32e50000 {
1279 compatible = !! 808 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
1280 reg = <0x32e5 809 reg = <0x32e50000 0x200>;
1281 interrupts = 810 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
1282 clocks = <&cl 811 clocks = <&clk IMX8MM_CLK_USB1_CTRL_ROOT>;
>> 812 clock-names = "usb1_ctrl_root_clk";
1283 assigned-cloc 813 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1284 assigned-cloc 814 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1285 phys = <&usbp !! 815 fsl,usbphy = <&usbphynop2>;
1286 fsl,usbmisc = 816 fsl,usbmisc = <&usbmisc2 0>;
1287 power-domains <<
1288 status = "dis 817 status = "disabled";
1289 }; 818 };
1290 819
1291 usbmisc2: usbmisc@32e 820 usbmisc2: usbmisc@32e50200 {
1292 compatible = !! 821 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
1293 <<
1294 #index-cells 822 #index-cells = <1>;
1295 reg = <0x32e5 823 reg = <0x32e50200 0x200>;
1296 }; 824 };
1297 825
1298 pcie_phy: pcie-phy@32 <<
1299 compatible = <<
1300 reg = <0x32f0 <<
1301 clocks = <&cl <<
1302 clock-names = <<
1303 assigned-cloc <<
1304 assigned-cloc <<
1305 assigned-cloc <<
1306 resets = <&sr <<
1307 reset-names = <<
1308 #phy-cells = <<
1309 status = "dis <<
1310 }; <<
1311 }; 826 };
1312 827
1313 dma_apbh: dma-controller@3300 828 dma_apbh: dma-controller@33000000 {
1314 compatible = "fsl,imx 829 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1315 reg = <0x33000000 0x2 830 reg = <0x33000000 0x2000>;
1316 interrupts = <GIC_SPI 831 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1317 <GIC_SPI 832 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1318 <GIC_SPI 833 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1319 <GIC_SPI 834 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
>> 835 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
1320 #dma-cells = <1>; 836 #dma-cells = <1>;
1321 dma-channels = <4>; 837 dma-channels = <4>;
1322 clocks = <&clk IMX8MM 838 clocks = <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1323 }; 839 };
1324 840
1325 gpmi: nand-controller@3300200 841 gpmi: nand-controller@33002000 {
1326 compatible = "fsl,imx 842 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1327 #address-cells = <1>; 843 #address-cells = <1>;
1328 #size-cells = <0>; 844 #size-cells = <0>;
1329 reg = <0x33002000 0x2 845 reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
1330 reg-names = "gpmi-nan 846 reg-names = "gpmi-nand", "bch";
1331 interrupts = <GIC_SPI 847 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1332 interrupt-names = "bc 848 interrupt-names = "bch";
1333 clocks = <&clk IMX8MM 849 clocks = <&clk IMX8MM_CLK_NAND_ROOT>,
1334 <&clk IMX8MM 850 <&clk IMX8MM_CLK_NAND_USDHC_BUS_RAWNAND_CLK>;
1335 clock-names = "gpmi_i 851 clock-names = "gpmi_io", "gpmi_bch_apb";
1336 dmas = <&dma_apbh 0>; 852 dmas = <&dma_apbh 0>;
1337 dma-names = "rx-tx"; 853 dma-names = "rx-tx";
1338 status = "disabled"; 854 status = "disabled";
1339 }; 855 };
1340 856
1341 pcie0: pcie@33800000 { <<
1342 compatible = "fsl,imx <<
1343 reg = <0x33800000 0x4 <<
1344 reg-names = "dbi", "c <<
1345 #address-cells = <3>; <<
1346 #size-cells = <2>; <<
1347 device_type = "pci"; <<
1348 bus-range = <0x00 0xf <<
1349 ranges = <0x81000000 <<
1350 <0x82000000 <<
1351 num-lanes = <1>; <<
1352 num-viewport = <4>; <<
1353 interrupts = <GIC_SPI <<
1354 interrupt-names = "ms <<
1355 #interrupt-cells = <1 <<
1356 interrupt-map-mask = <<
1357 interrupt-map = <0 0 <<
1358 <0 0 <<
1359 <0 0 <<
1360 <0 0 <<
1361 fsl,max-link-speed = <<
1362 linux,pci-domain = <0 <<
1363 clocks = <&clk IMX8MM <<
1364 <&clk IMX8MM <<
1365 <&clk IMX8MM <<
1366 clock-names = "pcie", <<
1367 power-domains = <&pgc <<
1368 resets = <&src IMX8MQ <<
1369 <&src IMX8MQ <<
1370 reset-names = "apps", <<
1371 phys = <&pcie_phy>; <<
1372 phy-names = "pcie-phy <<
1373 status = "disabled"; <<
1374 }; <<
1375 <<
1376 pcie0_ep: pcie-ep@33800000 { <<
1377 compatible = "fsl,imx <<
1378 reg = <0x33800000 0x4 <<
1379 <0x18000000 0x8 <<
1380 reg-names = "dbi", "a <<
1381 num-lanes = <1>; <<
1382 interrupts = <GIC_SPI <<
1383 interrupt-names = "dm <<
1384 fsl,max-link-speed = <<
1385 clocks = <&clk IMX8MM <<
1386 <&clk IMX8MM <<
1387 <&clk IMX8MM <<
1388 clock-names = "pcie", <<
1389 power-domains = <&pgc <<
1390 resets = <&src IMX8MQ <<
1391 <&src IMX8MQ <<
1392 reset-names = "apps", <<
1393 phys = <&pcie_phy>; <<
1394 phy-names = "pcie-phy <<
1395 num-ib-windows = <4>; <<
1396 num-ob-windows = <4>; <<
1397 status = "disabled"; <<
1398 }; <<
1399 <<
1400 gpu_3d: gpu@38000000 { <<
1401 compatible = "vivante <<
1402 reg = <0x38000000 0x8 <<
1403 interrupts = <GIC_SPI <<
1404 clocks = <&clk IMX8MM <<
1405 <&clk IMX8MM <<
1406 <&clk IMX8MM <<
1407 <&clk IMX8MM <<
1408 clock-names = "reg", <<
1409 assigned-clocks = <&c <<
1410 <&c <<
1411 assigned-clock-parent <<
1412 assigned-clock-rates <<
1413 power-domains = <&pgc <<
1414 }; <<
1415 <<
1416 gpu_2d: gpu@38008000 { <<
1417 compatible = "vivante <<
1418 reg = <0x38008000 0x8 <<
1419 interrupts = <GIC_SPI <<
1420 clocks = <&clk IMX8MM <<
1421 <&clk IMX8MM <<
1422 <&clk IMX8MM <<
1423 clock-names = "reg", <<
1424 assigned-clocks = <&c <<
1425 <&c <<
1426 assigned-clock-parent <<
1427 assigned-clock-rates <<
1428 power-domains = <&pgc <<
1429 }; <<
1430 <<
1431 vpu_g1: video-codec@38300000 <<
1432 compatible = "nxp,imx <<
1433 reg = <0x38300000 0x1 <<
1434 interrupts = <GIC_SPI <<
1435 clocks = <&clk IMX8MM <<
1436 power-domains = <&vpu <<
1437 }; <<
1438 <<
1439 vpu_g2: video-codec@38310000 <<
1440 compatible = "nxp,imx <<
1441 reg = <0x38310000 0x1 <<
1442 interrupts = <GIC_SPI <<
1443 clocks = <&clk IMX8MM <<
1444 power-domains = <&vpu <<
1445 }; <<
1446 <<
1447 vpu_blk_ctrl: blk-ctrl@383300 <<
1448 compatible = "fsl,imx <<
1449 reg = <0x38330000 0x1 <<
1450 power-domains = <&pgc <<
1451 <&pgc <<
1452 power-domain-names = <<
1453 clocks = <&clk IMX8MM <<
1454 <&clk IMX8MM <<
1455 <&clk IMX8MM <<
1456 clock-names = "g1", " <<
1457 assigned-clocks = <&c <<
1458 <&c <<
1459 assigned-clock-parent <<
1460 <<
1461 assigned-clock-rates <<
1462 <<
1463 #power-domain-cells = <<
1464 }; <<
1465 <<
1466 gic: interrupt-controller@388 857 gic: interrupt-controller@38800000 {
1467 compatible = "arm,gic 858 compatible = "arm,gic-v3";
1468 reg = <0x38800000 0x1 859 reg = <0x38800000 0x10000>, /* GIC Dist */
1469 <0x38880000 0xc 860 <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base) */
1470 #interrupt-cells = <3 861 #interrupt-cells = <3>;
1471 interrupt-controller; 862 interrupt-controller;
1472 interrupts = <GIC_PPI 863 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1473 }; 864 };
1474 865
1475 ddrc: memory-controller@3d400 <<
1476 compatible = "fsl,imx <<
1477 reg = <0x3d400000 0x4 <<
1478 clock-names = "core", <<
1479 clocks = <&clk IMX8MM <<
1480 <&clk IMX8MM <<
1481 <&clk IMX8MM <<
1482 <&clk IMX8MM <<
1483 }; <<
1484 <<
1485 ddr-pmu@3d800000 { 866 ddr-pmu@3d800000 {
1486 compatible = "fsl,imx 867 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
1487 reg = <0x3d800000 0x4 868 reg = <0x3d800000 0x400000>;
>> 869 interrupt-parent = <&gic>;
1488 interrupts = <GIC_SPI 870 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1489 }; 871 };
1490 }; 872 };
1491 }; 873 };
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