1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2021 Collabora Ltd.
4 * Copyright 2021 BSH Hausgeraete GmbH
5 */
6
7 /dts-v1/;
8
9 #include "imx8mn-bsh-smm-s2-common.dtsi"
10 #include <dt-bindings/sound/tlv320aic31xx.h>
11
12 / {
13 model = "BSH SMM S2 PRO";
14 compatible = "bsh,imx8mn-bsh-smm-s2pro
15
16 memory@40000000 {
17 device_type = "memory";
18 reg = <0x0 0x40000000 0x0 0x20
19 };
20
21 sound-tlv320aic31xx {
22 compatible = "fsl,imx-audio-tl
23 model = "tlv320aic31xx-hifi";
24 audio-cpu = <&sai3>;
25 audio-codec = <&tlv320dac3101>
26 audio-asrc = <&easrc>;
27 audio-routing =
28 "Ext Spk", "SPL",
29 "Ext Spk", "SPR";
30 mclk-id = <PLL_CLKIN_BCLK>;
31 };
32
33 vdd_input: vdd_input {
34 compatible = "regulator-fixed"
35 regulator-name = "vdd_input";
36 regulator-min-microvolt = <500
37 regulator-max-microvolt = <500
38 };
39 };
40
41 &easrc {
42 fsl,asrc-rate = <48000>;
43 fsl,asrc-format = <10>;
44 status = "okay";
45 };
46
47 &i2c2 {
48 clock-frequency = <400000>;
49 pinctrl-names = "default";
50 pinctrl-0 = <&pinctrl_i2c2>;
51 status = "okay";
52
53 tlv320dac3101: audio-codec@18 {
54 compatible = "ti,tlv320dac3101
55 pinctrl-names = "default";
56 pinctrl-0 = <&pinctrl_dac_rst>
57 reg = <0x18>;
58 #sound-dai-cells = <0>;
59 HPVDD-supply = <&buck4_reg>;
60 SPRVDD-supply = <&vdd_input>;
61 SPLVDD-supply = <&vdd_input>;
62 AVDD-supply = <&buck4_reg>;
63 IOVDD-supply = <&buck4_reg>;
64 DVDD-supply = <&buck5_reg>;
65 reset-gpios = <&gpio1 6 GPIO_A
66 ai31xx-micbias-vg = <MICBIAS_A
67 clocks = <&clk IMX8MN_CLK_SAI3
68 };
69 };
70
71 &sai3 {
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_sai3>;
74 assigned-clocks = <&clk IMX8MN_CLK_SAI
75 assigned-clock-parents = <&clk IMX8MN_
76 assigned-clock-rates = <24576000>;
77 fsl,sai-mclk-direction-output;
78 status = "okay";
79 };
80
81 /* eMMC */
82 &usdhc1 {
83 pinctrl-names = "default", "state_100m
84 pinctrl-0 = <&pinctrl_usdhc1>;
85 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
86 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
87 bus-width = <8>;
88 non-removable;
89 status = "okay";
90 };
91
92 &iomuxc {
93 pinctrl_dac_rst: dacrstgrp {
94 fsl,pins = <
95 MX8MN_IOMUXC_GPIO1_IO0
96 >;
97 };
98
99 pinctrl_espi2: espi2grp {
100 fsl,pins = <
101 MX8MN_IOMUXC_ECSPI2_SC
102 MX8MN_IOMUXC_ECSPI2_MO
103 MX8MN_IOMUXC_ECSPI2_MI
104 MX8MN_IOMUXC_ECSPI2_SS
105 >;
106 };
107
108 pinctrl_i2c2: i2c2grp {
109 fsl,pins = <
110 MX8MN_IOMUXC_I2C2_SCL_
111 MX8MN_IOMUXC_I2C2_SDA_
112 >;
113 };
114
115 pinctrl_sai3: sai3grp {
116 fsl,pins = <
117 MX8MN_IOMUXC_SAI3_TXFS
118 MX8MN_IOMUXC_SAI3_TXC_
119 MX8MN_IOMUXC_SAI3_TXD_
120 >;
121 };
122
123 pinctrl_usdhc1: usdhc1grp {
124 fsl,pins = <
125 MX8MN_IOMUXC_SD1_CLK_U
126 MX8MN_IOMUXC_SD1_CMD_U
127 MX8MN_IOMUXC_SD1_DATA0
128 MX8MN_IOMUXC_SD1_DATA1
129 MX8MN_IOMUXC_SD1_DATA2
130 MX8MN_IOMUXC_SD1_DATA3
131 MX8MN_IOMUXC_SD1_DATA4
132 MX8MN_IOMUXC_SD1_DATA5
133 MX8MN_IOMUXC_SD1_DATA6
134 MX8MN_IOMUXC_SD1_DATA7
135 MX8MN_IOMUXC_SD1_STROB
136 >;
137 };
138
139 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
140 fsl,pins = <
141 MX8MN_IOMUXC_SD1_CLK_U
142 MX8MN_IOMUXC_SD1_CMD_U
143 MX8MN_IOMUXC_SD1_DATA0
144 MX8MN_IOMUXC_SD1_DATA1
145 MX8MN_IOMUXC_SD1_DATA2
146 MX8MN_IOMUXC_SD1_DATA3
147 MX8MN_IOMUXC_SD1_DATA4
148 MX8MN_IOMUXC_SD1_DATA5
149 MX8MN_IOMUXC_SD1_DATA6
150 MX8MN_IOMUXC_SD1_DATA7
151 MX8MN_IOMUXC_SD1_STROB
152 >;
153 };
154
155 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
156 fsl,pins = <
157 MX8MN_IOMUXC_SD1_CLK_U
158 MX8MN_IOMUXC_SD1_CMD_U
159 MX8MN_IOMUXC_SD1_DATA0
160 MX8MN_IOMUXC_SD1_DATA1
161 MX8MN_IOMUXC_SD1_DATA2
162 MX8MN_IOMUXC_SD1_DATA3
163 MX8MN_IOMUXC_SD1_DATA4
164 MX8MN_IOMUXC_SD1_DATA5
165 MX8MN_IOMUXC_SD1_DATA6
166 MX8MN_IOMUXC_SD1_DATA7
167 MX8MN_IOMUXC_SD1_STROB
168 >;
169 };
170 };
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