1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 */
5
6 /dts-v1/;
7
8 #include "imx8mn.dtsi"
9 #include "imx8mn-evk.dtsi"
10
11 / {
12 model = "NXP i.MX8MNano DDR4 EVK board
13 compatible = "fsl,imx8mn-ddr4-evk", "f
14 };
15
16 &A53_0 {
17 cpu-supply = <&buck2_reg>;
18 };
19
20 &A53_1 {
21 cpu-supply = <&buck2_reg>;
22 };
23
24 &A53_2 {
25 cpu-supply = <&buck2_reg>;
26 };
27
28 &A53_3 {
29 cpu-supply = <&buck2_reg>;
30 };
31
32 &ddrc {
33 operating-points-v2 = <&ddrc_opp_table
34
35 ddrc_opp_table: opp-table {
36 compatible = "operating-points
37
38 opp-25000000 {
39 opp-hz = /bits/ 64 <25
40 };
41
42 opp-100000000 {
43 opp-hz = /bits/ 64 <10
44 };
45
46 opp-600000000 {
47 opp-hz = /bits/ 64 <60
48 };
49 };
50 };
51
52 &i2c1 {
53 pmic@4b {
54 compatible = "rohm,bd71847";
55 reg = <0x4b>;
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_pmic>;
58 interrupt-parent = <&gpio1>;
59 interrupts = <3 IRQ_TYPE_LEVEL
60 rohm,reset-snvs-powered;
61
62 #clock-cells = <0>;
63 clocks = <&osc_32k>;
64 clock-output-names = "clk-32k-
65
66 regulators {
67 buck1_reg: BUCK1 {
68 regulator-name
69 regulator-min-
70 regulator-max-
71 regulator-boot
72 regulator-alwa
73 regulator-ramp
74 };
75
76 buck2_reg: BUCK2 {
77 regulator-name
78 regulator-min-
79 regulator-max-
80 regulator-boot
81 regulator-alwa
82 regulator-ramp
83 };
84
85 buck3_reg: BUCK3 {
86 // BUCK5 in da
87 regulator-name
88 regulator-min-
89 regulator-max-
90 };
91
92 buck4_reg: BUCK4 {
93 // BUCK6 in da
94 regulator-name
95 regulator-min-
96 regulator-max-
97 regulator-boot
98 regulator-alwa
99 };
100
101 buck5_reg: BUCK5 {
102 // BUCK7 in da
103 regulator-name
104 regulator-min-
105 regulator-max-
106 regulator-boot
107 regulator-alwa
108 };
109
110 buck6_reg: BUCK6 {
111 // BUCK8 in da
112 regulator-name
113 regulator-min-
114 regulator-max-
115 regulator-boot
116 regulator-alwa
117 };
118
119 ldo1_reg: LDO1 {
120 regulator-name
121 regulator-min-
122 regulator-max-
123 regulator-boot
124 regulator-alwa
125 };
126
127 ldo2_reg: LDO2 {
128 regulator-name
129 regulator-min-
130 regulator-max-
131 regulator-boot
132 regulator-alwa
133 };
134
135 ldo3_reg: LDO3 {
136 regulator-name
137 regulator-min-
138 regulator-max-
139 regulator-boot
140 regulator-alwa
141 };
142
143 ldo4_reg: LDO4 {
144 regulator-name
145 regulator-min-
146 regulator-max-
147 regulator-boot
148 regulator-alwa
149 };
150
151 ldo6_reg: LDO6 {
152 regulator-name
153 regulator-min-
154 regulator-max-
155 regulator-boot
156 regulator-alwa
157 };
158 };
159 };
160 };
161
162 &i2c2 {
163 hdmi@3d {
164 avdd-supply = <&buck5_reg>;
165 dvdd-supply = <&buck5_reg>;
166 pvdd-supply = <&buck5_reg>;
167 a2vdd-supply = <&buck5_reg>;
168 v1p2-supply = <&buck5_reg>;
169 };
170 };
171
172 &i2c3 {
173 camera@3c {
174 DOVDD-supply = <&buck5_reg>;
175 };
176 };
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