1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8mn.dtsi" 8 #include "imx8mn.dtsi"
9 #include "imx8mn-evk.dtsi" <<
10 9
11 / { 10 / {
12 model = "NXP i.MX8MNano DDR4 EVK board 11 model = "NXP i.MX8MNano DDR4 EVK board";
13 compatible = "fsl,imx8mn-ddr4-evk", "f 12 compatible = "fsl,imx8mn-ddr4-evk", "fsl,imx8mn";
>> 13
>> 14 chosen {
>> 15 stdout-path = &uart2;
>> 16 };
>> 17
>> 18 reg_usdhc2_vmmc: regulator-usdhc2 {
>> 19 compatible = "regulator-fixed";
>> 20 pinctrl-names = "default";
>> 21 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
>> 22 regulator-name = "VSD_3V3";
>> 23 regulator-min-microvolt = <3300000>;
>> 24 regulator-max-microvolt = <3300000>;
>> 25 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
>> 26 enable-active-high;
>> 27 };
14 }; 28 };
15 29
16 &A53_0 { 30 &A53_0 {
17 cpu-supply = <&buck2_reg>; 31 cpu-supply = <&buck2_reg>;
18 }; 32 };
19 33
20 &A53_1 { !! 34 &iomuxc {
21 cpu-supply = <&buck2_reg>; !! 35 pinctrl-names = "default";
22 }; <<
23 36
24 &A53_2 { !! 37 pinctrl_fec1: fec1grp {
25 cpu-supply = <&buck2_reg>; !! 38 fsl,pins = <
26 }; !! 39 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
>> 40 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
>> 41 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
>> 42 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
>> 43 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
>> 44 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
>> 45 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
>> 46 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
>> 47 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
>> 48 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
>> 49 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
>> 50 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
>> 51 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
>> 52 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
>> 53 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
>> 54 >;
>> 55 };
27 56
28 &A53_3 { !! 57 pinctrl_i2c1: i2c1grp {
29 cpu-supply = <&buck2_reg>; !! 58 fsl,pins = <
30 }; !! 59 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
>> 60 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
>> 61 >;
>> 62 };
31 63
32 &ddrc { !! 64 pinctrl_pmic: pmicirq {
33 operating-points-v2 = <&ddrc_opp_table !! 65 fsl,pins = <
>> 66 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>> 67 >;
>> 68 };
34 69
35 ddrc_opp_table: opp-table { !! 70 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
36 compatible = "operating-points !! 71 fsl,pins = <
>> 72 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>> 73 >;
>> 74 };
37 75
38 opp-25000000 { !! 76 pinctrl_uart2: uart2grp {
39 opp-hz = /bits/ 64 <25 !! 77 fsl,pins = <
40 }; !! 78 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
>> 79 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
>> 80 >;
>> 81 };
41 82
42 opp-100000000 { !! 83 pinctrl_usdhc2_gpio: usdhc2grpgpio {
43 opp-hz = /bits/ 64 <10 !! 84 fsl,pins = <
44 }; !! 85 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>> 86 >;
>> 87 };
>> 88
>> 89 pinctrl_usdhc2: usdhc2grp {
>> 90 fsl,pins = <
>> 91 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
>> 92 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
>> 93 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
>> 94 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
>> 95 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
>> 96 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
>> 97 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 98 >;
>> 99 };
>> 100
>> 101 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
>> 102 fsl,pins = <
>> 103 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
>> 104 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
>> 105 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
>> 106 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
>> 107 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
>> 108 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
>> 109 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 110 >;
>> 111 };
>> 112
>> 113 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
>> 114 fsl,pins = <
>> 115 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
>> 116 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
>> 117 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
>> 118 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
>> 119 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
>> 120 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
>> 121 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
>> 122 >;
>> 123 };
>> 124
>> 125 pinctrl_usdhc3: usdhc3grp {
>> 126 fsl,pins = <
>> 127 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
>> 128 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
>> 129 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
>> 130 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
>> 131 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
>> 132 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
>> 133 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
>> 134 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
>> 135 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
>> 136 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
>> 137 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
>> 138 >;
>> 139 };
>> 140
>> 141 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
>> 142 fsl,pins = <
>> 143 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
>> 144 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
>> 145 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
>> 146 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
>> 147 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
>> 148 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
>> 149 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
>> 150 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
>> 151 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
>> 152 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
>> 153 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
>> 154 >;
>> 155 };
>> 156
>> 157 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
>> 158 fsl,pins = <
>> 159 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
>> 160 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
>> 161 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
>> 162 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
>> 163 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
>> 164 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
>> 165 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
>> 166 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
>> 167 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
>> 168 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
>> 169 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
>> 170 >;
>> 171 };
>> 172
>> 173 pinctrl_wdog: wdoggrp {
>> 174 fsl,pins = <
>> 175 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
>> 176 >;
>> 177 };
>> 178 };
45 179
46 opp-600000000 { !! 180 &fec1 {
47 opp-hz = /bits/ 64 <60 !! 181 pinctrl-names = "default";
>> 182 pinctrl-0 = <&pinctrl_fec1>;
>> 183 phy-mode = "rgmii-id";
>> 184 phy-handle = <ðphy0>;
>> 185 fsl,magic-packet;
>> 186 status = "okay";
>> 187
>> 188 mdio {
>> 189 #address-cells = <1>;
>> 190 #size-cells = <0>;
>> 191
>> 192 ethphy0: ethernet-phy@0 {
>> 193 compatible = "ethernet-phy-ieee802.3-c22";
>> 194 reg = <0>;
>> 195 at803x,led-act-blind-workaround;
>> 196 at803x,eee-disabled;
>> 197 at803x,vddio-1p8v;
48 }; 198 };
49 }; 199 };
50 }; 200 };
51 201
52 &i2c1 { 202 &i2c1 {
>> 203 clock-frequency = <400000>;
>> 204 pinctrl-names = "default";
>> 205 pinctrl-0 = <&pinctrl_i2c1>;
>> 206 status = "okay";
>> 207
53 pmic@4b { 208 pmic@4b {
54 compatible = "rohm,bd71847"; 209 compatible = "rohm,bd71847";
55 reg = <0x4b>; 210 reg = <0x4b>;
56 pinctrl-names = "default"; <<
57 pinctrl-0 = <&pinctrl_pmic>; 211 pinctrl-0 = <&pinctrl_pmic>;
58 interrupt-parent = <&gpio1>; 212 interrupt-parent = <&gpio1>;
59 interrupts = <3 IRQ_TYPE_LEVEL !! 213 interrupts = <3 GPIO_ACTIVE_LOW>;
60 rohm,reset-snvs-powered; 214 rohm,reset-snvs-powered;
61 215
62 #clock-cells = <0>; 216 #clock-cells = <0>;
63 clocks = <&osc_32k>; !! 217 clocks = <&osc_32k 0>;
64 clock-output-names = "clk-32k- 218 clock-output-names = "clk-32k-out";
65 219
66 regulators { 220 regulators {
67 buck1_reg: BUCK1 { 221 buck1_reg: BUCK1 {
68 regulator-name !! 222 regulator-name = "BUCK1";
69 regulator-min- 223 regulator-min-microvolt = <700000>;
70 regulator-max- 224 regulator-max-microvolt = <1300000>;
71 regulator-boot 225 regulator-boot-on;
72 regulator-alwa 226 regulator-always-on;
73 regulator-ramp 227 regulator-ramp-delay = <1250>;
74 }; 228 };
75 229
76 buck2_reg: BUCK2 { 230 buck2_reg: BUCK2 {
77 regulator-name !! 231 regulator-name = "BUCK2";
78 regulator-min- 232 regulator-min-microvolt = <700000>;
79 regulator-max- 233 regulator-max-microvolt = <1300000>;
80 regulator-boot 234 regulator-boot-on;
81 regulator-alwa 235 regulator-always-on;
82 regulator-ramp 236 regulator-ramp-delay = <1250>;
83 }; 237 };
84 238
85 buck3_reg: BUCK3 { 239 buck3_reg: BUCK3 {
86 // BUCK5 in da 240 // BUCK5 in datasheet
87 regulator-name !! 241 regulator-name = "BUCK3";
88 regulator-min- 242 regulator-min-microvolt = <700000>;
89 regulator-max- 243 regulator-max-microvolt = <1350000>;
90 }; 244 };
91 245
92 buck4_reg: BUCK4 { 246 buck4_reg: BUCK4 {
93 // BUCK6 in da 247 // BUCK6 in datasheet
94 regulator-name !! 248 regulator-name = "BUCK4";
95 regulator-min- 249 regulator-min-microvolt = <3000000>;
96 regulator-max- 250 regulator-max-microvolt = <3300000>;
97 regulator-boot 251 regulator-boot-on;
98 regulator-alwa 252 regulator-always-on;
99 }; 253 };
100 254
101 buck5_reg: BUCK5 { 255 buck5_reg: BUCK5 {
102 // BUCK7 in da 256 // BUCK7 in datasheet
103 regulator-name !! 257 regulator-name = "BUCK5";
104 regulator-min- 258 regulator-min-microvolt = <1605000>;
105 regulator-max- 259 regulator-max-microvolt = <1995000>;
106 regulator-boot 260 regulator-boot-on;
107 regulator-alwa 261 regulator-always-on;
108 }; 262 };
109 263
110 buck6_reg: BUCK6 { 264 buck6_reg: BUCK6 {
111 // BUCK8 in da 265 // BUCK8 in datasheet
112 regulator-name !! 266 regulator-name = "BUCK6";
113 regulator-min- 267 regulator-min-microvolt = <800000>;
114 regulator-max- 268 regulator-max-microvolt = <1400000>;
115 regulator-boot 269 regulator-boot-on;
116 regulator-alwa 270 regulator-always-on;
117 }; 271 };
118 272
119 ldo1_reg: LDO1 { 273 ldo1_reg: LDO1 {
120 regulator-name !! 274 regulator-name = "LDO1";
121 regulator-min- 275 regulator-min-microvolt = <1600000>;
122 regulator-max- 276 regulator-max-microvolt = <3300000>;
123 regulator-boot 277 regulator-boot-on;
124 regulator-alwa 278 regulator-always-on;
125 }; 279 };
126 280
127 ldo2_reg: LDO2 { 281 ldo2_reg: LDO2 {
128 regulator-name !! 282 regulator-name = "LDO2";
129 regulator-min- 283 regulator-min-microvolt = <800000>;
130 regulator-max- 284 regulator-max-microvolt = <900000>;
131 regulator-boot 285 regulator-boot-on;
132 regulator-alwa 286 regulator-always-on;
133 }; 287 };
134 288
135 ldo3_reg: LDO3 { 289 ldo3_reg: LDO3 {
136 regulator-name !! 290 regulator-name = "LDO3";
137 regulator-min- 291 regulator-min-microvolt = <1800000>;
138 regulator-max- 292 regulator-max-microvolt = <3300000>;
139 regulator-boot 293 regulator-boot-on;
140 regulator-alwa 294 regulator-always-on;
141 }; 295 };
142 296
143 ldo4_reg: LDO4 { 297 ldo4_reg: LDO4 {
144 regulator-name !! 298 regulator-name = "LDO4";
145 regulator-min- 299 regulator-min-microvolt = <900000>;
146 regulator-max- 300 regulator-max-microvolt = <1800000>;
147 regulator-boot 301 regulator-boot-on;
148 regulator-alwa 302 regulator-always-on;
149 }; 303 };
150 304
151 ldo6_reg: LDO6 { 305 ldo6_reg: LDO6 {
152 regulator-name !! 306 regulator-name = "LDO6";
153 regulator-min- 307 regulator-min-microvolt = <900000>;
154 regulator-max- 308 regulator-max-microvolt = <1800000>;
155 regulator-boot 309 regulator-boot-on;
156 regulator-alwa 310 regulator-always-on;
157 }; 311 };
158 }; 312 };
159 }; 313 };
160 }; 314 };
161 315
162 &i2c2 { !! 316 &snvs_pwrkey {
163 hdmi@3d { !! 317 status = "okay";
164 avdd-supply = <&buck5_reg>; <<
165 dvdd-supply = <&buck5_reg>; <<
166 pvdd-supply = <&buck5_reg>; <<
167 a2vdd-supply = <&buck5_reg>; <<
168 v1p2-supply = <&buck5_reg>; <<
169 }; <<
170 }; 318 };
171 319
172 &i2c3 { !! 320 &uart2 { /* console */
173 camera@3c { !! 321 pinctrl-names = "default";
174 DOVDD-supply = <&buck5_reg>; !! 322 pinctrl-0 = <&pinctrl_uart2>;
175 }; !! 323 status = "okay";
>> 324 };
>> 325
>> 326 &usdhc2 {
>> 327 pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> 328 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
>> 329 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
>> 330 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
>> 331 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
>> 332 bus-width = <4>;
>> 333 vmmc-supply = <®_usdhc2_vmmc>;
>> 334 status = "okay";
>> 335 };
>> 336
>> 337 &usdhc3 {
>> 338 pinctrl-names = "default", "state_100mhz", "state_200mhz";
>> 339 pinctrl-0 = <&pinctrl_usdhc3>;
>> 340 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
>> 341 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
>> 342 bus-width = <8>;
>> 343 non-removable;
>> 344 status = "okay";
>> 345 };
>> 346
>> 347 &wdog1 {
>> 348 pinctrl-names = "default";
>> 349 pinctrl-0 = <&pinctrl_wdog>;
>> 350 fsl,ext-reset-output;
>> 351 status = "okay";
176 }; 352 };
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