1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/usb/pd.h> <<
7 #include "imx8mn.dtsi" 6 #include "imx8mn.dtsi"
8 7
9 / { 8 / {
10 chosen { 9 chosen {
11 stdout-path = &uart2; 10 stdout-path = &uart2;
12 }; 11 };
13 12
14 gpio-leds { 13 gpio-leds {
15 compatible = "gpio-leds"; 14 compatible = "gpio-leds";
16 pinctrl-names = "default"; 15 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led 16 pinctrl-0 = <&pinctrl_gpio_led>;
18 17
19 status { 18 status {
20 label = "yellow:status 19 label = "yellow:status";
21 gpios = <&gpio3 16 GPI 20 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on"; 21 default-state = "on";
23 }; 22 };
24 }; 23 };
25 24
26 hdmi-connector { <<
27 compatible = "hdmi-connector"; <<
28 label = "hdmi"; <<
29 type = "a"; <<
30 <<
31 port { <<
32 hdmi_connector_in: end <<
33 remote-endpoin <<
34 }; <<
35 }; <<
36 }; <<
37 <<
38 memory@40000000 { <<
39 device_type = "memory"; <<
40 reg = <0x0 0x40000000 0 0x8000 <<
41 }; <<
42 <<
43 reg_usdhc2_vmmc: regulator-usdhc2 { 25 reg_usdhc2_vmmc: regulator-usdhc2 {
44 compatible = "regulator-fixed" 26 compatible = "regulator-fixed";
45 pinctrl-names = "default"; 27 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usdh 28 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
47 regulator-name = "VSD_3V3"; 29 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <330 30 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <330 31 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio2 19 GPIO_ACTIVE_ 32 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51 off-on-delay-us = <12000>; <<
52 enable-active-high; 33 enable-active-high;
53 }; 34 };
54 <<
55 reg_1v5: regulator-1v5 { <<
56 compatible = "regulator-fixed" <<
57 regulator-name = "VDD_1V5"; <<
58 regulator-min-microvolt = <150 <<
59 regulator-max-microvolt = <150 <<
60 }; <<
61 <<
62 reg_1v8: regulator-1v8 { <<
63 compatible = "regulator-fixed" <<
64 regulator-name = "VDD_1V8"; <<
65 regulator-min-microvolt = <180 <<
66 regulator-max-microvolt = <180 <<
67 }; <<
68 <<
69 reg_vddext_3v3: regulator-vddext-3v3 { <<
70 compatible = "regulator-fixed" <<
71 regulator-name = "VDDEXT_3V3"; <<
72 regulator-min-microvolt = <330 <<
73 regulator-max-microvolt = <330 <<
74 }; <<
75 <<
76 ir-receiver { <<
77 compatible = "gpio-ir-receiver <<
78 gpios = <&gpio1 13 GPIO_ACTIVE <<
79 pinctrl-names = "default"; <<
80 pinctrl-0 = <&pinctrl_ir>; <<
81 linux,autosuspend-period = <12 <<
82 }; <<
83 <<
84 audio_codec_bt_sco: audio-codec-bt-sco <<
85 compatible = "linux,bt-sco"; <<
86 #sound-dai-cells = <1>; <<
87 }; <<
88 <<
89 wm8524: audio-codec { <<
90 #sound-dai-cells = <0>; <<
91 compatible = "wlf,wm8524"; <<
92 pinctrl-names = "default"; <<
93 pinctrl-0 = <&pinctrl_gpio_wlf <<
94 wlf,mute-gpios = <&gpio5 21 GP <<
95 }; <<
96 <<
97 sound-bt-sco { <<
98 compatible = "simple-audio-car <<
99 simple-audio-card,name = "bt-s <<
100 simple-audio-card,format = "ds <<
101 simple-audio-card,bitclock-inv <<
102 simple-audio-card,frame-master <<
103 simple-audio-card,bitclock-mas <<
104 <<
105 btcpu: simple-audio-card,cpu { <<
106 sound-dai = <&sai2>; <<
107 dai-tdm-slot-num = <2> <<
108 dai-tdm-slot-width = < <<
109 }; <<
110 <<
111 simple-audio-card,codec { <<
112 sound-dai = <&audio_co <<
113 }; <<
114 }; <<
115 <<
116 sound-wm8524 { <<
117 compatible = "fsl,imx-audio-wm <<
118 model = "wm8524-audio"; <<
119 audio-cpu = <&sai3>; <<
120 audio-codec = <&wm8524>; <<
121 audio-asrc = <&easrc>; <<
122 audio-routing = <<
123 "Line Out Jack", "LINE <<
124 "Line Out Jack", "LINE <<
125 }; <<
126 <<
127 spdif_out: spdif-out { <<
128 compatible = "linux,spdif-dit" <<
129 #sound-dai-cells = <0>; <<
130 }; <<
131 <<
132 spdif_in: spdif-in { <<
133 compatible = "linux,spdif-dir" <<
134 #sound-dai-cells = <0>; <<
135 }; <<
136 <<
137 sound-spdif { <<
138 compatible = "fsl,imx-audio-sp <<
139 model = "imx-spdif"; <<
140 audio-cpu = <&spdif1>; <<
141 audio-codec = <&spdif_out>, <& <<
142 }; <<
143 <<
144 sound-micfil { <<
145 compatible = "fsl,imx-audio-ca <<
146 model = "micfil-audio"; <<
147 <<
148 pri-dai-link { <<
149 link-name = "micfil hi <<
150 format = "i2s"; <<
151 <<
152 cpu { <<
153 sound-dai = <& <<
154 }; <<
155 }; <<
156 }; <<
157 }; <<
158 <<
159 &easrc { <<
160 fsl,asrc-rate = <48000>; <<
161 status = "okay"; <<
162 }; 35 };
163 36
164 &fec1 { 37 &fec1 {
165 pinctrl-names = "default"; 38 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec1>; 39 pinctrl-0 = <&pinctrl_fec1>;
167 phy-mode = "rgmii-id"; 40 phy-mode = "rgmii-id";
168 phy-handle = <ðphy0>; 41 phy-handle = <ðphy0>;
169 fsl,magic-packet; 42 fsl,magic-packet;
170 status = "okay"; 43 status = "okay";
171 44
172 mdio { 45 mdio {
173 #address-cells = <1>; 46 #address-cells = <1>;
174 #size-cells = <0>; 47 #size-cells = <0>;
175 48
176 ethphy0: ethernet-phy@0 { 49 ethphy0: ethernet-phy@0 {
177 compatible = "ethernet 50 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <0>; 51 reg = <0>;
179 reset-gpios = <&gpio4 <<
180 reset-assert-us = <100 <<
181 qca,disable-smarteee; <<
182 vddio-supply = <&vddio <<
183 <<
184 vddio: vddio-regulator <<
185 regulator-min- <<
186 regulator-max- <<
187 }; <<
188 }; 52 };
189 }; 53 };
190 }; 54 };
191 55
192 &flexspi { <<
193 pinctrl-names = "default"; <<
194 pinctrl-0 = <&pinctrl_flexspi>; <<
195 status = "okay"; <<
196 <<
197 flash0: flash@0 { <<
198 compatible = "jedec,spi-nor"; <<
199 reg = <0>; <<
200 #address-cells = <1>; <<
201 #size-cells = <1>; <<
202 spi-max-frequency = <166000000 <<
203 spi-tx-bus-width = <4>; <<
204 spi-rx-bus-width = <4>; <<
205 }; <<
206 }; <<
207 <<
208 &i2c1 { 56 &i2c1 {
209 clock-frequency = <400000>; 57 clock-frequency = <400000>;
210 pinctrl-names = "default"; 58 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>; 59 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "okay"; 60 status = "okay";
213 }; 61 };
214 62
215 &i2c2 { <<
216 clock-frequency = <400000>; <<
217 pinctrl-names = "default", "gpio"; <<
218 pinctrl-0 = <&pinctrl_i2c2>; <<
219 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
220 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
221 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
222 status = "okay"; <<
223 <<
224 hdmi@3d { <<
225 compatible = "adi,adv7535"; <<
226 reg = <0x3d>; <<
227 interrupt-parent = <&gpio1>; <<
228 interrupts = <9 IRQ_TYPE_EDGE_ <<
229 adi,dsi-lanes = <4>; <<
230 v3p3-supply = <®_vddext_3v3 <<
231 <<
232 ports { <<
233 #address-cells = <1>; <<
234 #size-cells = <0>; <<
235 <<
236 port@0 { <<
237 reg = <0>; <<
238 <<
239 adv7535_in: en <<
240 remote <<
241 }; <<
242 }; <<
243 <<
244 port@1 { <<
245 reg = <1>; <<
246 <<
247 adv7535_out: e <<
248 remote <<
249 }; <<
250 }; <<
251 <<
252 }; <<
253 }; <<
254 <<
255 ptn5110: tcpc@50 { <<
256 compatible = "nxp,ptn5110", "t <<
257 pinctrl-names = "default"; <<
258 pinctrl-0 = <&pinctrl_typec1>; <<
259 reg = <0x50>; <<
260 interrupt-parent = <&gpio2>; <<
261 interrupts = <11 IRQ_TYPE_LEVE <<
262 status = "okay"; <<
263 <<
264 typec1_con: connector { <<
265 compatible = "usb-c-co <<
266 label = "USB-C"; <<
267 power-role = "dual"; <<
268 data-role = "dual"; <<
269 try-power-role = "sink <<
270 source-pdos = <PDO_FIX <<
271 sink-pdos = <PDO_FIXED <<
272 PDO_VAR(5 <<
273 op-sink-microwatt = <1 <<
274 self-powered; <<
275 <<
276 port { <<
277 typec1_dr_sw: <<
278 remote <<
279 }; <<
280 }; <<
281 }; <<
282 }; <<
283 }; <<
284 <<
285 &i2c3 { <<
286 clock-frequency = <400000>; <<
287 pinctrl-names = "default", "gpio"; <<
288 pinctrl-0 = <&pinctrl_i2c3>; <<
289 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
290 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIG <<
291 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIG <<
292 status = "okay"; <<
293 <<
294 pca6416: gpio@20 { <<
295 compatible = "ti,tca6416"; <<
296 reg = <0x20>; <<
297 gpio-controller; <<
298 #gpio-cells = <2>; <<
299 }; <<
300 <<
301 camera@3c { <<
302 compatible = "ovti,ov5640"; <<
303 reg = <0x3c>; <<
304 pinctrl-names = "default"; <<
305 pinctrl-0 = <&pinctrl_camera>; <<
306 clocks = <&clk IMX8MN_CLK_CLKO <<
307 clock-names = "xclk"; <<
308 assigned-clocks = <&clk IMX8MN <<
309 assigned-clock-parents = <&clk <<
310 assigned-clock-rates = <240000 <<
311 powerdown-gpios = <&gpio1 7 GP <<
312 reset-gpios = <&gpio1 6 GPIO_A <<
313 AVDD-supply = <®_1v8>; <<
314 DVDD-supply = <®_1v5>; <<
315 <<
316 port { <<
317 ov5640_to_mipi_csi2: e <<
318 remote-endpoin <<
319 clock-lanes = <<
320 data-lanes = < <<
321 }; <<
322 }; <<
323 }; <<
324 }; <<
325 <<
326 &isi { <<
327 status = "okay"; <<
328 }; <<
329 <<
330 &micfil { <<
331 #sound-dai-cells = <0>; <<
332 pinctrl-names = "default"; <<
333 pinctrl-0 = <&pinctrl_pdm>; <<
334 assigned-clocks = <&clk IMX8MN_CLK_PDM <<
335 assigned-clock-parents = <&clk IMX8MN_ <<
336 assigned-clock-rates = <196608000>; <<
337 status = "okay"; <<
338 }; <<
339 <<
340 &mipi_csi { <<
341 status = "okay"; <<
342 <<
343 ports { <<
344 port@0 { <<
345 imx8mn_mipi_csi_in: en <<
346 remote-endpoin <<
347 data-lanes = < <<
348 }; <<
349 }; <<
350 }; <<
351 }; <<
352 <<
353 &lcdif { <<
354 status = "okay"; <<
355 }; <<
356 <<
357 &mipi_dsi { <<
358 samsung,esc-clock-frequency = <1000000 <<
359 status = "okay"; <<
360 <<
361 ports { <<
362 port@1 { <<
363 reg = <1>; <<
364 <<
365 dsi_out: endpoint { <<
366 remote-endpoin <<
367 data-lanes = < <<
368 }; <<
369 }; <<
370 }; <<
371 }; <<
372 <<
373 &sai2 { <<
374 #sound-dai-cells = <0>; <<
375 pinctrl-names = "default"; <<
376 pinctrl-0 = <&pinctrl_sai2>; <<
377 assigned-clocks = <&clk IMX8MN_CLK_SAI <<
378 assigned-clock-parents = <&clk IMX8MN_ <<
379 assigned-clock-rates = <24576000>; <<
380 status = "okay"; <<
381 }; <<
382 <<
383 &sai3 { <<
384 pinctrl-names = "default"; <<
385 pinctrl-0 = <&pinctrl_sai3>; <<
386 assigned-clocks = <&clk IMX8MN_CLK_SAI <<
387 assigned-clock-parents = <&clk IMX8MN_ <<
388 assigned-clock-rates = <24576000>; <<
389 fsl,sai-mclk-direction-output; <<
390 status = "okay"; <<
391 }; <<
392 <<
393 &snvs_pwrkey { 63 &snvs_pwrkey {
394 status = "okay"; 64 status = "okay";
395 }; 65 };
396 66
397 &spdif1 { <<
398 pinctrl-names = "default"; <<
399 pinctrl-0 = <&pinctrl_spdif1>; <<
400 assigned-clocks = <&clk IMX8MN_CLK_SPD <<
401 assigned-clock-parents = <&clk IMX8MN_ <<
402 assigned-clock-rates = <24576000>; <<
403 status = "okay"; <<
404 }; <<
405 <<
406 &uart1 { /* BT */ <<
407 pinctrl-names = "default"; <<
408 pinctrl-0 = <&pinctrl_uart1>; <<
409 assigned-clocks = <&clk IMX8MN_CLK_UAR <<
410 assigned-clock-parents = <&clk IMX8MN_ <<
411 uart-has-rtscts; <<
412 status = "okay"; <<
413 }; <<
414 <<
415 &uart2 { /* console */ 67 &uart2 { /* console */
416 pinctrl-names = "default"; 68 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart2>; 69 pinctrl-0 = <&pinctrl_uart2>;
418 status = "okay"; 70 status = "okay";
419 }; 71 };
420 72
421 &uart3 { <<
422 pinctrl-names = "default"; <<
423 pinctrl-0 = <&pinctrl_uart3>; <<
424 assigned-clocks = <&clk IMX8MN_CLK_UAR <<
425 assigned-clock-parents = <&clk IMX8MN_ <<
426 uart-has-rtscts; <<
427 status = "okay"; <<
428 }; <<
429 <<
430 &usbphynop1 { <<
431 wakeup-source; <<
432 }; <<
433 <<
434 &usbotg1 { <<
435 dr_mode = "otg"; <<
436 hnp-disable; <<
437 srp-disable; <<
438 adp-disable; <<
439 usb-role-switch; <<
440 disable-over-current; <<
441 samsung,picophy-pre-emp-curr-control = <<
442 samsung,picophy-dc-vol-level-adjust = <<
443 status = "okay"; <<
444 <<
445 port { <<
446 usb1_drd_sw: endpoint { <<
447 remote-endpoint = <&ty <<
448 }; <<
449 }; <<
450 }; <<
451 <<
452 &usdhc2 { 73 &usdhc2 {
453 assigned-clocks = <&clk IMX8MN_CLK_USD 74 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
454 assigned-clock-rates = <200000000>; 75 assigned-clock-rates = <200000000>;
455 pinctrl-names = "default", "state_100m 76 pinctrl-names = "default", "state_100mhz", "state_200mhz";
456 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 77 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
457 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 78 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
458 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 79 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
459 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 80 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
460 bus-width = <4>; 81 bus-width = <4>;
461 vmmc-supply = <®_usdhc2_vmmc>; 82 vmmc-supply = <®_usdhc2_vmmc>;
462 status = "okay"; 83 status = "okay";
463 }; 84 };
464 85
465 &usdhc3 { 86 &usdhc3 {
466 assigned-clocks = <&clk IMX8MN_CLK_USD 87 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
467 assigned-clock-rates = <400000000>; 88 assigned-clock-rates = <400000000>;
468 pinctrl-names = "default", "state_100m 89 pinctrl-names = "default", "state_100mhz", "state_200mhz";
469 pinctrl-0 = <&pinctrl_usdhc3>; 90 pinctrl-0 = <&pinctrl_usdhc3>;
470 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 91 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
471 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 92 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
472 bus-width = <8>; 93 bus-width = <8>;
473 non-removable; 94 non-removable;
474 status = "okay"; 95 status = "okay";
475 }; 96 };
476 97
477 &wdog1 { 98 &wdog1 {
478 pinctrl-names = "default"; 99 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_wdog>; 100 pinctrl-0 = <&pinctrl_wdog>;
480 fsl,ext-reset-output; 101 fsl,ext-reset-output;
481 status = "okay"; 102 status = "okay";
482 }; 103 };
483 104
484 &iomuxc { 105 &iomuxc {
485 pinctrl_camera: cameragrp { !! 106 pinctrl-names = "default";
486 fsl,pins = < <<
487 MX8MN_IOMUXC_GPIO1_IO0 <<
488 MX8MN_IOMUXC_GPIO1_IO0 <<
489 MX8MN_IOMUXC_GPIO1_IO1 <<
490 >; <<
491 }; <<
492 107
493 pinctrl_fec1: fec1grp { 108 pinctrl_fec1: fec1grp {
494 fsl,pins = < 109 fsl,pins = <
495 MX8MN_IOMUXC_ENET_MDC_ 110 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
496 MX8MN_IOMUXC_ENET_MDIO 111 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
497 MX8MN_IOMUXC_ENET_TD3_ 112 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
498 MX8MN_IOMUXC_ENET_TD2_ 113 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
499 MX8MN_IOMUXC_ENET_TD1_ 114 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
500 MX8MN_IOMUXC_ENET_TD0_ 115 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
501 MX8MN_IOMUXC_ENET_RD3_ 116 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
502 MX8MN_IOMUXC_ENET_RD2_ 117 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
503 MX8MN_IOMUXC_ENET_RD1_ 118 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
504 MX8MN_IOMUXC_ENET_RD0_ 119 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
505 MX8MN_IOMUXC_ENET_TXC_ 120 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
506 MX8MN_IOMUXC_ENET_RXC_ 121 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
507 MX8MN_IOMUXC_ENET_RX_C 122 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
508 MX8MN_IOMUXC_ENET_TX_C 123 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
509 MX8MN_IOMUXC_SAI2_RXC_ 124 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
510 >; 125 >;
511 }; 126 };
512 127
513 pinctrl_flexspi: flexspigrp { <<
514 fsl,pins = < <<
515 MX8MN_IOMUXC_NAND_ALE_ <<
516 MX8MN_IOMUXC_NAND_CE0_ <<
517 MX8MN_IOMUXC_NAND_DATA <<
518 MX8MN_IOMUXC_NAND_DATA <<
519 MX8MN_IOMUXC_NAND_DATA <<
520 MX8MN_IOMUXC_NAND_DATA <<
521 >; <<
522 }; <<
523 <<
524 pinctrl_gpio_led: gpioledgrp { 128 pinctrl_gpio_led: gpioledgrp {
525 fsl,pins = < 129 fsl,pins = <
526 MX8MN_IOMUXC_NAND_READ 130 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
527 >; 131 >;
528 }; 132 };
529 133
530 pinctrl_gpio_wlf: gpiowlfgrp { <<
531 fsl,pins = < <<
532 MX8MN_IOMUXC_I2C4_SDA_ <<
533 >; <<
534 }; <<
535 <<
536 pinctrl_ir: irgrp { <<
537 fsl,pins = < <<
538 MX8MN_IOMUXC_GPIO1_IO1 <<
539 >; <<
540 }; <<
541 <<
542 pinctrl_i2c1: i2c1grp { 134 pinctrl_i2c1: i2c1grp {
543 fsl,pins = < 135 fsl,pins = <
544 MX8MN_IOMUXC_I2C1_SCL_ 136 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
545 MX8MN_IOMUXC_I2C1_SDA_ 137 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
546 >; 138 >;
547 }; 139 };
548 140
549 pinctrl_i2c2: i2c2grp { !! 141 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
550 fsl,pins = < <<
551 MX8MN_IOMUXC_I2C2_SCL_ <<
552 MX8MN_IOMUXC_I2C2_SDA_ <<
553 >; <<
554 }; <<
555 <<
556 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
557 fsl,pins = < <<
558 MX8MN_IOMUXC_I2C2_SCL_ <<
559 MX8MN_IOMUXC_I2C2_SDA_ <<
560 >; <<
561 }; <<
562 <<
563 pinctrl_i2c3: i2c3grp { <<
564 fsl,pins = < <<
565 MX8MN_IOMUXC_I2C3_SCL_ <<
566 MX8MN_IOMUXC_I2C3_SDA_ <<
567 >; <<
568 }; <<
569 <<
570 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
571 fsl,pins = < <<
572 MX8MN_IOMUXC_I2C3_SCL_ <<
573 MX8MN_IOMUXC_I2C3_SDA_ <<
574 >; <<
575 }; <<
576 <<
577 pinctrl_pdm: pdmgrp { <<
578 fsl,pins = < <<
579 MX8MN_IOMUXC_SAI5_MCLK <<
580 MX8MN_IOMUXC_SAI5_RXC_ <<
581 MX8MN_IOMUXC_SAI5_RXFS <<
582 MX8MN_IOMUXC_SAI5_RXD0 <<
583 MX8MN_IOMUXC_SAI5_RXD1 <<
584 MX8MN_IOMUXC_SAI5_RXD2 <<
585 MX8MN_IOMUXC_SAI5_RXD3 <<
586 >; <<
587 }; <<
588 <<
589 pinctrl_pmic: pmicirqgrp { <<
590 fsl,pins = < <<
591 MX8MN_IOMUXC_GPIO1_IO0 <<
592 >; <<
593 }; <<
594 <<
595 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc <<
596 fsl,pins = < 142 fsl,pins = <
597 MX8MN_IOMUXC_SD2_RESET 143 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
598 >; 144 >;
599 }; 145 };
600 146
601 pinctrl_sai2: sai2grp { <<
602 fsl,pins = < <<
603 MX8MN_IOMUXC_SAI2_TXC_ <<
604 MX8MN_IOMUXC_SAI2_TXFS <<
605 MX8MN_IOMUXC_SAI2_TXD0 <<
606 MX8MN_IOMUXC_SAI2_RXD0 <<
607 >; <<
608 }; <<
609 <<
610 pinctrl_sai3: sai3grp { <<
611 fsl,pins = < <<
612 MX8MN_IOMUXC_SAI3_TXFS <<
613 MX8MN_IOMUXC_SAI3_TXC_ <<
614 MX8MN_IOMUXC_SAI3_MCLK <<
615 MX8MN_IOMUXC_SAI3_TXD_ <<
616 >; <<
617 }; <<
618 <<
619 pinctrl_spdif1: spdif1grp { <<
620 fsl,pins = < <<
621 MX8MN_IOMUXC_SPDIF_TX_ <<
622 MX8MN_IOMUXC_SPDIF_RX_ <<
623 >; <<
624 }; <<
625 <<
626 pinctrl_typec1: typec1grp { <<
627 fsl,pins = < <<
628 MX8MN_IOMUXC_SD1_STROB <<
629 >; <<
630 }; <<
631 <<
632 pinctrl_uart1: uart1grp { <<
633 fsl,pins = < <<
634 MX8MN_IOMUXC_UART1_RXD <<
635 MX8MN_IOMUXC_UART1_TXD <<
636 MX8MN_IOMUXC_UART3_RXD <<
637 MX8MN_IOMUXC_UART3_TXD <<
638 >; <<
639 }; <<
640 <<
641 pinctrl_uart2: uart2grp { 147 pinctrl_uart2: uart2grp {
642 fsl,pins = < 148 fsl,pins = <
643 MX8MN_IOMUXC_UART2_RXD 149 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
644 MX8MN_IOMUXC_UART2_TXD 150 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
645 >; 151 >;
646 }; 152 };
647 153
648 pinctrl_uart3: uart3grp { !! 154 pinctrl_usdhc2_gpio: usdhc2grpgpio {
649 fsl,pins = < <<
650 MX8MN_IOMUXC_ECSPI1_SC <<
651 MX8MN_IOMUXC_ECSPI1_MO <<
652 MX8MN_IOMUXC_ECSPI1_SS <<
653 MX8MN_IOMUXC_ECSPI1_MI <<
654 >; <<
655 }; <<
656 <<
657 pinctrl_usdhc2_gpio: usdhc2gpiogrp { <<
658 fsl,pins = < 155 fsl,pins = <
659 MX8MN_IOMUXC_GPIO1_IO1 156 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
660 >; 157 >;
661 }; 158 };
662 159
663 pinctrl_usdhc2: usdhc2grp { 160 pinctrl_usdhc2: usdhc2grp {
664 fsl,pins = < 161 fsl,pins = <
665 MX8MN_IOMUXC_SD2_CLK_U 162 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
666 MX8MN_IOMUXC_SD2_CMD_U 163 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
667 MX8MN_IOMUXC_SD2_DATA0 164 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
668 MX8MN_IOMUXC_SD2_DATA1 165 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
669 MX8MN_IOMUXC_SD2_DATA2 166 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
670 MX8MN_IOMUXC_SD2_DATA3 167 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
671 MX8MN_IOMUXC_GPIO1_IO0 168 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
672 >; 169 >;
673 }; 170 };
674 171
675 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr !! 172 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
676 fsl,pins = < 173 fsl,pins = <
677 MX8MN_IOMUXC_SD2_CLK_U 174 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
678 MX8MN_IOMUXC_SD2_CMD_U 175 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
679 MX8MN_IOMUXC_SD2_DATA0 176 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
680 MX8MN_IOMUXC_SD2_DATA1 177 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
681 MX8MN_IOMUXC_SD2_DATA2 178 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
682 MX8MN_IOMUXC_SD2_DATA3 179 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
683 MX8MN_IOMUXC_GPIO1_IO0 180 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
684 >; 181 >;
685 }; 182 };
686 183
687 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr !! 184 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
688 fsl,pins = < 185 fsl,pins = <
689 MX8MN_IOMUXC_SD2_CLK_U 186 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
690 MX8MN_IOMUXC_SD2_CMD_U 187 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
691 MX8MN_IOMUXC_SD2_DATA0 188 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
692 MX8MN_IOMUXC_SD2_DATA1 189 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
693 MX8MN_IOMUXC_SD2_DATA2 190 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
694 MX8MN_IOMUXC_SD2_DATA3 191 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
695 MX8MN_IOMUXC_GPIO1_IO0 192 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
696 >; 193 >;
697 }; 194 };
698 195
699 pinctrl_usdhc3: usdhc3grp { 196 pinctrl_usdhc3: usdhc3grp {
700 fsl,pins = < 197 fsl,pins = <
701 MX8MN_IOMUXC_NAND_WE_B 198 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
702 MX8MN_IOMUXC_NAND_WP_B 199 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
703 MX8MN_IOMUXC_NAND_DATA 200 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
704 MX8MN_IOMUXC_NAND_DATA 201 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
705 MX8MN_IOMUXC_NAND_DATA 202 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
706 MX8MN_IOMUXC_NAND_DATA 203 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
707 MX8MN_IOMUXC_NAND_RE_B 204 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
708 MX8MN_IOMUXC_NAND_CE2_ 205 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
709 MX8MN_IOMUXC_NAND_CE3_ 206 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
710 MX8MN_IOMUXC_NAND_CLE_ 207 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
711 MX8MN_IOMUXC_NAND_CE1_ 208 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
712 >; 209 >;
713 }; 210 };
714 211
715 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr !! 212 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
716 fsl,pins = < 213 fsl,pins = <
717 MX8MN_IOMUXC_NAND_WE_B 214 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
718 MX8MN_IOMUXC_NAND_WP_B 215 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
719 MX8MN_IOMUXC_NAND_DATA 216 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
720 MX8MN_IOMUXC_NAND_DATA 217 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
721 MX8MN_IOMUXC_NAND_DATA 218 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
722 MX8MN_IOMUXC_NAND_DATA 219 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
723 MX8MN_IOMUXC_NAND_RE_B 220 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
724 MX8MN_IOMUXC_NAND_CE2_ 221 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
725 MX8MN_IOMUXC_NAND_CE3_ 222 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
726 MX8MN_IOMUXC_NAND_CLE_ 223 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
727 MX8MN_IOMUXC_NAND_CE1_ 224 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
728 >; 225 >;
729 }; 226 };
730 227
731 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr !! 228 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
732 fsl,pins = < 229 fsl,pins = <
733 MX8MN_IOMUXC_NAND_WE_B 230 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
734 MX8MN_IOMUXC_NAND_WP_B 231 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
735 MX8MN_IOMUXC_NAND_DATA 232 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
736 MX8MN_IOMUXC_NAND_DATA 233 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
737 MX8MN_IOMUXC_NAND_DATA 234 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
738 MX8MN_IOMUXC_NAND_DATA 235 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
739 MX8MN_IOMUXC_NAND_RE_B 236 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
740 MX8MN_IOMUXC_NAND_CE2_ 237 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
741 MX8MN_IOMUXC_NAND_CE3_ 238 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
742 MX8MN_IOMUXC_NAND_CLE_ 239 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
743 MX8MN_IOMUXC_NAND_CE1_ 240 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
744 >; 241 >;
745 }; 242 };
746 243
747 pinctrl_wdog: wdoggrp { 244 pinctrl_wdog: wdoggrp {
748 fsl,pins = < 245 fsl,pins = <
749 MX8MN_IOMUXC_GPIO1_IO0 !! 246 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
750 >; 247 >;
751 }; 248 };
752 }; 249 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.