1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/usb/pd.h> 6 #include <dt-bindings/usb/pd.h>
7 #include "imx8mn.dtsi" 7 #include "imx8mn.dtsi"
8 8
9 / { 9 / {
10 chosen { 10 chosen {
11 stdout-path = &uart2; 11 stdout-path = &uart2;
12 }; 12 };
13 13
14 gpio-leds { 14 gpio-leds {
15 compatible = "gpio-leds"; 15 compatible = "gpio-leds";
16 pinctrl-names = "default"; 16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led 17 pinctrl-0 = <&pinctrl_gpio_led>;
18 18
19 status { 19 status {
20 label = "yellow:status 20 label = "yellow:status";
21 gpios = <&gpio3 16 GPI 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on"; 22 default-state = "on";
23 }; 23 };
24 }; 24 };
25 25
26 hdmi-connector { <<
27 compatible = "hdmi-connector"; <<
28 label = "hdmi"; <<
29 type = "a"; <<
30 <<
31 port { <<
32 hdmi_connector_in: end <<
33 remote-endpoin <<
34 }; <<
35 }; <<
36 }; <<
37 <<
38 memory@40000000 { 26 memory@40000000 {
39 device_type = "memory"; 27 device_type = "memory";
40 reg = <0x0 0x40000000 0 0x8000 28 reg = <0x0 0x40000000 0 0x80000000>;
41 }; 29 };
42 30
43 reg_usdhc2_vmmc: regulator-usdhc2 { 31 reg_usdhc2_vmmc: regulator-usdhc2 {
44 compatible = "regulator-fixed" 32 compatible = "regulator-fixed";
45 pinctrl-names = "default"; 33 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usdh 34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
47 regulator-name = "VSD_3V3"; 35 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <330 36 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <330 37 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio2 19 GPIO_ACTIVE_ 38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51 off-on-delay-us = <12000>; <<
52 enable-active-high; 39 enable-active-high;
53 }; 40 };
54 41
55 reg_1v5: regulator-1v5 { <<
56 compatible = "regulator-fixed" <<
57 regulator-name = "VDD_1V5"; <<
58 regulator-min-microvolt = <150 <<
59 regulator-max-microvolt = <150 <<
60 }; <<
61 <<
62 reg_1v8: regulator-1v8 { <<
63 compatible = "regulator-fixed" <<
64 regulator-name = "VDD_1V8"; <<
65 regulator-min-microvolt = <180 <<
66 regulator-max-microvolt = <180 <<
67 }; <<
68 <<
69 reg_vddext_3v3: regulator-vddext-3v3 { <<
70 compatible = "regulator-fixed" <<
71 regulator-name = "VDDEXT_3V3"; <<
72 regulator-min-microvolt = <330 <<
73 regulator-max-microvolt = <330 <<
74 }; <<
75 <<
76 ir-receiver { 42 ir-receiver {
77 compatible = "gpio-ir-receiver 43 compatible = "gpio-ir-receiver";
78 gpios = <&gpio1 13 GPIO_ACTIVE 44 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
79 pinctrl-names = "default"; 45 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_ir>; 46 pinctrl-0 = <&pinctrl_ir>;
81 linux,autosuspend-period = <12 47 linux,autosuspend-period = <125>;
82 }; 48 };
83 49
84 audio_codec_bt_sco: audio-codec-bt-sco 50 audio_codec_bt_sco: audio-codec-bt-sco {
85 compatible = "linux,bt-sco"; 51 compatible = "linux,bt-sco";
86 #sound-dai-cells = <1>; 52 #sound-dai-cells = <1>;
87 }; 53 };
88 54
89 wm8524: audio-codec { 55 wm8524: audio-codec {
90 #sound-dai-cells = <0>; 56 #sound-dai-cells = <0>;
91 compatible = "wlf,wm8524"; 57 compatible = "wlf,wm8524";
92 pinctrl-names = "default"; 58 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gpio_wlf 59 pinctrl-0 = <&pinctrl_gpio_wlf>;
94 wlf,mute-gpios = <&gpio5 21 GP 60 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
>> 61 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
>> 62 clock-names = "mclk";
95 }; 63 };
96 64
97 sound-bt-sco { 65 sound-bt-sco {
98 compatible = "simple-audio-car 66 compatible = "simple-audio-card";
99 simple-audio-card,name = "bt-s 67 simple-audio-card,name = "bt-sco-audio";
100 simple-audio-card,format = "ds 68 simple-audio-card,format = "dsp_a";
101 simple-audio-card,bitclock-inv 69 simple-audio-card,bitclock-inversion;
102 simple-audio-card,frame-master 70 simple-audio-card,frame-master = <&btcpu>;
103 simple-audio-card,bitclock-mas 71 simple-audio-card,bitclock-master = <&btcpu>;
104 72
105 btcpu: simple-audio-card,cpu { 73 btcpu: simple-audio-card,cpu {
106 sound-dai = <&sai2>; 74 sound-dai = <&sai2>;
107 dai-tdm-slot-num = <2> 75 dai-tdm-slot-num = <2>;
108 dai-tdm-slot-width = < 76 dai-tdm-slot-width = <16>;
109 }; 77 };
110 78
111 simple-audio-card,codec { 79 simple-audio-card,codec {
112 sound-dai = <&audio_co 80 sound-dai = <&audio_codec_bt_sco 1>;
113 }; 81 };
114 }; 82 };
115 83
116 sound-wm8524 { 84 sound-wm8524 {
117 compatible = "fsl,imx-audio-wm 85 compatible = "fsl,imx-audio-wm8524";
118 model = "wm8524-audio"; 86 model = "wm8524-audio";
119 audio-cpu = <&sai3>; 87 audio-cpu = <&sai3>;
120 audio-codec = <&wm8524>; 88 audio-codec = <&wm8524>;
121 audio-asrc = <&easrc>; 89 audio-asrc = <&easrc>;
122 audio-routing = 90 audio-routing =
123 "Line Out Jack", "LINE 91 "Line Out Jack", "LINEVOUTL",
124 "Line Out Jack", "LINE 92 "Line Out Jack", "LINEVOUTR";
125 }; 93 };
126 94
127 spdif_out: spdif-out { <<
128 compatible = "linux,spdif-dit" <<
129 #sound-dai-cells = <0>; <<
130 }; <<
131 <<
132 spdif_in: spdif-in { <<
133 compatible = "linux,spdif-dir" <<
134 #sound-dai-cells = <0>; <<
135 }; <<
136 <<
137 sound-spdif { 95 sound-spdif {
138 compatible = "fsl,imx-audio-sp 96 compatible = "fsl,imx-audio-spdif";
139 model = "imx-spdif"; 97 model = "imx-spdif";
140 audio-cpu = <&spdif1>; !! 98 spdif-controller = <&spdif1>;
141 audio-codec = <&spdif_out>, <& !! 99 spdif-out;
142 }; !! 100 spdif-in;
143 <<
144 sound-micfil { <<
145 compatible = "fsl,imx-audio-ca <<
146 model = "micfil-audio"; <<
147 <<
148 pri-dai-link { <<
149 link-name = "micfil hi <<
150 format = "i2s"; <<
151 <<
152 cpu { <<
153 sound-dai = <& <<
154 }; <<
155 }; <<
156 }; 101 };
157 }; 102 };
158 103
159 &easrc { 104 &easrc {
160 fsl,asrc-rate = <48000>; 105 fsl,asrc-rate = <48000>;
161 status = "okay"; 106 status = "okay";
162 }; 107 };
163 108
164 &fec1 { 109 &fec1 {
165 pinctrl-names = "default"; 110 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec1>; 111 pinctrl-0 = <&pinctrl_fec1>;
167 phy-mode = "rgmii-id"; 112 phy-mode = "rgmii-id";
168 phy-handle = <ðphy0>; 113 phy-handle = <ðphy0>;
169 fsl,magic-packet; 114 fsl,magic-packet;
170 status = "okay"; 115 status = "okay";
171 116
172 mdio { 117 mdio {
173 #address-cells = <1>; 118 #address-cells = <1>;
174 #size-cells = <0>; 119 #size-cells = <0>;
175 120
176 ethphy0: ethernet-phy@0 { 121 ethphy0: ethernet-phy@0 {
177 compatible = "ethernet 122 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <0>; 123 reg = <0>;
179 reset-gpios = <&gpio4 124 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
180 reset-assert-us = <100 125 reset-assert-us = <10000>;
181 qca,disable-smarteee; 126 qca,disable-smarteee;
182 vddio-supply = <&vddio 127 vddio-supply = <&vddio>;
183 128
184 vddio: vddio-regulator 129 vddio: vddio-regulator {
185 regulator-min- 130 regulator-min-microvolt = <1800000>;
186 regulator-max- 131 regulator-max-microvolt = <1800000>;
187 }; 132 };
188 }; 133 };
189 }; 134 };
190 }; 135 };
191 136
192 &flexspi { 137 &flexspi {
193 pinctrl-names = "default"; 138 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_flexspi>; 139 pinctrl-0 = <&pinctrl_flexspi>;
195 status = "okay"; 140 status = "okay";
196 141
197 flash0: flash@0 { 142 flash0: flash@0 {
198 compatible = "jedec,spi-nor"; 143 compatible = "jedec,spi-nor";
199 reg = <0>; 144 reg = <0>;
200 #address-cells = <1>; 145 #address-cells = <1>;
201 #size-cells = <1>; 146 #size-cells = <1>;
202 spi-max-frequency = <166000000 147 spi-max-frequency = <166000000>;
203 spi-tx-bus-width = <4>; 148 spi-tx-bus-width = <4>;
204 spi-rx-bus-width = <4>; 149 spi-rx-bus-width = <4>;
205 }; 150 };
206 }; 151 };
207 152
208 &i2c1 { 153 &i2c1 {
209 clock-frequency = <400000>; 154 clock-frequency = <400000>;
210 pinctrl-names = "default"; 155 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>; 156 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "okay"; 157 status = "okay";
213 }; 158 };
214 159
215 &i2c2 { 160 &i2c2 {
216 clock-frequency = <400000>; 161 clock-frequency = <400000>;
217 pinctrl-names = "default", "gpio"; !! 162 pinctrl-names = "default";
218 pinctrl-0 = <&pinctrl_i2c2>; 163 pinctrl-0 = <&pinctrl_i2c2>;
219 pinctrl-1 = <&pinctrl_i2c2_gpio>; !! 164 status = "okay";
220 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
221 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
222 status = "okay"; <<
223 <<
224 hdmi@3d { <<
225 compatible = "adi,adv7535"; <<
226 reg = <0x3d>; <<
227 interrupt-parent = <&gpio1>; <<
228 interrupts = <9 IRQ_TYPE_EDGE_ <<
229 adi,dsi-lanes = <4>; <<
230 v3p3-supply = <®_vddext_3v3 <<
231 <<
232 ports { <<
233 #address-cells = <1>; <<
234 #size-cells = <0>; <<
235 <<
236 port@0 { <<
237 reg = <0>; <<
238 <<
239 adv7535_in: en <<
240 remote <<
241 }; <<
242 }; <<
243 <<
244 port@1 { <<
245 reg = <1>; <<
246 <<
247 adv7535_out: e <<
248 remote <<
249 }; <<
250 }; <<
251 <<
252 }; <<
253 }; <<
254 165
255 ptn5110: tcpc@50 { 166 ptn5110: tcpc@50 {
256 compatible = "nxp,ptn5110", "t !! 167 compatible = "nxp,ptn5110";
257 pinctrl-names = "default"; 168 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_typec1>; 169 pinctrl-0 = <&pinctrl_typec1>;
259 reg = <0x50>; 170 reg = <0x50>;
260 interrupt-parent = <&gpio2>; 171 interrupt-parent = <&gpio2>;
261 interrupts = <11 IRQ_TYPE_LEVE 172 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
262 status = "okay"; 173 status = "okay";
263 174
>> 175 port {
>> 176 typec1_dr_sw: endpoint {
>> 177 remote-endpoint = <&usb1_drd_sw>;
>> 178 };
>> 179 };
>> 180
264 typec1_con: connector { 181 typec1_con: connector {
265 compatible = "usb-c-co 182 compatible = "usb-c-connector";
266 label = "USB-C"; 183 label = "USB-C";
267 power-role = "dual"; 184 power-role = "dual";
268 data-role = "dual"; 185 data-role = "dual";
269 try-power-role = "sink 186 try-power-role = "sink";
270 source-pdos = <PDO_FIX 187 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
271 sink-pdos = <PDO_FIXED 188 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
272 PDO_VAR(5 189 PDO_VAR(5000, 20000, 3000)>;
273 op-sink-microwatt = <1 190 op-sink-microwatt = <15000000>;
274 self-powered; 191 self-powered;
275 <<
276 port { <<
277 typec1_dr_sw: <<
278 remote <<
279 }; <<
280 }; <<
281 }; 192 };
282 }; 193 };
283 }; 194 };
284 195
285 &i2c3 { 196 &i2c3 {
286 clock-frequency = <400000>; 197 clock-frequency = <400000>;
287 pinctrl-names = "default", "gpio"; !! 198 pinctrl-names = "default";
288 pinctrl-0 = <&pinctrl_i2c3>; 199 pinctrl-0 = <&pinctrl_i2c3>;
289 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
290 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIG <<
291 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIG <<
292 status = "okay"; 200 status = "okay";
293 201
294 pca6416: gpio@20 { 202 pca6416: gpio@20 {
295 compatible = "ti,tca6416"; 203 compatible = "ti,tca6416";
296 reg = <0x20>; 204 reg = <0x20>;
297 gpio-controller; 205 gpio-controller;
298 #gpio-cells = <2>; 206 #gpio-cells = <2>;
299 }; 207 };
300 <<
301 camera@3c { <<
302 compatible = "ovti,ov5640"; <<
303 reg = <0x3c>; <<
304 pinctrl-names = "default"; <<
305 pinctrl-0 = <&pinctrl_camera>; <<
306 clocks = <&clk IMX8MN_CLK_CLKO <<
307 clock-names = "xclk"; <<
308 assigned-clocks = <&clk IMX8MN <<
309 assigned-clock-parents = <&clk <<
310 assigned-clock-rates = <240000 <<
311 powerdown-gpios = <&gpio1 7 GP <<
312 reset-gpios = <&gpio1 6 GPIO_A <<
313 AVDD-supply = <®_1v8>; <<
314 DVDD-supply = <®_1v5>; <<
315 <<
316 port { <<
317 ov5640_to_mipi_csi2: e <<
318 remote-endpoin <<
319 clock-lanes = <<
320 data-lanes = < <<
321 }; <<
322 }; <<
323 }; <<
324 }; <<
325 <<
326 &isi { <<
327 status = "okay"; <<
328 }; <<
329 <<
330 &micfil { <<
331 #sound-dai-cells = <0>; <<
332 pinctrl-names = "default"; <<
333 pinctrl-0 = <&pinctrl_pdm>; <<
334 assigned-clocks = <&clk IMX8MN_CLK_PDM <<
335 assigned-clock-parents = <&clk IMX8MN_ <<
336 assigned-clock-rates = <196608000>; <<
337 status = "okay"; <<
338 }; <<
339 <<
340 &mipi_csi { <<
341 status = "okay"; <<
342 <<
343 ports { <<
344 port@0 { <<
345 imx8mn_mipi_csi_in: en <<
346 remote-endpoin <<
347 data-lanes = < <<
348 }; <<
349 }; <<
350 }; <<
351 }; <<
352 <<
353 &lcdif { <<
354 status = "okay"; <<
355 }; <<
356 <<
357 &mipi_dsi { <<
358 samsung,esc-clock-frequency = <1000000 <<
359 status = "okay"; <<
360 <<
361 ports { <<
362 port@1 { <<
363 reg = <1>; <<
364 <<
365 dsi_out: endpoint { <<
366 remote-endpoin <<
367 data-lanes = < <<
368 }; <<
369 }; <<
370 }; <<
371 }; 208 };
372 209
373 &sai2 { 210 &sai2 {
374 #sound-dai-cells = <0>; 211 #sound-dai-cells = <0>;
375 pinctrl-names = "default"; 212 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_sai2>; 213 pinctrl-0 = <&pinctrl_sai2>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI 214 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
378 assigned-clock-parents = <&clk IMX8MN_ 215 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
379 assigned-clock-rates = <24576000>; 216 assigned-clock-rates = <24576000>;
380 status = "okay"; 217 status = "okay";
381 }; 218 };
382 219
383 &sai3 { 220 &sai3 {
384 pinctrl-names = "default"; 221 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_sai3>; 222 pinctrl-0 = <&pinctrl_sai3>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI 223 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
387 assigned-clock-parents = <&clk IMX8MN_ 224 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
388 assigned-clock-rates = <24576000>; 225 assigned-clock-rates = <24576000>;
389 fsl,sai-mclk-direction-output; 226 fsl,sai-mclk-direction-output;
390 status = "okay"; 227 status = "okay";
391 }; 228 };
392 229
393 &snvs_pwrkey { 230 &snvs_pwrkey {
394 status = "okay"; 231 status = "okay";
395 }; 232 };
396 233
397 &spdif1 { 234 &spdif1 {
398 pinctrl-names = "default"; 235 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_spdif1>; 236 pinctrl-0 = <&pinctrl_spdif1>;
400 assigned-clocks = <&clk IMX8MN_CLK_SPD 237 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
401 assigned-clock-parents = <&clk IMX8MN_ 238 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
402 assigned-clock-rates = <24576000>; 239 assigned-clock-rates = <24576000>;
403 status = "okay"; 240 status = "okay";
404 }; 241 };
405 242
406 &uart1 { /* BT */ <<
407 pinctrl-names = "default"; <<
408 pinctrl-0 = <&pinctrl_uart1>; <<
409 assigned-clocks = <&clk IMX8MN_CLK_UAR <<
410 assigned-clock-parents = <&clk IMX8MN_ <<
411 uart-has-rtscts; <<
412 status = "okay"; <<
413 }; <<
414 <<
415 &uart2 { /* console */ 243 &uart2 { /* console */
416 pinctrl-names = "default"; 244 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart2>; 245 pinctrl-0 = <&pinctrl_uart2>;
418 status = "okay"; 246 status = "okay";
419 }; 247 };
420 248
421 &uart3 { 249 &uart3 {
422 pinctrl-names = "default"; 250 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_uart3>; 251 pinctrl-0 = <&pinctrl_uart3>;
424 assigned-clocks = <&clk IMX8MN_CLK_UAR 252 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
425 assigned-clock-parents = <&clk IMX8MN_ 253 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
426 uart-has-rtscts; 254 uart-has-rtscts;
427 status = "okay"; 255 status = "okay";
428 }; 256 };
429 257
430 &usbphynop1 { <<
431 wakeup-source; <<
432 }; <<
433 <<
434 &usbotg1 { 258 &usbotg1 {
435 dr_mode = "otg"; 259 dr_mode = "otg";
436 hnp-disable; 260 hnp-disable;
437 srp-disable; 261 srp-disable;
438 adp-disable; 262 adp-disable;
439 usb-role-switch; 263 usb-role-switch;
440 disable-over-current; 264 disable-over-current;
441 samsung,picophy-pre-emp-curr-control = 265 samsung,picophy-pre-emp-curr-control = <3>;
442 samsung,picophy-dc-vol-level-adjust = 266 samsung,picophy-dc-vol-level-adjust = <7>;
443 status = "okay"; 267 status = "okay";
444 268
445 port { 269 port {
446 usb1_drd_sw: endpoint { 270 usb1_drd_sw: endpoint {
447 remote-endpoint = <&ty 271 remote-endpoint = <&typec1_dr_sw>;
448 }; 272 };
449 }; 273 };
450 }; 274 };
451 275
452 &usdhc2 { 276 &usdhc2 {
453 assigned-clocks = <&clk IMX8MN_CLK_USD 277 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
454 assigned-clock-rates = <200000000>; 278 assigned-clock-rates = <200000000>;
455 pinctrl-names = "default", "state_100m 279 pinctrl-names = "default", "state_100mhz", "state_200mhz";
456 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 280 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
457 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 281 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
458 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 282 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
459 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 283 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
460 bus-width = <4>; 284 bus-width = <4>;
461 vmmc-supply = <®_usdhc2_vmmc>; 285 vmmc-supply = <®_usdhc2_vmmc>;
462 status = "okay"; 286 status = "okay";
463 }; 287 };
464 288
465 &usdhc3 { 289 &usdhc3 {
466 assigned-clocks = <&clk IMX8MN_CLK_USD 290 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
467 assigned-clock-rates = <400000000>; 291 assigned-clock-rates = <400000000>;
468 pinctrl-names = "default", "state_100m 292 pinctrl-names = "default", "state_100mhz", "state_200mhz";
469 pinctrl-0 = <&pinctrl_usdhc3>; 293 pinctrl-0 = <&pinctrl_usdhc3>;
470 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 294 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
471 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 295 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
472 bus-width = <8>; 296 bus-width = <8>;
473 non-removable; 297 non-removable;
474 status = "okay"; 298 status = "okay";
475 }; 299 };
476 300
477 &wdog1 { 301 &wdog1 {
478 pinctrl-names = "default"; 302 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_wdog>; 303 pinctrl-0 = <&pinctrl_wdog>;
480 fsl,ext-reset-output; 304 fsl,ext-reset-output;
481 status = "okay"; 305 status = "okay";
482 }; 306 };
483 307
484 &iomuxc { 308 &iomuxc {
485 pinctrl_camera: cameragrp { <<
486 fsl,pins = < <<
487 MX8MN_IOMUXC_GPIO1_IO0 <<
488 MX8MN_IOMUXC_GPIO1_IO0 <<
489 MX8MN_IOMUXC_GPIO1_IO1 <<
490 >; <<
491 }; <<
492 <<
493 pinctrl_fec1: fec1grp { 309 pinctrl_fec1: fec1grp {
494 fsl,pins = < 310 fsl,pins = <
495 MX8MN_IOMUXC_ENET_MDC_ 311 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
496 MX8MN_IOMUXC_ENET_MDIO 312 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
497 MX8MN_IOMUXC_ENET_TD3_ 313 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
498 MX8MN_IOMUXC_ENET_TD2_ 314 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
499 MX8MN_IOMUXC_ENET_TD1_ 315 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
500 MX8MN_IOMUXC_ENET_TD0_ 316 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
501 MX8MN_IOMUXC_ENET_RD3_ 317 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
502 MX8MN_IOMUXC_ENET_RD2_ 318 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
503 MX8MN_IOMUXC_ENET_RD1_ 319 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
504 MX8MN_IOMUXC_ENET_RD0_ 320 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
505 MX8MN_IOMUXC_ENET_TXC_ 321 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
506 MX8MN_IOMUXC_ENET_RXC_ 322 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
507 MX8MN_IOMUXC_ENET_RX_C 323 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
508 MX8MN_IOMUXC_ENET_TX_C 324 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
509 MX8MN_IOMUXC_SAI2_RXC_ 325 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
510 >; 326 >;
511 }; 327 };
512 328
513 pinctrl_flexspi: flexspigrp { 329 pinctrl_flexspi: flexspigrp {
514 fsl,pins = < 330 fsl,pins = <
515 MX8MN_IOMUXC_NAND_ALE_ 331 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
516 MX8MN_IOMUXC_NAND_CE0_ 332 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
517 MX8MN_IOMUXC_NAND_DATA 333 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
518 MX8MN_IOMUXC_NAND_DATA 334 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
519 MX8MN_IOMUXC_NAND_DATA 335 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
520 MX8MN_IOMUXC_NAND_DATA 336 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
521 >; 337 >;
522 }; 338 };
523 339
524 pinctrl_gpio_led: gpioledgrp { 340 pinctrl_gpio_led: gpioledgrp {
525 fsl,pins = < 341 fsl,pins = <
526 MX8MN_IOMUXC_NAND_READ 342 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
527 >; 343 >;
528 }; 344 };
529 345
530 pinctrl_gpio_wlf: gpiowlfgrp { 346 pinctrl_gpio_wlf: gpiowlfgrp {
531 fsl,pins = < 347 fsl,pins = <
532 MX8MN_IOMUXC_I2C4_SDA_ 348 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
533 >; 349 >;
534 }; 350 };
535 351
536 pinctrl_ir: irgrp { 352 pinctrl_ir: irgrp {
537 fsl,pins = < 353 fsl,pins = <
538 MX8MN_IOMUXC_GPIO1_IO1 354 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
539 >; 355 >;
540 }; 356 };
541 357
542 pinctrl_i2c1: i2c1grp { 358 pinctrl_i2c1: i2c1grp {
543 fsl,pins = < 359 fsl,pins = <
544 MX8MN_IOMUXC_I2C1_SCL_ 360 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
545 MX8MN_IOMUXC_I2C1_SDA_ 361 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
546 >; 362 >;
547 }; 363 };
548 364
549 pinctrl_i2c2: i2c2grp { 365 pinctrl_i2c2: i2c2grp {
550 fsl,pins = < 366 fsl,pins = <
551 MX8MN_IOMUXC_I2C2_SCL_ 367 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
552 MX8MN_IOMUXC_I2C2_SDA_ 368 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
553 >; 369 >;
554 }; 370 };
555 371
556 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
557 fsl,pins = < <<
558 MX8MN_IOMUXC_I2C2_SCL_ <<
559 MX8MN_IOMUXC_I2C2_SDA_ <<
560 >; <<
561 }; <<
562 <<
563 pinctrl_i2c3: i2c3grp { 372 pinctrl_i2c3: i2c3grp {
564 fsl,pins = < 373 fsl,pins = <
565 MX8MN_IOMUXC_I2C3_SCL_ 374 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
566 MX8MN_IOMUXC_I2C3_SDA_ 375 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
567 >; 376 >;
568 }; 377 };
569 378
570 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
571 fsl,pins = < <<
572 MX8MN_IOMUXC_I2C3_SCL_ <<
573 MX8MN_IOMUXC_I2C3_SDA_ <<
574 >; <<
575 }; <<
576 <<
577 pinctrl_pdm: pdmgrp { <<
578 fsl,pins = < <<
579 MX8MN_IOMUXC_SAI5_MCLK <<
580 MX8MN_IOMUXC_SAI5_RXC_ <<
581 MX8MN_IOMUXC_SAI5_RXFS <<
582 MX8MN_IOMUXC_SAI5_RXD0 <<
583 MX8MN_IOMUXC_SAI5_RXD1 <<
584 MX8MN_IOMUXC_SAI5_RXD2 <<
585 MX8MN_IOMUXC_SAI5_RXD3 <<
586 >; <<
587 }; <<
588 <<
589 pinctrl_pmic: pmicirqgrp { 379 pinctrl_pmic: pmicirqgrp {
590 fsl,pins = < 380 fsl,pins = <
591 MX8MN_IOMUXC_GPIO1_IO0 381 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
592 >; 382 >;
593 }; 383 };
594 384
595 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 385 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
596 fsl,pins = < 386 fsl,pins = <
597 MX8MN_IOMUXC_SD2_RESET 387 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
598 >; 388 >;
599 }; 389 };
600 390
601 pinctrl_sai2: sai2grp { 391 pinctrl_sai2: sai2grp {
602 fsl,pins = < 392 fsl,pins = <
603 MX8MN_IOMUXC_SAI2_TXC_ 393 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
604 MX8MN_IOMUXC_SAI2_TXFS 394 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
605 MX8MN_IOMUXC_SAI2_TXD0 395 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
606 MX8MN_IOMUXC_SAI2_RXD0 396 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
607 >; 397 >;
608 }; 398 };
609 399
610 pinctrl_sai3: sai3grp { 400 pinctrl_sai3: sai3grp {
611 fsl,pins = < 401 fsl,pins = <
612 MX8MN_IOMUXC_SAI3_TXFS 402 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
613 MX8MN_IOMUXC_SAI3_TXC_ 403 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
614 MX8MN_IOMUXC_SAI3_MCLK 404 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
615 MX8MN_IOMUXC_SAI3_TXD_ 405 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
616 >; 406 >;
617 }; 407 };
618 408
619 pinctrl_spdif1: spdif1grp { 409 pinctrl_spdif1: spdif1grp {
620 fsl,pins = < 410 fsl,pins = <
621 MX8MN_IOMUXC_SPDIF_TX_ 411 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
622 MX8MN_IOMUXC_SPDIF_RX_ 412 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
623 >; 413 >;
624 }; 414 };
625 415
626 pinctrl_typec1: typec1grp { 416 pinctrl_typec1: typec1grp {
627 fsl,pins = < 417 fsl,pins = <
628 MX8MN_IOMUXC_SD1_STROB 418 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
629 >; <<
630 }; <<
631 <<
632 pinctrl_uart1: uart1grp { <<
633 fsl,pins = < <<
634 MX8MN_IOMUXC_UART1_RXD <<
635 MX8MN_IOMUXC_UART1_TXD <<
636 MX8MN_IOMUXC_UART3_RXD <<
637 MX8MN_IOMUXC_UART3_TXD <<
638 >; 419 >;
639 }; 420 };
640 421
641 pinctrl_uart2: uart2grp { 422 pinctrl_uart2: uart2grp {
642 fsl,pins = < 423 fsl,pins = <
643 MX8MN_IOMUXC_UART2_RXD 424 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
644 MX8MN_IOMUXC_UART2_TXD 425 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
645 >; 426 >;
646 }; 427 };
647 428
648 pinctrl_uart3: uart3grp { 429 pinctrl_uart3: uart3grp {
649 fsl,pins = < 430 fsl,pins = <
650 MX8MN_IOMUXC_ECSPI1_SC 431 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
651 MX8MN_IOMUXC_ECSPI1_MO 432 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
652 MX8MN_IOMUXC_ECSPI1_SS 433 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
653 MX8MN_IOMUXC_ECSPI1_MI 434 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
654 >; 435 >;
655 }; 436 };
656 437
657 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 438 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
658 fsl,pins = < 439 fsl,pins = <
659 MX8MN_IOMUXC_GPIO1_IO1 440 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
660 >; 441 >;
661 }; 442 };
662 443
663 pinctrl_usdhc2: usdhc2grp { 444 pinctrl_usdhc2: usdhc2grp {
664 fsl,pins = < 445 fsl,pins = <
665 MX8MN_IOMUXC_SD2_CLK_U 446 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
666 MX8MN_IOMUXC_SD2_CMD_U 447 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
667 MX8MN_IOMUXC_SD2_DATA0 448 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
668 MX8MN_IOMUXC_SD2_DATA1 449 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
669 MX8MN_IOMUXC_SD2_DATA2 450 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
670 MX8MN_IOMUXC_SD2_DATA3 451 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
671 MX8MN_IOMUXC_GPIO1_IO0 452 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
672 >; 453 >;
673 }; 454 };
674 455
675 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 456 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
676 fsl,pins = < 457 fsl,pins = <
677 MX8MN_IOMUXC_SD2_CLK_U 458 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
678 MX8MN_IOMUXC_SD2_CMD_U 459 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
679 MX8MN_IOMUXC_SD2_DATA0 460 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
680 MX8MN_IOMUXC_SD2_DATA1 461 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
681 MX8MN_IOMUXC_SD2_DATA2 462 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
682 MX8MN_IOMUXC_SD2_DATA3 463 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
683 MX8MN_IOMUXC_GPIO1_IO0 464 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
684 >; 465 >;
685 }; 466 };
686 467
687 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 468 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
688 fsl,pins = < 469 fsl,pins = <
689 MX8MN_IOMUXC_SD2_CLK_U 470 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
690 MX8MN_IOMUXC_SD2_CMD_U 471 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
691 MX8MN_IOMUXC_SD2_DATA0 472 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
692 MX8MN_IOMUXC_SD2_DATA1 473 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
693 MX8MN_IOMUXC_SD2_DATA2 474 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
694 MX8MN_IOMUXC_SD2_DATA3 475 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
695 MX8MN_IOMUXC_GPIO1_IO0 476 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
696 >; 477 >;
697 }; 478 };
698 479
699 pinctrl_usdhc3: usdhc3grp { 480 pinctrl_usdhc3: usdhc3grp {
700 fsl,pins = < 481 fsl,pins = <
701 MX8MN_IOMUXC_NAND_WE_B 482 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
702 MX8MN_IOMUXC_NAND_WP_B 483 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
703 MX8MN_IOMUXC_NAND_DATA 484 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
704 MX8MN_IOMUXC_NAND_DATA 485 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
705 MX8MN_IOMUXC_NAND_DATA 486 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
706 MX8MN_IOMUXC_NAND_DATA 487 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
707 MX8MN_IOMUXC_NAND_RE_B 488 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
708 MX8MN_IOMUXC_NAND_CE2_ 489 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
709 MX8MN_IOMUXC_NAND_CE3_ 490 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
710 MX8MN_IOMUXC_NAND_CLE_ 491 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
711 MX8MN_IOMUXC_NAND_CE1_ 492 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
712 >; 493 >;
713 }; 494 };
714 495
715 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 496 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
716 fsl,pins = < 497 fsl,pins = <
717 MX8MN_IOMUXC_NAND_WE_B 498 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
718 MX8MN_IOMUXC_NAND_WP_B 499 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
719 MX8MN_IOMUXC_NAND_DATA 500 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
720 MX8MN_IOMUXC_NAND_DATA 501 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
721 MX8MN_IOMUXC_NAND_DATA 502 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
722 MX8MN_IOMUXC_NAND_DATA 503 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
723 MX8MN_IOMUXC_NAND_RE_B 504 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
724 MX8MN_IOMUXC_NAND_CE2_ 505 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
725 MX8MN_IOMUXC_NAND_CE3_ 506 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
726 MX8MN_IOMUXC_NAND_CLE_ 507 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
727 MX8MN_IOMUXC_NAND_CE1_ 508 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
728 >; 509 >;
729 }; 510 };
730 511
731 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 512 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
732 fsl,pins = < 513 fsl,pins = <
733 MX8MN_IOMUXC_NAND_WE_B 514 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
734 MX8MN_IOMUXC_NAND_WP_B 515 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
735 MX8MN_IOMUXC_NAND_DATA 516 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
736 MX8MN_IOMUXC_NAND_DATA 517 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
737 MX8MN_IOMUXC_NAND_DATA 518 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
738 MX8MN_IOMUXC_NAND_DATA 519 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
739 MX8MN_IOMUXC_NAND_RE_B 520 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
740 MX8MN_IOMUXC_NAND_CE2_ 521 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
741 MX8MN_IOMUXC_NAND_CE3_ 522 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
742 MX8MN_IOMUXC_NAND_CLE_ 523 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
743 MX8MN_IOMUXC_NAND_CE1_ 524 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
744 >; 525 >;
745 }; 526 };
746 527
747 pinctrl_wdog: wdoggrp { 528 pinctrl_wdog: wdoggrp {
748 fsl,pins = < 529 fsl,pins = <
749 MX8MN_IOMUXC_GPIO1_IO0 530 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
750 >; 531 >;
751 }; 532 };
752 }; 533 };
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