1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/usb/pd.h> 6 #include <dt-bindings/usb/pd.h>
7 #include "imx8mn.dtsi" 7 #include "imx8mn.dtsi"
8 8
9 / { 9 / {
10 chosen { 10 chosen {
11 stdout-path = &uart2; 11 stdout-path = &uart2;
12 }; 12 };
13 13
14 gpio-leds { 14 gpio-leds {
15 compatible = "gpio-leds"; 15 compatible = "gpio-leds";
16 pinctrl-names = "default"; 16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led 17 pinctrl-0 = <&pinctrl_gpio_led>;
18 18
19 status { 19 status {
20 label = "yellow:status 20 label = "yellow:status";
21 gpios = <&gpio3 16 GPI 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on"; 22 default-state = "on";
23 }; 23 };
24 }; 24 };
25 25
26 hdmi-connector { <<
27 compatible = "hdmi-connector"; <<
28 label = "hdmi"; <<
29 type = "a"; <<
30 <<
31 port { <<
32 hdmi_connector_in: end <<
33 remote-endpoin <<
34 }; <<
35 }; <<
36 }; <<
37 <<
38 memory@40000000 { 26 memory@40000000 {
39 device_type = "memory"; 27 device_type = "memory";
40 reg = <0x0 0x40000000 0 0x8000 28 reg = <0x0 0x40000000 0 0x80000000>;
41 }; 29 };
42 30
43 reg_usdhc2_vmmc: regulator-usdhc2 { 31 reg_usdhc2_vmmc: regulator-usdhc2 {
44 compatible = "regulator-fixed" 32 compatible = "regulator-fixed";
45 pinctrl-names = "default"; 33 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usdh 34 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
47 regulator-name = "VSD_3V3"; 35 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <330 36 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <330 37 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio2 19 GPIO_ACTIVE_ 38 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51 off-on-delay-us = <12000>; 39 off-on-delay-us = <12000>;
52 enable-active-high; 40 enable-active-high;
53 }; 41 };
54 42
55 reg_1v5: regulator-1v5 { <<
56 compatible = "regulator-fixed" <<
57 regulator-name = "VDD_1V5"; <<
58 regulator-min-microvolt = <150 <<
59 regulator-max-microvolt = <150 <<
60 }; <<
61 <<
62 reg_1v8: regulator-1v8 { <<
63 compatible = "regulator-fixed" <<
64 regulator-name = "VDD_1V8"; <<
65 regulator-min-microvolt = <180 <<
66 regulator-max-microvolt = <180 <<
67 }; <<
68 <<
69 reg_vddext_3v3: regulator-vddext-3v3 { <<
70 compatible = "regulator-fixed" <<
71 regulator-name = "VDDEXT_3V3"; <<
72 regulator-min-microvolt = <330 <<
73 regulator-max-microvolt = <330 <<
74 }; <<
75 <<
76 ir-receiver { 43 ir-receiver {
77 compatible = "gpio-ir-receiver 44 compatible = "gpio-ir-receiver";
78 gpios = <&gpio1 13 GPIO_ACTIVE 45 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
79 pinctrl-names = "default"; 46 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_ir>; 47 pinctrl-0 = <&pinctrl_ir>;
81 linux,autosuspend-period = <12 48 linux,autosuspend-period = <125>;
82 }; 49 };
83 50
84 audio_codec_bt_sco: audio-codec-bt-sco 51 audio_codec_bt_sco: audio-codec-bt-sco {
85 compatible = "linux,bt-sco"; 52 compatible = "linux,bt-sco";
86 #sound-dai-cells = <1>; 53 #sound-dai-cells = <1>;
87 }; 54 };
88 55
89 wm8524: audio-codec { 56 wm8524: audio-codec {
90 #sound-dai-cells = <0>; 57 #sound-dai-cells = <0>;
91 compatible = "wlf,wm8524"; 58 compatible = "wlf,wm8524";
92 pinctrl-names = "default"; 59 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gpio_wlf 60 pinctrl-0 = <&pinctrl_gpio_wlf>;
94 wlf,mute-gpios = <&gpio5 21 GP 61 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
>> 62 clocks = <&clk IMX8MN_CLK_SAI3_ROOT>;
>> 63 clock-names = "mclk";
95 }; 64 };
96 65
97 sound-bt-sco { 66 sound-bt-sco {
98 compatible = "simple-audio-car 67 compatible = "simple-audio-card";
99 simple-audio-card,name = "bt-s 68 simple-audio-card,name = "bt-sco-audio";
100 simple-audio-card,format = "ds 69 simple-audio-card,format = "dsp_a";
101 simple-audio-card,bitclock-inv 70 simple-audio-card,bitclock-inversion;
102 simple-audio-card,frame-master 71 simple-audio-card,frame-master = <&btcpu>;
103 simple-audio-card,bitclock-mas 72 simple-audio-card,bitclock-master = <&btcpu>;
104 73
105 btcpu: simple-audio-card,cpu { 74 btcpu: simple-audio-card,cpu {
106 sound-dai = <&sai2>; 75 sound-dai = <&sai2>;
107 dai-tdm-slot-num = <2> 76 dai-tdm-slot-num = <2>;
108 dai-tdm-slot-width = < 77 dai-tdm-slot-width = <16>;
109 }; 78 };
110 79
111 simple-audio-card,codec { 80 simple-audio-card,codec {
112 sound-dai = <&audio_co 81 sound-dai = <&audio_codec_bt_sco 1>;
113 }; 82 };
114 }; 83 };
115 84
116 sound-wm8524 { 85 sound-wm8524 {
117 compatible = "fsl,imx-audio-wm 86 compatible = "fsl,imx-audio-wm8524";
118 model = "wm8524-audio"; 87 model = "wm8524-audio";
119 audio-cpu = <&sai3>; 88 audio-cpu = <&sai3>;
120 audio-codec = <&wm8524>; 89 audio-codec = <&wm8524>;
121 audio-asrc = <&easrc>; 90 audio-asrc = <&easrc>;
122 audio-routing = 91 audio-routing =
123 "Line Out Jack", "LINE 92 "Line Out Jack", "LINEVOUTL",
124 "Line Out Jack", "LINE 93 "Line Out Jack", "LINEVOUTR";
125 }; 94 };
126 95
127 spdif_out: spdif-out { <<
128 compatible = "linux,spdif-dit" <<
129 #sound-dai-cells = <0>; <<
130 }; <<
131 <<
132 spdif_in: spdif-in { <<
133 compatible = "linux,spdif-dir" <<
134 #sound-dai-cells = <0>; <<
135 }; <<
136 <<
137 sound-spdif { 96 sound-spdif {
138 compatible = "fsl,imx-audio-sp 97 compatible = "fsl,imx-audio-spdif";
139 model = "imx-spdif"; 98 model = "imx-spdif";
140 audio-cpu = <&spdif1>; !! 99 spdif-controller = <&spdif1>;
141 audio-codec = <&spdif_out>, <& !! 100 spdif-out;
142 }; !! 101 spdif-in;
143 <<
144 sound-micfil { <<
145 compatible = "fsl,imx-audio-ca <<
146 model = "micfil-audio"; <<
147 <<
148 pri-dai-link { <<
149 link-name = "micfil hi <<
150 format = "i2s"; <<
151 <<
152 cpu { <<
153 sound-dai = <& <<
154 }; <<
155 }; <<
156 }; 102 };
157 }; 103 };
158 104
159 &easrc { 105 &easrc {
160 fsl,asrc-rate = <48000>; 106 fsl,asrc-rate = <48000>;
161 status = "okay"; 107 status = "okay";
162 }; 108 };
163 109
164 &fec1 { 110 &fec1 {
165 pinctrl-names = "default"; 111 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec1>; 112 pinctrl-0 = <&pinctrl_fec1>;
167 phy-mode = "rgmii-id"; 113 phy-mode = "rgmii-id";
168 phy-handle = <ðphy0>; 114 phy-handle = <ðphy0>;
169 fsl,magic-packet; 115 fsl,magic-packet;
170 status = "okay"; 116 status = "okay";
171 117
172 mdio { 118 mdio {
173 #address-cells = <1>; 119 #address-cells = <1>;
174 #size-cells = <0>; 120 #size-cells = <0>;
175 121
176 ethphy0: ethernet-phy@0 { 122 ethphy0: ethernet-phy@0 {
177 compatible = "ethernet 123 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <0>; 124 reg = <0>;
179 reset-gpios = <&gpio4 125 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
180 reset-assert-us = <100 126 reset-assert-us = <10000>;
181 qca,disable-smarteee; 127 qca,disable-smarteee;
182 vddio-supply = <&vddio 128 vddio-supply = <&vddio>;
183 129
184 vddio: vddio-regulator 130 vddio: vddio-regulator {
185 regulator-min- 131 regulator-min-microvolt = <1800000>;
186 regulator-max- 132 regulator-max-microvolt = <1800000>;
187 }; 133 };
188 }; 134 };
189 }; 135 };
190 }; 136 };
191 137
192 &flexspi { 138 &flexspi {
193 pinctrl-names = "default"; 139 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_flexspi>; 140 pinctrl-0 = <&pinctrl_flexspi>;
195 status = "okay"; 141 status = "okay";
196 142
197 flash0: flash@0 { 143 flash0: flash@0 {
198 compatible = "jedec,spi-nor"; 144 compatible = "jedec,spi-nor";
199 reg = <0>; 145 reg = <0>;
200 #address-cells = <1>; 146 #address-cells = <1>;
201 #size-cells = <1>; 147 #size-cells = <1>;
202 spi-max-frequency = <166000000 148 spi-max-frequency = <166000000>;
203 spi-tx-bus-width = <4>; 149 spi-tx-bus-width = <4>;
204 spi-rx-bus-width = <4>; 150 spi-rx-bus-width = <4>;
205 }; 151 };
206 }; 152 };
207 153
208 &i2c1 { 154 &i2c1 {
209 clock-frequency = <400000>; 155 clock-frequency = <400000>;
210 pinctrl-names = "default"; 156 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>; 157 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "okay"; 158 status = "okay";
213 }; 159 };
214 160
215 &i2c2 { 161 &i2c2 {
216 clock-frequency = <400000>; 162 clock-frequency = <400000>;
217 pinctrl-names = "default", "gpio"; 163 pinctrl-names = "default", "gpio";
218 pinctrl-0 = <&pinctrl_i2c2>; 164 pinctrl-0 = <&pinctrl_i2c2>;
219 pinctrl-1 = <&pinctrl_i2c2_gpio>; 165 pinctrl-1 = <&pinctrl_i2c2_gpio>;
220 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI !! 166 scl-gpios = <&gpio5 16 GPIO_ACTIVE_HIGH>;
221 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI !! 167 sda-gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>;
222 status = "okay"; 168 status = "okay";
223 169
224 hdmi@3d { <<
225 compatible = "adi,adv7535"; <<
226 reg = <0x3d>; <<
227 interrupt-parent = <&gpio1>; <<
228 interrupts = <9 IRQ_TYPE_EDGE_ <<
229 adi,dsi-lanes = <4>; <<
230 v3p3-supply = <®_vddext_3v3 <<
231 <<
232 ports { <<
233 #address-cells = <1>; <<
234 #size-cells = <0>; <<
235 <<
236 port@0 { <<
237 reg = <0>; <<
238 <<
239 adv7535_in: en <<
240 remote <<
241 }; <<
242 }; <<
243 <<
244 port@1 { <<
245 reg = <1>; <<
246 <<
247 adv7535_out: e <<
248 remote <<
249 }; <<
250 }; <<
251 <<
252 }; <<
253 }; <<
254 <<
255 ptn5110: tcpc@50 { 170 ptn5110: tcpc@50 {
256 compatible = "nxp,ptn5110", "t !! 171 compatible = "nxp,ptn5110";
257 pinctrl-names = "default"; 172 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_typec1>; 173 pinctrl-0 = <&pinctrl_typec1>;
259 reg = <0x50>; 174 reg = <0x50>;
260 interrupt-parent = <&gpio2>; 175 interrupt-parent = <&gpio2>;
261 interrupts = <11 IRQ_TYPE_LEVE 176 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
262 status = "okay"; 177 status = "okay";
263 178
>> 179 port {
>> 180 typec1_dr_sw: endpoint {
>> 181 remote-endpoint = <&usb1_drd_sw>;
>> 182 };
>> 183 };
>> 184
264 typec1_con: connector { 185 typec1_con: connector {
265 compatible = "usb-c-co 186 compatible = "usb-c-connector";
266 label = "USB-C"; 187 label = "USB-C";
267 power-role = "dual"; 188 power-role = "dual";
268 data-role = "dual"; 189 data-role = "dual";
269 try-power-role = "sink 190 try-power-role = "sink";
270 source-pdos = <PDO_FIX 191 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
271 sink-pdos = <PDO_FIXED 192 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
272 PDO_VAR(5 193 PDO_VAR(5000, 20000, 3000)>;
273 op-sink-microwatt = <1 194 op-sink-microwatt = <15000000>;
274 self-powered; 195 self-powered;
275 <<
276 port { <<
277 typec1_dr_sw: <<
278 remote <<
279 }; <<
280 }; <<
281 }; 196 };
282 }; 197 };
283 }; 198 };
284 199
285 &i2c3 { 200 &i2c3 {
286 clock-frequency = <400000>; 201 clock-frequency = <400000>;
287 pinctrl-names = "default", "gpio"; 202 pinctrl-names = "default", "gpio";
288 pinctrl-0 = <&pinctrl_i2c3>; 203 pinctrl-0 = <&pinctrl_i2c3>;
289 pinctrl-1 = <&pinctrl_i2c3_gpio>; 204 pinctrl-1 = <&pinctrl_i2c3_gpio>;
290 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIG 205 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
291 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIG 206 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
292 status = "okay"; 207 status = "okay";
293 208
294 pca6416: gpio@20 { 209 pca6416: gpio@20 {
295 compatible = "ti,tca6416"; 210 compatible = "ti,tca6416";
296 reg = <0x20>; 211 reg = <0x20>;
297 gpio-controller; 212 gpio-controller;
298 #gpio-cells = <2>; 213 #gpio-cells = <2>;
299 }; 214 };
300 <<
301 camera@3c { <<
302 compatible = "ovti,ov5640"; <<
303 reg = <0x3c>; <<
304 pinctrl-names = "default"; <<
305 pinctrl-0 = <&pinctrl_camera>; <<
306 clocks = <&clk IMX8MN_CLK_CLKO <<
307 clock-names = "xclk"; <<
308 assigned-clocks = <&clk IMX8MN <<
309 assigned-clock-parents = <&clk <<
310 assigned-clock-rates = <240000 <<
311 powerdown-gpios = <&gpio1 7 GP <<
312 reset-gpios = <&gpio1 6 GPIO_A <<
313 AVDD-supply = <®_1v8>; <<
314 DVDD-supply = <®_1v5>; <<
315 <<
316 port { <<
317 ov5640_to_mipi_csi2: e <<
318 remote-endpoin <<
319 clock-lanes = <<
320 data-lanes = < <<
321 }; <<
322 }; <<
323 }; <<
324 }; <<
325 <<
326 &isi { <<
327 status = "okay"; <<
328 }; <<
329 <<
330 &micfil { <<
331 #sound-dai-cells = <0>; <<
332 pinctrl-names = "default"; <<
333 pinctrl-0 = <&pinctrl_pdm>; <<
334 assigned-clocks = <&clk IMX8MN_CLK_PDM <<
335 assigned-clock-parents = <&clk IMX8MN_ <<
336 assigned-clock-rates = <196608000>; <<
337 status = "okay"; <<
338 }; <<
339 <<
340 &mipi_csi { <<
341 status = "okay"; <<
342 <<
343 ports { <<
344 port@0 { <<
345 imx8mn_mipi_csi_in: en <<
346 remote-endpoin <<
347 data-lanes = < <<
348 }; <<
349 }; <<
350 }; <<
351 }; <<
352 <<
353 &lcdif { <<
354 status = "okay"; <<
355 }; <<
356 <<
357 &mipi_dsi { <<
358 samsung,esc-clock-frequency = <1000000 <<
359 status = "okay"; <<
360 <<
361 ports { <<
362 port@1 { <<
363 reg = <1>; <<
364 <<
365 dsi_out: endpoint { <<
366 remote-endpoin <<
367 data-lanes = < <<
368 }; <<
369 }; <<
370 }; <<
371 }; 215 };
372 216
373 &sai2 { 217 &sai2 {
374 #sound-dai-cells = <0>; 218 #sound-dai-cells = <0>;
375 pinctrl-names = "default"; 219 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_sai2>; 220 pinctrl-0 = <&pinctrl_sai2>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI 221 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
378 assigned-clock-parents = <&clk IMX8MN_ 222 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
379 assigned-clock-rates = <24576000>; 223 assigned-clock-rates = <24576000>;
380 status = "okay"; 224 status = "okay";
381 }; 225 };
382 226
383 &sai3 { 227 &sai3 {
384 pinctrl-names = "default"; 228 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_sai3>; 229 pinctrl-0 = <&pinctrl_sai3>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI 230 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
387 assigned-clock-parents = <&clk IMX8MN_ 231 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
388 assigned-clock-rates = <24576000>; 232 assigned-clock-rates = <24576000>;
389 fsl,sai-mclk-direction-output; 233 fsl,sai-mclk-direction-output;
390 status = "okay"; 234 status = "okay";
391 }; 235 };
392 236
393 &snvs_pwrkey { 237 &snvs_pwrkey {
394 status = "okay"; 238 status = "okay";
395 }; 239 };
396 240
397 &spdif1 { 241 &spdif1 {
398 pinctrl-names = "default"; 242 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_spdif1>; 243 pinctrl-0 = <&pinctrl_spdif1>;
400 assigned-clocks = <&clk IMX8MN_CLK_SPD 244 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
401 assigned-clock-parents = <&clk IMX8MN_ 245 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
402 assigned-clock-rates = <24576000>; 246 assigned-clock-rates = <24576000>;
403 status = "okay"; 247 status = "okay";
404 }; 248 };
405 249
406 &uart1 { /* BT */ 250 &uart1 { /* BT */
407 pinctrl-names = "default"; 251 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_uart1>; 252 pinctrl-0 = <&pinctrl_uart1>;
409 assigned-clocks = <&clk IMX8MN_CLK_UAR 253 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
410 assigned-clock-parents = <&clk IMX8MN_ 254 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
411 uart-has-rtscts; 255 uart-has-rtscts;
412 status = "okay"; 256 status = "okay";
413 }; 257 };
414 258
415 &uart2 { /* console */ 259 &uart2 { /* console */
416 pinctrl-names = "default"; 260 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart2>; 261 pinctrl-0 = <&pinctrl_uart2>;
418 status = "okay"; 262 status = "okay";
419 }; 263 };
420 264
421 &uart3 { 265 &uart3 {
422 pinctrl-names = "default"; 266 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_uart3>; 267 pinctrl-0 = <&pinctrl_uart3>;
424 assigned-clocks = <&clk IMX8MN_CLK_UAR 268 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
425 assigned-clock-parents = <&clk IMX8MN_ 269 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
426 uart-has-rtscts; 270 uart-has-rtscts;
427 status = "okay"; 271 status = "okay";
428 }; 272 };
429 273
430 &usbphynop1 { 274 &usbphynop1 {
431 wakeup-source; 275 wakeup-source;
432 }; 276 };
433 277
434 &usbotg1 { 278 &usbotg1 {
435 dr_mode = "otg"; 279 dr_mode = "otg";
436 hnp-disable; 280 hnp-disable;
437 srp-disable; 281 srp-disable;
438 adp-disable; 282 adp-disable;
439 usb-role-switch; 283 usb-role-switch;
440 disable-over-current; 284 disable-over-current;
441 samsung,picophy-pre-emp-curr-control = 285 samsung,picophy-pre-emp-curr-control = <3>;
442 samsung,picophy-dc-vol-level-adjust = 286 samsung,picophy-dc-vol-level-adjust = <7>;
443 status = "okay"; 287 status = "okay";
444 288
445 port { 289 port {
446 usb1_drd_sw: endpoint { 290 usb1_drd_sw: endpoint {
447 remote-endpoint = <&ty 291 remote-endpoint = <&typec1_dr_sw>;
448 }; 292 };
449 }; 293 };
450 }; 294 };
451 295
452 &usdhc2 { 296 &usdhc2 {
453 assigned-clocks = <&clk IMX8MN_CLK_USD 297 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
454 assigned-clock-rates = <200000000>; 298 assigned-clock-rates = <200000000>;
455 pinctrl-names = "default", "state_100m 299 pinctrl-names = "default", "state_100mhz", "state_200mhz";
456 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 300 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
457 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 301 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
458 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 302 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
459 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 303 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
460 bus-width = <4>; 304 bus-width = <4>;
461 vmmc-supply = <®_usdhc2_vmmc>; 305 vmmc-supply = <®_usdhc2_vmmc>;
462 status = "okay"; 306 status = "okay";
463 }; 307 };
464 308
465 &usdhc3 { 309 &usdhc3 {
466 assigned-clocks = <&clk IMX8MN_CLK_USD 310 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
467 assigned-clock-rates = <400000000>; 311 assigned-clock-rates = <400000000>;
468 pinctrl-names = "default", "state_100m 312 pinctrl-names = "default", "state_100mhz", "state_200mhz";
469 pinctrl-0 = <&pinctrl_usdhc3>; 313 pinctrl-0 = <&pinctrl_usdhc3>;
470 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 314 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
471 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 315 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
472 bus-width = <8>; 316 bus-width = <8>;
473 non-removable; 317 non-removable;
474 status = "okay"; 318 status = "okay";
475 }; 319 };
476 320
477 &wdog1 { 321 &wdog1 {
478 pinctrl-names = "default"; 322 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_wdog>; 323 pinctrl-0 = <&pinctrl_wdog>;
480 fsl,ext-reset-output; 324 fsl,ext-reset-output;
481 status = "okay"; 325 status = "okay";
482 }; 326 };
483 327
484 &iomuxc { 328 &iomuxc {
485 pinctrl_camera: cameragrp { <<
486 fsl,pins = < <<
487 MX8MN_IOMUXC_GPIO1_IO0 <<
488 MX8MN_IOMUXC_GPIO1_IO0 <<
489 MX8MN_IOMUXC_GPIO1_IO1 <<
490 >; <<
491 }; <<
492 <<
493 pinctrl_fec1: fec1grp { 329 pinctrl_fec1: fec1grp {
494 fsl,pins = < 330 fsl,pins = <
495 MX8MN_IOMUXC_ENET_MDC_ 331 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
496 MX8MN_IOMUXC_ENET_MDIO 332 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
497 MX8MN_IOMUXC_ENET_TD3_ 333 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
498 MX8MN_IOMUXC_ENET_TD2_ 334 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
499 MX8MN_IOMUXC_ENET_TD1_ 335 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
500 MX8MN_IOMUXC_ENET_TD0_ 336 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
501 MX8MN_IOMUXC_ENET_RD3_ 337 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
502 MX8MN_IOMUXC_ENET_RD2_ 338 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
503 MX8MN_IOMUXC_ENET_RD1_ 339 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
504 MX8MN_IOMUXC_ENET_RD0_ 340 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
505 MX8MN_IOMUXC_ENET_TXC_ 341 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
506 MX8MN_IOMUXC_ENET_RXC_ 342 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
507 MX8MN_IOMUXC_ENET_RX_C 343 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
508 MX8MN_IOMUXC_ENET_TX_C 344 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
509 MX8MN_IOMUXC_SAI2_RXC_ 345 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
510 >; 346 >;
511 }; 347 };
512 348
513 pinctrl_flexspi: flexspigrp { 349 pinctrl_flexspi: flexspigrp {
514 fsl,pins = < 350 fsl,pins = <
515 MX8MN_IOMUXC_NAND_ALE_ 351 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
516 MX8MN_IOMUXC_NAND_CE0_ 352 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
517 MX8MN_IOMUXC_NAND_DATA 353 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
518 MX8MN_IOMUXC_NAND_DATA 354 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
519 MX8MN_IOMUXC_NAND_DATA 355 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
520 MX8MN_IOMUXC_NAND_DATA 356 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
521 >; 357 >;
522 }; 358 };
523 359
524 pinctrl_gpio_led: gpioledgrp { 360 pinctrl_gpio_led: gpioledgrp {
525 fsl,pins = < 361 fsl,pins = <
526 MX8MN_IOMUXC_NAND_READ 362 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
527 >; 363 >;
528 }; 364 };
529 365
530 pinctrl_gpio_wlf: gpiowlfgrp { 366 pinctrl_gpio_wlf: gpiowlfgrp {
531 fsl,pins = < 367 fsl,pins = <
532 MX8MN_IOMUXC_I2C4_SDA_ 368 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
533 >; 369 >;
534 }; 370 };
535 371
536 pinctrl_ir: irgrp { 372 pinctrl_ir: irgrp {
537 fsl,pins = < 373 fsl,pins = <
538 MX8MN_IOMUXC_GPIO1_IO1 374 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
539 >; 375 >;
540 }; 376 };
541 377
542 pinctrl_i2c1: i2c1grp { 378 pinctrl_i2c1: i2c1grp {
543 fsl,pins = < 379 fsl,pins = <
544 MX8MN_IOMUXC_I2C1_SCL_ 380 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
545 MX8MN_IOMUXC_I2C1_SDA_ 381 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
546 >; 382 >;
547 }; 383 };
548 384
549 pinctrl_i2c2: i2c2grp { 385 pinctrl_i2c2: i2c2grp {
550 fsl,pins = < 386 fsl,pins = <
551 MX8MN_IOMUXC_I2C2_SCL_ 387 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
552 MX8MN_IOMUXC_I2C2_SDA_ 388 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
553 >; 389 >;
554 }; 390 };
555 391
556 pinctrl_i2c2_gpio: i2c2gpiogrp { !! 392 pinctrl_i2c2_gpio: i2c2grp-gpio {
557 fsl,pins = < 393 fsl,pins = <
558 MX8MN_IOMUXC_I2C2_SCL_ 394 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
559 MX8MN_IOMUXC_I2C2_SDA_ 395 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
560 >; 396 >;
561 }; 397 };
562 398
563 pinctrl_i2c3: i2c3grp { 399 pinctrl_i2c3: i2c3grp {
564 fsl,pins = < 400 fsl,pins = <
565 MX8MN_IOMUXC_I2C3_SCL_ 401 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
566 MX8MN_IOMUXC_I2C3_SDA_ 402 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
567 >; 403 >;
568 }; 404 };
569 405
570 pinctrl_i2c3_gpio: i2c3gpiogrp { !! 406 pinctrl_i2c3_gpio: i2c3grp-gpio {
571 fsl,pins = < 407 fsl,pins = <
572 MX8MN_IOMUXC_I2C3_SCL_ 408 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
573 MX8MN_IOMUXC_I2C3_SDA_ 409 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
574 >; <<
575 }; <<
576 <<
577 pinctrl_pdm: pdmgrp { <<
578 fsl,pins = < <<
579 MX8MN_IOMUXC_SAI5_MCLK <<
580 MX8MN_IOMUXC_SAI5_RXC_ <<
581 MX8MN_IOMUXC_SAI5_RXFS <<
582 MX8MN_IOMUXC_SAI5_RXD0 <<
583 MX8MN_IOMUXC_SAI5_RXD1 <<
584 MX8MN_IOMUXC_SAI5_RXD2 <<
585 MX8MN_IOMUXC_SAI5_RXD3 <<
586 >; 410 >;
587 }; 411 };
588 412
589 pinctrl_pmic: pmicirqgrp { 413 pinctrl_pmic: pmicirqgrp {
590 fsl,pins = < 414 fsl,pins = <
591 MX8MN_IOMUXC_GPIO1_IO0 415 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
592 >; 416 >;
593 }; 417 };
594 418
595 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 419 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
596 fsl,pins = < 420 fsl,pins = <
597 MX8MN_IOMUXC_SD2_RESET 421 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
598 >; 422 >;
599 }; 423 };
600 424
601 pinctrl_sai2: sai2grp { 425 pinctrl_sai2: sai2grp {
602 fsl,pins = < 426 fsl,pins = <
603 MX8MN_IOMUXC_SAI2_TXC_ 427 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
604 MX8MN_IOMUXC_SAI2_TXFS 428 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
605 MX8MN_IOMUXC_SAI2_TXD0 429 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
606 MX8MN_IOMUXC_SAI2_RXD0 430 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
607 >; 431 >;
608 }; 432 };
609 433
610 pinctrl_sai3: sai3grp { 434 pinctrl_sai3: sai3grp {
611 fsl,pins = < 435 fsl,pins = <
612 MX8MN_IOMUXC_SAI3_TXFS 436 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
613 MX8MN_IOMUXC_SAI3_TXC_ 437 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
614 MX8MN_IOMUXC_SAI3_MCLK 438 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
615 MX8MN_IOMUXC_SAI3_TXD_ 439 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
616 >; 440 >;
617 }; 441 };
618 442
619 pinctrl_spdif1: spdif1grp { 443 pinctrl_spdif1: spdif1grp {
620 fsl,pins = < 444 fsl,pins = <
621 MX8MN_IOMUXC_SPDIF_TX_ 445 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
622 MX8MN_IOMUXC_SPDIF_RX_ 446 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
623 >; 447 >;
624 }; 448 };
625 449
626 pinctrl_typec1: typec1grp { 450 pinctrl_typec1: typec1grp {
627 fsl,pins = < 451 fsl,pins = <
628 MX8MN_IOMUXC_SD1_STROB 452 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
629 >; 453 >;
630 }; 454 };
631 455
632 pinctrl_uart1: uart1grp { 456 pinctrl_uart1: uart1grp {
633 fsl,pins = < 457 fsl,pins = <
634 MX8MN_IOMUXC_UART1_RXD 458 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
635 MX8MN_IOMUXC_UART1_TXD 459 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
636 MX8MN_IOMUXC_UART3_RXD 460 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
637 MX8MN_IOMUXC_UART3_TXD 461 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
638 >; 462 >;
639 }; 463 };
640 464
641 pinctrl_uart2: uart2grp { 465 pinctrl_uart2: uart2grp {
642 fsl,pins = < 466 fsl,pins = <
643 MX8MN_IOMUXC_UART2_RXD 467 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
644 MX8MN_IOMUXC_UART2_TXD 468 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
645 >; 469 >;
646 }; 470 };
647 471
648 pinctrl_uart3: uart3grp { 472 pinctrl_uart3: uart3grp {
649 fsl,pins = < 473 fsl,pins = <
650 MX8MN_IOMUXC_ECSPI1_SC 474 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
651 MX8MN_IOMUXC_ECSPI1_MO 475 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
652 MX8MN_IOMUXC_ECSPI1_SS 476 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
653 MX8MN_IOMUXC_ECSPI1_MI 477 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
654 >; 478 >;
655 }; 479 };
656 480
657 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 481 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
658 fsl,pins = < 482 fsl,pins = <
659 MX8MN_IOMUXC_GPIO1_IO1 483 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
660 >; 484 >;
661 }; 485 };
662 486
663 pinctrl_usdhc2: usdhc2grp { 487 pinctrl_usdhc2: usdhc2grp {
664 fsl,pins = < 488 fsl,pins = <
665 MX8MN_IOMUXC_SD2_CLK_U 489 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
666 MX8MN_IOMUXC_SD2_CMD_U 490 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
667 MX8MN_IOMUXC_SD2_DATA0 491 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
668 MX8MN_IOMUXC_SD2_DATA1 492 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
669 MX8MN_IOMUXC_SD2_DATA2 493 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
670 MX8MN_IOMUXC_SD2_DATA3 494 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
671 MX8MN_IOMUXC_GPIO1_IO0 495 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
672 >; 496 >;
673 }; 497 };
674 498
675 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 499 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
676 fsl,pins = < 500 fsl,pins = <
677 MX8MN_IOMUXC_SD2_CLK_U 501 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
678 MX8MN_IOMUXC_SD2_CMD_U 502 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
679 MX8MN_IOMUXC_SD2_DATA0 503 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
680 MX8MN_IOMUXC_SD2_DATA1 504 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
681 MX8MN_IOMUXC_SD2_DATA2 505 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
682 MX8MN_IOMUXC_SD2_DATA3 506 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
683 MX8MN_IOMUXC_GPIO1_IO0 507 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
684 >; 508 >;
685 }; 509 };
686 510
687 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 511 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
688 fsl,pins = < 512 fsl,pins = <
689 MX8MN_IOMUXC_SD2_CLK_U 513 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
690 MX8MN_IOMUXC_SD2_CMD_U 514 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
691 MX8MN_IOMUXC_SD2_DATA0 515 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
692 MX8MN_IOMUXC_SD2_DATA1 516 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
693 MX8MN_IOMUXC_SD2_DATA2 517 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
694 MX8MN_IOMUXC_SD2_DATA3 518 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
695 MX8MN_IOMUXC_GPIO1_IO0 519 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
696 >; 520 >;
697 }; 521 };
698 522
699 pinctrl_usdhc3: usdhc3grp { 523 pinctrl_usdhc3: usdhc3grp {
700 fsl,pins = < 524 fsl,pins = <
701 MX8MN_IOMUXC_NAND_WE_B 525 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
702 MX8MN_IOMUXC_NAND_WP_B 526 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
703 MX8MN_IOMUXC_NAND_DATA 527 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
704 MX8MN_IOMUXC_NAND_DATA 528 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
705 MX8MN_IOMUXC_NAND_DATA 529 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
706 MX8MN_IOMUXC_NAND_DATA 530 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
707 MX8MN_IOMUXC_NAND_RE_B 531 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
708 MX8MN_IOMUXC_NAND_CE2_ 532 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
709 MX8MN_IOMUXC_NAND_CE3_ 533 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
710 MX8MN_IOMUXC_NAND_CLE_ 534 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
711 MX8MN_IOMUXC_NAND_CE1_ 535 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
712 >; 536 >;
713 }; 537 };
714 538
715 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 539 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
716 fsl,pins = < 540 fsl,pins = <
717 MX8MN_IOMUXC_NAND_WE_B 541 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
718 MX8MN_IOMUXC_NAND_WP_B 542 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
719 MX8MN_IOMUXC_NAND_DATA 543 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
720 MX8MN_IOMUXC_NAND_DATA 544 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
721 MX8MN_IOMUXC_NAND_DATA 545 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
722 MX8MN_IOMUXC_NAND_DATA 546 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
723 MX8MN_IOMUXC_NAND_RE_B 547 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
724 MX8MN_IOMUXC_NAND_CE2_ 548 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
725 MX8MN_IOMUXC_NAND_CE3_ 549 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
726 MX8MN_IOMUXC_NAND_CLE_ 550 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
727 MX8MN_IOMUXC_NAND_CE1_ 551 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
728 >; 552 >;
729 }; 553 };
730 554
731 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 555 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
732 fsl,pins = < 556 fsl,pins = <
733 MX8MN_IOMUXC_NAND_WE_B 557 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
734 MX8MN_IOMUXC_NAND_WP_B 558 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
735 MX8MN_IOMUXC_NAND_DATA 559 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
736 MX8MN_IOMUXC_NAND_DATA 560 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
737 MX8MN_IOMUXC_NAND_DATA 561 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
738 MX8MN_IOMUXC_NAND_DATA 562 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
739 MX8MN_IOMUXC_NAND_RE_B 563 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
740 MX8MN_IOMUXC_NAND_CE2_ 564 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
741 MX8MN_IOMUXC_NAND_CE3_ 565 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
742 MX8MN_IOMUXC_NAND_CLE_ 566 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
743 MX8MN_IOMUXC_NAND_CE1_ 567 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
744 >; 568 >;
745 }; 569 };
746 570
747 pinctrl_wdog: wdoggrp { 571 pinctrl_wdog: wdoggrp {
748 fsl,pins = < 572 fsl,pins = <
749 MX8MN_IOMUXC_GPIO1_IO0 573 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
750 >; 574 >;
751 }; 575 };
752 }; 576 };
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