1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/usb/pd.h> 6 #include <dt-bindings/usb/pd.h>
7 #include "imx8mn.dtsi" 7 #include "imx8mn.dtsi"
8 8
9 / { 9 / {
10 chosen { 10 chosen {
11 stdout-path = &uart2; 11 stdout-path = &uart2;
12 }; 12 };
13 13
14 gpio-leds { 14 gpio-leds {
15 compatible = "gpio-leds"; 15 compatible = "gpio-leds";
16 pinctrl-names = "default"; 16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led 17 pinctrl-0 = <&pinctrl_gpio_led>;
18 18
19 status { 19 status {
20 label = "yellow:status 20 label = "yellow:status";
21 gpios = <&gpio3 16 GPI 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on"; 22 default-state = "on";
23 }; 23 };
24 }; 24 };
25 25
26 hdmi-connector { 26 hdmi-connector {
27 compatible = "hdmi-connector"; 27 compatible = "hdmi-connector";
28 label = "hdmi"; 28 label = "hdmi";
29 type = "a"; 29 type = "a";
30 30
31 port { 31 port {
32 hdmi_connector_in: end 32 hdmi_connector_in: endpoint {
33 remote-endpoin !! 33 remote-endpoint = <&adv7533_out>;
34 }; 34 };
35 }; 35 };
36 }; 36 };
37 37
38 memory@40000000 { 38 memory@40000000 {
39 device_type = "memory"; 39 device_type = "memory";
40 reg = <0x0 0x40000000 0 0x8000 40 reg = <0x0 0x40000000 0 0x80000000>;
41 }; 41 };
42 42
43 reg_usdhc2_vmmc: regulator-usdhc2 { 43 reg_usdhc2_vmmc: regulator-usdhc2 {
44 compatible = "regulator-fixed" 44 compatible = "regulator-fixed";
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usdh 46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
47 regulator-name = "VSD_3V3"; 47 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <330 48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <330 49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio2 19 GPIO_ACTIVE_ 50 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51 off-on-delay-us = <12000>; 51 off-on-delay-us = <12000>;
52 enable-active-high; 52 enable-active-high;
53 }; 53 };
54 54
55 reg_1v5: regulator-1v5 { <<
56 compatible = "regulator-fixed" <<
57 regulator-name = "VDD_1V5"; <<
58 regulator-min-microvolt = <150 <<
59 regulator-max-microvolt = <150 <<
60 }; <<
61 <<
62 reg_1v8: regulator-1v8 { <<
63 compatible = "regulator-fixed" <<
64 regulator-name = "VDD_1V8"; <<
65 regulator-min-microvolt = <180 <<
66 regulator-max-microvolt = <180 <<
67 }; <<
68 <<
69 reg_vddext_3v3: regulator-vddext-3v3 { <<
70 compatible = "regulator-fixed" <<
71 regulator-name = "VDDEXT_3V3"; <<
72 regulator-min-microvolt = <330 <<
73 regulator-max-microvolt = <330 <<
74 }; <<
75 <<
76 ir-receiver { 55 ir-receiver {
77 compatible = "gpio-ir-receiver 56 compatible = "gpio-ir-receiver";
78 gpios = <&gpio1 13 GPIO_ACTIVE 57 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
79 pinctrl-names = "default"; 58 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_ir>; 59 pinctrl-0 = <&pinctrl_ir>;
81 linux,autosuspend-period = <12 60 linux,autosuspend-period = <125>;
82 }; 61 };
83 62
84 audio_codec_bt_sco: audio-codec-bt-sco 63 audio_codec_bt_sco: audio-codec-bt-sco {
85 compatible = "linux,bt-sco"; 64 compatible = "linux,bt-sco";
86 #sound-dai-cells = <1>; 65 #sound-dai-cells = <1>;
87 }; 66 };
88 67
89 wm8524: audio-codec { 68 wm8524: audio-codec {
90 #sound-dai-cells = <0>; 69 #sound-dai-cells = <0>;
91 compatible = "wlf,wm8524"; 70 compatible = "wlf,wm8524";
92 pinctrl-names = "default"; 71 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gpio_wlf 72 pinctrl-0 = <&pinctrl_gpio_wlf>;
94 wlf,mute-gpios = <&gpio5 21 GP 73 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
95 }; 74 };
96 75
97 sound-bt-sco { 76 sound-bt-sco {
98 compatible = "simple-audio-car 77 compatible = "simple-audio-card";
99 simple-audio-card,name = "bt-s 78 simple-audio-card,name = "bt-sco-audio";
100 simple-audio-card,format = "ds 79 simple-audio-card,format = "dsp_a";
101 simple-audio-card,bitclock-inv 80 simple-audio-card,bitclock-inversion;
102 simple-audio-card,frame-master 81 simple-audio-card,frame-master = <&btcpu>;
103 simple-audio-card,bitclock-mas 82 simple-audio-card,bitclock-master = <&btcpu>;
104 83
105 btcpu: simple-audio-card,cpu { 84 btcpu: simple-audio-card,cpu {
106 sound-dai = <&sai2>; 85 sound-dai = <&sai2>;
107 dai-tdm-slot-num = <2> 86 dai-tdm-slot-num = <2>;
108 dai-tdm-slot-width = < 87 dai-tdm-slot-width = <16>;
109 }; 88 };
110 89
111 simple-audio-card,codec { 90 simple-audio-card,codec {
112 sound-dai = <&audio_co 91 sound-dai = <&audio_codec_bt_sco 1>;
113 }; 92 };
114 }; 93 };
115 94
116 sound-wm8524 { 95 sound-wm8524 {
117 compatible = "fsl,imx-audio-wm 96 compatible = "fsl,imx-audio-wm8524";
118 model = "wm8524-audio"; 97 model = "wm8524-audio";
119 audio-cpu = <&sai3>; 98 audio-cpu = <&sai3>;
120 audio-codec = <&wm8524>; 99 audio-codec = <&wm8524>;
121 audio-asrc = <&easrc>; 100 audio-asrc = <&easrc>;
122 audio-routing = 101 audio-routing =
123 "Line Out Jack", "LINE 102 "Line Out Jack", "LINEVOUTL",
124 "Line Out Jack", "LINE 103 "Line Out Jack", "LINEVOUTR";
125 }; 104 };
126 105
127 spdif_out: spdif-out { <<
128 compatible = "linux,spdif-dit" <<
129 #sound-dai-cells = <0>; <<
130 }; <<
131 <<
132 spdif_in: spdif-in { <<
133 compatible = "linux,spdif-dir" <<
134 #sound-dai-cells = <0>; <<
135 }; <<
136 <<
137 sound-spdif { 106 sound-spdif {
138 compatible = "fsl,imx-audio-sp 107 compatible = "fsl,imx-audio-spdif";
139 model = "imx-spdif"; 108 model = "imx-spdif";
140 audio-cpu = <&spdif1>; !! 109 spdif-controller = <&spdif1>;
141 audio-codec = <&spdif_out>, <& !! 110 spdif-out;
142 }; !! 111 spdif-in;
143 <<
144 sound-micfil { <<
145 compatible = "fsl,imx-audio-ca <<
146 model = "micfil-audio"; <<
147 <<
148 pri-dai-link { <<
149 link-name = "micfil hi <<
150 format = "i2s"; <<
151 <<
152 cpu { <<
153 sound-dai = <& <<
154 }; <<
155 }; <<
156 }; 112 };
157 }; 113 };
158 114
159 &easrc { 115 &easrc {
160 fsl,asrc-rate = <48000>; 116 fsl,asrc-rate = <48000>;
161 status = "okay"; 117 status = "okay";
162 }; 118 };
163 119
164 &fec1 { 120 &fec1 {
165 pinctrl-names = "default"; 121 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec1>; 122 pinctrl-0 = <&pinctrl_fec1>;
167 phy-mode = "rgmii-id"; 123 phy-mode = "rgmii-id";
168 phy-handle = <ðphy0>; 124 phy-handle = <ðphy0>;
169 fsl,magic-packet; 125 fsl,magic-packet;
170 status = "okay"; 126 status = "okay";
171 127
172 mdio { 128 mdio {
173 #address-cells = <1>; 129 #address-cells = <1>;
174 #size-cells = <0>; 130 #size-cells = <0>;
175 131
176 ethphy0: ethernet-phy@0 { 132 ethphy0: ethernet-phy@0 {
177 compatible = "ethernet 133 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <0>; 134 reg = <0>;
179 reset-gpios = <&gpio4 135 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
180 reset-assert-us = <100 136 reset-assert-us = <10000>;
181 qca,disable-smarteee; 137 qca,disable-smarteee;
182 vddio-supply = <&vddio 138 vddio-supply = <&vddio>;
183 139
184 vddio: vddio-regulator 140 vddio: vddio-regulator {
185 regulator-min- 141 regulator-min-microvolt = <1800000>;
186 regulator-max- 142 regulator-max-microvolt = <1800000>;
187 }; 143 };
188 }; 144 };
189 }; 145 };
190 }; 146 };
191 147
192 &flexspi { 148 &flexspi {
193 pinctrl-names = "default"; 149 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_flexspi>; 150 pinctrl-0 = <&pinctrl_flexspi>;
195 status = "okay"; 151 status = "okay";
196 152
197 flash0: flash@0 { 153 flash0: flash@0 {
198 compatible = "jedec,spi-nor"; 154 compatible = "jedec,spi-nor";
199 reg = <0>; 155 reg = <0>;
200 #address-cells = <1>; 156 #address-cells = <1>;
201 #size-cells = <1>; 157 #size-cells = <1>;
202 spi-max-frequency = <166000000 158 spi-max-frequency = <166000000>;
203 spi-tx-bus-width = <4>; 159 spi-tx-bus-width = <4>;
204 spi-rx-bus-width = <4>; 160 spi-rx-bus-width = <4>;
205 }; 161 };
206 }; 162 };
207 163
208 &i2c1 { 164 &i2c1 {
209 clock-frequency = <400000>; 165 clock-frequency = <400000>;
210 pinctrl-names = "default"; 166 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>; 167 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "okay"; 168 status = "okay";
213 }; 169 };
214 170
215 &i2c2 { 171 &i2c2 {
216 clock-frequency = <400000>; 172 clock-frequency = <400000>;
217 pinctrl-names = "default", "gpio"; 173 pinctrl-names = "default", "gpio";
218 pinctrl-0 = <&pinctrl_i2c2>; 174 pinctrl-0 = <&pinctrl_i2c2>;
219 pinctrl-1 = <&pinctrl_i2c2_gpio>; 175 pinctrl-1 = <&pinctrl_i2c2_gpio>;
220 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 176 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
221 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 177 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
222 status = "okay"; 178 status = "okay";
223 179
224 hdmi@3d { 180 hdmi@3d {
225 compatible = "adi,adv7535"; 181 compatible = "adi,adv7535";
226 reg = <0x3d>; !! 182 reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
227 interrupt-parent = <&gpio1>; !! 183 reg-names = "main", "cec", "edid", "packet";
228 interrupts = <9 IRQ_TYPE_EDGE_ <<
229 adi,dsi-lanes = <4>; 184 adi,dsi-lanes = <4>;
230 v3p3-supply = <®_vddext_3v3 !! 185
>> 186 adi,input-depth = <8>;
>> 187 adi,input-colorspace = "rgb";
>> 188 adi,input-clock = "1x";
>> 189 adi,input-style = <1>;
>> 190 adi,input-justification = "evenly";
231 191
232 ports { 192 ports {
233 #address-cells = <1>; 193 #address-cells = <1>;
234 #size-cells = <0>; 194 #size-cells = <0>;
235 195
236 port@0 { 196 port@0 {
237 reg = <0>; 197 reg = <0>;
238 198
239 adv7535_in: en !! 199 adv7533_in: endpoint {
240 remote 200 remote-endpoint = <&dsi_out>;
241 }; 201 };
242 }; 202 };
243 203
244 port@1 { 204 port@1 {
245 reg = <1>; 205 reg = <1>;
246 206
247 adv7535_out: e !! 207 adv7533_out: endpoint {
248 remote 208 remote-endpoint = <&hdmi_connector_in>;
249 }; 209 };
250 }; 210 };
251 211
252 }; 212 };
253 }; 213 };
254 214
255 ptn5110: tcpc@50 { 215 ptn5110: tcpc@50 {
256 compatible = "nxp,ptn5110", "t !! 216 compatible = "nxp,ptn5110";
257 pinctrl-names = "default"; 217 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_typec1>; 218 pinctrl-0 = <&pinctrl_typec1>;
259 reg = <0x50>; 219 reg = <0x50>;
260 interrupt-parent = <&gpio2>; 220 interrupt-parent = <&gpio2>;
261 interrupts = <11 IRQ_TYPE_LEVE 221 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
262 status = "okay"; 222 status = "okay";
263 223
>> 224 port {
>> 225 typec1_dr_sw: endpoint {
>> 226 remote-endpoint = <&usb1_drd_sw>;
>> 227 };
>> 228 };
>> 229
264 typec1_con: connector { 230 typec1_con: connector {
265 compatible = "usb-c-co 231 compatible = "usb-c-connector";
266 label = "USB-C"; 232 label = "USB-C";
267 power-role = "dual"; 233 power-role = "dual";
268 data-role = "dual"; 234 data-role = "dual";
269 try-power-role = "sink 235 try-power-role = "sink";
270 source-pdos = <PDO_FIX 236 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
271 sink-pdos = <PDO_FIXED 237 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
272 PDO_VAR(5 238 PDO_VAR(5000, 20000, 3000)>;
273 op-sink-microwatt = <1 239 op-sink-microwatt = <15000000>;
274 self-powered; 240 self-powered;
275 <<
276 port { <<
277 typec1_dr_sw: <<
278 remote <<
279 }; <<
280 }; <<
281 }; 241 };
282 }; 242 };
283 }; 243 };
284 244
285 &i2c3 { 245 &i2c3 {
286 clock-frequency = <400000>; 246 clock-frequency = <400000>;
287 pinctrl-names = "default", "gpio"; 247 pinctrl-names = "default", "gpio";
288 pinctrl-0 = <&pinctrl_i2c3>; 248 pinctrl-0 = <&pinctrl_i2c3>;
289 pinctrl-1 = <&pinctrl_i2c3_gpio>; 249 pinctrl-1 = <&pinctrl_i2c3_gpio>;
290 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIG 250 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
291 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIG 251 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
292 status = "okay"; 252 status = "okay";
293 253
294 pca6416: gpio@20 { 254 pca6416: gpio@20 {
295 compatible = "ti,tca6416"; 255 compatible = "ti,tca6416";
296 reg = <0x20>; 256 reg = <0x20>;
297 gpio-controller; 257 gpio-controller;
298 #gpio-cells = <2>; 258 #gpio-cells = <2>;
299 }; 259 };
300 260
301 camera@3c { 261 camera@3c {
302 compatible = "ovti,ov5640"; 262 compatible = "ovti,ov5640";
303 reg = <0x3c>; 263 reg = <0x3c>;
304 pinctrl-names = "default"; 264 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_camera>; 265 pinctrl-0 = <&pinctrl_camera>;
306 clocks = <&clk IMX8MN_CLK_CLKO 266 clocks = <&clk IMX8MN_CLK_CLKO1>;
307 clock-names = "xclk"; 267 clock-names = "xclk";
308 assigned-clocks = <&clk IMX8MN 268 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
309 assigned-clock-parents = <&clk 269 assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
310 assigned-clock-rates = <240000 270 assigned-clock-rates = <24000000>;
311 powerdown-gpios = <&gpio1 7 GP 271 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
312 reset-gpios = <&gpio1 6 GPIO_A 272 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
313 AVDD-supply = <®_1v8>; <<
314 DVDD-supply = <®_1v5>; <<
315 273
316 port { 274 port {
317 ov5640_to_mipi_csi2: e 275 ov5640_to_mipi_csi2: endpoint {
318 remote-endpoin 276 remote-endpoint = <&imx8mn_mipi_csi_in>;
319 clock-lanes = 277 clock-lanes = <0>;
320 data-lanes = < 278 data-lanes = <1 2>;
321 }; 279 };
322 }; 280 };
323 }; 281 };
324 }; 282 };
325 283
326 &isi { 284 &isi {
327 status = "okay"; 285 status = "okay";
328 }; 286 };
329 287
330 &micfil { <<
331 #sound-dai-cells = <0>; <<
332 pinctrl-names = "default"; <<
333 pinctrl-0 = <&pinctrl_pdm>; <<
334 assigned-clocks = <&clk IMX8MN_CLK_PDM <<
335 assigned-clock-parents = <&clk IMX8MN_ <<
336 assigned-clock-rates = <196608000>; <<
337 status = "okay"; <<
338 }; <<
339 <<
340 &mipi_csi { 288 &mipi_csi {
341 status = "okay"; 289 status = "okay";
342 290
343 ports { 291 ports {
344 port@0 { 292 port@0 {
345 imx8mn_mipi_csi_in: en 293 imx8mn_mipi_csi_in: endpoint {
346 remote-endpoin 294 remote-endpoint = <&ov5640_to_mipi_csi2>;
347 data-lanes = < 295 data-lanes = <1 2>;
348 }; 296 };
349 }; 297 };
350 }; 298 };
351 }; 299 };
352 300
353 &lcdif { 301 &lcdif {
354 status = "okay"; 302 status = "okay";
355 }; 303 };
356 304
357 &mipi_dsi { 305 &mipi_dsi {
358 samsung,esc-clock-frequency = <1000000 306 samsung,esc-clock-frequency = <10000000>;
359 status = "okay"; 307 status = "okay";
360 308
361 ports { 309 ports {
362 port@1 { 310 port@1 {
363 reg = <1>; 311 reg = <1>;
364 312
365 dsi_out: endpoint { 313 dsi_out: endpoint {
366 remote-endpoin !! 314 remote-endpoint = <&adv7533_in>;
367 data-lanes = < 315 data-lanes = <1 2 3 4>;
368 }; 316 };
369 }; 317 };
370 }; 318 };
371 }; 319 };
372 320
373 &sai2 { 321 &sai2 {
374 #sound-dai-cells = <0>; 322 #sound-dai-cells = <0>;
375 pinctrl-names = "default"; 323 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_sai2>; 324 pinctrl-0 = <&pinctrl_sai2>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI 325 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
378 assigned-clock-parents = <&clk IMX8MN_ 326 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
379 assigned-clock-rates = <24576000>; 327 assigned-clock-rates = <24576000>;
380 status = "okay"; 328 status = "okay";
381 }; 329 };
382 330
383 &sai3 { 331 &sai3 {
384 pinctrl-names = "default"; 332 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_sai3>; 333 pinctrl-0 = <&pinctrl_sai3>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI 334 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
387 assigned-clock-parents = <&clk IMX8MN_ 335 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
388 assigned-clock-rates = <24576000>; 336 assigned-clock-rates = <24576000>;
389 fsl,sai-mclk-direction-output; 337 fsl,sai-mclk-direction-output;
390 status = "okay"; 338 status = "okay";
391 }; 339 };
392 340
393 &snvs_pwrkey { 341 &snvs_pwrkey {
394 status = "okay"; 342 status = "okay";
395 }; 343 };
396 344
397 &spdif1 { 345 &spdif1 {
398 pinctrl-names = "default"; 346 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_spdif1>; 347 pinctrl-0 = <&pinctrl_spdif1>;
400 assigned-clocks = <&clk IMX8MN_CLK_SPD 348 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
401 assigned-clock-parents = <&clk IMX8MN_ 349 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
402 assigned-clock-rates = <24576000>; 350 assigned-clock-rates = <24576000>;
403 status = "okay"; 351 status = "okay";
404 }; 352 };
405 353
406 &uart1 { /* BT */ 354 &uart1 { /* BT */
407 pinctrl-names = "default"; 355 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_uart1>; 356 pinctrl-0 = <&pinctrl_uart1>;
409 assigned-clocks = <&clk IMX8MN_CLK_UAR 357 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
410 assigned-clock-parents = <&clk IMX8MN_ 358 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
411 uart-has-rtscts; 359 uart-has-rtscts;
412 status = "okay"; 360 status = "okay";
413 }; 361 };
414 362
415 &uart2 { /* console */ 363 &uart2 { /* console */
416 pinctrl-names = "default"; 364 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart2>; 365 pinctrl-0 = <&pinctrl_uart2>;
418 status = "okay"; 366 status = "okay";
419 }; 367 };
420 368
421 &uart3 { 369 &uart3 {
422 pinctrl-names = "default"; 370 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_uart3>; 371 pinctrl-0 = <&pinctrl_uart3>;
424 assigned-clocks = <&clk IMX8MN_CLK_UAR 372 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
425 assigned-clock-parents = <&clk IMX8MN_ 373 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
426 uart-has-rtscts; 374 uart-has-rtscts;
427 status = "okay"; 375 status = "okay";
428 }; 376 };
429 377
430 &usbphynop1 { 378 &usbphynop1 {
431 wakeup-source; 379 wakeup-source;
432 }; 380 };
433 381
434 &usbotg1 { 382 &usbotg1 {
435 dr_mode = "otg"; 383 dr_mode = "otg";
436 hnp-disable; 384 hnp-disable;
437 srp-disable; 385 srp-disable;
438 adp-disable; 386 adp-disable;
439 usb-role-switch; 387 usb-role-switch;
440 disable-over-current; 388 disable-over-current;
441 samsung,picophy-pre-emp-curr-control = 389 samsung,picophy-pre-emp-curr-control = <3>;
442 samsung,picophy-dc-vol-level-adjust = 390 samsung,picophy-dc-vol-level-adjust = <7>;
443 status = "okay"; 391 status = "okay";
444 392
445 port { 393 port {
446 usb1_drd_sw: endpoint { 394 usb1_drd_sw: endpoint {
447 remote-endpoint = <&ty 395 remote-endpoint = <&typec1_dr_sw>;
448 }; 396 };
449 }; 397 };
450 }; 398 };
451 399
452 &usdhc2 { 400 &usdhc2 {
453 assigned-clocks = <&clk IMX8MN_CLK_USD 401 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
454 assigned-clock-rates = <200000000>; 402 assigned-clock-rates = <200000000>;
455 pinctrl-names = "default", "state_100m 403 pinctrl-names = "default", "state_100mhz", "state_200mhz";
456 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 404 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
457 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 405 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
458 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 406 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
459 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 407 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
460 bus-width = <4>; 408 bus-width = <4>;
461 vmmc-supply = <®_usdhc2_vmmc>; 409 vmmc-supply = <®_usdhc2_vmmc>;
462 status = "okay"; 410 status = "okay";
463 }; 411 };
464 412
465 &usdhc3 { 413 &usdhc3 {
466 assigned-clocks = <&clk IMX8MN_CLK_USD 414 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
467 assigned-clock-rates = <400000000>; 415 assigned-clock-rates = <400000000>;
468 pinctrl-names = "default", "state_100m 416 pinctrl-names = "default", "state_100mhz", "state_200mhz";
469 pinctrl-0 = <&pinctrl_usdhc3>; 417 pinctrl-0 = <&pinctrl_usdhc3>;
470 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 418 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
471 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 419 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
472 bus-width = <8>; 420 bus-width = <8>;
473 non-removable; 421 non-removable;
474 status = "okay"; 422 status = "okay";
475 }; 423 };
476 424
477 &wdog1 { 425 &wdog1 {
478 pinctrl-names = "default"; 426 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_wdog>; 427 pinctrl-0 = <&pinctrl_wdog>;
480 fsl,ext-reset-output; 428 fsl,ext-reset-output;
481 status = "okay"; 429 status = "okay";
482 }; 430 };
483 431
484 &iomuxc { 432 &iomuxc {
485 pinctrl_camera: cameragrp { 433 pinctrl_camera: cameragrp {
486 fsl,pins = < 434 fsl,pins = <
487 MX8MN_IOMUXC_GPIO1_IO0 435 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
488 MX8MN_IOMUXC_GPIO1_IO0 436 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
489 MX8MN_IOMUXC_GPIO1_IO1 437 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
490 >; 438 >;
491 }; 439 };
492 440
493 pinctrl_fec1: fec1grp { 441 pinctrl_fec1: fec1grp {
494 fsl,pins = < 442 fsl,pins = <
495 MX8MN_IOMUXC_ENET_MDC_ 443 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
496 MX8MN_IOMUXC_ENET_MDIO 444 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
497 MX8MN_IOMUXC_ENET_TD3_ 445 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
498 MX8MN_IOMUXC_ENET_TD2_ 446 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
499 MX8MN_IOMUXC_ENET_TD1_ 447 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
500 MX8MN_IOMUXC_ENET_TD0_ 448 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
501 MX8MN_IOMUXC_ENET_RD3_ 449 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
502 MX8MN_IOMUXC_ENET_RD2_ 450 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
503 MX8MN_IOMUXC_ENET_RD1_ 451 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
504 MX8MN_IOMUXC_ENET_RD0_ 452 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
505 MX8MN_IOMUXC_ENET_TXC_ 453 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
506 MX8MN_IOMUXC_ENET_RXC_ 454 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
507 MX8MN_IOMUXC_ENET_RX_C 455 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
508 MX8MN_IOMUXC_ENET_TX_C 456 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
509 MX8MN_IOMUXC_SAI2_RXC_ 457 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
510 >; 458 >;
511 }; 459 };
512 460
513 pinctrl_flexspi: flexspigrp { 461 pinctrl_flexspi: flexspigrp {
514 fsl,pins = < 462 fsl,pins = <
515 MX8MN_IOMUXC_NAND_ALE_ 463 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
516 MX8MN_IOMUXC_NAND_CE0_ 464 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
517 MX8MN_IOMUXC_NAND_DATA 465 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
518 MX8MN_IOMUXC_NAND_DATA 466 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
519 MX8MN_IOMUXC_NAND_DATA 467 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
520 MX8MN_IOMUXC_NAND_DATA 468 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
521 >; 469 >;
522 }; 470 };
523 471
524 pinctrl_gpio_led: gpioledgrp { 472 pinctrl_gpio_led: gpioledgrp {
525 fsl,pins = < 473 fsl,pins = <
526 MX8MN_IOMUXC_NAND_READ 474 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
527 >; 475 >;
528 }; 476 };
529 477
530 pinctrl_gpio_wlf: gpiowlfgrp { 478 pinctrl_gpio_wlf: gpiowlfgrp {
531 fsl,pins = < 479 fsl,pins = <
532 MX8MN_IOMUXC_I2C4_SDA_ 480 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
533 >; 481 >;
534 }; 482 };
535 483
536 pinctrl_ir: irgrp { 484 pinctrl_ir: irgrp {
537 fsl,pins = < 485 fsl,pins = <
538 MX8MN_IOMUXC_GPIO1_IO1 486 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
539 >; 487 >;
540 }; 488 };
541 489
542 pinctrl_i2c1: i2c1grp { 490 pinctrl_i2c1: i2c1grp {
543 fsl,pins = < 491 fsl,pins = <
544 MX8MN_IOMUXC_I2C1_SCL_ 492 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
545 MX8MN_IOMUXC_I2C1_SDA_ 493 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
546 >; 494 >;
547 }; 495 };
548 496
549 pinctrl_i2c2: i2c2grp { 497 pinctrl_i2c2: i2c2grp {
550 fsl,pins = < 498 fsl,pins = <
551 MX8MN_IOMUXC_I2C2_SCL_ 499 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
552 MX8MN_IOMUXC_I2C2_SDA_ 500 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
553 >; 501 >;
554 }; 502 };
555 503
556 pinctrl_i2c2_gpio: i2c2gpiogrp { 504 pinctrl_i2c2_gpio: i2c2gpiogrp {
557 fsl,pins = < 505 fsl,pins = <
558 MX8MN_IOMUXC_I2C2_SCL_ 506 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
559 MX8MN_IOMUXC_I2C2_SDA_ 507 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
560 >; 508 >;
561 }; 509 };
562 510
563 pinctrl_i2c3: i2c3grp { 511 pinctrl_i2c3: i2c3grp {
564 fsl,pins = < 512 fsl,pins = <
565 MX8MN_IOMUXC_I2C3_SCL_ 513 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
566 MX8MN_IOMUXC_I2C3_SDA_ 514 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
567 >; 515 >;
568 }; 516 };
569 517
570 pinctrl_i2c3_gpio: i2c3gpiogrp { 518 pinctrl_i2c3_gpio: i2c3gpiogrp {
571 fsl,pins = < 519 fsl,pins = <
572 MX8MN_IOMUXC_I2C3_SCL_ 520 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
573 MX8MN_IOMUXC_I2C3_SDA_ 521 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
574 >; <<
575 }; <<
576 <<
577 pinctrl_pdm: pdmgrp { <<
578 fsl,pins = < <<
579 MX8MN_IOMUXC_SAI5_MCLK <<
580 MX8MN_IOMUXC_SAI5_RXC_ <<
581 MX8MN_IOMUXC_SAI5_RXFS <<
582 MX8MN_IOMUXC_SAI5_RXD0 <<
583 MX8MN_IOMUXC_SAI5_RXD1 <<
584 MX8MN_IOMUXC_SAI5_RXD2 <<
585 MX8MN_IOMUXC_SAI5_RXD3 <<
586 >; 522 >;
587 }; 523 };
588 524
589 pinctrl_pmic: pmicirqgrp { 525 pinctrl_pmic: pmicirqgrp {
590 fsl,pins = < 526 fsl,pins = <
591 MX8MN_IOMUXC_GPIO1_IO0 527 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
592 >; 528 >;
593 }; 529 };
594 530
595 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 531 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
596 fsl,pins = < 532 fsl,pins = <
597 MX8MN_IOMUXC_SD2_RESET 533 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
598 >; 534 >;
599 }; 535 };
600 536
601 pinctrl_sai2: sai2grp { 537 pinctrl_sai2: sai2grp {
602 fsl,pins = < 538 fsl,pins = <
603 MX8MN_IOMUXC_SAI2_TXC_ 539 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
604 MX8MN_IOMUXC_SAI2_TXFS 540 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
605 MX8MN_IOMUXC_SAI2_TXD0 541 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
606 MX8MN_IOMUXC_SAI2_RXD0 542 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
607 >; 543 >;
608 }; 544 };
609 545
610 pinctrl_sai3: sai3grp { 546 pinctrl_sai3: sai3grp {
611 fsl,pins = < 547 fsl,pins = <
612 MX8MN_IOMUXC_SAI3_TXFS 548 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
613 MX8MN_IOMUXC_SAI3_TXC_ 549 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
614 MX8MN_IOMUXC_SAI3_MCLK 550 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
615 MX8MN_IOMUXC_SAI3_TXD_ 551 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
616 >; 552 >;
617 }; 553 };
618 554
619 pinctrl_spdif1: spdif1grp { 555 pinctrl_spdif1: spdif1grp {
620 fsl,pins = < 556 fsl,pins = <
621 MX8MN_IOMUXC_SPDIF_TX_ 557 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
622 MX8MN_IOMUXC_SPDIF_RX_ 558 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
623 >; 559 >;
624 }; 560 };
625 561
626 pinctrl_typec1: typec1grp { 562 pinctrl_typec1: typec1grp {
627 fsl,pins = < 563 fsl,pins = <
628 MX8MN_IOMUXC_SD1_STROB 564 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
629 >; 565 >;
630 }; 566 };
631 567
632 pinctrl_uart1: uart1grp { 568 pinctrl_uart1: uart1grp {
633 fsl,pins = < 569 fsl,pins = <
634 MX8MN_IOMUXC_UART1_RXD 570 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
635 MX8MN_IOMUXC_UART1_TXD 571 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
636 MX8MN_IOMUXC_UART3_RXD 572 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
637 MX8MN_IOMUXC_UART3_TXD 573 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
638 >; 574 >;
639 }; 575 };
640 576
641 pinctrl_uart2: uart2grp { 577 pinctrl_uart2: uart2grp {
642 fsl,pins = < 578 fsl,pins = <
643 MX8MN_IOMUXC_UART2_RXD 579 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
644 MX8MN_IOMUXC_UART2_TXD 580 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
645 >; 581 >;
646 }; 582 };
647 583
648 pinctrl_uart3: uart3grp { 584 pinctrl_uart3: uart3grp {
649 fsl,pins = < 585 fsl,pins = <
650 MX8MN_IOMUXC_ECSPI1_SC 586 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
651 MX8MN_IOMUXC_ECSPI1_MO 587 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
652 MX8MN_IOMUXC_ECSPI1_SS 588 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
653 MX8MN_IOMUXC_ECSPI1_MI 589 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
654 >; 590 >;
655 }; 591 };
656 592
657 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 593 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
658 fsl,pins = < 594 fsl,pins = <
659 MX8MN_IOMUXC_GPIO1_IO1 595 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
660 >; 596 >;
661 }; 597 };
662 598
663 pinctrl_usdhc2: usdhc2grp { 599 pinctrl_usdhc2: usdhc2grp {
664 fsl,pins = < 600 fsl,pins = <
665 MX8MN_IOMUXC_SD2_CLK_U 601 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
666 MX8MN_IOMUXC_SD2_CMD_U 602 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
667 MX8MN_IOMUXC_SD2_DATA0 603 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
668 MX8MN_IOMUXC_SD2_DATA1 604 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
669 MX8MN_IOMUXC_SD2_DATA2 605 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
670 MX8MN_IOMUXC_SD2_DATA3 606 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
671 MX8MN_IOMUXC_GPIO1_IO0 607 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
672 >; 608 >;
673 }; 609 };
674 610
675 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 611 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
676 fsl,pins = < 612 fsl,pins = <
677 MX8MN_IOMUXC_SD2_CLK_U 613 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
678 MX8MN_IOMUXC_SD2_CMD_U 614 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
679 MX8MN_IOMUXC_SD2_DATA0 615 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
680 MX8MN_IOMUXC_SD2_DATA1 616 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
681 MX8MN_IOMUXC_SD2_DATA2 617 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
682 MX8MN_IOMUXC_SD2_DATA3 618 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
683 MX8MN_IOMUXC_GPIO1_IO0 619 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
684 >; 620 >;
685 }; 621 };
686 622
687 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 623 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
688 fsl,pins = < 624 fsl,pins = <
689 MX8MN_IOMUXC_SD2_CLK_U 625 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
690 MX8MN_IOMUXC_SD2_CMD_U 626 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
691 MX8MN_IOMUXC_SD2_DATA0 627 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
692 MX8MN_IOMUXC_SD2_DATA1 628 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
693 MX8MN_IOMUXC_SD2_DATA2 629 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
694 MX8MN_IOMUXC_SD2_DATA3 630 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
695 MX8MN_IOMUXC_GPIO1_IO0 631 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
696 >; 632 >;
697 }; 633 };
698 634
699 pinctrl_usdhc3: usdhc3grp { 635 pinctrl_usdhc3: usdhc3grp {
700 fsl,pins = < 636 fsl,pins = <
701 MX8MN_IOMUXC_NAND_WE_B 637 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
702 MX8MN_IOMUXC_NAND_WP_B 638 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
703 MX8MN_IOMUXC_NAND_DATA 639 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
704 MX8MN_IOMUXC_NAND_DATA 640 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
705 MX8MN_IOMUXC_NAND_DATA 641 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
706 MX8MN_IOMUXC_NAND_DATA 642 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
707 MX8MN_IOMUXC_NAND_RE_B 643 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
708 MX8MN_IOMUXC_NAND_CE2_ 644 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
709 MX8MN_IOMUXC_NAND_CE3_ 645 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
710 MX8MN_IOMUXC_NAND_CLE_ 646 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
711 MX8MN_IOMUXC_NAND_CE1_ 647 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
712 >; 648 >;
713 }; 649 };
714 650
715 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 651 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
716 fsl,pins = < 652 fsl,pins = <
717 MX8MN_IOMUXC_NAND_WE_B 653 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
718 MX8MN_IOMUXC_NAND_WP_B 654 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
719 MX8MN_IOMUXC_NAND_DATA 655 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
720 MX8MN_IOMUXC_NAND_DATA 656 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
721 MX8MN_IOMUXC_NAND_DATA 657 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
722 MX8MN_IOMUXC_NAND_DATA 658 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
723 MX8MN_IOMUXC_NAND_RE_B 659 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
724 MX8MN_IOMUXC_NAND_CE2_ 660 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
725 MX8MN_IOMUXC_NAND_CE3_ 661 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
726 MX8MN_IOMUXC_NAND_CLE_ 662 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
727 MX8MN_IOMUXC_NAND_CE1_ 663 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
728 >; 664 >;
729 }; 665 };
730 666
731 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 667 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
732 fsl,pins = < 668 fsl,pins = <
733 MX8MN_IOMUXC_NAND_WE_B 669 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
734 MX8MN_IOMUXC_NAND_WP_B 670 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
735 MX8MN_IOMUXC_NAND_DATA 671 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
736 MX8MN_IOMUXC_NAND_DATA 672 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
737 MX8MN_IOMUXC_NAND_DATA 673 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
738 MX8MN_IOMUXC_NAND_DATA 674 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
739 MX8MN_IOMUXC_NAND_RE_B 675 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
740 MX8MN_IOMUXC_NAND_CE2_ 676 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
741 MX8MN_IOMUXC_NAND_CE3_ 677 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
742 MX8MN_IOMUXC_NAND_CLE_ 678 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
743 MX8MN_IOMUXC_NAND_CE1_ 679 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
744 >; 680 >;
745 }; 681 };
746 682
747 pinctrl_wdog: wdoggrp { 683 pinctrl_wdog: wdoggrp {
748 fsl,pins = < 684 fsl,pins = <
749 MX8MN_IOMUXC_GPIO1_IO0 685 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
750 >; 686 >;
751 }; 687 };
752 }; 688 };
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