1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/usb/pd.h> 6 #include <dt-bindings/usb/pd.h>
7 #include "imx8mn.dtsi" 7 #include "imx8mn.dtsi"
8 8
9 / { 9 / {
10 chosen { 10 chosen {
11 stdout-path = &uart2; 11 stdout-path = &uart2;
12 }; 12 };
13 13
14 gpio-leds { 14 gpio-leds {
15 compatible = "gpio-leds"; 15 compatible = "gpio-leds";
16 pinctrl-names = "default"; 16 pinctrl-names = "default";
17 pinctrl-0 = <&pinctrl_gpio_led 17 pinctrl-0 = <&pinctrl_gpio_led>;
18 18
19 status { 19 status {
20 label = "yellow:status 20 label = "yellow:status";
21 gpios = <&gpio3 16 GPI 21 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
22 default-state = "on"; 22 default-state = "on";
23 }; 23 };
24 }; 24 };
25 25
26 hdmi-connector { 26 hdmi-connector {
27 compatible = "hdmi-connector"; 27 compatible = "hdmi-connector";
28 label = "hdmi"; 28 label = "hdmi";
29 type = "a"; 29 type = "a";
30 30
31 port { 31 port {
32 hdmi_connector_in: end 32 hdmi_connector_in: endpoint {
33 remote-endpoin !! 33 remote-endpoint = <&adv7533_out>;
34 }; 34 };
35 }; 35 };
36 }; 36 };
37 37
38 memory@40000000 { 38 memory@40000000 {
39 device_type = "memory"; 39 device_type = "memory";
40 reg = <0x0 0x40000000 0 0x8000 40 reg = <0x0 0x40000000 0 0x80000000>;
41 }; 41 };
42 42
43 reg_usdhc2_vmmc: regulator-usdhc2 { 43 reg_usdhc2_vmmc: regulator-usdhc2 {
44 compatible = "regulator-fixed" 44 compatible = "regulator-fixed";
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_reg_usdh 46 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
47 regulator-name = "VSD_3V3"; 47 regulator-name = "VSD_3V3";
48 regulator-min-microvolt = <330 48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <330 49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio2 19 GPIO_ACTIVE_ 50 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
51 off-on-delay-us = <12000>; 51 off-on-delay-us = <12000>;
52 enable-active-high; 52 enable-active-high;
53 }; 53 };
54 54
55 reg_1v5: regulator-1v5 { <<
56 compatible = "regulator-fixed" <<
57 regulator-name = "VDD_1V5"; <<
58 regulator-min-microvolt = <150 <<
59 regulator-max-microvolt = <150 <<
60 }; <<
61 <<
62 reg_1v8: regulator-1v8 { <<
63 compatible = "regulator-fixed" <<
64 regulator-name = "VDD_1V8"; <<
65 regulator-min-microvolt = <180 <<
66 regulator-max-microvolt = <180 <<
67 }; <<
68 <<
69 reg_vddext_3v3: regulator-vddext-3v3 { <<
70 compatible = "regulator-fixed" <<
71 regulator-name = "VDDEXT_3V3"; <<
72 regulator-min-microvolt = <330 <<
73 regulator-max-microvolt = <330 <<
74 }; <<
75 <<
76 ir-receiver { 55 ir-receiver {
77 compatible = "gpio-ir-receiver 56 compatible = "gpio-ir-receiver";
78 gpios = <&gpio1 13 GPIO_ACTIVE 57 gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
79 pinctrl-names = "default"; 58 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_ir>; 59 pinctrl-0 = <&pinctrl_ir>;
81 linux,autosuspend-period = <12 60 linux,autosuspend-period = <125>;
82 }; 61 };
83 62
84 audio_codec_bt_sco: audio-codec-bt-sco 63 audio_codec_bt_sco: audio-codec-bt-sco {
85 compatible = "linux,bt-sco"; 64 compatible = "linux,bt-sco";
86 #sound-dai-cells = <1>; 65 #sound-dai-cells = <1>;
87 }; 66 };
88 67
89 wm8524: audio-codec { 68 wm8524: audio-codec {
90 #sound-dai-cells = <0>; 69 #sound-dai-cells = <0>;
91 compatible = "wlf,wm8524"; 70 compatible = "wlf,wm8524";
92 pinctrl-names = "default"; 71 pinctrl-names = "default";
93 pinctrl-0 = <&pinctrl_gpio_wlf 72 pinctrl-0 = <&pinctrl_gpio_wlf>;
94 wlf,mute-gpios = <&gpio5 21 GP 73 wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
95 }; 74 };
96 75
97 sound-bt-sco { 76 sound-bt-sco {
98 compatible = "simple-audio-car 77 compatible = "simple-audio-card";
99 simple-audio-card,name = "bt-s 78 simple-audio-card,name = "bt-sco-audio";
100 simple-audio-card,format = "ds 79 simple-audio-card,format = "dsp_a";
101 simple-audio-card,bitclock-inv 80 simple-audio-card,bitclock-inversion;
102 simple-audio-card,frame-master 81 simple-audio-card,frame-master = <&btcpu>;
103 simple-audio-card,bitclock-mas 82 simple-audio-card,bitclock-master = <&btcpu>;
104 83
105 btcpu: simple-audio-card,cpu { 84 btcpu: simple-audio-card,cpu {
106 sound-dai = <&sai2>; 85 sound-dai = <&sai2>;
107 dai-tdm-slot-num = <2> 86 dai-tdm-slot-num = <2>;
108 dai-tdm-slot-width = < 87 dai-tdm-slot-width = <16>;
109 }; 88 };
110 89
111 simple-audio-card,codec { 90 simple-audio-card,codec {
112 sound-dai = <&audio_co 91 sound-dai = <&audio_codec_bt_sco 1>;
113 }; 92 };
114 }; 93 };
115 94
116 sound-wm8524 { 95 sound-wm8524 {
117 compatible = "fsl,imx-audio-wm 96 compatible = "fsl,imx-audio-wm8524";
118 model = "wm8524-audio"; 97 model = "wm8524-audio";
119 audio-cpu = <&sai3>; 98 audio-cpu = <&sai3>;
120 audio-codec = <&wm8524>; 99 audio-codec = <&wm8524>;
121 audio-asrc = <&easrc>; 100 audio-asrc = <&easrc>;
122 audio-routing = 101 audio-routing =
123 "Line Out Jack", "LINE 102 "Line Out Jack", "LINEVOUTL",
124 "Line Out Jack", "LINE 103 "Line Out Jack", "LINEVOUTR";
125 }; 104 };
126 105
127 spdif_out: spdif-out { <<
128 compatible = "linux,spdif-dit" <<
129 #sound-dai-cells = <0>; <<
130 }; <<
131 <<
132 spdif_in: spdif-in { <<
133 compatible = "linux,spdif-dir" <<
134 #sound-dai-cells = <0>; <<
135 }; <<
136 <<
137 sound-spdif { 106 sound-spdif {
138 compatible = "fsl,imx-audio-sp 107 compatible = "fsl,imx-audio-spdif";
139 model = "imx-spdif"; 108 model = "imx-spdif";
140 audio-cpu = <&spdif1>; !! 109 spdif-controller = <&spdif1>;
141 audio-codec = <&spdif_out>, <& !! 110 spdif-out;
>> 111 spdif-in;
142 }; 112 };
143 113
144 sound-micfil { 114 sound-micfil {
145 compatible = "fsl,imx-audio-ca 115 compatible = "fsl,imx-audio-card";
146 model = "micfil-audio"; 116 model = "micfil-audio";
147 117
148 pri-dai-link { 118 pri-dai-link {
149 link-name = "micfil hi 119 link-name = "micfil hifi";
150 format = "i2s"; 120 format = "i2s";
151 121
152 cpu { 122 cpu {
153 sound-dai = <& 123 sound-dai = <&micfil>;
154 }; 124 };
155 }; 125 };
156 }; 126 };
157 }; 127 };
158 128
159 &easrc { 129 &easrc {
160 fsl,asrc-rate = <48000>; 130 fsl,asrc-rate = <48000>;
161 status = "okay"; 131 status = "okay";
162 }; 132 };
163 133
164 &fec1 { 134 &fec1 {
165 pinctrl-names = "default"; 135 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_fec1>; 136 pinctrl-0 = <&pinctrl_fec1>;
167 phy-mode = "rgmii-id"; 137 phy-mode = "rgmii-id";
168 phy-handle = <ðphy0>; 138 phy-handle = <ðphy0>;
169 fsl,magic-packet; 139 fsl,magic-packet;
170 status = "okay"; 140 status = "okay";
171 141
172 mdio { 142 mdio {
173 #address-cells = <1>; 143 #address-cells = <1>;
174 #size-cells = <0>; 144 #size-cells = <0>;
175 145
176 ethphy0: ethernet-phy@0 { 146 ethphy0: ethernet-phy@0 {
177 compatible = "ethernet 147 compatible = "ethernet-phy-ieee802.3-c22";
178 reg = <0>; 148 reg = <0>;
179 reset-gpios = <&gpio4 149 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
180 reset-assert-us = <100 150 reset-assert-us = <10000>;
181 qca,disable-smarteee; 151 qca,disable-smarteee;
182 vddio-supply = <&vddio 152 vddio-supply = <&vddio>;
183 153
184 vddio: vddio-regulator 154 vddio: vddio-regulator {
185 regulator-min- 155 regulator-min-microvolt = <1800000>;
186 regulator-max- 156 regulator-max-microvolt = <1800000>;
187 }; 157 };
188 }; 158 };
189 }; 159 };
190 }; 160 };
191 161
192 &flexspi { 162 &flexspi {
193 pinctrl-names = "default"; 163 pinctrl-names = "default";
194 pinctrl-0 = <&pinctrl_flexspi>; 164 pinctrl-0 = <&pinctrl_flexspi>;
195 status = "okay"; 165 status = "okay";
196 166
197 flash0: flash@0 { 167 flash0: flash@0 {
198 compatible = "jedec,spi-nor"; 168 compatible = "jedec,spi-nor";
199 reg = <0>; 169 reg = <0>;
200 #address-cells = <1>; 170 #address-cells = <1>;
201 #size-cells = <1>; 171 #size-cells = <1>;
202 spi-max-frequency = <166000000 172 spi-max-frequency = <166000000>;
203 spi-tx-bus-width = <4>; 173 spi-tx-bus-width = <4>;
204 spi-rx-bus-width = <4>; 174 spi-rx-bus-width = <4>;
205 }; 175 };
206 }; 176 };
207 177
208 &i2c1 { 178 &i2c1 {
209 clock-frequency = <400000>; 179 clock-frequency = <400000>;
210 pinctrl-names = "default"; 180 pinctrl-names = "default";
211 pinctrl-0 = <&pinctrl_i2c1>; 181 pinctrl-0 = <&pinctrl_i2c1>;
212 status = "okay"; 182 status = "okay";
213 }; 183 };
214 184
215 &i2c2 { 185 &i2c2 {
216 clock-frequency = <400000>; 186 clock-frequency = <400000>;
217 pinctrl-names = "default", "gpio"; 187 pinctrl-names = "default", "gpio";
218 pinctrl-0 = <&pinctrl_i2c2>; 188 pinctrl-0 = <&pinctrl_i2c2>;
219 pinctrl-1 = <&pinctrl_i2c2_gpio>; 189 pinctrl-1 = <&pinctrl_i2c2_gpio>;
220 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 190 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
221 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 191 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
222 status = "okay"; 192 status = "okay";
223 193
224 hdmi@3d { 194 hdmi@3d {
225 compatible = "adi,adv7535"; 195 compatible = "adi,adv7535";
226 reg = <0x3d>; !! 196 reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>;
227 interrupt-parent = <&gpio1>; !! 197 reg-names = "main", "cec", "edid", "packet";
228 interrupts = <9 IRQ_TYPE_EDGE_ <<
229 adi,dsi-lanes = <4>; 198 adi,dsi-lanes = <4>;
230 v3p3-supply = <®_vddext_3v3 !! 199
>> 200 adi,input-depth = <8>;
>> 201 adi,input-colorspace = "rgb";
>> 202 adi,input-clock = "1x";
>> 203 adi,input-style = <1>;
>> 204 adi,input-justification = "evenly";
231 205
232 ports { 206 ports {
233 #address-cells = <1>; 207 #address-cells = <1>;
234 #size-cells = <0>; 208 #size-cells = <0>;
235 209
236 port@0 { 210 port@0 {
237 reg = <0>; 211 reg = <0>;
238 212
239 adv7535_in: en !! 213 adv7533_in: endpoint {
240 remote 214 remote-endpoint = <&dsi_out>;
241 }; 215 };
242 }; 216 };
243 217
244 port@1 { 218 port@1 {
245 reg = <1>; 219 reg = <1>;
246 220
247 adv7535_out: e !! 221 adv7533_out: endpoint {
248 remote 222 remote-endpoint = <&hdmi_connector_in>;
249 }; 223 };
250 }; 224 };
251 225
252 }; 226 };
253 }; 227 };
254 228
255 ptn5110: tcpc@50 { 229 ptn5110: tcpc@50 {
256 compatible = "nxp,ptn5110", "t !! 230 compatible = "nxp,ptn5110";
257 pinctrl-names = "default"; 231 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_typec1>; 232 pinctrl-0 = <&pinctrl_typec1>;
259 reg = <0x50>; 233 reg = <0x50>;
260 interrupt-parent = <&gpio2>; 234 interrupt-parent = <&gpio2>;
261 interrupts = <11 IRQ_TYPE_LEVE 235 interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
262 status = "okay"; 236 status = "okay";
263 237
264 typec1_con: connector { 238 typec1_con: connector {
265 compatible = "usb-c-co 239 compatible = "usb-c-connector";
266 label = "USB-C"; 240 label = "USB-C";
267 power-role = "dual"; 241 power-role = "dual";
268 data-role = "dual"; 242 data-role = "dual";
269 try-power-role = "sink 243 try-power-role = "sink";
270 source-pdos = <PDO_FIX 244 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
271 sink-pdos = <PDO_FIXED 245 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)
272 PDO_VAR(5 246 PDO_VAR(5000, 20000, 3000)>;
273 op-sink-microwatt = <1 247 op-sink-microwatt = <15000000>;
274 self-powered; 248 self-powered;
275 249
276 port { 250 port {
277 typec1_dr_sw: 251 typec1_dr_sw: endpoint {
278 remote 252 remote-endpoint = <&usb1_drd_sw>;
279 }; 253 };
280 }; 254 };
281 }; 255 };
282 }; 256 };
283 }; 257 };
284 258
285 &i2c3 { 259 &i2c3 {
286 clock-frequency = <400000>; 260 clock-frequency = <400000>;
287 pinctrl-names = "default", "gpio"; 261 pinctrl-names = "default", "gpio";
288 pinctrl-0 = <&pinctrl_i2c3>; 262 pinctrl-0 = <&pinctrl_i2c3>;
289 pinctrl-1 = <&pinctrl_i2c3_gpio>; 263 pinctrl-1 = <&pinctrl_i2c3_gpio>;
290 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIG 264 scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
291 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIG 265 sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
292 status = "okay"; 266 status = "okay";
293 267
294 pca6416: gpio@20 { 268 pca6416: gpio@20 {
295 compatible = "ti,tca6416"; 269 compatible = "ti,tca6416";
296 reg = <0x20>; 270 reg = <0x20>;
297 gpio-controller; 271 gpio-controller;
298 #gpio-cells = <2>; 272 #gpio-cells = <2>;
299 }; 273 };
300 274
301 camera@3c { 275 camera@3c {
302 compatible = "ovti,ov5640"; 276 compatible = "ovti,ov5640";
303 reg = <0x3c>; 277 reg = <0x3c>;
304 pinctrl-names = "default"; 278 pinctrl-names = "default";
305 pinctrl-0 = <&pinctrl_camera>; 279 pinctrl-0 = <&pinctrl_camera>;
306 clocks = <&clk IMX8MN_CLK_CLKO 280 clocks = <&clk IMX8MN_CLK_CLKO1>;
307 clock-names = "xclk"; 281 clock-names = "xclk";
308 assigned-clocks = <&clk IMX8MN 282 assigned-clocks = <&clk IMX8MN_CLK_CLKO1>;
309 assigned-clock-parents = <&clk 283 assigned-clock-parents = <&clk IMX8MN_CLK_24M>;
310 assigned-clock-rates = <240000 284 assigned-clock-rates = <24000000>;
311 powerdown-gpios = <&gpio1 7 GP 285 powerdown-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
312 reset-gpios = <&gpio1 6 GPIO_A 286 reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
313 AVDD-supply = <®_1v8>; <<
314 DVDD-supply = <®_1v5>; <<
315 287
316 port { 288 port {
317 ov5640_to_mipi_csi2: e 289 ov5640_to_mipi_csi2: endpoint {
318 remote-endpoin 290 remote-endpoint = <&imx8mn_mipi_csi_in>;
319 clock-lanes = 291 clock-lanes = <0>;
320 data-lanes = < 292 data-lanes = <1 2>;
321 }; 293 };
322 }; 294 };
323 }; 295 };
324 }; 296 };
325 297
326 &isi { 298 &isi {
327 status = "okay"; 299 status = "okay";
328 }; 300 };
329 301
330 &micfil { 302 &micfil {
331 #sound-dai-cells = <0>; 303 #sound-dai-cells = <0>;
332 pinctrl-names = "default"; 304 pinctrl-names = "default";
333 pinctrl-0 = <&pinctrl_pdm>; 305 pinctrl-0 = <&pinctrl_pdm>;
334 assigned-clocks = <&clk IMX8MN_CLK_PDM 306 assigned-clocks = <&clk IMX8MN_CLK_PDM>;
335 assigned-clock-parents = <&clk IMX8MN_ 307 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
336 assigned-clock-rates = <196608000>; 308 assigned-clock-rates = <196608000>;
337 status = "okay"; 309 status = "okay";
338 }; 310 };
339 311
340 &mipi_csi { 312 &mipi_csi {
341 status = "okay"; 313 status = "okay";
342 314
343 ports { 315 ports {
344 port@0 { 316 port@0 {
345 imx8mn_mipi_csi_in: en 317 imx8mn_mipi_csi_in: endpoint {
346 remote-endpoin 318 remote-endpoint = <&ov5640_to_mipi_csi2>;
347 data-lanes = < 319 data-lanes = <1 2>;
348 }; 320 };
349 }; 321 };
350 }; 322 };
351 }; 323 };
352 324
353 &lcdif { 325 &lcdif {
354 status = "okay"; 326 status = "okay";
355 }; 327 };
356 328
357 &mipi_dsi { 329 &mipi_dsi {
358 samsung,esc-clock-frequency = <1000000 330 samsung,esc-clock-frequency = <10000000>;
359 status = "okay"; 331 status = "okay";
360 332
361 ports { 333 ports {
362 port@1 { 334 port@1 {
363 reg = <1>; 335 reg = <1>;
364 336
365 dsi_out: endpoint { 337 dsi_out: endpoint {
366 remote-endpoin !! 338 remote-endpoint = <&adv7533_in>;
367 data-lanes = < 339 data-lanes = <1 2 3 4>;
368 }; 340 };
369 }; 341 };
370 }; 342 };
371 }; 343 };
372 344
373 &sai2 { 345 &sai2 {
374 #sound-dai-cells = <0>; 346 #sound-dai-cells = <0>;
375 pinctrl-names = "default"; 347 pinctrl-names = "default";
376 pinctrl-0 = <&pinctrl_sai2>; 348 pinctrl-0 = <&pinctrl_sai2>;
377 assigned-clocks = <&clk IMX8MN_CLK_SAI 349 assigned-clocks = <&clk IMX8MN_CLK_SAI2>;
378 assigned-clock-parents = <&clk IMX8MN_ 350 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
379 assigned-clock-rates = <24576000>; 351 assigned-clock-rates = <24576000>;
380 status = "okay"; 352 status = "okay";
381 }; 353 };
382 354
383 &sai3 { 355 &sai3 {
384 pinctrl-names = "default"; 356 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_sai3>; 357 pinctrl-0 = <&pinctrl_sai3>;
386 assigned-clocks = <&clk IMX8MN_CLK_SAI 358 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
387 assigned-clock-parents = <&clk IMX8MN_ 359 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
388 assigned-clock-rates = <24576000>; 360 assigned-clock-rates = <24576000>;
389 fsl,sai-mclk-direction-output; 361 fsl,sai-mclk-direction-output;
390 status = "okay"; 362 status = "okay";
391 }; 363 };
392 364
393 &snvs_pwrkey { 365 &snvs_pwrkey {
394 status = "okay"; 366 status = "okay";
395 }; 367 };
396 368
397 &spdif1 { 369 &spdif1 {
398 pinctrl-names = "default"; 370 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_spdif1>; 371 pinctrl-0 = <&pinctrl_spdif1>;
400 assigned-clocks = <&clk IMX8MN_CLK_SPD 372 assigned-clocks = <&clk IMX8MN_CLK_SPDIF1>;
401 assigned-clock-parents = <&clk IMX8MN_ 373 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
402 assigned-clock-rates = <24576000>; 374 assigned-clock-rates = <24576000>;
403 status = "okay"; 375 status = "okay";
404 }; 376 };
405 377
406 &uart1 { /* BT */ 378 &uart1 { /* BT */
407 pinctrl-names = "default"; 379 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_uart1>; 380 pinctrl-0 = <&pinctrl_uart1>;
409 assigned-clocks = <&clk IMX8MN_CLK_UAR 381 assigned-clocks = <&clk IMX8MN_CLK_UART1>;
410 assigned-clock-parents = <&clk IMX8MN_ 382 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
411 uart-has-rtscts; 383 uart-has-rtscts;
412 status = "okay"; 384 status = "okay";
413 }; 385 };
414 386
415 &uart2 { /* console */ 387 &uart2 { /* console */
416 pinctrl-names = "default"; 388 pinctrl-names = "default";
417 pinctrl-0 = <&pinctrl_uart2>; 389 pinctrl-0 = <&pinctrl_uart2>;
418 status = "okay"; 390 status = "okay";
419 }; 391 };
420 392
421 &uart3 { 393 &uart3 {
422 pinctrl-names = "default"; 394 pinctrl-names = "default";
423 pinctrl-0 = <&pinctrl_uart3>; 395 pinctrl-0 = <&pinctrl_uart3>;
424 assigned-clocks = <&clk IMX8MN_CLK_UAR 396 assigned-clocks = <&clk IMX8MN_CLK_UART3>;
425 assigned-clock-parents = <&clk IMX8MN_ 397 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
426 uart-has-rtscts; 398 uart-has-rtscts;
427 status = "okay"; 399 status = "okay";
428 }; 400 };
429 401
430 &usbphynop1 { 402 &usbphynop1 {
431 wakeup-source; 403 wakeup-source;
432 }; 404 };
433 405
434 &usbotg1 { 406 &usbotg1 {
435 dr_mode = "otg"; 407 dr_mode = "otg";
436 hnp-disable; 408 hnp-disable;
437 srp-disable; 409 srp-disable;
438 adp-disable; 410 adp-disable;
439 usb-role-switch; 411 usb-role-switch;
440 disable-over-current; 412 disable-over-current;
441 samsung,picophy-pre-emp-curr-control = 413 samsung,picophy-pre-emp-curr-control = <3>;
442 samsung,picophy-dc-vol-level-adjust = 414 samsung,picophy-dc-vol-level-adjust = <7>;
443 status = "okay"; 415 status = "okay";
444 416
445 port { 417 port {
446 usb1_drd_sw: endpoint { 418 usb1_drd_sw: endpoint {
447 remote-endpoint = <&ty 419 remote-endpoint = <&typec1_dr_sw>;
448 }; 420 };
449 }; 421 };
450 }; 422 };
451 423
452 &usdhc2 { 424 &usdhc2 {
453 assigned-clocks = <&clk IMX8MN_CLK_USD 425 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
454 assigned-clock-rates = <200000000>; 426 assigned-clock-rates = <200000000>;
455 pinctrl-names = "default", "state_100m 427 pinctrl-names = "default", "state_100mhz", "state_200mhz";
456 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 428 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
457 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 429 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
458 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 430 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
459 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW> 431 cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
460 bus-width = <4>; 432 bus-width = <4>;
461 vmmc-supply = <®_usdhc2_vmmc>; 433 vmmc-supply = <®_usdhc2_vmmc>;
462 status = "okay"; 434 status = "okay";
463 }; 435 };
464 436
465 &usdhc3 { 437 &usdhc3 {
466 assigned-clocks = <&clk IMX8MN_CLK_USD 438 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
467 assigned-clock-rates = <400000000>; 439 assigned-clock-rates = <400000000>;
468 pinctrl-names = "default", "state_100m 440 pinctrl-names = "default", "state_100mhz", "state_200mhz";
469 pinctrl-0 = <&pinctrl_usdhc3>; 441 pinctrl-0 = <&pinctrl_usdhc3>;
470 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 442 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
471 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 443 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
472 bus-width = <8>; 444 bus-width = <8>;
473 non-removable; 445 non-removable;
474 status = "okay"; 446 status = "okay";
475 }; 447 };
476 448
477 &wdog1 { 449 &wdog1 {
478 pinctrl-names = "default"; 450 pinctrl-names = "default";
479 pinctrl-0 = <&pinctrl_wdog>; 451 pinctrl-0 = <&pinctrl_wdog>;
480 fsl,ext-reset-output; 452 fsl,ext-reset-output;
481 status = "okay"; 453 status = "okay";
482 }; 454 };
483 455
484 &iomuxc { 456 &iomuxc {
485 pinctrl_camera: cameragrp { 457 pinctrl_camera: cameragrp {
486 fsl,pins = < 458 fsl,pins = <
487 MX8MN_IOMUXC_GPIO1_IO0 459 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19
488 MX8MN_IOMUXC_GPIO1_IO0 460 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
489 MX8MN_IOMUXC_GPIO1_IO1 461 MX8MN_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1 0x59
490 >; 462 >;
491 }; 463 };
492 464
493 pinctrl_fec1: fec1grp { 465 pinctrl_fec1: fec1grp {
494 fsl,pins = < 466 fsl,pins = <
495 MX8MN_IOMUXC_ENET_MDC_ 467 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
496 MX8MN_IOMUXC_ENET_MDIO 468 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
497 MX8MN_IOMUXC_ENET_TD3_ 469 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
498 MX8MN_IOMUXC_ENET_TD2_ 470 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
499 MX8MN_IOMUXC_ENET_TD1_ 471 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
500 MX8MN_IOMUXC_ENET_TD0_ 472 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
501 MX8MN_IOMUXC_ENET_RD3_ 473 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
502 MX8MN_IOMUXC_ENET_RD2_ 474 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
503 MX8MN_IOMUXC_ENET_RD1_ 475 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
504 MX8MN_IOMUXC_ENET_RD0_ 476 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
505 MX8MN_IOMUXC_ENET_TXC_ 477 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
506 MX8MN_IOMUXC_ENET_RXC_ 478 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
507 MX8MN_IOMUXC_ENET_RX_C 479 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
508 MX8MN_IOMUXC_ENET_TX_C 480 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
509 MX8MN_IOMUXC_SAI2_RXC_ 481 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x19
510 >; 482 >;
511 }; 483 };
512 484
513 pinctrl_flexspi: flexspigrp { 485 pinctrl_flexspi: flexspigrp {
514 fsl,pins = < 486 fsl,pins = <
515 MX8MN_IOMUXC_NAND_ALE_ 487 MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
516 MX8MN_IOMUXC_NAND_CE0_ 488 MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
517 MX8MN_IOMUXC_NAND_DATA 489 MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
518 MX8MN_IOMUXC_NAND_DATA 490 MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
519 MX8MN_IOMUXC_NAND_DATA 491 MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
520 MX8MN_IOMUXC_NAND_DATA 492 MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
521 >; 493 >;
522 }; 494 };
523 495
524 pinctrl_gpio_led: gpioledgrp { 496 pinctrl_gpio_led: gpioledgrp {
525 fsl,pins = < 497 fsl,pins = <
526 MX8MN_IOMUXC_NAND_READ 498 MX8MN_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
527 >; 499 >;
528 }; 500 };
529 501
530 pinctrl_gpio_wlf: gpiowlfgrp { 502 pinctrl_gpio_wlf: gpiowlfgrp {
531 fsl,pins = < 503 fsl,pins = <
532 MX8MN_IOMUXC_I2C4_SDA_ 504 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0xd6
533 >; 505 >;
534 }; 506 };
535 507
536 pinctrl_ir: irgrp { 508 pinctrl_ir: irgrp {
537 fsl,pins = < 509 fsl,pins = <
538 MX8MN_IOMUXC_GPIO1_IO1 510 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x4f
539 >; 511 >;
540 }; 512 };
541 513
542 pinctrl_i2c1: i2c1grp { 514 pinctrl_i2c1: i2c1grp {
543 fsl,pins = < 515 fsl,pins = <
544 MX8MN_IOMUXC_I2C1_SCL_ 516 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
545 MX8MN_IOMUXC_I2C1_SDA_ 517 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
546 >; 518 >;
547 }; 519 };
548 520
549 pinctrl_i2c2: i2c2grp { 521 pinctrl_i2c2: i2c2grp {
550 fsl,pins = < 522 fsl,pins = <
551 MX8MN_IOMUXC_I2C2_SCL_ 523 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
552 MX8MN_IOMUXC_I2C2_SDA_ 524 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
553 >; 525 >;
554 }; 526 };
555 527
556 pinctrl_i2c2_gpio: i2c2gpiogrp { 528 pinctrl_i2c2_gpio: i2c2gpiogrp {
557 fsl,pins = < 529 fsl,pins = <
558 MX8MN_IOMUXC_I2C2_SCL_ 530 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1c3
559 MX8MN_IOMUXC_I2C2_SDA_ 531 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1c3
560 >; 532 >;
561 }; 533 };
562 534
563 pinctrl_i2c3: i2c3grp { 535 pinctrl_i2c3: i2c3grp {
564 fsl,pins = < 536 fsl,pins = <
565 MX8MN_IOMUXC_I2C3_SCL_ 537 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
566 MX8MN_IOMUXC_I2C3_SDA_ 538 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
567 >; 539 >;
568 }; 540 };
569 541
570 pinctrl_i2c3_gpio: i2c3gpiogrp { 542 pinctrl_i2c3_gpio: i2c3gpiogrp {
571 fsl,pins = < 543 fsl,pins = <
572 MX8MN_IOMUXC_I2C3_SCL_ 544 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1c3
573 MX8MN_IOMUXC_I2C3_SDA_ 545 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1c3
574 >; 546 >;
575 }; 547 };
576 548
577 pinctrl_pdm: pdmgrp { 549 pinctrl_pdm: pdmgrp {
578 fsl,pins = < 550 fsl,pins = <
579 MX8MN_IOMUXC_SAI5_MCLK 551 MX8MN_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
580 MX8MN_IOMUXC_SAI5_RXC_ 552 MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
581 MX8MN_IOMUXC_SAI5_RXFS 553 MX8MN_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
582 MX8MN_IOMUXC_SAI5_RXD0 554 MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6
583 MX8MN_IOMUXC_SAI5_RXD1 555 MX8MN_IOMUXC_SAI5_RXD1_PDM_BIT_STREAM1 0xd6
584 MX8MN_IOMUXC_SAI5_RXD2 556 MX8MN_IOMUXC_SAI5_RXD2_PDM_BIT_STREAM2 0xd6
585 MX8MN_IOMUXC_SAI5_RXD3 557 MX8MN_IOMUXC_SAI5_RXD3_PDM_BIT_STREAM3 0xd6
586 >; 558 >;
587 }; 559 };
588 560
589 pinctrl_pmic: pmicirqgrp { 561 pinctrl_pmic: pmicirqgrp {
590 fsl,pins = < 562 fsl,pins = <
591 MX8MN_IOMUXC_GPIO1_IO0 563 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
592 >; 564 >;
593 }; 565 };
594 566
595 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 567 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
596 fsl,pins = < 568 fsl,pins = <
597 MX8MN_IOMUXC_SD2_RESET 569 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
598 >; 570 >;
599 }; 571 };
600 572
601 pinctrl_sai2: sai2grp { 573 pinctrl_sai2: sai2grp {
602 fsl,pins = < 574 fsl,pins = <
603 MX8MN_IOMUXC_SAI2_TXC_ 575 MX8MN_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
604 MX8MN_IOMUXC_SAI2_TXFS 576 MX8MN_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
605 MX8MN_IOMUXC_SAI2_TXD0 577 MX8MN_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
606 MX8MN_IOMUXC_SAI2_RXD0 578 MX8MN_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
607 >; 579 >;
608 }; 580 };
609 581
610 pinctrl_sai3: sai3grp { 582 pinctrl_sai3: sai3grp {
611 fsl,pins = < 583 fsl,pins = <
612 MX8MN_IOMUXC_SAI3_TXFS 584 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
613 MX8MN_IOMUXC_SAI3_TXC_ 585 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
614 MX8MN_IOMUXC_SAI3_MCLK 586 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
615 MX8MN_IOMUXC_SAI3_TXD_ 587 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
616 >; 588 >;
617 }; 589 };
618 590
619 pinctrl_spdif1: spdif1grp { 591 pinctrl_spdif1: spdif1grp {
620 fsl,pins = < 592 fsl,pins = <
621 MX8MN_IOMUXC_SPDIF_TX_ 593 MX8MN_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
622 MX8MN_IOMUXC_SPDIF_RX_ 594 MX8MN_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
623 >; 595 >;
624 }; 596 };
625 597
626 pinctrl_typec1: typec1grp { 598 pinctrl_typec1: typec1grp {
627 fsl,pins = < 599 fsl,pins = <
628 MX8MN_IOMUXC_SD1_STROB 600 MX8MN_IOMUXC_SD1_STROBE_GPIO2_IO11 0x159
629 >; 601 >;
630 }; 602 };
631 603
632 pinctrl_uart1: uart1grp { 604 pinctrl_uart1: uart1grp {
633 fsl,pins = < 605 fsl,pins = <
634 MX8MN_IOMUXC_UART1_RXD 606 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
635 MX8MN_IOMUXC_UART1_TXD 607 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
636 MX8MN_IOMUXC_UART3_RXD 608 MX8MN_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
637 MX8MN_IOMUXC_UART3_TXD 609 MX8MN_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
638 >; 610 >;
639 }; 611 };
640 612
641 pinctrl_uart2: uart2grp { 613 pinctrl_uart2: uart2grp {
642 fsl,pins = < 614 fsl,pins = <
643 MX8MN_IOMUXC_UART2_RXD 615 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
644 MX8MN_IOMUXC_UART2_TXD 616 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
645 >; 617 >;
646 }; 618 };
647 619
648 pinctrl_uart3: uart3grp { 620 pinctrl_uart3: uart3grp {
649 fsl,pins = < 621 fsl,pins = <
650 MX8MN_IOMUXC_ECSPI1_SC 622 MX8MN_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
651 MX8MN_IOMUXC_ECSPI1_MO 623 MX8MN_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
652 MX8MN_IOMUXC_ECSPI1_SS 624 MX8MN_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
653 MX8MN_IOMUXC_ECSPI1_MI 625 MX8MN_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
654 >; 626 >;
655 }; 627 };
656 628
657 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 629 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
658 fsl,pins = < 630 fsl,pins = <
659 MX8MN_IOMUXC_GPIO1_IO1 631 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
660 >; 632 >;
661 }; 633 };
662 634
663 pinctrl_usdhc2: usdhc2grp { 635 pinctrl_usdhc2: usdhc2grp {
664 fsl,pins = < 636 fsl,pins = <
665 MX8MN_IOMUXC_SD2_CLK_U 637 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
666 MX8MN_IOMUXC_SD2_CMD_U 638 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
667 MX8MN_IOMUXC_SD2_DATA0 639 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
668 MX8MN_IOMUXC_SD2_DATA1 640 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
669 MX8MN_IOMUXC_SD2_DATA2 641 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
670 MX8MN_IOMUXC_SD2_DATA3 642 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
671 MX8MN_IOMUXC_GPIO1_IO0 643 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
672 >; 644 >;
673 }; 645 };
674 646
675 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 647 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
676 fsl,pins = < 648 fsl,pins = <
677 MX8MN_IOMUXC_SD2_CLK_U 649 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
678 MX8MN_IOMUXC_SD2_CMD_U 650 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
679 MX8MN_IOMUXC_SD2_DATA0 651 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
680 MX8MN_IOMUXC_SD2_DATA1 652 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
681 MX8MN_IOMUXC_SD2_DATA2 653 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
682 MX8MN_IOMUXC_SD2_DATA3 654 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
683 MX8MN_IOMUXC_GPIO1_IO0 655 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
684 >; 656 >;
685 }; 657 };
686 658
687 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 659 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
688 fsl,pins = < 660 fsl,pins = <
689 MX8MN_IOMUXC_SD2_CLK_U 661 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
690 MX8MN_IOMUXC_SD2_CMD_U 662 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
691 MX8MN_IOMUXC_SD2_DATA0 663 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
692 MX8MN_IOMUXC_SD2_DATA1 664 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
693 MX8MN_IOMUXC_SD2_DATA2 665 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
694 MX8MN_IOMUXC_SD2_DATA3 666 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
695 MX8MN_IOMUXC_GPIO1_IO0 667 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
696 >; 668 >;
697 }; 669 };
698 670
699 pinctrl_usdhc3: usdhc3grp { 671 pinctrl_usdhc3: usdhc3grp {
700 fsl,pins = < 672 fsl,pins = <
701 MX8MN_IOMUXC_NAND_WE_B 673 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000190
702 MX8MN_IOMUXC_NAND_WP_B 674 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
703 MX8MN_IOMUXC_NAND_DATA 675 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
704 MX8MN_IOMUXC_NAND_DATA 676 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
705 MX8MN_IOMUXC_NAND_DATA 677 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
706 MX8MN_IOMUXC_NAND_DATA 678 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
707 MX8MN_IOMUXC_NAND_RE_B 679 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
708 MX8MN_IOMUXC_NAND_CE2_ 680 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
709 MX8MN_IOMUXC_NAND_CE3_ 681 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
710 MX8MN_IOMUXC_NAND_CLE_ 682 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
711 MX8MN_IOMUXC_NAND_CE1_ 683 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
712 >; 684 >;
713 }; 685 };
714 686
715 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 687 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
716 fsl,pins = < 688 fsl,pins = <
717 MX8MN_IOMUXC_NAND_WE_B 689 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
718 MX8MN_IOMUXC_NAND_WP_B 690 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
719 MX8MN_IOMUXC_NAND_DATA 691 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
720 MX8MN_IOMUXC_NAND_DATA 692 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
721 MX8MN_IOMUXC_NAND_DATA 693 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
722 MX8MN_IOMUXC_NAND_DATA 694 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
723 MX8MN_IOMUXC_NAND_RE_B 695 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
724 MX8MN_IOMUXC_NAND_CE2_ 696 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
725 MX8MN_IOMUXC_NAND_CE3_ 697 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
726 MX8MN_IOMUXC_NAND_CLE_ 698 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
727 MX8MN_IOMUXC_NAND_CE1_ 699 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
728 >; 700 >;
729 }; 701 };
730 702
731 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 703 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
732 fsl,pins = < 704 fsl,pins = <
733 MX8MN_IOMUXC_NAND_WE_B 705 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
734 MX8MN_IOMUXC_NAND_WP_B 706 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
735 MX8MN_IOMUXC_NAND_DATA 707 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
736 MX8MN_IOMUXC_NAND_DATA 708 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
737 MX8MN_IOMUXC_NAND_DATA 709 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
738 MX8MN_IOMUXC_NAND_DATA 710 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
739 MX8MN_IOMUXC_NAND_RE_B 711 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
740 MX8MN_IOMUXC_NAND_CE2_ 712 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
741 MX8MN_IOMUXC_NAND_CE3_ 713 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
742 MX8MN_IOMUXC_NAND_CLE_ 714 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
743 MX8MN_IOMUXC_NAND_CE1_ 715 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
744 >; 716 >;
745 }; 717 };
746 718
747 pinctrl_wdog: wdoggrp { 719 pinctrl_wdog: wdoggrp {
748 fsl,pins = < 720 fsl,pins = <
749 MX8MN_IOMUXC_GPIO1_IO0 721 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
750 >; 722 >;
751 }; 723 };
752 }; 724 };
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