1 // SPDX-License-Identifier: (GPL-2.0-or-later
2 /*
3 * Copyright 2020-2021 TQ-Systems GmbH
4 */
5
6 #include "imx8mn.dtsi"
7
8 / {
9 model = "TQ-Systems i.MX8MN TQMa8MxNL"
10 compatible = "tq,imx8mn-tqma8mqnl", "f
11
12 memory@40000000 {
13 device_type = "memory";
14 /* our minimum RAM config wil
15 reg = <0x00000000 0x40000000 0
16 };
17
18 /* e-MMC IO, needed for HS modes */
19 reg_vcc1v8: regulator-vcc1v8 {
20 compatible = "regulator-fixed"
21 regulator-name = "TQMA8MXNL_VC
22 regulator-min-microvolt = <180
23 regulator-max-microvolt = <180
24 };
25
26 reg_vcc3v3: regulator-vcc3v3 {
27 compatible = "regulator-fixed"
28 regulator-name = "TQMA8MXNL_VC
29 regulator-min-microvolt = <330
30 regulator-max-microvolt = <330
31 };
32
33 reserved-memory {
34 #address-cells = <2>;
35 #size-cells = <2>;
36 ranges;
37
38 /* global autoconfigured regio
39 linux,cma {
40 compatible = "shared-d
41 reusable;
42 /* 640 MiB */
43 size = <0 0x28000000>;
44 /* 1024 - 128 MiB, ou
45 alloc-ranges = <0 0x40
46 linux,cma-default;
47 };
48 };
49 };
50
51 &A53_0 {
52 cpu-supply = <&buck2_reg>;
53 };
54
55 &flexspi {
56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_flexspi>;
58 status = "okay";
59
60 flash0: flash@0 {
61 compatible = "jedec,spi-nor";
62 reg = <0>;
63 spi-max-frequency = <84000000>
64 spi-tx-bus-width = <1>;
65 spi-rx-bus-width = <4>;
66
67 partitions {
68 compatible = "fixed-pa
69 #address-cells = <1>;
70 #size-cells = <1>;
71 };
72 };
73 };
74
75 &i2c1 {
76 clock-frequency = <100000>;
77 pinctrl-names = "default", "gpio";
78 pinctrl-0 = <&pinctrl_i2c1>;
79 pinctrl-1 = <&pinctrl_i2c1_gpio>;
80 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI
81 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI
82 status = "okay";
83
84 sensor0: temperature-sensor@1b {
85 compatible = "nxp,se97b", "jed
86 reg = <0x1b>;
87 };
88
89 pca9450: pmic@25 {
90 compatible = "nxp,pca9450a";
91 reg = <0x25>;
92
93 /* PMIC PCA9450 PMIC_nINT GPIO
94 pinctrl-0 = <&pinctrl_pmic>;
95 pinctrl-names = "default";
96 interrupt-parent = <&gpio1>;
97 interrupts = <8 IRQ_TYPE_LEVEL
98
99 regulators {
100 /* V_0V85_SOC: 0.85 ..
101 buck1_reg: BUCK1 {
102 regulator-name
103 regulator-min-
104 regulator-max-
105 regulator-boot
106 regulator-alwa
107 regulator-ramp
108 };
109
110 /* VDD_ARM */
111 buck2_reg: BUCK2 {
112 regulator-name
113 regulator-min-
114 regulator-max-
115 regulator-boot
116 regulator-alwa
117 nxp,dvs-run-vo
118 nxp,dvs-standb
119 regulator-ramp
120 };
121
122 /* V_0V85_GPU / DRAM:
123 buck3_reg: BUCK3 {
124 regulator-name
125 regulator-min-
126 regulator-max-
127 regulator-boot
128 regulator-alwa
129 regulator-ramp
130 };
131
132 /* VCC3V3 -> VMMC, ...
133 buck4_reg: BUCK4 {
134 regulator-name
135 regulator-min-
136 regulator-max-
137 regulator-boot
138 regulator-alwa
139 };
140
141 /* V_1V8 -> VQMMC, SPI
142 buck5_reg: BUCK5 {
143 regulator-name
144 regulator-min-
145 regulator-max-
146 regulator-boot
147 regulator-alwa
148 };
149
150 /* V_1V1 -> RAM, ... m
151 buck6_reg: BUCK6 {
152 regulator-name
153 regulator-min-
154 regulator-max-
155 regulator-boot
156 regulator-alwa
157 };
158
159 /* V_1V8_SNVS */
160 ldo1_reg: LDO1 {
161 regulator-name
162 regulator-min-
163 regulator-max-
164 regulator-boot
165 regulator-alwa
166 };
167
168 /* V_0V8_SNVS */
169 ldo2_reg: LDO2 {
170 regulator-name
171 regulator-min-
172 regulator-max-
173 regulator-boot
174 regulator-alwa
175 };
176
177 /* V_1V8_ANA */
178 ldo3_reg: LDO3 {
179 regulator-name
180 regulator-min-
181 regulator-max-
182 regulator-boot
183 regulator-alwa
184 };
185
186 /* V_0V9_MIPI */
187 ldo4_reg: LDO4 {
188 regulator-name
189 regulator-min-
190 regulator-max-
191 regulator-boot
192 regulator-alwa
193 };
194
195 /* VCC SD IO - switche
196 ldo5_reg: LDO5 {
197 regulator-name
198 regulator-min-
199 regulator-max-
200 };
201 };
202 };
203
204 pcf85063: rtc@51 {
205 compatible = "nxp,pcf85063a";
206 reg = <0x51>;
207 quartz-load-femtofarads = <700
208 };
209
210 eeprom1: eeprom@53 {
211 compatible = "nxp,se97b", "atm
212 read-only;
213 reg = <0x53>;
214 pagesize = <16>;
215 vcc-supply = <®_vcc3v3>;
216 };
217
218 eeprom0: eeprom@57 {
219 compatible = "atmel,24c64";
220 reg = <0x57>;
221 pagesize = <32>;
222 vcc-supply = <®_vcc3v3>;
223 };
224 };
225
226 &mipi_dsi {
227 vddcore-supply = <&ldo4_reg>;
228 vddio-supply = <&ldo3_reg>;
229 };
230
231 &usdhc3 {
232 pinctrl-names = "default", "state_100m
233 pinctrl-0 = <&pinctrl_usdhc3>;
234 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
235 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
236 bus-width = <8>;
237 non-removable;
238 no-sd;
239 no-sdio;
240 vmmc-supply = <®_vcc3v3>;
241 vqmmc-supply = <®_vcc1v8>;
242 status = "okay";
243 };
244
245 /*
246 * Attention:
247 * wdog reset is routed to PMIC, PMIC must be
248 * without LDO for SNVS. GPIO1_IO02 must not b
249 */
250 &wdog1 {
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_wdog>;
253 fsl,ext-reset-output;
254 status = "okay";
255 };
256
257 &iomuxc {
258 pinctrl_flexspi: flexspigrp {
259 fsl,pins = <MX8MN_IOMUXC_NAND_
260 <MX8MN_IOMUXC_NAND_
261 <MX8MN_IOMUXC_NAND_
262 <MX8MN_IOMUXC_NAND_
263 <MX8MN_IOMUXC_NAND_
264 <MX8MN_IOMUXC_NAND_
265 };
266
267 pinctrl_i2c1: i2c1grp {
268 fsl,pins = <MX8MN_IOMUXC_I2C1_
269 <MX8MN_IOMUXC_I2C1_
270 };
271
272 pinctrl_i2c1_gpio: i2c1gpiogrp {
273 fsl,pins = <MX8MN_IOMUXC_I2C1_
274 <MX8MN_IOMUXC_I2C1_
275 };
276
277 pinctrl_pmic: pmicgrp {
278 fsl,pins = <MX8MN_IOMUXC_GPIO1
279 };
280
281 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc
282 fsl,pins = <MX8MN_IOMUXC_SD2_R
283 };
284
285 pinctrl_usdhc3: usdhc3grp {
286 fsl,pins = <MX8MN_IOMUXC_NAND_
287 <MX8MN_IOMUXC_NAND_
288 <MX8MN_IOMUXC_NAND_
289 <MX8MN_IOMUXC_NAND_
290 <MX8MN_IOMUXC_NAND_
291 <MX8MN_IOMUXC_NAND_
292 <MX8MN_IOMUXC_NAND_
293 <MX8MN_IOMUXC_NAND_
294 <MX8MN_IOMUXC_NAND_
295 <MX8MN_IOMUXC_NAND_
296 <MX8MN_IOMUXC_NAND_
297 <MX8MN_IOMUXC_NAND_
298 };
299
300 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr
301 fsl,pins = <MX8MN_IOMUXC_NAND_
302 <MX8MN_IOMUXC_NAND_
303 <MX8MN_IOMUXC_NAND_
304 <MX8MN_IOMUXC_NAND_
305 <MX8MN_IOMUXC_NAND_
306 <MX8MN_IOMUXC_NAND_
307 <MX8MN_IOMUXC_NAND_
308 <MX8MN_IOMUXC_NAND_
309 <MX8MN_IOMUXC_NAND_
310 <MX8MN_IOMUXC_NAND_
311 <MX8MN_IOMUXC_NAND_
312 <MX8MN_IOMUXC_NAND_
313 };
314
315 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr
316 fsl,pins = <MX8MN_IOMUXC_NAND_
317 <MX8MN_IOMUXC_NAND_
318 <MX8MN_IOMUXC_NAND_
319 <MX8MN_IOMUXC_NAND_
320 <MX8MN_IOMUXC_NAND_
321 <MX8MN_IOMUXC_NAND_
322 <MX8MN_IOMUXC_NAND_
323 <MX8MN_IOMUXC_NAND_
324 <MX8MN_IOMUXC_NAND_
325 <MX8MN_IOMUXC_NAND_
326 <MX8MN_IOMUXC_NAND_
327 <MX8MN_IOMUXC_NAND_
328 };
329
330 pinctrl_wdog: wdoggrp {
331 fsl,pins = <MX8MN_IOMUXC_GPIO1
332 };
333 };
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