1 // SPDX-License-Identifier: (GPL-2.0-or-later 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)
2 /* 2 /*
3 * Copyright 2020-2021 TQ-Systems GmbH 3 * Copyright 2020-2021 TQ-Systems GmbH
4 */ 4 */
5 5
6 #include "imx8mn.dtsi" 6 #include "imx8mn.dtsi"
7 7
8 / { 8 / {
9 model = "TQ-Systems i.MX8MN TQMa8MxNL" 9 model = "TQ-Systems i.MX8MN TQMa8MxNL";
10 compatible = "tq,imx8mn-tqma8mqnl", "f 10 compatible = "tq,imx8mn-tqma8mqnl", "fsl,imx8mn";
11 11
12 memory@40000000 { 12 memory@40000000 {
13 device_type = "memory"; 13 device_type = "memory";
14 /* our minimum RAM config wil 14 /* our minimum RAM config will be 1024 MiB */
15 reg = <0x00000000 0x40000000 0 15 reg = <0x00000000 0x40000000 0 0x40000000>;
16 }; 16 };
17 17
18 /* e-MMC IO, needed for HS modes */ 18 /* e-MMC IO, needed for HS modes */
19 reg_vcc1v8: regulator-vcc1v8 { 19 reg_vcc1v8: regulator-vcc1v8 {
20 compatible = "regulator-fixed" 20 compatible = "regulator-fixed";
21 regulator-name = "TQMA8MXNL_VC 21 regulator-name = "TQMA8MXNL_VCC1V8";
22 regulator-min-microvolt = <180 22 regulator-min-microvolt = <1800000>;
23 regulator-max-microvolt = <180 23 regulator-max-microvolt = <1800000>;
24 }; 24 };
25 25
26 reg_vcc3v3: regulator-vcc3v3 { 26 reg_vcc3v3: regulator-vcc3v3 {
27 compatible = "regulator-fixed" 27 compatible = "regulator-fixed";
28 regulator-name = "TQMA8MXNL_VC 28 regulator-name = "TQMA8MXNL_VCC3V3";
29 regulator-min-microvolt = <330 29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <330 30 regulator-max-microvolt = <3300000>;
31 }; 31 };
32 32
33 reserved-memory { 33 reserved-memory {
34 #address-cells = <2>; 34 #address-cells = <2>;
35 #size-cells = <2>; 35 #size-cells = <2>;
36 ranges; 36 ranges;
37 37
38 /* global autoconfigured regio 38 /* global autoconfigured region for contiguous allocations */
39 linux,cma { 39 linux,cma {
40 compatible = "shared-d 40 compatible = "shared-dma-pool";
41 reusable; 41 reusable;
42 /* 640 MiB */ 42 /* 640 MiB */
43 size = <0 0x28000000>; 43 size = <0 0x28000000>;
44 /* 1024 - 128 MiB, ou 44 /* 1024 - 128 MiB, our minimum RAM config will be 1024 MiB */
45 alloc-ranges = <0 0x40 45 alloc-ranges = <0 0x40000000 0 0x78000000>;
46 linux,cma-default; 46 linux,cma-default;
47 }; 47 };
48 }; 48 };
49 }; 49 };
50 50
51 &A53_0 { 51 &A53_0 {
52 cpu-supply = <&buck2_reg>; 52 cpu-supply = <&buck2_reg>;
53 }; 53 };
54 54
55 &flexspi { 55 &flexspi {
56 pinctrl-names = "default"; 56 pinctrl-names = "default";
57 pinctrl-0 = <&pinctrl_flexspi>; 57 pinctrl-0 = <&pinctrl_flexspi>;
58 status = "okay"; 58 status = "okay";
59 59
60 flash0: flash@0 { 60 flash0: flash@0 {
61 compatible = "jedec,spi-nor"; 61 compatible = "jedec,spi-nor";
62 reg = <0>; 62 reg = <0>;
>> 63 #address-cells = <1>;
>> 64 #size-cells = <1>;
63 spi-max-frequency = <84000000> 65 spi-max-frequency = <84000000>;
64 spi-tx-bus-width = <1>; 66 spi-tx-bus-width = <1>;
65 spi-rx-bus-width = <4>; 67 spi-rx-bus-width = <4>;
66 <<
67 partitions { <<
68 compatible = "fixed-pa <<
69 #address-cells = <1>; <<
70 #size-cells = <1>; <<
71 }; <<
72 }; 68 };
73 }; 69 };
74 70
75 &i2c1 { 71 &i2c1 {
76 clock-frequency = <100000>; 72 clock-frequency = <100000>;
77 pinctrl-names = "default", "gpio"; 73 pinctrl-names = "default", "gpio";
78 pinctrl-0 = <&pinctrl_i2c1>; 74 pinctrl-0 = <&pinctrl_i2c1>;
79 pinctrl-1 = <&pinctrl_i2c1_gpio>; 75 pinctrl-1 = <&pinctrl_i2c1_gpio>;
80 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 76 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
81 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 77 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
82 status = "okay"; 78 status = "okay";
83 79
84 sensor0: temperature-sensor@1b { 80 sensor0: temperature-sensor@1b {
85 compatible = "nxp,se97b", "jed 81 compatible = "nxp,se97b", "jedec,jc-42.4-temp";
86 reg = <0x1b>; 82 reg = <0x1b>;
87 }; 83 };
88 84
89 pca9450: pmic@25 { 85 pca9450: pmic@25 {
90 compatible = "nxp,pca9450a"; 86 compatible = "nxp,pca9450a";
91 reg = <0x25>; 87 reg = <0x25>;
92 88
93 /* PMIC PCA9450 PMIC_nINT GPIO 89 /* PMIC PCA9450 PMIC_nINT GPIO1_IO08 */
94 pinctrl-0 = <&pinctrl_pmic>; 90 pinctrl-0 = <&pinctrl_pmic>;
95 pinctrl-names = "default"; 91 pinctrl-names = "default";
96 interrupt-parent = <&gpio1>; 92 interrupt-parent = <&gpio1>;
97 interrupts = <8 IRQ_TYPE_LEVEL 93 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
98 94
99 regulators { 95 regulators {
100 /* V_0V85_SOC: 0.85 .. 96 /* V_0V85_SOC: 0.85 .. 0.95 */
101 buck1_reg: BUCK1 { 97 buck1_reg: BUCK1 {
102 regulator-name 98 regulator-name = "BUCK1";
103 regulator-min- 99 regulator-min-microvolt = <850000>;
104 regulator-max- 100 regulator-max-microvolt = <950000>;
105 regulator-boot 101 regulator-boot-on;
106 regulator-alwa 102 regulator-always-on;
107 regulator-ramp 103 regulator-ramp-delay = <3125>;
108 }; 104 };
109 105
110 /* VDD_ARM */ 106 /* VDD_ARM */
111 buck2_reg: BUCK2 { 107 buck2_reg: BUCK2 {
112 regulator-name 108 regulator-name = "BUCK2";
113 regulator-min- 109 regulator-min-microvolt = <850000>;
114 regulator-max- 110 regulator-max-microvolt = <1000000>;
115 regulator-boot 111 regulator-boot-on;
116 regulator-alwa 112 regulator-always-on;
117 nxp,dvs-run-vo 113 nxp,dvs-run-voltage = <950000>;
118 nxp,dvs-standb 114 nxp,dvs-standby-voltage = <850000>;
119 regulator-ramp 115 regulator-ramp-delay = <3125>;
120 }; 116 };
121 117
122 /* V_0V85_GPU / DRAM: 118 /* V_0V85_GPU / DRAM: shall be equal to BUCK1 for i.MX8MN */
123 buck3_reg: BUCK3 { 119 buck3_reg: BUCK3 {
124 regulator-name 120 regulator-name = "BUCK3";
125 regulator-min- 121 regulator-min-microvolt = <850000>;
126 regulator-max- 122 regulator-max-microvolt = <950000>;
127 regulator-boot 123 regulator-boot-on;
128 regulator-alwa 124 regulator-always-on;
129 regulator-ramp 125 regulator-ramp-delay = <3125>;
130 }; 126 };
131 127
132 /* VCC3V3 -> VMMC, ... 128 /* VCC3V3 -> VMMC, ... must not be changed */
133 buck4_reg: BUCK4 { 129 buck4_reg: BUCK4 {
134 regulator-name 130 regulator-name = "BUCK4";
135 regulator-min- 131 regulator-min-microvolt = <3300000>;
136 regulator-max- 132 regulator-max-microvolt = <3300000>;
137 regulator-boot 133 regulator-boot-on;
138 regulator-alwa 134 regulator-always-on;
139 }; 135 };
140 136
141 /* V_1V8 -> VQMMC, SPI 137 /* V_1V8 -> VQMMC, SPI-NOR, ... must not be changed */
142 buck5_reg: BUCK5 { 138 buck5_reg: BUCK5 {
143 regulator-name 139 regulator-name = "BUCK5";
144 regulator-min- 140 regulator-min-microvolt = <1800000>;
145 regulator-max- 141 regulator-max-microvolt = <1800000>;
146 regulator-boot 142 regulator-boot-on;
147 regulator-alwa 143 regulator-always-on;
148 }; 144 };
149 145
150 /* V_1V1 -> RAM, ... m 146 /* V_1V1 -> RAM, ... must not be changed */
151 buck6_reg: BUCK6 { 147 buck6_reg: BUCK6 {
152 regulator-name 148 regulator-name = "BUCK6";
153 regulator-min- 149 regulator-min-microvolt = <1100000>;
154 regulator-max- 150 regulator-max-microvolt = <1100000>;
155 regulator-boot 151 regulator-boot-on;
156 regulator-alwa 152 regulator-always-on;
157 }; 153 };
158 154
159 /* V_1V8_SNVS */ 155 /* V_1V8_SNVS */
160 ldo1_reg: LDO1 { 156 ldo1_reg: LDO1 {
161 regulator-name 157 regulator-name = "LDO1";
162 regulator-min- 158 regulator-min-microvolt = <1800000>;
163 regulator-max- 159 regulator-max-microvolt = <1800000>;
164 regulator-boot 160 regulator-boot-on;
165 regulator-alwa 161 regulator-always-on;
166 }; 162 };
167 163
168 /* V_0V8_SNVS */ 164 /* V_0V8_SNVS */
169 ldo2_reg: LDO2 { 165 ldo2_reg: LDO2 {
170 regulator-name 166 regulator-name = "LDO2";
171 regulator-min- 167 regulator-min-microvolt = <800000>;
172 regulator-max- 168 regulator-max-microvolt = <850000>;
173 regulator-boot 169 regulator-boot-on;
174 regulator-alwa 170 regulator-always-on;
175 }; 171 };
176 172
177 /* V_1V8_ANA */ 173 /* V_1V8_ANA */
178 ldo3_reg: LDO3 { 174 ldo3_reg: LDO3 {
179 regulator-name 175 regulator-name = "LDO3";
180 regulator-min- 176 regulator-min-microvolt = <1800000>;
181 regulator-max- 177 regulator-max-microvolt = <1800000>;
182 regulator-boot 178 regulator-boot-on;
183 regulator-alwa 179 regulator-always-on;
184 }; 180 };
185 181
186 /* V_0V9_MIPI */ 182 /* V_0V9_MIPI */
187 ldo4_reg: LDO4 { 183 ldo4_reg: LDO4 {
188 regulator-name 184 regulator-name = "LDO4";
189 regulator-min- 185 regulator-min-microvolt = <900000>;
190 regulator-max- 186 regulator-max-microvolt = <900000>;
191 regulator-boot 187 regulator-boot-on;
192 regulator-alwa 188 regulator-always-on;
193 }; 189 };
194 190
195 /* VCC SD IO - switche 191 /* VCC SD IO - switched using SD2 VSELECT */
196 ldo5_reg: LDO5 { 192 ldo5_reg: LDO5 {
197 regulator-name 193 regulator-name = "LDO5";
198 regulator-min- 194 regulator-min-microvolt = <1800000>;
199 regulator-max- 195 regulator-max-microvolt = <3300000>;
200 }; 196 };
201 }; 197 };
202 }; 198 };
203 199
204 pcf85063: rtc@51 { 200 pcf85063: rtc@51 {
205 compatible = "nxp,pcf85063a"; 201 compatible = "nxp,pcf85063a";
206 reg = <0x51>; 202 reg = <0x51>;
207 quartz-load-femtofarads = <700 203 quartz-load-femtofarads = <7000>;
208 }; 204 };
209 205
210 eeprom1: eeprom@53 { 206 eeprom1: eeprom@53 {
211 compatible = "nxp,se97b", "atm 207 compatible = "nxp,se97b", "atmel,24c02";
212 read-only; 208 read-only;
213 reg = <0x53>; 209 reg = <0x53>;
214 pagesize = <16>; 210 pagesize = <16>;
215 vcc-supply = <®_vcc3v3>; <<
216 }; 211 };
217 212
218 eeprom0: eeprom@57 { 213 eeprom0: eeprom@57 {
219 compatible = "atmel,24c64"; 214 compatible = "atmel,24c64";
220 reg = <0x57>; 215 reg = <0x57>;
221 pagesize = <32>; 216 pagesize = <32>;
222 vcc-supply = <®_vcc3v3>; <<
223 }; 217 };
224 }; <<
225 <<
226 &mipi_dsi { <<
227 vddcore-supply = <&ldo4_reg>; <<
228 vddio-supply = <&ldo3_reg>; <<
229 }; 218 };
230 219
231 &usdhc3 { 220 &usdhc3 {
232 pinctrl-names = "default", "state_100m 221 pinctrl-names = "default", "state_100mhz", "state_200mhz";
233 pinctrl-0 = <&pinctrl_usdhc3>; 222 pinctrl-0 = <&pinctrl_usdhc3>;
234 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 223 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
235 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 224 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
236 bus-width = <8>; 225 bus-width = <8>;
237 non-removable; 226 non-removable;
238 no-sd; 227 no-sd;
239 no-sdio; 228 no-sdio;
240 vmmc-supply = <®_vcc3v3>; 229 vmmc-supply = <®_vcc3v3>;
241 vqmmc-supply = <®_vcc1v8>; 230 vqmmc-supply = <®_vcc1v8>;
242 status = "okay"; 231 status = "okay";
243 }; 232 };
244 233
245 /* 234 /*
246 * Attention: 235 * Attention:
247 * wdog reset is routed to PMIC, PMIC must be 236 * wdog reset is routed to PMIC, PMIC must be preconfigured to force POR
248 * without LDO for SNVS. GPIO1_IO02 must not b 237 * without LDO for SNVS. GPIO1_IO02 must not be used as GPIO.
249 */ 238 */
250 &wdog1 { 239 &wdog1 {
251 pinctrl-names = "default"; 240 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_wdog>; 241 pinctrl-0 = <&pinctrl_wdog>;
253 fsl,ext-reset-output; 242 fsl,ext-reset-output;
254 status = "okay"; 243 status = "okay";
255 }; 244 };
256 245
257 &iomuxc { 246 &iomuxc {
258 pinctrl_flexspi: flexspigrp { 247 pinctrl_flexspi: flexspigrp {
259 fsl,pins = <MX8MN_IOMUXC_NAND_ 248 fsl,pins = <MX8MN_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x84>,
260 <MX8MN_IOMUXC_NAND_ 249 <MX8MN_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x84>,
261 <MX8MN_IOMUXC_NAND_ 250 <MX8MN_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x84>,
262 <MX8MN_IOMUXC_NAND_ 251 <MX8MN_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x84>,
263 <MX8MN_IOMUXC_NAND_ 252 <MX8MN_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x84>,
264 <MX8MN_IOMUXC_NAND_ 253 <MX8MN_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x84>;
265 }; 254 };
266 255
267 pinctrl_i2c1: i2c1grp { 256 pinctrl_i2c1: i2c1grp {
268 fsl,pins = <MX8MN_IOMUXC_I2C1_ 257 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c4>,
269 <MX8MN_IOMUXC_I2C1_ 258 <MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c4>;
270 }; 259 };
271 260
272 pinctrl_i2c1_gpio: i2c1gpiogrp { 261 pinctrl_i2c1_gpio: i2c1gpiogrp {
273 fsl,pins = <MX8MN_IOMUXC_I2C1_ 262 fsl,pins = <MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c4>,
274 <MX8MN_IOMUXC_I2C1_ 263 <MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c4>;
275 }; 264 };
276 265
277 pinctrl_pmic: pmicgrp { 266 pinctrl_pmic: pmicgrp {
278 fsl,pins = <MX8MN_IOMUXC_GPIO1 267 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>;
279 }; 268 };
280 269
281 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 270 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
282 fsl,pins = <MX8MN_IOMUXC_SD2_R 271 fsl,pins = <MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x84>;
283 }; 272 };
284 273
285 pinctrl_usdhc3: usdhc3grp { 274 pinctrl_usdhc3: usdhc3grp {
286 fsl,pins = <MX8MN_IOMUXC_NAND_ 275 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d4>,
287 <MX8MN_IOMUXC_NAND_ 276 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
288 <MX8MN_IOMUXC_NAND_ 277 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
289 <MX8MN_IOMUXC_NAND_ 278 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
290 <MX8MN_IOMUXC_NAND_ 279 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
291 <MX8MN_IOMUXC_NAND_ 280 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
292 <MX8MN_IOMUXC_NAND_ 281 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
293 <MX8MN_IOMUXC_NAND_ 282 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
294 <MX8MN_IOMUXC_NAND_ 283 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
295 <MX8MN_IOMUXC_NAND_ 284 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
296 <MX8MN_IOMUXC_NAND_ 285 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
297 <MX8MN_IOMUXC_NAND_ 286 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
298 }; 287 };
299 288
300 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 289 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
301 fsl,pins = <MX8MN_IOMUXC_NAND_ 290 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d2>,
302 <MX8MN_IOMUXC_NAND_ 291 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
303 <MX8MN_IOMUXC_NAND_ 292 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
304 <MX8MN_IOMUXC_NAND_ 293 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
305 <MX8MN_IOMUXC_NAND_ 294 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
306 <MX8MN_IOMUXC_NAND_ 295 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
307 <MX8MN_IOMUXC_NAND_ 296 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
308 <MX8MN_IOMUXC_NAND_ 297 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
309 <MX8MN_IOMUXC_NAND_ 298 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
310 <MX8MN_IOMUXC_NAND_ 299 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
311 <MX8MN_IOMUXC_NAND_ 300 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
312 <MX8MN_IOMUXC_NAND_ 301 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
313 }; 302 };
314 303
315 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 304 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
316 fsl,pins = <MX8MN_IOMUXC_NAND_ 305 fsl,pins = <MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x1d6>,
317 <MX8MN_IOMUXC_NAND_ 306 <MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d2>,
318 <MX8MN_IOMUXC_NAND_ 307 <MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4>,
319 <MX8MN_IOMUXC_NAND_ 308 <MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4>,
320 <MX8MN_IOMUXC_NAND_ 309 <MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4>,
321 <MX8MN_IOMUXC_NAND_ 310 <MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4>,
322 <MX8MN_IOMUXC_NAND_ 311 <MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4>,
323 <MX8MN_IOMUXC_NAND_ 312 <MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4>,
324 <MX8MN_IOMUXC_NAND_ 313 <MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4>,
325 <MX8MN_IOMUXC_NAND_ 314 <MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4>,
326 <MX8MN_IOMUXC_NAND_ 315 <MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x84>,
327 <MX8MN_IOMUXC_NAND_ 316 <MX8MN_IOMUXC_NAND_READY_B_USDHC3_RESET_B 0x84>;
328 }; 317 };
329 318
330 pinctrl_wdog: wdoggrp { 319 pinctrl_wdog: wdoggrp {
331 fsl,pins = <MX8MN_IOMUXC_GPIO1 320 fsl,pins = <MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x84>;
332 }; 321 };
333 }; 322 };
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