1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 * Copyright 2019-2020 Variscite Ltd. 4 * Copyright 2019-2020 Variscite Ltd.
5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk 5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
6 */ 6 */
7 7
8 #include "imx8mn.dtsi" 8 #include "imx8mn.dtsi"
9 9
10 / { 10 / {
11 model = "Variscite VAR-SOM-MX8MN modul 11 model = "Variscite VAR-SOM-MX8MN module";
12 compatible = "variscite,var-som-mx8mn" 12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
13 13
14 chosen { 14 chosen {
15 stdout-path = &uart4; 15 stdout-path = &uart4;
16 }; 16 };
17 17
18 memory@40000000 { 18 memory@40000000 {
19 device_type = "memory"; 19 device_type = "memory";
20 reg = <0x0 0x40000000 0 0x4000 20 reg = <0x0 0x40000000 0 0x40000000>;
21 }; 21 };
22 22
23 reg_eth_phy: regulator-eth-phy { 23 reg_eth_phy: regulator-eth-phy {
24 compatible = "regulator-fixed" 24 compatible = "regulator-fixed";
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_reg_eth_ 26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
27 regulator-name = "eth_phy_pwr" 27 regulator-name = "eth_phy_pwr";
28 regulator-min-microvolt = <330 28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <330 29 regulator-max-microvolt = <3300000>;
30 regulator-enable-ramp-delay = 30 regulator-enable-ramp-delay = <20000>;
31 gpio = <&gpio2 9 GPIO_ACTIVE_H 31 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
32 enable-active-high; 32 enable-active-high;
33 }; 33 };
34 <<
35 reg_3v3_fixed: regulator-3v3-fixed { <<
36 compatible = "regulator-fixed" <<
37 regulator-name = "fixed_3v3"; <<
38 regulator-min-microvolt = <330 <<
39 regulator-max-microvolt = <330 <<
40 regulator-always-on; <<
41 }; <<
42 }; 34 };
43 35
44 &A53_0 { 36 &A53_0 {
45 cpu-supply = <&buck2_reg>; 37 cpu-supply = <&buck2_reg>;
46 }; 38 };
47 39
48 &A53_1 { 40 &A53_1 {
49 cpu-supply = <&buck2_reg>; 41 cpu-supply = <&buck2_reg>;
50 }; 42 };
51 43
52 &A53_2 { 44 &A53_2 {
53 cpu-supply = <&buck2_reg>; 45 cpu-supply = <&buck2_reg>;
54 }; 46 };
55 47
56 &A53_3 { 48 &A53_3 {
57 cpu-supply = <&buck2_reg>; 49 cpu-supply = <&buck2_reg>;
58 }; 50 };
59 51
60 &ecspi1 { 52 &ecspi1 {
61 pinctrl-names = "default"; 53 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_ecspi1>; 54 pinctrl-0 = <&pinctrl_ecspi1>;
63 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW> 55 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
64 <&gpio1 0 GPIO_ACTIVE_LOW> 56 <&gpio1 0 GPIO_ACTIVE_LOW>;
65 /delete-property/ dmas; 57 /delete-property/ dmas;
66 /delete-property/ dma-names; 58 /delete-property/ dma-names;
67 status = "okay"; 59 status = "okay";
68 60
69 /* Resistive touch controller */ 61 /* Resistive touch controller */
70 touchscreen@0 { 62 touchscreen@0 {
71 reg = <0>; 63 reg = <0>;
72 compatible = "ti,ads7846"; 64 compatible = "ti,ads7846";
73 pinctrl-names = "default"; 65 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_restouch 66 pinctrl-0 = <&pinctrl_restouch>;
75 interrupt-parent = <&gpio1>; 67 interrupt-parent = <&gpio1>;
76 interrupts = <3 IRQ_TYPE_EDGE_ 68 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
77 69
78 spi-max-frequency = <1500000>; 70 spi-max-frequency = <1500000>;
79 pendown-gpio = <&gpio1 3 GPIO_ 71 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
80 72
81 ti,x-min = /bits/ 16 <125>; 73 ti,x-min = /bits/ 16 <125>;
82 touchscreen-size-x = <4008>; 74 touchscreen-size-x = <4008>;
83 ti,y-min = /bits/ 16 <282>; 75 ti,y-min = /bits/ 16 <282>;
84 touchscreen-size-y = <3864>; 76 touchscreen-size-y = <3864>;
85 ti,x-plate-ohms = /bits/ 16 <1 77 ti,x-plate-ohms = /bits/ 16 <180>;
86 touchscreen-max-pressure = <25 78 touchscreen-max-pressure = <255>;
87 touchscreen-average-samples = 79 touchscreen-average-samples = <10>;
88 ti,debounce-tol = /bits/ 16 <3 80 ti,debounce-tol = /bits/ 16 <3>;
89 ti,debounce-rep = /bits/ 16 <1 81 ti,debounce-rep = /bits/ 16 <1>;
90 ti,settle-delay-usec = /bits/ 82 ti,settle-delay-usec = /bits/ 16 <150>;
91 ti,keep-vref-on; 83 ti,keep-vref-on;
92 wakeup-source; 84 wakeup-source;
93 }; 85 };
94 }; 86 };
95 87
96 &fec1 { 88 &fec1 {
97 pinctrl-names = "default", "sleep"; 89 pinctrl-names = "default", "sleep";
98 pinctrl-0 = <&pinctrl_fec1>; 90 pinctrl-0 = <&pinctrl_fec1>;
99 pinctrl-1 = <&pinctrl_fec1_sleep>; 91 pinctrl-1 = <&pinctrl_fec1_sleep>;
100 phy-mode = "rgmii"; 92 phy-mode = "rgmii";
101 phy-handle = <ðphy>; 93 phy-handle = <ðphy>;
102 phy-supply = <®_eth_phy>; 94 phy-supply = <®_eth_phy>;
103 fsl,magic-packet; 95 fsl,magic-packet;
104 status = "okay"; 96 status = "okay";
105 97
106 mdio { 98 mdio {
107 #address-cells = <1>; 99 #address-cells = <1>;
108 #size-cells = <0>; 100 #size-cells = <0>;
109 101
110 ethphy: ethernet-phy@4 { /* AR 102 ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
111 compatible = "ethernet 103 compatible = "ethernet-phy-ieee802.3-c22";
112 reg = <4>; 104 reg = <4>;
113 reset-gpios = <&gpio1 105 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
114 reset-assert-us = <100 106 reset-assert-us = <10000>;
115 /* 107 /*
116 * Deassert delay: 108 * Deassert delay:
117 * ADIN1300 requires 5 109 * ADIN1300 requires 5ms.
118 * AR8033 requires 1 110 * AR8033 requires 1ms.
119 */ 111 */
120 reset-deassert-us = <2 112 reset-deassert-us = <20000>;
121 }; 113 };
122 }; 114 };
123 }; 115 };
124 116
125 &i2c1 { 117 &i2c1 {
126 clock-frequency = <400000>; 118 clock-frequency = <400000>;
127 pinctrl-names = "default"; 119 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c1>; 120 pinctrl-0 = <&pinctrl_i2c1>;
129 status = "okay"; 121 status = "okay";
130 122
131 pmic@4b { 123 pmic@4b {
132 compatible = "rohm,bd71847"; 124 compatible = "rohm,bd71847";
133 reg = <0x4b>; 125 reg = <0x4b>;
134 pinctrl-names = "default"; 126 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_pmic>; 127 pinctrl-0 = <&pinctrl_pmic>;
136 interrupt-parent = <&gpio2>; 128 interrupt-parent = <&gpio2>;
137 interrupts = <8 IRQ_TYPE_LEVEL 129 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
138 rohm,reset-snvs-powered; 130 rohm,reset-snvs-powered;
139 131
140 regulators { 132 regulators {
141 buck1_reg: BUCK1 { 133 buck1_reg: BUCK1 {
142 regulator-name 134 regulator-name = "buck1";
143 regulator-min- 135 regulator-min-microvolt = <700000>;
144 regulator-max- 136 regulator-max-microvolt = <1300000>;
145 regulator-boot 137 regulator-boot-on;
146 regulator-alwa 138 regulator-always-on;
147 regulator-ramp 139 regulator-ramp-delay = <1250>;
148 }; 140 };
149 141
150 buck2_reg: BUCK2 { 142 buck2_reg: BUCK2 {
151 regulator-name 143 regulator-name = "buck2";
152 regulator-min- 144 regulator-min-microvolt = <700000>;
153 regulator-max- 145 regulator-max-microvolt = <1300000>;
154 regulator-boot 146 regulator-boot-on;
155 regulator-alwa 147 regulator-always-on;
156 regulator-ramp 148 regulator-ramp-delay = <1250>;
157 rohm,dvs-run-v 149 rohm,dvs-run-voltage = <1000000>;
158 rohm,dvs-idle- 150 rohm,dvs-idle-voltage = <900000>;
159 }; 151 };
160 152
161 buck3_reg: BUCK3 { 153 buck3_reg: BUCK3 {
162 regulator-name 154 regulator-name = "buck3";
163 regulator-min- 155 regulator-min-microvolt = <700000>;
164 regulator-max- 156 regulator-max-microvolt = <1350000>;
165 regulator-boot 157 regulator-boot-on;
166 regulator-alwa 158 regulator-always-on;
167 }; 159 };
168 160
169 buck4_reg: BUCK4 { 161 buck4_reg: BUCK4 {
170 regulator-name 162 regulator-name = "buck4";
171 regulator-min- 163 regulator-min-microvolt = <2600000>;
172 regulator-max- 164 regulator-max-microvolt = <3300000>;
173 regulator-boot 165 regulator-boot-on;
174 regulator-alwa 166 regulator-always-on;
175 }; 167 };
176 168
177 buck5_reg: BUCK5 { 169 buck5_reg: BUCK5 {
178 regulator-name 170 regulator-name = "buck5";
179 regulator-min- 171 regulator-min-microvolt = <1605000>;
180 regulator-max- 172 regulator-max-microvolt = <1995000>;
181 regulator-boot 173 regulator-boot-on;
182 regulator-alwa 174 regulator-always-on;
183 }; 175 };
184 176
185 buck6_reg: BUCK6 { 177 buck6_reg: BUCK6 {
186 regulator-name 178 regulator-name = "buck6";
187 regulator-min- 179 regulator-min-microvolt = <800000>;
188 regulator-max- 180 regulator-max-microvolt = <1400000>;
189 regulator-boot 181 regulator-boot-on;
190 regulator-alwa 182 regulator-always-on;
191 }; 183 };
192 184
193 ldo1_reg: LDO1 { 185 ldo1_reg: LDO1 {
194 regulator-name 186 regulator-name = "ldo1";
195 regulator-min- 187 regulator-min-microvolt = <1600000>;
196 regulator-max- 188 regulator-max-microvolt = <1900000>;
197 regulator-boot 189 regulator-boot-on;
198 regulator-alwa 190 regulator-always-on;
199 }; 191 };
200 192
201 ldo2_reg: LDO2 { 193 ldo2_reg: LDO2 {
202 regulator-name 194 regulator-name = "ldo2";
203 regulator-min- 195 regulator-min-microvolt = <800000>;
204 regulator-max- 196 regulator-max-microvolt = <900000>;
205 regulator-boot 197 regulator-boot-on;
206 regulator-alwa 198 regulator-always-on;
207 }; 199 };
208 200
209 ldo3_reg: LDO3 { 201 ldo3_reg: LDO3 {
210 regulator-name 202 regulator-name = "ldo3";
211 regulator-min- 203 regulator-min-microvolt = <1800000>;
212 regulator-max- 204 regulator-max-microvolt = <3300000>;
213 regulator-boot 205 regulator-boot-on;
214 regulator-alwa 206 regulator-always-on;
215 }; 207 };
216 208
217 ldo4_reg: LDO4 { 209 ldo4_reg: LDO4 {
218 regulator-name 210 regulator-name = "ldo4";
219 regulator-min- 211 regulator-min-microvolt = <900000>;
220 regulator-max- 212 regulator-max-microvolt = <1800000>;
221 regulator-alwa 213 regulator-always-on;
222 }; 214 };
223 215
224 ldo5_reg: LDO5 { 216 ldo5_reg: LDO5 {
225 regulator-name !! 217 regulator-compatible = "ldo5";
226 regulator-min- 218 regulator-min-microvolt = <1800000>;
227 regulator-max- 219 regulator-max-microvolt = <1800000>;
228 regulator-alwa 220 regulator-always-on;
229 }; 221 };
230 222
231 ldo6_reg: LDO6 { 223 ldo6_reg: LDO6 {
232 regulator-name 224 regulator-name = "ldo6";
233 regulator-min- 225 regulator-min-microvolt = <900000>;
234 regulator-max- 226 regulator-max-microvolt = <1800000>;
235 regulator-boot 227 regulator-boot-on;
236 regulator-alwa 228 regulator-always-on;
237 }; 229 };
238 }; 230 };
239 }; <<
240 <<
241 eeprom_som: eeprom@52 { <<
242 compatible = "atmel,24c04"; <<
243 reg = <0x52>; <<
244 pagesize = <16>; <<
245 vcc-supply = <®_3v3_fixed>; <<
246 }; 231 };
247 }; 232 };
248 233
249 &i2c3 { 234 &i2c3 {
250 clock-frequency = <400000>; 235 clock-frequency = <400000>;
251 pinctrl-names = "default"; 236 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c3>; 237 pinctrl-0 = <&pinctrl_i2c3>;
253 status = "okay"; 238 status = "okay";
254 239
255 /* TODO: configure audio, as of now ju 240 /* TODO: configure audio, as of now just put a placeholder */
256 wm8904: codec@1a { 241 wm8904: codec@1a {
257 compatible = "wlf,wm8904"; 242 compatible = "wlf,wm8904";
258 reg = <0x1a>; 243 reg = <0x1a>;
259 status = "disabled"; 244 status = "disabled";
260 }; 245 };
261 }; 246 };
262 247
263 &snvs_pwrkey { 248 &snvs_pwrkey {
264 status = "okay"; 249 status = "okay";
265 }; 250 };
266 251
267 /* Bluetooth */ 252 /* Bluetooth */
268 &uart2 { 253 &uart2 {
269 pinctrl-names = "default"; 254 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart2>; 255 pinctrl-0 = <&pinctrl_uart2>;
271 assigned-clocks = <&clk IMX8MN_CLK_UAR 256 assigned-clocks = <&clk IMX8MN_CLK_UART2>;
272 assigned-clock-parents = <&clk IMX8MN_ 257 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
273 uart-has-rtscts; 258 uart-has-rtscts;
274 status = "okay"; 259 status = "okay";
275 }; 260 };
276 261
277 /* Console */ 262 /* Console */
278 &uart4 { 263 &uart4 {
279 pinctrl-names = "default"; 264 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_uart4>; 265 pinctrl-0 = <&pinctrl_uart4>;
281 status = "okay"; 266 status = "okay";
282 }; 267 };
283 268
284 &usbotg1 { 269 &usbotg1 {
285 dr_mode = "otg"; 270 dr_mode = "otg";
286 usb-role-switch; 271 usb-role-switch;
287 status = "okay"; 272 status = "okay";
288 }; 273 };
289 274
290 /* WIFI */ 275 /* WIFI */
291 &usdhc1 { 276 &usdhc1 {
292 #address-cells = <1>; 277 #address-cells = <1>;
293 #size-cells = <0>; 278 #size-cells = <0>;
294 pinctrl-names = "default", "state_100m 279 pinctrl-names = "default", "state_100mhz", "state_200mhz";
295 pinctrl-0 = <&pinctrl_usdhc1>; 280 pinctrl-0 = <&pinctrl_usdhc1>;
296 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 281 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
297 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 282 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
298 bus-width = <4>; 283 bus-width = <4>;
299 non-removable; 284 non-removable;
300 keep-power-in-suspend; 285 keep-power-in-suspend;
301 status = "okay"; 286 status = "okay";
302 287
303 brcmf: bcrmf@1 { 288 brcmf: bcrmf@1 {
304 reg = <1>; 289 reg = <1>;
305 compatible = "brcm,bcm4329-fma 290 compatible = "brcm,bcm4329-fmac";
306 }; 291 };
307 }; 292 };
308 293
309 /* SD */ 294 /* SD */
310 &usdhc2 { 295 &usdhc2 {
311 assigned-clocks = <&clk IMX8MN_CLK_USD 296 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
312 assigned-clock-rates = <200000000>; 297 assigned-clock-rates = <200000000>;
313 pinctrl-names = "default", "state_100m 298 pinctrl-names = "default", "state_100mhz", "state_200mhz";
314 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 299 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
315 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 300 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
316 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 301 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
317 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW> 302 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
318 bus-width = <4>; 303 bus-width = <4>;
319 vmmc-supply = <®_usdhc2_vmmc>; 304 vmmc-supply = <®_usdhc2_vmmc>;
320 status = "okay"; 305 status = "okay";
321 }; 306 };
322 307
323 /* eMMC */ 308 /* eMMC */
324 &usdhc3 { 309 &usdhc3 {
325 assigned-clocks = <&clk IMX8MN_CLK_USD 310 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
326 assigned-clock-rates = <400000000>; 311 assigned-clock-rates = <400000000>;
327 pinctrl-names = "default", "state_100m 312 pinctrl-names = "default", "state_100mhz", "state_200mhz";
328 pinctrl-0 = <&pinctrl_usdhc3>; 313 pinctrl-0 = <&pinctrl_usdhc3>;
329 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 314 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
330 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 315 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
331 bus-width = <8>; 316 bus-width = <8>;
332 non-removable; 317 non-removable;
333 status = "okay"; 318 status = "okay";
334 }; 319 };
335 320
336 &wdog1 { 321 &wdog1 {
337 pinctrl-names = "default"; 322 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_wdog>; 323 pinctrl-0 = <&pinctrl_wdog>;
339 fsl,ext-reset-output; 324 fsl,ext-reset-output;
340 status = "okay"; 325 status = "okay";
341 }; 326 };
342 327
343 &iomuxc { 328 &iomuxc {
344 pinctrl_ecspi1: ecspi1grp { 329 pinctrl_ecspi1: ecspi1grp {
345 fsl,pins = < 330 fsl,pins = <
346 MX8MN_IOMUXC_ECSPI1_SC 331 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
347 MX8MN_IOMUXC_ECSPI1_MO 332 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
348 MX8MN_IOMUXC_ECSPI1_MI 333 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
349 MX8MN_IOMUXC_GPIO1_IO1 334 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
350 MX8MN_IOMUXC_GPIO1_IO0 335 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
351 >; 336 >;
352 }; 337 };
353 338
354 pinctrl_fec1: fec1grp { 339 pinctrl_fec1: fec1grp {
355 fsl,pins = < 340 fsl,pins = <
356 MX8MN_IOMUXC_ENET_MDC_ 341 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
357 MX8MN_IOMUXC_ENET_MDIO 342 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
358 MX8MN_IOMUXC_ENET_TD3_ 343 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
359 MX8MN_IOMUXC_ENET_TD2_ 344 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
360 MX8MN_IOMUXC_ENET_TD1_ 345 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
361 MX8MN_IOMUXC_ENET_TD0_ 346 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
362 MX8MN_IOMUXC_ENET_RD3_ 347 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
363 MX8MN_IOMUXC_ENET_RD2_ 348 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
364 MX8MN_IOMUXC_ENET_RD1_ 349 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
365 MX8MN_IOMUXC_ENET_RD0_ 350 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
366 MX8MN_IOMUXC_ENET_TXC_ 351 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
367 MX8MN_IOMUXC_ENET_RXC_ 352 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
368 MX8MN_IOMUXC_ENET_RX_C 353 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
369 MX8MN_IOMUXC_ENET_TX_C 354 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
370 MX8MN_IOMUXC_GPIO1_IO0 355 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x159
371 >; 356 >;
372 }; 357 };
373 358
374 pinctrl_fec1_sleep: fec1sleepgrp { 359 pinctrl_fec1_sleep: fec1sleepgrp {
375 fsl,pins = < 360 fsl,pins = <
376 MX8MN_IOMUXC_ENET_MDC_ 361 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
377 MX8MN_IOMUXC_ENET_MDIO 362 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
378 MX8MN_IOMUXC_ENET_TD3_ 363 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
379 MX8MN_IOMUXC_ENET_TD2_ 364 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
380 MX8MN_IOMUXC_ENET_TD1_ 365 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
381 MX8MN_IOMUXC_ENET_TD0_ 366 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
382 MX8MN_IOMUXC_ENET_RD3_ 367 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
383 MX8MN_IOMUXC_ENET_RD2_ 368 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
384 MX8MN_IOMUXC_ENET_RD1_ 369 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
385 MX8MN_IOMUXC_ENET_RD0_ 370 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
386 MX8MN_IOMUXC_ENET_TXC_ 371 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
387 MX8MN_IOMUXC_ENET_RXC_ 372 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
388 MX8MN_IOMUXC_ENET_RX_C 373 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
389 MX8MN_IOMUXC_ENET_TX_C 374 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
390 MX8MN_IOMUXC_GPIO1_IO0 375 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
391 >; 376 >;
392 }; 377 };
393 378
394 pinctrl_i2c1: i2c1grp { 379 pinctrl_i2c1: i2c1grp {
395 fsl,pins = < 380 fsl,pins = <
396 MX8MN_IOMUXC_I2C1_SCL_ 381 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
397 MX8MN_IOMUXC_I2C1_SDA_ 382 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
398 >; 383 >;
399 }; 384 };
400 385
401 pinctrl_i2c3: i2c3grp { 386 pinctrl_i2c3: i2c3grp {
402 fsl,pins = < 387 fsl,pins = <
403 MX8MN_IOMUXC_I2C3_SCL_ 388 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
404 MX8MN_IOMUXC_I2C3_SDA_ 389 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
405 >; 390 >;
406 }; 391 };
407 392
408 pinctrl_pmic: pmicirqgrp { 393 pinctrl_pmic: pmicirqgrp {
409 fsl,pins = < 394 fsl,pins = <
410 MX8MN_IOMUXC_SD1_DATA6 395 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
411 >; 396 >;
412 }; 397 };
413 398
414 pinctrl_reg_eth_phy: regethphygrp { 399 pinctrl_reg_eth_phy: regethphygrp {
415 fsl,pins = < 400 fsl,pins = <
416 MX8MN_IOMUXC_SD1_DATA7 401 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
417 >; 402 >;
418 }; 403 };
419 404
420 pinctrl_restouch: restouchgrp { 405 pinctrl_restouch: restouchgrp {
421 fsl,pins = < 406 fsl,pins = <
422 MX8MN_IOMUXC_GPIO1_IO0 407 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
423 >; 408 >;
424 }; 409 };
425 410
426 pinctrl_uart2: uart2grp { 411 pinctrl_uart2: uart2grp {
427 fsl,pins = < 412 fsl,pins = <
428 MX8MN_IOMUXC_SAI3_TXFS 413 MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
429 MX8MN_IOMUXC_SAI3_TXC_ 414 MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
430 MX8MN_IOMUXC_SAI3_RXC_ 415 MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
431 MX8MN_IOMUXC_SAI3_RXD_ 416 MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
432 >; 417 >;
433 }; 418 };
434 419
435 pinctrl_uart4: uart4grp { 420 pinctrl_uart4: uart4grp {
436 fsl,pins = < 421 fsl,pins = <
437 MX8MN_IOMUXC_UART4_RXD 422 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
438 MX8MN_IOMUXC_UART4_TXD 423 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
439 >; 424 >;
440 }; 425 };
441 426
442 pinctrl_usdhc1: usdhc1grp { 427 pinctrl_usdhc1: usdhc1grp {
443 fsl,pins = < 428 fsl,pins = <
444 MX8MN_IOMUXC_SD1_CLK_U 429 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
445 MX8MN_IOMUXC_SD1_CMD_U 430 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
446 MX8MN_IOMUXC_SD1_DATA0 431 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
447 MX8MN_IOMUXC_SD1_DATA1 432 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
448 MX8MN_IOMUXC_SD1_DATA2 433 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
449 MX8MN_IOMUXC_SD1_DATA3 434 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
450 >; 435 >;
451 }; 436 };
452 437
453 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 438 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
454 fsl,pins = < 439 fsl,pins = <
455 MX8MN_IOMUXC_SD1_CLK_U 440 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
456 MX8MN_IOMUXC_SD1_CMD_U 441 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
457 MX8MN_IOMUXC_SD1_DATA0 442 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
458 MX8MN_IOMUXC_SD1_DATA1 443 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
459 MX8MN_IOMUXC_SD1_DATA2 444 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
460 MX8MN_IOMUXC_SD1_DATA3 445 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
461 >; 446 >;
462 }; 447 };
463 448
464 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 449 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
465 fsl,pins = < 450 fsl,pins = <
466 MX8MN_IOMUXC_SD1_CLK_U 451 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
467 MX8MN_IOMUXC_SD1_CMD_U 452 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
468 MX8MN_IOMUXC_SD1_DATA0 453 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
469 MX8MN_IOMUXC_SD1_DATA1 454 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
470 MX8MN_IOMUXC_SD1_DATA2 455 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
471 MX8MN_IOMUXC_SD1_DATA3 456 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
472 >; 457 >;
473 }; 458 };
474 459
475 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 460 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
476 fsl,pins = < 461 fsl,pins = <
477 MX8MN_IOMUXC_GPIO1_IO1 462 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
478 >; 463 >;
479 }; 464 };
480 465
481 pinctrl_usdhc2: usdhc2grp { 466 pinctrl_usdhc2: usdhc2grp {
482 fsl,pins = < 467 fsl,pins = <
483 MX8MN_IOMUXC_SD2_CLK_U 468 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
484 MX8MN_IOMUXC_SD2_CMD_U 469 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
485 MX8MN_IOMUXC_SD2_DATA0 470 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
486 MX8MN_IOMUXC_SD2_DATA1 471 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
487 MX8MN_IOMUXC_SD2_DATA2 472 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
488 MX8MN_IOMUXC_SD2_DATA3 473 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
489 MX8MN_IOMUXC_GPIO1_IO0 474 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
490 >; 475 >;
491 }; 476 };
492 477
493 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 478 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
494 fsl,pins = < 479 fsl,pins = <
495 MX8MN_IOMUXC_SD2_CLK_U 480 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
496 MX8MN_IOMUXC_SD2_CMD_U 481 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
497 MX8MN_IOMUXC_SD2_DATA0 482 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
498 MX8MN_IOMUXC_SD2_DATA1 483 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
499 MX8MN_IOMUXC_SD2_DATA2 484 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
500 MX8MN_IOMUXC_SD2_DATA3 485 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
501 MX8MN_IOMUXC_GPIO1_IO0 486 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
502 >; 487 >;
503 }; 488 };
504 489
505 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 490 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
506 fsl,pins = < 491 fsl,pins = <
507 MX8MN_IOMUXC_SD2_CLK_U 492 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
508 MX8MN_IOMUXC_SD2_CMD_U 493 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
509 MX8MN_IOMUXC_SD2_DATA0 494 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
510 MX8MN_IOMUXC_SD2_DATA1 495 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
511 MX8MN_IOMUXC_SD2_DATA2 496 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
512 MX8MN_IOMUXC_SD2_DATA3 497 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
513 MX8MN_IOMUXC_GPIO1_IO0 498 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
514 >; 499 >;
515 }; 500 };
516 501
517 pinctrl_usdhc3: usdhc3grp { 502 pinctrl_usdhc3: usdhc3grp {
518 fsl,pins = < 503 fsl,pins = <
519 MX8MN_IOMUXC_NAND_WE_B 504 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
520 MX8MN_IOMUXC_NAND_WP_B 505 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
521 MX8MN_IOMUXC_NAND_DATA 506 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
522 MX8MN_IOMUXC_NAND_DATA 507 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
523 MX8MN_IOMUXC_NAND_DATA 508 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
524 MX8MN_IOMUXC_NAND_DATA 509 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
525 MX8MN_IOMUXC_NAND_RE_B 510 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
526 MX8MN_IOMUXC_NAND_CE2_ 511 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
527 MX8MN_IOMUXC_NAND_CE3_ 512 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
528 MX8MN_IOMUXC_NAND_CLE_ 513 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
529 MX8MN_IOMUXC_NAND_CE1_ 514 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
530 >; 515 >;
531 }; 516 };
532 517
533 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 518 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
534 fsl,pins = < 519 fsl,pins = <
535 MX8MN_IOMUXC_NAND_WE_B 520 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
536 MX8MN_IOMUXC_NAND_WP_B 521 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
537 MX8MN_IOMUXC_NAND_DATA 522 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
538 MX8MN_IOMUXC_NAND_DATA 523 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
539 MX8MN_IOMUXC_NAND_DATA 524 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
540 MX8MN_IOMUXC_NAND_DATA 525 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
541 MX8MN_IOMUXC_NAND_RE_B 526 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
542 MX8MN_IOMUXC_NAND_CE2_ 527 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
543 MX8MN_IOMUXC_NAND_CE3_ 528 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
544 MX8MN_IOMUXC_NAND_CLE_ 529 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
545 MX8MN_IOMUXC_NAND_CE1_ 530 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
546 >; 531 >;
547 }; 532 };
548 533
549 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 534 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
550 fsl,pins = < 535 fsl,pins = <
551 MX8MN_IOMUXC_NAND_WE_B 536 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
552 MX8MN_IOMUXC_NAND_WP_B 537 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
553 MX8MN_IOMUXC_NAND_DATA 538 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
554 MX8MN_IOMUXC_NAND_DATA 539 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
555 MX8MN_IOMUXC_NAND_DATA 540 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
556 MX8MN_IOMUXC_NAND_DATA 541 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
557 MX8MN_IOMUXC_NAND_RE_B 542 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
558 MX8MN_IOMUXC_NAND_CE2_ 543 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
559 MX8MN_IOMUXC_NAND_CE3_ 544 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
560 MX8MN_IOMUXC_NAND_CLE_ 545 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
561 MX8MN_IOMUXC_NAND_CE1_ 546 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
562 >; 547 >;
563 }; 548 };
564 549
565 pinctrl_wdog: wdoggrp { 550 pinctrl_wdog: wdoggrp {
566 fsl,pins = < 551 fsl,pins = <
567 MX8MN_IOMUXC_GPIO1_IO0 552 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
568 >; 553 >;
569 }; 554 };
570 }; 555 };
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