1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 * Copyright 2019-2020 Variscite Ltd. 4 * Copyright 2019-2020 Variscite Ltd.
5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk 5 * Copyright (C) 2020 Krzysztof Kozlowski <krzk@kernel.org>
6 */ 6 */
7 7
8 #include "imx8mn.dtsi" 8 #include "imx8mn.dtsi"
9 9
10 / { 10 / {
11 model = "Variscite VAR-SOM-MX8MN modul 11 model = "Variscite VAR-SOM-MX8MN module";
12 compatible = "variscite,var-som-mx8mn" 12 compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
13 13
14 chosen { 14 chosen {
15 stdout-path = &uart4; 15 stdout-path = &uart4;
16 }; 16 };
17 17
18 memory@40000000 { 18 memory@40000000 {
19 device_type = "memory"; 19 device_type = "memory";
20 reg = <0x0 0x40000000 0 0x4000 20 reg = <0x0 0x40000000 0 0x40000000>;
21 }; 21 };
22 22
23 reg_eth_phy: regulator-eth-phy { 23 reg_eth_phy: regulator-eth-phy {
24 compatible = "regulator-fixed" 24 compatible = "regulator-fixed";
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_reg_eth_ 26 pinctrl-0 = <&pinctrl_reg_eth_phy>;
27 regulator-name = "eth_phy_pwr" 27 regulator-name = "eth_phy_pwr";
28 regulator-min-microvolt = <330 28 regulator-min-microvolt = <3300000>;
29 regulator-max-microvolt = <330 29 regulator-max-microvolt = <3300000>;
30 regulator-enable-ramp-delay = <<
31 gpio = <&gpio2 9 GPIO_ACTIVE_H 30 gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
32 enable-active-high; 31 enable-active-high;
33 }; 32 };
34 <<
35 reg_3v3_fixed: regulator-3v3-fixed { <<
36 compatible = "regulator-fixed" <<
37 regulator-name = "fixed_3v3"; <<
38 regulator-min-microvolt = <330 <<
39 regulator-max-microvolt = <330 <<
40 regulator-always-on; <<
41 }; <<
42 }; 33 };
43 34
44 &A53_0 { 35 &A53_0 {
45 cpu-supply = <&buck2_reg>; 36 cpu-supply = <&buck2_reg>;
46 }; 37 };
47 38
48 &A53_1 { 39 &A53_1 {
49 cpu-supply = <&buck2_reg>; 40 cpu-supply = <&buck2_reg>;
50 }; 41 };
51 42
52 &A53_2 { 43 &A53_2 {
53 cpu-supply = <&buck2_reg>; 44 cpu-supply = <&buck2_reg>;
54 }; 45 };
55 46
56 &A53_3 { 47 &A53_3 {
57 cpu-supply = <&buck2_reg>; 48 cpu-supply = <&buck2_reg>;
58 }; 49 };
59 50
60 &ecspi1 { 51 &ecspi1 {
61 pinctrl-names = "default"; 52 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_ecspi1>; 53 pinctrl-0 = <&pinctrl_ecspi1>;
63 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW> 54 cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
64 <&gpio1 0 GPIO_ACTIVE_LOW> 55 <&gpio1 0 GPIO_ACTIVE_LOW>;
65 /delete-property/ dmas; 56 /delete-property/ dmas;
66 /delete-property/ dma-names; 57 /delete-property/ dma-names;
67 status = "okay"; 58 status = "okay";
68 59
69 /* Resistive touch controller */ 60 /* Resistive touch controller */
70 touchscreen@0 { 61 touchscreen@0 {
71 reg = <0>; 62 reg = <0>;
72 compatible = "ti,ads7846"; 63 compatible = "ti,ads7846";
73 pinctrl-names = "default"; 64 pinctrl-names = "default";
74 pinctrl-0 = <&pinctrl_restouch 65 pinctrl-0 = <&pinctrl_restouch>;
75 interrupt-parent = <&gpio1>; 66 interrupt-parent = <&gpio1>;
76 interrupts = <3 IRQ_TYPE_EDGE_ 67 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
77 68
78 spi-max-frequency = <1500000>; 69 spi-max-frequency = <1500000>;
79 pendown-gpio = <&gpio1 3 GPIO_ 70 pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
80 71
81 ti,x-min = /bits/ 16 <125>; 72 ti,x-min = /bits/ 16 <125>;
82 touchscreen-size-x = <4008>; 73 touchscreen-size-x = <4008>;
83 ti,y-min = /bits/ 16 <282>; 74 ti,y-min = /bits/ 16 <282>;
84 touchscreen-size-y = <3864>; 75 touchscreen-size-y = <3864>;
85 ti,x-plate-ohms = /bits/ 16 <1 76 ti,x-plate-ohms = /bits/ 16 <180>;
86 touchscreen-max-pressure = <25 77 touchscreen-max-pressure = <255>;
87 touchscreen-average-samples = 78 touchscreen-average-samples = <10>;
88 ti,debounce-tol = /bits/ 16 <3 79 ti,debounce-tol = /bits/ 16 <3>;
89 ti,debounce-rep = /bits/ 16 <1 80 ti,debounce-rep = /bits/ 16 <1>;
90 ti,settle-delay-usec = /bits/ 81 ti,settle-delay-usec = /bits/ 16 <150>;
91 ti,keep-vref-on; 82 ti,keep-vref-on;
92 wakeup-source; 83 wakeup-source;
93 }; 84 };
94 }; 85 };
95 86
96 &fec1 { 87 &fec1 {
97 pinctrl-names = "default", "sleep"; 88 pinctrl-names = "default", "sleep";
98 pinctrl-0 = <&pinctrl_fec1>; 89 pinctrl-0 = <&pinctrl_fec1>;
99 pinctrl-1 = <&pinctrl_fec1_sleep>; 90 pinctrl-1 = <&pinctrl_fec1_sleep>;
100 phy-mode = "rgmii"; 91 phy-mode = "rgmii";
101 phy-handle = <ðphy>; 92 phy-handle = <ðphy>;
102 phy-supply = <®_eth_phy>; 93 phy-supply = <®_eth_phy>;
103 fsl,magic-packet; 94 fsl,magic-packet;
104 status = "okay"; 95 status = "okay";
105 96
106 mdio { 97 mdio {
107 #address-cells = <1>; 98 #address-cells = <1>;
108 #size-cells = <0>; 99 #size-cells = <0>;
109 100
110 ethphy: ethernet-phy@4 { /* AR !! 101 ethphy: ethernet-phy@4 {
111 compatible = "ethernet 102 compatible = "ethernet-phy-ieee802.3-c22";
112 reg = <4>; 103 reg = <4>;
113 reset-gpios = <&gpio1 104 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
114 reset-assert-us = <100 105 reset-assert-us = <10000>;
115 /* <<
116 * Deassert delay: <<
117 * ADIN1300 requires 5 <<
118 * AR8033 requires 1 <<
119 */ <<
120 reset-deassert-us = <2 <<
121 }; 106 };
122 }; 107 };
123 }; 108 };
124 109
125 &i2c1 { 110 &i2c1 {
126 clock-frequency = <400000>; 111 clock-frequency = <400000>;
127 pinctrl-names = "default"; 112 pinctrl-names = "default";
128 pinctrl-0 = <&pinctrl_i2c1>; 113 pinctrl-0 = <&pinctrl_i2c1>;
129 status = "okay"; 114 status = "okay";
130 115
131 pmic@4b { 116 pmic@4b {
132 compatible = "rohm,bd71847"; 117 compatible = "rohm,bd71847";
133 reg = <0x4b>; 118 reg = <0x4b>;
134 pinctrl-names = "default"; 119 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_pmic>; 120 pinctrl-0 = <&pinctrl_pmic>;
136 interrupt-parent = <&gpio2>; 121 interrupt-parent = <&gpio2>;
137 interrupts = <8 IRQ_TYPE_LEVEL 122 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
138 rohm,reset-snvs-powered; 123 rohm,reset-snvs-powered;
139 124
140 regulators { 125 regulators {
141 buck1_reg: BUCK1 { 126 buck1_reg: BUCK1 {
142 regulator-name 127 regulator-name = "buck1";
143 regulator-min- 128 regulator-min-microvolt = <700000>;
144 regulator-max- 129 regulator-max-microvolt = <1300000>;
145 regulator-boot 130 regulator-boot-on;
146 regulator-alwa 131 regulator-always-on;
147 regulator-ramp 132 regulator-ramp-delay = <1250>;
148 }; 133 };
149 134
150 buck2_reg: BUCK2 { 135 buck2_reg: BUCK2 {
151 regulator-name 136 regulator-name = "buck2";
152 regulator-min- 137 regulator-min-microvolt = <700000>;
153 regulator-max- 138 regulator-max-microvolt = <1300000>;
154 regulator-boot 139 regulator-boot-on;
155 regulator-alwa 140 regulator-always-on;
156 regulator-ramp 141 regulator-ramp-delay = <1250>;
157 rohm,dvs-run-v 142 rohm,dvs-run-voltage = <1000000>;
158 rohm,dvs-idle- 143 rohm,dvs-idle-voltage = <900000>;
159 }; 144 };
160 145
161 buck3_reg: BUCK3 { 146 buck3_reg: BUCK3 {
162 regulator-name 147 regulator-name = "buck3";
163 regulator-min- 148 regulator-min-microvolt = <700000>;
164 regulator-max- 149 regulator-max-microvolt = <1350000>;
165 regulator-boot 150 regulator-boot-on;
166 regulator-alwa 151 regulator-always-on;
167 }; 152 };
168 153
169 buck4_reg: BUCK4 { 154 buck4_reg: BUCK4 {
170 regulator-name 155 regulator-name = "buck4";
171 regulator-min- 156 regulator-min-microvolt = <2600000>;
172 regulator-max- 157 regulator-max-microvolt = <3300000>;
173 regulator-boot 158 regulator-boot-on;
174 regulator-alwa 159 regulator-always-on;
175 }; 160 };
176 161
177 buck5_reg: BUCK5 { 162 buck5_reg: BUCK5 {
178 regulator-name 163 regulator-name = "buck5";
179 regulator-min- 164 regulator-min-microvolt = <1605000>;
180 regulator-max- 165 regulator-max-microvolt = <1995000>;
181 regulator-boot 166 regulator-boot-on;
182 regulator-alwa 167 regulator-always-on;
183 }; 168 };
184 169
185 buck6_reg: BUCK6 { 170 buck6_reg: BUCK6 {
186 regulator-name 171 regulator-name = "buck6";
187 regulator-min- 172 regulator-min-microvolt = <800000>;
188 regulator-max- 173 regulator-max-microvolt = <1400000>;
189 regulator-boot 174 regulator-boot-on;
190 regulator-alwa 175 regulator-always-on;
191 }; 176 };
192 177
193 ldo1_reg: LDO1 { 178 ldo1_reg: LDO1 {
194 regulator-name 179 regulator-name = "ldo1";
195 regulator-min- 180 regulator-min-microvolt = <1600000>;
196 regulator-max- 181 regulator-max-microvolt = <1900000>;
197 regulator-boot 182 regulator-boot-on;
198 regulator-alwa 183 regulator-always-on;
199 }; 184 };
200 185
201 ldo2_reg: LDO2 { 186 ldo2_reg: LDO2 {
202 regulator-name 187 regulator-name = "ldo2";
203 regulator-min- 188 regulator-min-microvolt = <800000>;
204 regulator-max- 189 regulator-max-microvolt = <900000>;
205 regulator-boot 190 regulator-boot-on;
206 regulator-alwa 191 regulator-always-on;
207 }; 192 };
208 193
209 ldo3_reg: LDO3 { 194 ldo3_reg: LDO3 {
210 regulator-name 195 regulator-name = "ldo3";
211 regulator-min- 196 regulator-min-microvolt = <1800000>;
212 regulator-max- 197 regulator-max-microvolt = <3300000>;
213 regulator-boot 198 regulator-boot-on;
214 regulator-alwa 199 regulator-always-on;
215 }; 200 };
216 201
217 ldo4_reg: LDO4 { 202 ldo4_reg: LDO4 {
218 regulator-name 203 regulator-name = "ldo4";
219 regulator-min- 204 regulator-min-microvolt = <900000>;
220 regulator-max- 205 regulator-max-microvolt = <1800000>;
221 regulator-alwa 206 regulator-always-on;
222 }; 207 };
223 208
224 ldo5_reg: LDO5 { 209 ldo5_reg: LDO5 {
225 regulator-name !! 210 regulator-compatible = "ldo5";
226 regulator-min- 211 regulator-min-microvolt = <1800000>;
227 regulator-max- 212 regulator-max-microvolt = <1800000>;
228 regulator-alwa 213 regulator-always-on;
229 }; 214 };
230 215
231 ldo6_reg: LDO6 { 216 ldo6_reg: LDO6 {
232 regulator-name 217 regulator-name = "ldo6";
233 regulator-min- 218 regulator-min-microvolt = <900000>;
234 regulator-max- 219 regulator-max-microvolt = <1800000>;
235 regulator-boot 220 regulator-boot-on;
236 regulator-alwa 221 regulator-always-on;
237 }; 222 };
238 }; 223 };
239 }; 224 };
240 <<
241 eeprom_som: eeprom@52 { <<
242 compatible = "atmel,24c04"; <<
243 reg = <0x52>; <<
244 pagesize = <16>; <<
245 vcc-supply = <®_3v3_fixed>; <<
246 }; <<
247 }; 225 };
248 226
249 &i2c3 { 227 &i2c3 {
250 clock-frequency = <400000>; 228 clock-frequency = <400000>;
251 pinctrl-names = "default"; 229 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_i2c3>; 230 pinctrl-0 = <&pinctrl_i2c3>;
253 status = "okay"; 231 status = "okay";
254 232
255 /* TODO: configure audio, as of now ju 233 /* TODO: configure audio, as of now just put a placeholder */
256 wm8904: codec@1a { 234 wm8904: codec@1a {
257 compatible = "wlf,wm8904"; 235 compatible = "wlf,wm8904";
258 reg = <0x1a>; 236 reg = <0x1a>;
259 status = "disabled"; 237 status = "disabled";
260 }; 238 };
261 }; 239 };
262 240
263 &snvs_pwrkey { 241 &snvs_pwrkey {
264 status = "okay"; 242 status = "okay";
265 }; 243 };
266 244
267 /* Bluetooth */ 245 /* Bluetooth */
268 &uart2 { 246 &uart2 {
269 pinctrl-names = "default"; 247 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_uart2>; 248 pinctrl-0 = <&pinctrl_uart2>;
271 assigned-clocks = <&clk IMX8MN_CLK_UAR 249 assigned-clocks = <&clk IMX8MN_CLK_UART2>;
272 assigned-clock-parents = <&clk IMX8MN_ 250 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
273 uart-has-rtscts; 251 uart-has-rtscts;
274 status = "okay"; 252 status = "okay";
275 }; 253 };
276 254
277 /* Console */ 255 /* Console */
278 &uart4 { 256 &uart4 {
279 pinctrl-names = "default"; 257 pinctrl-names = "default";
280 pinctrl-0 = <&pinctrl_uart4>; 258 pinctrl-0 = <&pinctrl_uart4>;
281 status = "okay"; 259 status = "okay";
282 }; 260 };
283 261
284 &usbotg1 { 262 &usbotg1 {
285 dr_mode = "otg"; 263 dr_mode = "otg";
286 usb-role-switch; 264 usb-role-switch;
287 status = "okay"; 265 status = "okay";
288 }; 266 };
289 267
290 /* WIFI */ 268 /* WIFI */
291 &usdhc1 { 269 &usdhc1 {
292 #address-cells = <1>; 270 #address-cells = <1>;
293 #size-cells = <0>; 271 #size-cells = <0>;
294 pinctrl-names = "default", "state_100m 272 pinctrl-names = "default", "state_100mhz", "state_200mhz";
295 pinctrl-0 = <&pinctrl_usdhc1>; 273 pinctrl-0 = <&pinctrl_usdhc1>;
296 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 274 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
297 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 275 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
298 bus-width = <4>; 276 bus-width = <4>;
299 non-removable; 277 non-removable;
300 keep-power-in-suspend; 278 keep-power-in-suspend;
301 status = "okay"; 279 status = "okay";
302 280
303 brcmf: bcrmf@1 { 281 brcmf: bcrmf@1 {
304 reg = <1>; 282 reg = <1>;
305 compatible = "brcm,bcm4329-fma 283 compatible = "brcm,bcm4329-fmac";
306 }; 284 };
307 }; 285 };
308 286
309 /* SD */ 287 /* SD */
310 &usdhc2 { 288 &usdhc2 {
311 assigned-clocks = <&clk IMX8MN_CLK_USD 289 assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
312 assigned-clock-rates = <200000000>; 290 assigned-clock-rates = <200000000>;
313 pinctrl-names = "default", "state_100m 291 pinctrl-names = "default", "state_100mhz", "state_200mhz";
314 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 292 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
315 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 293 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
316 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 294 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
317 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW> 295 cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
318 bus-width = <4>; 296 bus-width = <4>;
319 vmmc-supply = <®_usdhc2_vmmc>; 297 vmmc-supply = <®_usdhc2_vmmc>;
320 status = "okay"; 298 status = "okay";
321 }; 299 };
322 300
323 /* eMMC */ 301 /* eMMC */
324 &usdhc3 { 302 &usdhc3 {
325 assigned-clocks = <&clk IMX8MN_CLK_USD 303 assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
326 assigned-clock-rates = <400000000>; 304 assigned-clock-rates = <400000000>;
327 pinctrl-names = "default", "state_100m 305 pinctrl-names = "default", "state_100mhz", "state_200mhz";
328 pinctrl-0 = <&pinctrl_usdhc3>; 306 pinctrl-0 = <&pinctrl_usdhc3>;
329 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 307 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
330 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 308 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
331 bus-width = <8>; 309 bus-width = <8>;
332 non-removable; 310 non-removable;
333 status = "okay"; 311 status = "okay";
334 }; 312 };
335 313
336 &wdog1 { 314 &wdog1 {
337 pinctrl-names = "default"; 315 pinctrl-names = "default";
338 pinctrl-0 = <&pinctrl_wdog>; 316 pinctrl-0 = <&pinctrl_wdog>;
339 fsl,ext-reset-output; 317 fsl,ext-reset-output;
340 status = "okay"; 318 status = "okay";
341 }; 319 };
342 320
343 &iomuxc { 321 &iomuxc {
344 pinctrl_ecspi1: ecspi1grp { 322 pinctrl_ecspi1: ecspi1grp {
345 fsl,pins = < 323 fsl,pins = <
346 MX8MN_IOMUXC_ECSPI1_SC 324 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13
347 MX8MN_IOMUXC_ECSPI1_MO 325 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13
348 MX8MN_IOMUXC_ECSPI1_MI 326 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13
349 MX8MN_IOMUXC_GPIO1_IO1 327 MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x13
350 MX8MN_IOMUXC_GPIO1_IO0 328 MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x13
351 >; 329 >;
352 }; 330 };
353 331
354 pinctrl_fec1: fec1grp { 332 pinctrl_fec1: fec1grp {
355 fsl,pins = < 333 fsl,pins = <
356 MX8MN_IOMUXC_ENET_MDC_ 334 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
357 MX8MN_IOMUXC_ENET_MDIO 335 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
358 MX8MN_IOMUXC_ENET_TD3_ 336 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
359 MX8MN_IOMUXC_ENET_TD2_ 337 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
360 MX8MN_IOMUXC_ENET_TD1_ 338 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
361 MX8MN_IOMUXC_ENET_TD0_ 339 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
362 MX8MN_IOMUXC_ENET_RD3_ 340 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
363 MX8MN_IOMUXC_ENET_RD2_ 341 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
364 MX8MN_IOMUXC_ENET_RD1_ 342 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
365 MX8MN_IOMUXC_ENET_RD0_ 343 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
366 MX8MN_IOMUXC_ENET_TXC_ 344 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
367 MX8MN_IOMUXC_ENET_RXC_ 345 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
368 MX8MN_IOMUXC_ENET_RX_C 346 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
369 MX8MN_IOMUXC_ENET_TX_C 347 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
370 MX8MN_IOMUXC_GPIO1_IO0 !! 348 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
371 >; 349 >;
372 }; 350 };
373 351
374 pinctrl_fec1_sleep: fec1sleepgrp { 352 pinctrl_fec1_sleep: fec1sleepgrp {
375 fsl,pins = < 353 fsl,pins = <
376 MX8MN_IOMUXC_ENET_MDC_ 354 MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16 0x120
377 MX8MN_IOMUXC_ENET_MDIO 355 MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17 0x120
378 MX8MN_IOMUXC_ENET_TD3_ 356 MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18 0x120
379 MX8MN_IOMUXC_ENET_TD2_ 357 MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19 0x120
380 MX8MN_IOMUXC_ENET_TD1_ 358 MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20 0x120
381 MX8MN_IOMUXC_ENET_TD0_ 359 MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21 0x120
382 MX8MN_IOMUXC_ENET_RD3_ 360 MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29 0x120
383 MX8MN_IOMUXC_ENET_RD2_ 361 MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28 0x120
384 MX8MN_IOMUXC_ENET_RD1_ 362 MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27 0x120
385 MX8MN_IOMUXC_ENET_RD0_ 363 MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26 0x120
386 MX8MN_IOMUXC_ENET_TXC_ 364 MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23 0x120
387 MX8MN_IOMUXC_ENET_RXC_ 365 MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25 0x120
388 MX8MN_IOMUXC_ENET_RX_C 366 MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24 0x120
389 MX8MN_IOMUXC_ENET_TX_C 367 MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22 0x120
390 MX8MN_IOMUXC_GPIO1_IO0 368 MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x120
391 >; 369 >;
392 }; 370 };
393 371
394 pinctrl_i2c1: i2c1grp { 372 pinctrl_i2c1: i2c1grp {
395 fsl,pins = < 373 fsl,pins = <
396 MX8MN_IOMUXC_I2C1_SCL_ 374 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
397 MX8MN_IOMUXC_I2C1_SDA_ 375 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
398 >; 376 >;
399 }; 377 };
400 378
401 pinctrl_i2c3: i2c3grp { 379 pinctrl_i2c3: i2c3grp {
402 fsl,pins = < 380 fsl,pins = <
403 MX8MN_IOMUXC_I2C3_SCL_ 381 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
404 MX8MN_IOMUXC_I2C3_SDA_ 382 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
405 >; 383 >;
406 }; 384 };
407 385
408 pinctrl_pmic: pmicirqgrp { 386 pinctrl_pmic: pmicirqgrp {
409 fsl,pins = < 387 fsl,pins = <
410 MX8MN_IOMUXC_SD1_DATA6 388 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x141
411 >; 389 >;
412 }; 390 };
413 391
414 pinctrl_reg_eth_phy: regethphygrp { 392 pinctrl_reg_eth_phy: regethphygrp {
415 fsl,pins = < 393 fsl,pins = <
416 MX8MN_IOMUXC_SD1_DATA7 394 MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9 0x41
417 >; 395 >;
418 }; 396 };
419 397
420 pinctrl_restouch: restouchgrp { 398 pinctrl_restouch: restouchgrp {
421 fsl,pins = < 399 fsl,pins = <
422 MX8MN_IOMUXC_GPIO1_IO0 400 MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x1c0
423 >; 401 >;
424 }; 402 };
425 403
426 pinctrl_uart2: uart2grp { 404 pinctrl_uart2: uart2grp {
427 fsl,pins = < 405 fsl,pins = <
428 MX8MN_IOMUXC_SAI3_TXFS 406 MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX 0x140
429 MX8MN_IOMUXC_SAI3_TXC_ 407 MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX 0x140
430 MX8MN_IOMUXC_SAI3_RXC_ 408 MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B 0x140
431 MX8MN_IOMUXC_SAI3_RXD_ 409 MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B 0x140
432 >; 410 >;
433 }; 411 };
434 412
435 pinctrl_uart4: uart4grp { 413 pinctrl_uart4: uart4grp {
436 fsl,pins = < 414 fsl,pins = <
437 MX8MN_IOMUXC_UART4_RXD 415 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
438 MX8MN_IOMUXC_UART4_TXD 416 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
439 >; 417 >;
440 }; 418 };
441 419
442 pinctrl_usdhc1: usdhc1grp { 420 pinctrl_usdhc1: usdhc1grp {
443 fsl,pins = < 421 fsl,pins = <
444 MX8MN_IOMUXC_SD1_CLK_U 422 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
445 MX8MN_IOMUXC_SD1_CMD_U 423 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
446 MX8MN_IOMUXC_SD1_DATA0 424 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
447 MX8MN_IOMUXC_SD1_DATA1 425 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
448 MX8MN_IOMUXC_SD1_DATA2 426 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
449 MX8MN_IOMUXC_SD1_DATA3 427 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
450 >; 428 >;
451 }; 429 };
452 430
453 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 431 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
454 fsl,pins = < 432 fsl,pins = <
455 MX8MN_IOMUXC_SD1_CLK_U 433 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
456 MX8MN_IOMUXC_SD1_CMD_U 434 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
457 MX8MN_IOMUXC_SD1_DATA0 435 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
458 MX8MN_IOMUXC_SD1_DATA1 436 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
459 MX8MN_IOMUXC_SD1_DATA2 437 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
460 MX8MN_IOMUXC_SD1_DATA3 438 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
461 >; 439 >;
462 }; 440 };
463 441
464 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 442 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
465 fsl,pins = < 443 fsl,pins = <
466 MX8MN_IOMUXC_SD1_CLK_U 444 MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
467 MX8MN_IOMUXC_SD1_CMD_U 445 MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
468 MX8MN_IOMUXC_SD1_DATA0 446 MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
469 MX8MN_IOMUXC_SD1_DATA1 447 MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
470 MX8MN_IOMUXC_SD1_DATA2 448 MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
471 MX8MN_IOMUXC_SD1_DATA3 449 MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
472 >; 450 >;
473 }; 451 };
474 452
475 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 453 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
476 fsl,pins = < 454 fsl,pins = <
477 MX8MN_IOMUXC_GPIO1_IO1 455 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
478 >; 456 >;
479 }; 457 };
480 458
481 pinctrl_usdhc2: usdhc2grp { 459 pinctrl_usdhc2: usdhc2grp {
482 fsl,pins = < 460 fsl,pins = <
483 MX8MN_IOMUXC_SD2_CLK_U 461 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
484 MX8MN_IOMUXC_SD2_CMD_U 462 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
485 MX8MN_IOMUXC_SD2_DATA0 463 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
486 MX8MN_IOMUXC_SD2_DATA1 464 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
487 MX8MN_IOMUXC_SD2_DATA2 465 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
488 MX8MN_IOMUXC_SD2_DATA3 466 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
489 MX8MN_IOMUXC_GPIO1_IO0 467 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
490 >; 468 >;
491 }; 469 };
492 470
493 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 471 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
494 fsl,pins = < 472 fsl,pins = <
495 MX8MN_IOMUXC_SD2_CLK_U 473 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
496 MX8MN_IOMUXC_SD2_CMD_U 474 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
497 MX8MN_IOMUXC_SD2_DATA0 475 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
498 MX8MN_IOMUXC_SD2_DATA1 476 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
499 MX8MN_IOMUXC_SD2_DATA2 477 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
500 MX8MN_IOMUXC_SD2_DATA3 478 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
501 MX8MN_IOMUXC_GPIO1_IO0 479 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
502 >; 480 >;
503 }; 481 };
504 482
505 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 483 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
506 fsl,pins = < 484 fsl,pins = <
507 MX8MN_IOMUXC_SD2_CLK_U 485 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
508 MX8MN_IOMUXC_SD2_CMD_U 486 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
509 MX8MN_IOMUXC_SD2_DATA0 487 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
510 MX8MN_IOMUXC_SD2_DATA1 488 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
511 MX8MN_IOMUXC_SD2_DATA2 489 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
512 MX8MN_IOMUXC_SD2_DATA3 490 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
513 MX8MN_IOMUXC_GPIO1_IO0 491 MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
514 >; 492 >;
515 }; 493 };
516 494
517 pinctrl_usdhc3: usdhc3grp { 495 pinctrl_usdhc3: usdhc3grp {
518 fsl,pins = < 496 fsl,pins = <
519 MX8MN_IOMUXC_NAND_WE_B 497 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
520 MX8MN_IOMUXC_NAND_WP_B 498 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
521 MX8MN_IOMUXC_NAND_DATA 499 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
522 MX8MN_IOMUXC_NAND_DATA 500 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
523 MX8MN_IOMUXC_NAND_DATA 501 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
524 MX8MN_IOMUXC_NAND_DATA 502 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
525 MX8MN_IOMUXC_NAND_RE_B 503 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
526 MX8MN_IOMUXC_NAND_CE2_ 504 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
527 MX8MN_IOMUXC_NAND_CE3_ 505 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
528 MX8MN_IOMUXC_NAND_CLE_ 506 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
529 MX8MN_IOMUXC_NAND_CE1_ 507 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
530 >; 508 >;
531 }; 509 };
532 510
533 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 511 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
534 fsl,pins = < 512 fsl,pins = <
535 MX8MN_IOMUXC_NAND_WE_B 513 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
536 MX8MN_IOMUXC_NAND_WP_B 514 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
537 MX8MN_IOMUXC_NAND_DATA 515 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
538 MX8MN_IOMUXC_NAND_DATA 516 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
539 MX8MN_IOMUXC_NAND_DATA 517 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
540 MX8MN_IOMUXC_NAND_DATA 518 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
541 MX8MN_IOMUXC_NAND_RE_B 519 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
542 MX8MN_IOMUXC_NAND_CE2_ 520 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
543 MX8MN_IOMUXC_NAND_CE3_ 521 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
544 MX8MN_IOMUXC_NAND_CLE_ 522 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
545 MX8MN_IOMUXC_NAND_CE1_ 523 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
546 >; 524 >;
547 }; 525 };
548 526
549 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 527 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
550 fsl,pins = < 528 fsl,pins = <
551 MX8MN_IOMUXC_NAND_WE_B 529 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
552 MX8MN_IOMUXC_NAND_WP_B 530 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
553 MX8MN_IOMUXC_NAND_DATA 531 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
554 MX8MN_IOMUXC_NAND_DATA 532 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
555 MX8MN_IOMUXC_NAND_DATA 533 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
556 MX8MN_IOMUXC_NAND_DATA 534 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
557 MX8MN_IOMUXC_NAND_RE_B 535 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
558 MX8MN_IOMUXC_NAND_CE2_ 536 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
559 MX8MN_IOMUXC_NAND_CE3_ 537 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
560 MX8MN_IOMUXC_NAND_CLE_ 538 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
561 MX8MN_IOMUXC_NAND_CE1_ 539 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
562 >; 540 >;
563 }; 541 };
564 542
565 pinctrl_wdog: wdoggrp { 543 pinctrl_wdog: wdoggrp {
566 fsl,pins = < 544 fsl,pins = <
567 MX8MN_IOMUXC_GPIO1_IO0 545 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0x166
568 >; 546 >;
569 }; 547 };
570 }; 548 };
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