1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 12
13 #include "imx8mn.dtsi" 13 #include "imx8mn.dtsi"
14 14
15 / { 15 / {
16 model = "Gateworks Venice GW7902 i.MX8 16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl, 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18 18
19 aliases { 19 aliases {
20 usb0 = &usbotg1; 20 usb0 = &usbotg1;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 stdout-path = &uart2; 24 stdout-path = &uart2;
25 }; 25 };
26 26
27 memory@40000000 { 27 memory@40000000 {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x8000 29 reg = <0x0 0x40000000 0 0x80000000>;
30 }; 30 };
31 31
32 can20m: can20m { 32 can20m: can20m {
33 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 clock-frequency = <20000000>; 35 clock-frequency = <20000000>;
36 clock-output-names = "can20m"; 36 clock-output-names = "can20m";
37 }; 37 };
38 38
39 gpio-keys { 39 gpio-keys {
40 compatible = "gpio-keys"; 40 compatible = "gpio-keys";
41 41
42 key-user-pb { !! 42 user-pb {
43 label = "user_pb"; 43 label = "user_pb";
44 gpios = <&gpio 2 GPIO_ 44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 linux,code = <BTN_0>; 45 linux,code = <BTN_0>;
46 }; 46 };
47 47
48 key-user-pb1x { !! 48 user-pb1x {
49 label = "user_pb1x"; 49 label = "user_pb1x";
50 linux,code = <BTN_1>; 50 linux,code = <BTN_1>;
51 interrupt-parent = <&g 51 interrupt-parent = <&gsc>;
52 interrupts = <0>; 52 interrupts = <0>;
53 }; 53 };
54 54
55 key-erased { 55 key-erased {
56 label = "key_erased"; 56 label = "key_erased";
57 linux,code = <BTN_2>; 57 linux,code = <BTN_2>;
58 interrupt-parent = <&g 58 interrupt-parent = <&gsc>;
59 interrupts = <1>; 59 interrupts = <1>;
60 }; 60 };
61 61
62 key-eeprom-wp { !! 62 eeprom-wp {
63 label = "eeprom_wp"; 63 label = "eeprom_wp";
64 linux,code = <BTN_3>; 64 linux,code = <BTN_3>;
65 interrupt-parent = <&g 65 interrupt-parent = <&gsc>;
66 interrupts = <2>; 66 interrupts = <2>;
67 }; 67 };
68 68
69 key-tamper { !! 69 tamper {
70 label = "tamper"; 70 label = "tamper";
71 linux,code = <BTN_4>; 71 linux,code = <BTN_4>;
72 interrupt-parent = <&g 72 interrupt-parent = <&gsc>;
73 interrupts = <5>; 73 interrupts = <5>;
74 }; 74 };
75 75
76 switch-hold { 76 switch-hold {
77 label = "switch_hold"; 77 label = "switch_hold";
78 linux,code = <BTN_5>; 78 linux,code = <BTN_5>;
79 interrupt-parent = <&g 79 interrupt-parent = <&gsc>;
80 interrupts = <7>; 80 interrupts = <7>;
81 }; 81 };
82 }; 82 };
83 83
84 led-controller { 84 led-controller {
85 compatible = "gpio-leds"; 85 compatible = "gpio-leds";
86 pinctrl-names = "default"; 86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_led 87 pinctrl-0 = <&pinctrl_gpio_leds>;
88 88
89 led-0 { 89 led-0 {
90 function = LED_FUNCTIO 90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_ 91 color = <LED_COLOR_ID_GREEN>;
92 label = "panel1"; 92 label = "panel1";
93 gpios = <&gpio3 21 GPI 93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off"; 94 default-state = "off";
95 }; 95 };
96 96
97 led-1 { 97 led-1 {
98 function = LED_FUNCTIO 98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_ 99 color = <LED_COLOR_ID_GREEN>;
100 label = "panel2"; 100 label = "panel2";
101 gpios = <&gpio3 23 GPI 101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off"; 102 default-state = "off";
103 }; 103 };
104 104
105 led-2 { 105 led-2 {
106 function = LED_FUNCTIO 106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_ 107 color = <LED_COLOR_ID_GREEN>;
108 label = "panel3"; 108 label = "panel3";
109 gpios = <&gpio3 22 GPI 109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off"; 110 default-state = "off";
111 }; 111 };
112 112
113 led-3 { 113 led-3 {
114 function = LED_FUNCTIO 114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_ 115 color = <LED_COLOR_ID_GREEN>;
116 label = "panel4"; 116 label = "panel4";
117 gpios = <&gpio3 20 GPI 117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off"; 118 default-state = "off";
119 }; 119 };
120 120
121 led-4 { 121 led-4 {
122 function = LED_FUNCTIO 122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_ 123 color = <LED_COLOR_ID_GREEN>;
124 label = "panel5"; 124 label = "panel5";
125 gpios = <&gpio3 25 GPI 125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off"; 126 default-state = "off";
127 }; 127 };
128 }; 128 };
129 129
130 pps { 130 pps {
131 compatible = "pps-gpio"; 131 compatible = "pps-gpio";
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>; 133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE 134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135 status = "okay"; 135 status = "okay";
136 }; 136 };
137 137
138 reg_3p3v: regulator-3p3v { 138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed" 139 compatible = "regulator-fixed";
140 regulator-name = "3P3V"; 140 regulator-name = "3P3V";
141 regulator-min-microvolt = <330 141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <330 142 regulator-max-microvolt = <3300000>;
143 regulator-always-on; 143 regulator-always-on;
144 }; 144 };
145 145
146 reg_usb1_vbus: regulator-usb1 { 146 reg_usb1_vbus: regulator-usb1 {
147 compatible = "regulator-fixed" 147 compatible = "regulator-fixed";
148 pinctrl-names = "default"; 148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_reg_usb1 149 pinctrl-0 = <&pinctrl_reg_usb1>;
150 regulator-name = "usb_usb1_vbu 150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_H 151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152 enable-active-high; 152 enable-active-high;
153 regulator-min-microvolt = <500 153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <500 154 regulator-max-microvolt = <5000000>;
155 }; 155 };
156 156
157 reg_wifi: regulator-wifi { 157 reg_wifi: regulator-wifi {
158 compatible = "regulator-fixed" 158 compatible = "regulator-fixed";
159 pinctrl-names = "default"; 159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_reg_wl>; 160 pinctrl-0 = <&pinctrl_reg_wl>;
161 regulator-name = "wifi"; 161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_ 162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high; 163 enable-active-high;
164 startup-delay-us = <100>; 164 startup-delay-us = <100>;
165 regulator-min-microvolt = <330 165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <330 166 regulator-max-microvolt = <3300000>;
167 }; 167 };
168 }; 168 };
169 169
170 &A53_0 { 170 &A53_0 {
171 cpu-supply = <&buck2>; 171 cpu-supply = <&buck2>;
172 }; 172 };
173 173
174 &A53_1 { 174 &A53_1 {
175 cpu-supply = <&buck2>; 175 cpu-supply = <&buck2>;
176 }; 176 };
177 177
178 &A53_2 { 178 &A53_2 {
179 cpu-supply = <&buck2>; 179 cpu-supply = <&buck2>;
180 }; 180 };
181 181
182 &A53_3 { 182 &A53_3 {
183 cpu-supply = <&buck2>; 183 cpu-supply = <&buck2>;
184 }; 184 };
185 185
186 &ddrc { 186 &ddrc {
187 operating-points-v2 = <&ddrc_opp_table 187 operating-points-v2 = <&ddrc_opp_table>;
188 188
189 ddrc_opp_table: opp-table { 189 ddrc_opp_table: opp-table {
190 compatible = "operating-points 190 compatible = "operating-points-v2";
191 191
192 opp-25000000 { !! 192 opp-25M {
193 opp-hz = /bits/ 64 <25 193 opp-hz = /bits/ 64 <25000000>;
194 }; 194 };
195 195
196 opp-100000000 { !! 196 opp-100M {
197 opp-hz = /bits/ 64 <10 197 opp-hz = /bits/ 64 <100000000>;
198 }; 198 };
199 199
200 opp-750000000 { !! 200 opp-750M {
201 opp-hz = /bits/ 64 <75 201 opp-hz = /bits/ 64 <750000000>;
202 }; 202 };
203 }; 203 };
204 }; 204 };
205 205
206 &ecspi1 { 206 &ecspi1 {
207 pinctrl-names = "default"; 207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>; 208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210 status = "okay"; 210 status = "okay";
211 211
212 can@0 { 212 can@0 {
213 compatible = "microchip,mcp251 213 compatible = "microchip,mcp2515";
214 reg = <0>; 214 reg = <0>;
215 clocks = <&can20m>; 215 clocks = <&can20m>;
>> 216 oscillator-frequency = <20000000>;
216 interrupt-parent = <&gpio2>; 217 interrupt-parent = <&gpio2>;
217 interrupts = <3 IRQ_TYPE_LEVEL 218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218 spi-max-frequency = <10000000> 219 spi-max-frequency = <10000000>;
219 }; 220 };
220 }; 221 };
221 222
222 &disp_blk_ctrl { <<
223 status = "disabled"; <<
224 }; <<
225 <<
226 /* off-board header */ 223 /* off-board header */
227 &ecspi2 { 224 &ecspi2 {
228 pinctrl-names = "default"; 225 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_spi2>; 226 pinctrl-0 = <&pinctrl_spi2>;
230 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 227 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
231 status = "okay"; 228 status = "okay";
232 }; 229 };
233 230
234 &fec1 { 231 &fec1 {
235 pinctrl-names = "default"; 232 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_fec1>; 233 pinctrl-0 = <&pinctrl_fec1>;
237 phy-mode = "rgmii-id"; 234 phy-mode = "rgmii-id";
238 phy-handle = <ðphy0>; 235 phy-handle = <ðphy0>;
239 local-mac-address = [00 00 00 00 00 00 236 local-mac-address = [00 00 00 00 00 00];
240 status = "okay"; 237 status = "okay";
241 238
242 mdio { 239 mdio {
243 #address-cells = <1>; 240 #address-cells = <1>;
244 #size-cells = <0>; 241 #size-cells = <0>;
245 242
246 ethphy0: ethernet-phy@0 { 243 ethphy0: ethernet-phy@0 {
247 compatible = "ethernet 244 compatible = "ethernet-phy-ieee802.3-c22";
248 reg = <0>; 245 reg = <0>;
249 ti,rx-internal-delay = 246 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
250 ti,tx-internal-delay = 247 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
251 tx-fifo-depth = <DP838 248 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
252 rx-fifo-depth = <DP838 249 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
253 }; 250 };
254 }; 251 };
255 }; 252 };
256 253
257 &gpio1 { <<
258 gpio-line-names = "", "", "", "", "", <<
259 "m2_pwr_en", "", "", "", "", " <<
260 "", "", "", "", "", "", "", "" <<
261 "", "", "", "", "", "", "", "" <<
262 }; <<
263 <<
264 &gpio2 { <<
265 gpio-line-names = "", "", "", "", "", <<
266 "uart2_en#", "", "", "", "", " <<
267 "", "", "", "", "", "", "", "" <<
268 "", "", "", "", "", "", "", "" <<
269 }; <<
270 <<
271 &gpio3 { <<
272 gpio-line-names = "", "m2_gdis#", "", <<
273 "", "", "", "", "", "", "", "" <<
274 "", "", "", "", "", "", "", "" <<
275 "", "", "", "", "", "", "", "" <<
276 }; <<
277 <<
278 &gpio4 { <<
279 gpio-line-names = "", "", "", "", "", <<
280 "", "", "", "", "", "", "", "" <<
281 "", "", "", "", "", "app_gpio1 <<
282 "", "uart1_term", "uart1_half" <<
283 "mipi_gpio1", "", "", ""; <<
284 }; <<
285 <<
286 &gpio5 { <<
287 gpio-line-names = "", "", "", "mipi_gp <<
288 "mipi_gpio3", "mipi_gpio2", "" <<
289 "", "", "", "", "", "", "", "" <<
290 "", "", "", "", "", "", "", "" <<
291 "", "", "", "", "", "", "", "" <<
292 }; <<
293 <<
294 &gpu { <<
295 status = "disabled"; <<
296 }; <<
297 <<
298 &i2c1 { 254 &i2c1 {
299 clock-frequency = <100000>; 255 clock-frequency = <100000>;
300 pinctrl-names = "default", "gpio"; !! 256 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_i2c1>; 257 pinctrl-0 = <&pinctrl_i2c1>;
302 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
303 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI <<
304 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI <<
305 status = "okay"; 258 status = "okay";
306 259
307 gsc: gsc@20 { 260 gsc: gsc@20 {
308 compatible = "gw,gsc"; 261 compatible = "gw,gsc";
309 reg = <0x20>; 262 reg = <0x20>;
310 pinctrl-0 = <&pinctrl_gsc>; 263 pinctrl-0 = <&pinctrl_gsc>;
311 interrupt-parent = <&gpio2>; 264 interrupt-parent = <&gpio2>;
312 interrupts = <6 IRQ_TYPE_EDGE_ 265 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
313 interrupt-controller; 266 interrupt-controller;
314 #interrupt-cells = <1>; 267 #interrupt-cells = <1>;
315 #address-cells = <1>; <<
316 #size-cells = <0>; <<
317 268
318 adc { 269 adc {
319 compatible = "gw,gsc-a 270 compatible = "gw,gsc-adc";
320 #address-cells = <1>; 271 #address-cells = <1>;
321 #size-cells = <0>; 272 #size-cells = <0>;
322 273
323 channel@6 { 274 channel@6 {
324 gw,mode = <0>; 275 gw,mode = <0>;
325 reg = <0x06>; 276 reg = <0x06>;
326 label = "temp" 277 label = "temp";
327 }; 278 };
328 279
329 channel@8 { 280 channel@8 {
330 gw,mode = <3>; !! 281 gw,mode = <1>;
331 reg = <0x08>; 282 reg = <0x08>;
332 label = "vdd_b 283 label = "vdd_bat";
333 }; 284 };
334 285
335 channel@82 { 286 channel@82 {
336 gw,mode = <2>; 287 gw,mode = <2>;
337 reg = <0x82>; 288 reg = <0x82>;
338 label = "vin"; 289 label = "vin";
339 gw,voltage-div 290 gw,voltage-divider-ohms = <22100 1000>;
340 gw,voltage-off 291 gw,voltage-offset-microvolt = <700000>;
341 }; 292 };
342 293
343 channel@84 { 294 channel@84 {
344 gw,mode = <2>; 295 gw,mode = <2>;
345 reg = <0x84>; 296 reg = <0x84>;
346 label = "vin_4 297 label = "vin_4p0";
347 gw,voltage-div 298 gw,voltage-divider-ohms = <10000 10000>;
348 }; 299 };
349 300
350 channel@86 { 301 channel@86 {
351 gw,mode = <2>; 302 gw,mode = <2>;
352 reg = <0x86>; 303 reg = <0x86>;
353 label = "vdd_3 304 label = "vdd_3p3";
354 gw,voltage-div 305 gw,voltage-divider-ohms = <10000 10000>;
355 }; 306 };
356 307
357 channel@88 { 308 channel@88 {
358 gw,mode = <2>; 309 gw,mode = <2>;
359 reg = <0x88>; 310 reg = <0x88>;
360 label = "vdd_0 311 label = "vdd_0p9";
361 }; 312 };
362 313
363 channel@8c { 314 channel@8c {
364 gw,mode = <2>; 315 gw,mode = <2>;
365 reg = <0x8c>; 316 reg = <0x8c>;
366 label = "vdd_s 317 label = "vdd_soc";
367 }; 318 };
368 319
369 channel@8e { 320 channel@8e {
370 gw,mode = <2>; 321 gw,mode = <2>;
371 reg = <0x8e>; 322 reg = <0x8e>;
372 label = "vdd_a 323 label = "vdd_arm";
373 }; 324 };
374 325
375 channel@90 { 326 channel@90 {
376 gw,mode = <2>; 327 gw,mode = <2>;
377 reg = <0x90>; 328 reg = <0x90>;
378 label = "vdd_1 329 label = "vdd_1p8";
379 }; 330 };
380 331
381 channel@92 { 332 channel@92 {
382 gw,mode = <2>; 333 gw,mode = <2>;
383 reg = <0x92>; 334 reg = <0x92>;
384 label = "vdd_d 335 label = "vdd_dram";
385 }; 336 };
386 337
387 channel@98 { 338 channel@98 {
388 gw,mode = <2>; 339 gw,mode = <2>;
389 reg = <0x98>; 340 reg = <0x98>;
390 label = "vdd_1 341 label = "vdd_1p0";
391 }; 342 };
392 343
393 channel@9a { 344 channel@9a {
394 gw,mode = <2>; 345 gw,mode = <2>;
395 reg = <0x9a>; 346 reg = <0x9a>;
396 label = "vdd_2 347 label = "vdd_2p5";
397 gw,voltage-div 348 gw,voltage-divider-ohms = <10000 10000>;
398 }; 349 };
399 350
400 channel@9c { <<
401 gw,mode = <2>; <<
402 reg = <0x9c>; <<
403 label = "vdd_5 <<
404 gw,voltage-div <<
405 }; <<
406 <<
407 channel@a2 { 351 channel@a2 {
408 gw,mode = <2>; 352 gw,mode = <2>;
409 reg = <0xa2>; 353 reg = <0xa2>;
410 label = "vdd_g 354 label = "vdd_gsc";
411 gw,voltage-div 355 gw,voltage-divider-ohms = <10000 10000>;
412 }; 356 };
413 }; 357 };
414 }; 358 };
415 359
416 gpio: gpio@23 { 360 gpio: gpio@23 {
417 compatible = "nxp,pca9555"; 361 compatible = "nxp,pca9555";
418 reg = <0x23>; 362 reg = <0x23>;
419 gpio-controller; 363 gpio-controller;
420 #gpio-cells = <2>; 364 #gpio-cells = <2>;
421 interrupt-parent = <&gsc>; 365 interrupt-parent = <&gsc>;
422 interrupts = <4>; 366 interrupts = <4>;
423 }; 367 };
424 368
425 pmic@4b { 369 pmic@4b {
426 compatible = "rohm,bd71847"; 370 compatible = "rohm,bd71847";
427 reg = <0x4b>; 371 reg = <0x4b>;
428 pinctrl-names = "default"; 372 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_pmic>; 373 pinctrl-0 = <&pinctrl_pmic>;
430 interrupt-parent = <&gpio3>; 374 interrupt-parent = <&gpio3>;
431 interrupts = <8 IRQ_TYPE_LEVEL 375 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
432 rohm,reset-snvs-powered; 376 rohm,reset-snvs-powered;
433 #clock-cells = <0>; 377 #clock-cells = <0>;
434 clocks = <&osc_32k>; !! 378 clocks = <&osc_32k 0>;
435 clock-output-names = "clk-32k- 379 clock-output-names = "clk-32k-out";
436 380
437 regulators { 381 regulators {
438 /* vdd_soc: 0.805-0.90 382 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
439 BUCK1 { 383 BUCK1 {
440 regulator-name 384 regulator-name = "buck1";
441 regulator-min- 385 regulator-min-microvolt = <700000>;
442 regulator-max- 386 regulator-max-microvolt = <1300000>;
443 regulator-boot 387 regulator-boot-on;
444 regulator-alwa 388 regulator-always-on;
445 regulator-ramp 389 regulator-ramp-delay = <1250>;
446 }; 390 };
447 391
448 /* vdd_arm: 0.805-1.0V 392 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
449 buck2: BUCK2 { 393 buck2: BUCK2 {
450 regulator-name 394 regulator-name = "buck2";
451 regulator-min- 395 regulator-min-microvolt = <700000>;
452 regulator-max- 396 regulator-max-microvolt = <1300000>;
453 regulator-boot 397 regulator-boot-on;
454 regulator-alwa 398 regulator-always-on;
455 regulator-ramp 399 regulator-ramp-delay = <1250>;
456 rohm,dvs-run-v 400 rohm,dvs-run-voltage = <1000000>;
457 rohm,dvs-idle- 401 rohm,dvs-idle-voltage = <900000>;
458 }; 402 };
459 403
460 /* vdd_0p9: 0.805-1.0V 404 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
461 BUCK3 { 405 BUCK3 {
462 regulator-name 406 regulator-name = "buck3";
463 regulator-min- 407 regulator-min-microvolt = <700000>;
464 regulator-max- 408 regulator-max-microvolt = <1350000>;
465 regulator-boot 409 regulator-boot-on;
466 regulator-alwa 410 regulator-always-on;
467 }; 411 };
468 412
469 /* vdd_3p3 */ 413 /* vdd_3p3 */
470 BUCK4 { 414 BUCK4 {
471 regulator-name 415 regulator-name = "buck4";
472 regulator-min- 416 regulator-min-microvolt = <3000000>;
473 regulator-max- 417 regulator-max-microvolt = <3300000>;
474 regulator-boot 418 regulator-boot-on;
475 regulator-alwa 419 regulator-always-on;
476 }; 420 };
477 421
478 /* vdd_1p8 */ 422 /* vdd_1p8 */
479 BUCK5 { 423 BUCK5 {
480 regulator-name 424 regulator-name = "buck5";
481 regulator-min- 425 regulator-min-microvolt = <1605000>;
482 regulator-max- 426 regulator-max-microvolt = <1995000>;
483 regulator-boot 427 regulator-boot-on;
484 regulator-alwa 428 regulator-always-on;
485 }; 429 };
486 430
487 /* vdd_dram */ 431 /* vdd_dram */
488 BUCK6 { 432 BUCK6 {
489 regulator-name 433 regulator-name = "buck6";
490 regulator-min- 434 regulator-min-microvolt = <800000>;
491 regulator-max- 435 regulator-max-microvolt = <1400000>;
492 regulator-boot 436 regulator-boot-on;
493 regulator-alwa 437 regulator-always-on;
494 }; 438 };
495 439
496 /* nvcc_snvs_1p8 */ 440 /* nvcc_snvs_1p8 */
497 LDO1 { 441 LDO1 {
498 regulator-name 442 regulator-name = "ldo1";
499 regulator-min- 443 regulator-min-microvolt = <1600000>;
500 regulator-max- 444 regulator-max-microvolt = <1900000>;
501 regulator-boot 445 regulator-boot-on;
502 regulator-alwa 446 regulator-always-on;
503 }; 447 };
504 448
505 /* vdd_snvs_0p8 */ 449 /* vdd_snvs_0p8 */
506 LDO2 { 450 LDO2 {
507 regulator-name 451 regulator-name = "ldo2";
508 regulator-min- 452 regulator-min-microvolt = <800000>;
509 regulator-max- 453 regulator-max-microvolt = <900000>;
510 regulator-boot 454 regulator-boot-on;
511 regulator-alwa 455 regulator-always-on;
512 }; 456 };
513 457
514 /* vdda_1p8 */ 458 /* vdda_1p8 */
515 LDO3 { 459 LDO3 {
516 regulator-name 460 regulator-name = "ldo3";
517 regulator-min- 461 regulator-min-microvolt = <1800000>;
518 regulator-max- 462 regulator-max-microvolt = <3300000>;
519 regulator-boot 463 regulator-boot-on;
520 regulator-alwa 464 regulator-always-on;
521 }; 465 };
522 466
523 LDO4 { 467 LDO4 {
524 regulator-name 468 regulator-name = "ldo4";
525 regulator-min- 469 regulator-min-microvolt = <900000>;
526 regulator-max- 470 regulator-max-microvolt = <1800000>;
527 regulator-boot 471 regulator-boot-on;
528 regulator-alwa 472 regulator-always-on;
529 }; 473 };
530 474
531 LDO6 { 475 LDO6 {
532 regulator-name 476 regulator-name = "ldo6";
533 regulator-min- 477 regulator-min-microvolt = <900000>;
534 regulator-max- 478 regulator-max-microvolt = <1800000>;
535 regulator-boot 479 regulator-boot-on;
536 regulator-alwa 480 regulator-always-on;
537 }; 481 };
538 }; 482 };
539 }; 483 };
540 484
541 eeprom@50 { 485 eeprom@50 {
542 compatible = "atmel,24c02"; 486 compatible = "atmel,24c02";
543 reg = <0x50>; 487 reg = <0x50>;
544 pagesize = <16>; 488 pagesize = <16>;
545 }; 489 };
546 490
547 eeprom@51 { 491 eeprom@51 {
548 compatible = "atmel,24c02"; 492 compatible = "atmel,24c02";
549 reg = <0x51>; 493 reg = <0x51>;
550 pagesize = <16>; 494 pagesize = <16>;
551 }; 495 };
552 496
553 eeprom@52 { 497 eeprom@52 {
554 compatible = "atmel,24c02"; 498 compatible = "atmel,24c02";
555 reg = <0x52>; 499 reg = <0x52>;
556 pagesize = <16>; 500 pagesize = <16>;
557 }; 501 };
558 502
559 eeprom@53 { 503 eeprom@53 {
560 compatible = "atmel,24c02"; 504 compatible = "atmel,24c02";
561 reg = <0x53>; 505 reg = <0x53>;
562 pagesize = <16>; 506 pagesize = <16>;
563 }; 507 };
564 508
565 rtc@68 { 509 rtc@68 {
566 compatible = "dallas,ds1672"; 510 compatible = "dallas,ds1672";
567 reg = <0x68>; 511 reg = <0x68>;
568 }; 512 };
569 }; 513 };
570 514
571 &i2c2 { 515 &i2c2 {
572 clock-frequency = <400000>; 516 clock-frequency = <400000>;
573 pinctrl-names = "default", "gpio"; !! 517 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_i2c2>; 518 pinctrl-0 = <&pinctrl_i2c2>;
575 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
576 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
577 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
578 status = "okay"; 519 status = "okay";
579 520
580 accelerometer@19 { 521 accelerometer@19 {
581 compatible = "st,lis2de12"; 522 compatible = "st,lis2de12";
582 pinctrl-names = "default"; 523 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_accel>; 524 pinctrl-0 = <&pinctrl_accel>;
584 reg = <0x19>; 525 reg = <0x19>;
585 st,drdy-int-pin = <1>; 526 st,drdy-int-pin = <1>;
586 interrupt-parent = <&gpio1>; 527 interrupt-parent = <&gpio1>;
587 interrupts = <12 IRQ_TYPE_LEVE 528 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
>> 529 interrupt-names = "INT1";
588 }; 530 };
589 }; 531 };
590 532
591 /* off-board header */ 533 /* off-board header */
592 &i2c3 { 534 &i2c3 {
593 clock-frequency = <400000>; 535 clock-frequency = <400000>;
594 pinctrl-names = "default", "gpio"; !! 536 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_i2c3>; 537 pinctrl-0 = <&pinctrl_i2c3>;
596 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
597 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI <<
598 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI <<
599 status = "okay"; 538 status = "okay";
600 }; 539 };
601 540
602 /* off-board header */ 541 /* off-board header */
603 &i2c4 { 542 &i2c4 {
604 clock-frequency = <400000>; 543 clock-frequency = <400000>;
605 pinctrl-names = "default", "gpio"; !! 544 pinctrl-names = "default";
606 pinctrl-0 = <&pinctrl_i2c4>; 545 pinctrl-0 = <&pinctrl_i2c4>;
607 pinctrl-1 = <&pinctrl_i2c4_gpio>; <<
608 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI <<
609 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI <<
610 status = "okay"; 546 status = "okay";
611 }; 547 };
612 548
613 &pgc_gpumix { <<
614 status = "disabled"; <<
615 }; <<
616 <<
617 /* off-board header */ 549 /* off-board header */
618 &sai3 { 550 &sai3 {
619 pinctrl-names = "default"; 551 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_sai3>; 552 pinctrl-0 = <&pinctrl_sai3>;
621 assigned-clocks = <&clk IMX8MN_CLK_SAI 553 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
622 assigned-clock-parents = <&clk IMX8MN_ 554 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
623 assigned-clock-rates = <24576000>; 555 assigned-clock-rates = <24576000>;
624 status = "okay"; 556 status = "okay";
625 }; 557 };
626 558
627 /* RS232/RS485/RS422 selectable */ 559 /* RS232/RS485/RS422 selectable */
628 &uart1 { 560 &uart1 {
629 pinctrl-names = "default"; 561 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 562 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
631 status = "okay"; 563 status = "okay";
632 }; 564 };
633 565
634 /* RS232 console */ 566 /* RS232 console */
635 &uart2 { 567 &uart2 {
636 pinctrl-names = "default"; 568 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_uart2>; 569 pinctrl-0 = <&pinctrl_uart2>;
638 status = "okay"; 570 status = "okay";
639 }; 571 };
640 572
641 /* bluetooth HCI */ 573 /* bluetooth HCI */
642 &uart3 { 574 &uart3 {
643 pinctrl-names = "default"; 575 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 576 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
645 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 577 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
646 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 578 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
647 status = "okay"; 579 status = "okay";
648 580
649 bluetooth { 581 bluetooth {
650 compatible = "brcm,bcm4330-bt" 582 compatible = "brcm,bcm4330-bt";
651 shutdown-gpios = <&gpio2 12 GP 583 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
652 }; 584 };
653 }; 585 };
654 586
655 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 587 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
656 &uart4 { 588 &uart4 {
657 pinctrl-names = "default"; 589 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart4>; 590 pinctrl-0 = <&pinctrl_uart4>;
659 status = "okay"; 591 status = "okay";
660 }; 592 };
661 593
662 &usbotg1 { 594 &usbotg1 {
663 dr_mode = "host"; 595 dr_mode = "host";
664 vbus-supply = <®_usb1_vbus>; 596 vbus-supply = <®_usb1_vbus>;
665 disable-over-current; 597 disable-over-current;
666 status = "okay"; 598 status = "okay";
667 }; 599 };
668 600
669 /* SDIO WiFi */ 601 /* SDIO WiFi */
670 &usdhc2 { 602 &usdhc2 {
671 pinctrl-names = "default", "state_100m !! 603 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_usdhc2>; 604 pinctrl-0 = <&pinctrl_usdhc2>;
673 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; <<
674 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; <<
675 bus-width = <4>; 605 bus-width = <4>;
676 non-removable; 606 non-removable;
677 vmmc-supply = <®_wifi>; 607 vmmc-supply = <®_wifi>;
678 #address-cells = <1>; <<
679 #size-cells = <0>; <<
680 status = "okay"; 608 status = "okay";
681 <<
682 wifi@0 { <<
683 compatible = "brcm,bcm43455-fm <<
684 reg = <0>; <<
685 }; <<
686 }; 609 };
687 610
688 /* eMMC */ 611 /* eMMC */
689 &usdhc3 { 612 &usdhc3 {
690 pinctrl-names = "default", "state_100m 613 pinctrl-names = "default", "state_100mhz", "state_200mhz";
691 pinctrl-0 = <&pinctrl_usdhc3>; 614 pinctrl-0 = <&pinctrl_usdhc3>;
692 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 615 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
693 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 616 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
694 bus-width = <8>; 617 bus-width = <8>;
695 non-removable; 618 non-removable;
696 status = "okay"; 619 status = "okay";
697 }; 620 };
698 621
699 &wdog1 { 622 &wdog1 {
700 pinctrl-names = "default"; 623 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_wdog>; 624 pinctrl-0 = <&pinctrl_wdog>;
702 fsl,ext-reset-output; 625 fsl,ext-reset-output;
703 status = "okay"; 626 status = "okay";
704 }; 627 };
705 628
706 &iomuxc { 629 &iomuxc {
707 pinctrl-names = "default"; 630 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_hog>; 631 pinctrl-0 = <&pinctrl_hog>;
709 632
710 pinctrl_hog: hoggrp { 633 pinctrl_hog: hoggrp {
711 fsl,pins = < 634 fsl,pins = <
712 MX8MN_IOMUXC_NAND_CE0_ 635 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
713 MX8MN_IOMUXC_GPIO1_IO0 !! 636 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RST# */
714 MX8MN_IOMUXC_GPIO1_IO1 <<
715 MX8MN_IOMUXC_NAND_DATA 637 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
716 MX8MN_IOMUXC_GPIO1_IO1 638 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
717 MX8MN_IOMUXC_SAI2_RXFS 639 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
718 MX8MN_IOMUXC_SAI2_RXC_ <<
719 MX8MN_IOMUXC_SAI2_MCLK 640 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
720 MX8MN_IOMUXC_SD1_DATA6 641 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
721 MX8MN_IOMUXC_SAI3_RXFS 642 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
722 MX8MN_IOMUXC_SPDIF_EXT 643 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
723 MX8MN_IOMUXC_SPDIF_RX_ 644 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
724 MX8MN_IOMUXC_SPDIF_TX_ 645 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
725 >; 646 >;
726 }; 647 };
727 648
728 pinctrl_accel: accelgrp { 649 pinctrl_accel: accelgrp {
729 fsl,pins = < 650 fsl,pins = <
730 MX8MN_IOMUXC_GPIO1_IO1 651 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
731 >; 652 >;
732 }; 653 };
733 654
734 pinctrl_fec1: fec1grp { 655 pinctrl_fec1: fec1grp {
735 fsl,pins = < 656 fsl,pins = <
736 MX8MN_IOMUXC_ENET_MDC_ 657 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
737 MX8MN_IOMUXC_ENET_MDIO 658 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
738 MX8MN_IOMUXC_ENET_TD3_ 659 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
739 MX8MN_IOMUXC_ENET_TD2_ 660 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
740 MX8MN_IOMUXC_ENET_TD1_ 661 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
741 MX8MN_IOMUXC_ENET_TD0_ 662 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
742 MX8MN_IOMUXC_ENET_RD3_ 663 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
743 MX8MN_IOMUXC_ENET_RD2_ 664 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
744 MX8MN_IOMUXC_ENET_RD1_ 665 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
745 MX8MN_IOMUXC_ENET_RD0_ 666 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
746 MX8MN_IOMUXC_ENET_TXC_ 667 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
747 MX8MN_IOMUXC_ENET_RXC_ 668 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
748 MX8MN_IOMUXC_ENET_RX_C 669 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
749 MX8MN_IOMUXC_ENET_TX_C 670 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
750 MX8MN_IOMUXC_GPIO1_IO1 671 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
751 MX8MN_IOMUXC_GPIO1_IO1 672 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
>> 673 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
>> 674 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
752 >; 675 >;
753 }; 676 };
754 677
755 pinctrl_gsc: gscgrp { 678 pinctrl_gsc: gscgrp {
756 fsl,pins = < 679 fsl,pins = <
757 MX8MN_IOMUXC_SD1_DATA4 680 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
758 >; 681 >;
759 }; 682 };
760 683
761 pinctrl_i2c1: i2c1grp { 684 pinctrl_i2c1: i2c1grp {
762 fsl,pins = < 685 fsl,pins = <
763 MX8MN_IOMUXC_I2C1_SCL_ 686 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
764 MX8MN_IOMUXC_I2C1_SDA_ 687 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
765 >; 688 >;
766 }; 689 };
767 690
768 pinctrl_i2c1_gpio: i2c1gpiogrp { <<
769 fsl,pins = < <<
770 MX8MN_IOMUXC_I2C1_SCL_ <<
771 MX8MN_IOMUXC_I2C1_SDA_ <<
772 >; <<
773 }; <<
774 <<
775 pinctrl_i2c2: i2c2grp { 691 pinctrl_i2c2: i2c2grp {
776 fsl,pins = < 692 fsl,pins = <
777 MX8MN_IOMUXC_I2C2_SCL_ 693 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
778 MX8MN_IOMUXC_I2C2_SDA_ 694 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
779 >; 695 >;
780 }; 696 };
781 697
782 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
783 fsl,pins = < <<
784 MX8MN_IOMUXC_I2C2_SCL_ <<
785 MX8MN_IOMUXC_I2C2_SDA_ <<
786 >; <<
787 }; <<
788 <<
789 pinctrl_i2c3: i2c3grp { 698 pinctrl_i2c3: i2c3grp {
790 fsl,pins = < 699 fsl,pins = <
791 MX8MN_IOMUXC_I2C3_SCL_ 700 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
792 MX8MN_IOMUXC_I2C3_SDA_ 701 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
793 >; 702 >;
794 }; 703 };
795 704
796 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
797 fsl,pins = < <<
798 MX8MN_IOMUXC_I2C3_SCL_ <<
799 MX8MN_IOMUXC_I2C3_SDA_ <<
800 >; <<
801 }; <<
802 <<
803 pinctrl_i2c4: i2c4grp { 705 pinctrl_i2c4: i2c4grp {
804 fsl,pins = < 706 fsl,pins = <
805 MX8MN_IOMUXC_I2C4_SCL_ 707 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
806 MX8MN_IOMUXC_I2C4_SDA_ 708 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
807 >; 709 >;
808 }; 710 };
809 711
810 pinctrl_i2c4_gpio: i2c4gpiogrp { <<
811 fsl,pins = < <<
812 MX8MN_IOMUXC_I2C4_SCL_ <<
813 MX8MN_IOMUXC_I2C4_SDA_ <<
814 >; <<
815 }; <<
816 <<
817 pinctrl_gpio_leds: gpioledgrp { 712 pinctrl_gpio_leds: gpioledgrp {
818 fsl,pins = < 713 fsl,pins = <
819 MX8MN_IOMUXC_SAI5_RXD0 714 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
820 MX8MN_IOMUXC_SAI5_RXD2 715 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
821 MX8MN_IOMUXC_SAI5_RXD1 716 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
822 MX8MN_IOMUXC_SAI5_RXC_ 717 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
823 MX8MN_IOMUXC_SAI5_MCLK 718 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
824 >; 719 >;
825 }; 720 };
826 721
827 pinctrl_pmic: pmicgrp { 722 pinctrl_pmic: pmicgrp {
828 fsl,pins = < 723 fsl,pins = <
829 MX8MN_IOMUXC_NAND_DATA 724 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
830 >; 725 >;
831 }; 726 };
832 727
833 pinctrl_pps: ppsgrp { 728 pinctrl_pps: ppsgrp {
834 fsl,pins = < 729 fsl,pins = <
835 MX8MN_IOMUXC_SAI5_RXD3 730 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
836 >; 731 >;
837 }; 732 };
838 733
839 pinctrl_reg_wl: regwlgrp { 734 pinctrl_reg_wl: regwlgrp {
840 fsl,pins = < 735 fsl,pins = <
841 MX8MN_IOMUXC_SD2_RESET 736 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
842 >; 737 >;
843 }; 738 };
844 739
845 pinctrl_reg_usb1: regusb1grp { 740 pinctrl_reg_usb1: regusb1grp {
846 fsl,pins = < 741 fsl,pins = <
847 MX8MN_IOMUXC_SD1_DATA5 742 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
848 >; 743 >;
849 }; 744 };
850 745
851 pinctrl_sai3: sai3grp { 746 pinctrl_sai3: sai3grp {
852 fsl,pins = < 747 fsl,pins = <
853 MX8MN_IOMUXC_SAI3_MCLK 748 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
854 MX8MN_IOMUXC_SAI3_RXD_ 749 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
855 MX8MN_IOMUXC_SAI3_TXC_ 750 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
856 MX8MN_IOMUXC_SAI3_TXD_ 751 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
857 MX8MN_IOMUXC_SAI3_TXFS 752 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
858 >; 753 >;
859 }; 754 };
860 755
861 pinctrl_spi1: spi1grp { 756 pinctrl_spi1: spi1grp {
862 fsl,pins = < 757 fsl,pins = <
863 MX8MN_IOMUXC_ECSPI1_SC 758 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
864 MX8MN_IOMUXC_ECSPI1_MO 759 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
865 MX8MN_IOMUXC_ECSPI1_MI 760 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
866 MX8MN_IOMUXC_ECSPI1_SS 761 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
867 MX8MN_IOMUXC_SD1_DATA1 762 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
868 >; 763 >;
869 }; 764 };
870 765
871 pinctrl_spi2: spi2grp { 766 pinctrl_spi2: spi2grp {
872 fsl,pins = < 767 fsl,pins = <
873 MX8MN_IOMUXC_ECSPI2_SC 768 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
874 MX8MN_IOMUXC_ECSPI2_MO 769 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
875 MX8MN_IOMUXC_ECSPI2_MI 770 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
876 MX8MN_IOMUXC_ECSPI2_SS 771 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
877 >; 772 >;
878 }; 773 };
879 774
880 pinctrl_uart1: uart1grp { 775 pinctrl_uart1: uart1grp {
881 fsl,pins = < 776 fsl,pins = <
882 MX8MN_IOMUXC_UART1_RXD 777 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
883 MX8MN_IOMUXC_UART1_TXD 778 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
884 >; 779 >;
885 }; 780 };
886 781
887 pinctrl_uart1_gpio: uart1gpiogrp { 782 pinctrl_uart1_gpio: uart1gpiogrp {
888 fsl,pins = < 783 fsl,pins = <
889 MX8MN_IOMUXC_SAI2_TXD0 784 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
890 MX8MN_IOMUXC_SAI2_TXC_ 785 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
891 MX8MN_IOMUXC_SAI2_RXD0 786 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
892 >; 787 >;
893 }; 788 };
894 789
895 pinctrl_uart2: uart2grp { 790 pinctrl_uart2: uart2grp {
896 fsl,pins = < 791 fsl,pins = <
897 MX8MN_IOMUXC_UART2_RXD 792 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
898 MX8MN_IOMUXC_UART2_TXD 793 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
899 >; 794 >;
900 }; 795 };
901 796
902 pinctrl_uart3_gpio: uart3_gpiogrp { 797 pinctrl_uart3_gpio: uart3_gpiogrp {
903 fsl,pins = < 798 fsl,pins = <
904 MX8MN_IOMUXC_SD2_CD_B_ 799 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
905 >; 800 >;
906 }; 801 };
907 802
908 pinctrl_uart3: uart3grp { 803 pinctrl_uart3: uart3grp {
909 fsl,pins = < 804 fsl,pins = <
910 MX8MN_IOMUXC_UART3_RXD 805 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
911 MX8MN_IOMUXC_UART3_TXD 806 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
912 MX8MN_IOMUXC_SD1_CLK_G 807 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
913 MX8MN_IOMUXC_SD1_CMD_G 808 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
914 >; 809 >;
915 }; 810 };
916 811
917 pinctrl_uart4: uart4grp { 812 pinctrl_uart4: uart4grp {
918 fsl,pins = < 813 fsl,pins = <
919 MX8MN_IOMUXC_UART4_RXD 814 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
920 MX8MN_IOMUXC_UART4_TXD 815 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
921 MX8MN_IOMUXC_GPIO1_IO0 816 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
922 >; 817 >;
923 }; 818 };
924 819
925 pinctrl_usdhc2: usdhc2grp { 820 pinctrl_usdhc2: usdhc2grp {
926 fsl,pins = < 821 fsl,pins = <
927 MX8MN_IOMUXC_SD2_CLK_U 822 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
928 MX8MN_IOMUXC_SD2_CMD_U 823 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
929 MX8MN_IOMUXC_SD2_DATA0 824 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
930 MX8MN_IOMUXC_SD2_DATA1 825 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
931 MX8MN_IOMUXC_SD2_DATA2 826 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
932 MX8MN_IOMUXC_SD2_DATA3 827 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
933 >; <<
934 }; <<
935 <<
936 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr <<
937 fsl,pins = < <<
938 MX8MN_IOMUXC_SD2_CLK_U <<
939 MX8MN_IOMUXC_SD2_CMD_U <<
940 MX8MN_IOMUXC_SD2_DATA0 <<
941 MX8MN_IOMUXC_SD2_DATA1 <<
942 MX8MN_IOMUXC_SD2_DATA2 <<
943 MX8MN_IOMUXC_SD2_DATA3 <<
944 >; <<
945 }; <<
946 <<
947 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr <<
948 fsl,pins = < <<
949 MX8MN_IOMUXC_SD2_CLK_U <<
950 MX8MN_IOMUXC_SD2_CMD_U <<
951 MX8MN_IOMUXC_SD2_DATA0 <<
952 MX8MN_IOMUXC_SD2_DATA1 <<
953 MX8MN_IOMUXC_SD2_DATA2 <<
954 MX8MN_IOMUXC_SD2_DATA3 <<
955 >; 828 >;
956 }; 829 };
957 830
958 pinctrl_usdhc3: usdhc3grp { 831 pinctrl_usdhc3: usdhc3grp {
959 fsl,pins = < 832 fsl,pins = <
960 MX8MN_IOMUXC_NAND_WE_B 833 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
961 MX8MN_IOMUXC_NAND_WP_B 834 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
962 MX8MN_IOMUXC_NAND_DATA 835 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
963 MX8MN_IOMUXC_NAND_DATA 836 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
964 MX8MN_IOMUXC_NAND_DATA 837 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
965 MX8MN_IOMUXC_NAND_DATA 838 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
966 MX8MN_IOMUXC_NAND_RE_B 839 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
967 MX8MN_IOMUXC_NAND_CE2_ 840 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
968 MX8MN_IOMUXC_NAND_CE3_ 841 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
969 MX8MN_IOMUXC_NAND_CLE_ 842 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
970 MX8MN_IOMUXC_NAND_CE1_ 843 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
971 >; 844 >;
972 }; 845 };
973 846
974 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 847 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
975 fsl,pins = < 848 fsl,pins = <
976 MX8MN_IOMUXC_NAND_WE_B 849 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
977 MX8MN_IOMUXC_NAND_WP_B 850 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
978 MX8MN_IOMUXC_NAND_DATA 851 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
979 MX8MN_IOMUXC_NAND_DATA 852 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
980 MX8MN_IOMUXC_NAND_DATA 853 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
981 MX8MN_IOMUXC_NAND_DATA 854 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
982 MX8MN_IOMUXC_NAND_RE_B 855 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
983 MX8MN_IOMUXC_NAND_CE2_ 856 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
984 MX8MN_IOMUXC_NAND_CE3_ 857 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
985 MX8MN_IOMUXC_NAND_CLE_ 858 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
986 MX8MN_IOMUXC_NAND_CE1_ 859 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
987 >; 860 >;
988 }; 861 };
989 862
990 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 863 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
991 fsl,pins = < 864 fsl,pins = <
992 MX8MN_IOMUXC_NAND_WE_B 865 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
993 MX8MN_IOMUXC_NAND_WP_B 866 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
994 MX8MN_IOMUXC_NAND_DATA 867 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
995 MX8MN_IOMUXC_NAND_DATA 868 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
996 MX8MN_IOMUXC_NAND_DATA 869 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
997 MX8MN_IOMUXC_NAND_DATA 870 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
998 MX8MN_IOMUXC_NAND_RE_B 871 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
999 MX8MN_IOMUXC_NAND_CE2_ 872 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1000 MX8MN_IOMUXC_NAND_CE3 873 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1001 MX8MN_IOMUXC_NAND_CLE 874 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1002 MX8MN_IOMUXC_NAND_CE1 875 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1003 >; 876 >;
1004 }; 877 };
1005 878
1006 pinctrl_wdog: wdoggrp { 879 pinctrl_wdog: wdoggrp {
1007 fsl,pins = < 880 fsl,pins = <
1008 MX8MN_IOMUXC_GPIO1_IO 881 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1009 >; 882 >;
1010 }; 883 };
1011 }; 884 };
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