1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 12
13 #include "imx8mn.dtsi" 13 #include "imx8mn.dtsi"
14 14
15 / { 15 / {
16 model = "Gateworks Venice GW7902 i.MX8 16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl, 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18 18
19 aliases { 19 aliases {
20 usb0 = &usbotg1; 20 usb0 = &usbotg1;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 stdout-path = &uart2; 24 stdout-path = &uart2;
25 }; 25 };
26 26
27 memory@40000000 { 27 memory@40000000 {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x8000 29 reg = <0x0 0x40000000 0 0x80000000>;
30 }; 30 };
31 31
32 can20m: can20m { 32 can20m: can20m {
33 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 clock-frequency = <20000000>; 35 clock-frequency = <20000000>;
36 clock-output-names = "can20m"; 36 clock-output-names = "can20m";
37 }; 37 };
38 38
39 gpio-keys { 39 gpio-keys {
40 compatible = "gpio-keys"; 40 compatible = "gpio-keys";
41 41
42 key-user-pb { !! 42 user-pb {
43 label = "user_pb"; 43 label = "user_pb";
44 gpios = <&gpio 2 GPIO_ 44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 linux,code = <BTN_0>; 45 linux,code = <BTN_0>;
46 }; 46 };
47 47
48 key-user-pb1x { !! 48 user-pb1x {
49 label = "user_pb1x"; 49 label = "user_pb1x";
50 linux,code = <BTN_1>; 50 linux,code = <BTN_1>;
51 interrupt-parent = <&g 51 interrupt-parent = <&gsc>;
52 interrupts = <0>; 52 interrupts = <0>;
53 }; 53 };
54 54
55 key-erased { 55 key-erased {
56 label = "key_erased"; 56 label = "key_erased";
57 linux,code = <BTN_2>; 57 linux,code = <BTN_2>;
58 interrupt-parent = <&g 58 interrupt-parent = <&gsc>;
59 interrupts = <1>; 59 interrupts = <1>;
60 }; 60 };
61 61
62 key-eeprom-wp { !! 62 eeprom-wp {
63 label = "eeprom_wp"; 63 label = "eeprom_wp";
64 linux,code = <BTN_3>; 64 linux,code = <BTN_3>;
65 interrupt-parent = <&g 65 interrupt-parent = <&gsc>;
66 interrupts = <2>; 66 interrupts = <2>;
67 }; 67 };
68 68
69 key-tamper { !! 69 tamper {
70 label = "tamper"; 70 label = "tamper";
71 linux,code = <BTN_4>; 71 linux,code = <BTN_4>;
72 interrupt-parent = <&g 72 interrupt-parent = <&gsc>;
73 interrupts = <5>; 73 interrupts = <5>;
74 }; 74 };
75 75
76 switch-hold { 76 switch-hold {
77 label = "switch_hold"; 77 label = "switch_hold";
78 linux,code = <BTN_5>; 78 linux,code = <BTN_5>;
79 interrupt-parent = <&g 79 interrupt-parent = <&gsc>;
80 interrupts = <7>; 80 interrupts = <7>;
81 }; 81 };
82 }; 82 };
83 83
84 led-controller { 84 led-controller {
85 compatible = "gpio-leds"; 85 compatible = "gpio-leds";
86 pinctrl-names = "default"; 86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_led 87 pinctrl-0 = <&pinctrl_gpio_leds>;
88 88
89 led-0 { 89 led-0 {
90 function = LED_FUNCTIO 90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_ 91 color = <LED_COLOR_ID_GREEN>;
92 label = "panel1"; 92 label = "panel1";
93 gpios = <&gpio3 21 GPI 93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off"; 94 default-state = "off";
95 }; 95 };
96 96
97 led-1 { 97 led-1 {
98 function = LED_FUNCTIO 98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_ 99 color = <LED_COLOR_ID_GREEN>;
100 label = "panel2"; 100 label = "panel2";
101 gpios = <&gpio3 23 GPI 101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off"; 102 default-state = "off";
103 }; 103 };
104 104
105 led-2 { 105 led-2 {
106 function = LED_FUNCTIO 106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_ 107 color = <LED_COLOR_ID_GREEN>;
108 label = "panel3"; 108 label = "panel3";
109 gpios = <&gpio3 22 GPI 109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off"; 110 default-state = "off";
111 }; 111 };
112 112
113 led-3 { 113 led-3 {
114 function = LED_FUNCTIO 114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_ 115 color = <LED_COLOR_ID_GREEN>;
116 label = "panel4"; 116 label = "panel4";
117 gpios = <&gpio3 20 GPI 117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off"; 118 default-state = "off";
119 }; 119 };
120 120
121 led-4 { 121 led-4 {
122 function = LED_FUNCTIO 122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_ 123 color = <LED_COLOR_ID_GREEN>;
124 label = "panel5"; 124 label = "panel5";
125 gpios = <&gpio3 25 GPI 125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off"; 126 default-state = "off";
127 }; 127 };
128 }; 128 };
129 129
130 pps { 130 pps {
131 compatible = "pps-gpio"; 131 compatible = "pps-gpio";
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>; 133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE 134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135 status = "okay"; 135 status = "okay";
136 }; 136 };
137 137
138 reg_3p3v: regulator-3p3v { 138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed" 139 compatible = "regulator-fixed";
140 regulator-name = "3P3V"; 140 regulator-name = "3P3V";
141 regulator-min-microvolt = <330 141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <330 142 regulator-max-microvolt = <3300000>;
143 regulator-always-on; 143 regulator-always-on;
144 }; 144 };
145 145
146 reg_usb1_vbus: regulator-usb1 { 146 reg_usb1_vbus: regulator-usb1 {
147 compatible = "regulator-fixed" 147 compatible = "regulator-fixed";
148 pinctrl-names = "default"; 148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_reg_usb1 149 pinctrl-0 = <&pinctrl_reg_usb1>;
150 regulator-name = "usb_usb1_vbu 150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_H 151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152 enable-active-high; 152 enable-active-high;
153 regulator-min-microvolt = <500 153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <500 154 regulator-max-microvolt = <5000000>;
155 }; 155 };
156 156
157 reg_wifi: regulator-wifi { 157 reg_wifi: regulator-wifi {
158 compatible = "regulator-fixed" 158 compatible = "regulator-fixed";
159 pinctrl-names = "default"; 159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_reg_wl>; 160 pinctrl-0 = <&pinctrl_reg_wl>;
161 regulator-name = "wifi"; 161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_ 162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high; 163 enable-active-high;
164 startup-delay-us = <100>; 164 startup-delay-us = <100>;
165 regulator-min-microvolt = <330 165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <330 166 regulator-max-microvolt = <3300000>;
167 }; 167 };
168 }; 168 };
169 169
170 &A53_0 { 170 &A53_0 {
171 cpu-supply = <&buck2>; 171 cpu-supply = <&buck2>;
172 }; 172 };
173 173
174 &A53_1 { 174 &A53_1 {
175 cpu-supply = <&buck2>; 175 cpu-supply = <&buck2>;
176 }; 176 };
177 177
178 &A53_2 { 178 &A53_2 {
179 cpu-supply = <&buck2>; 179 cpu-supply = <&buck2>;
180 }; 180 };
181 181
182 &A53_3 { 182 &A53_3 {
183 cpu-supply = <&buck2>; 183 cpu-supply = <&buck2>;
184 }; 184 };
185 185
186 &ddrc { 186 &ddrc {
187 operating-points-v2 = <&ddrc_opp_table 187 operating-points-v2 = <&ddrc_opp_table>;
188 188
189 ddrc_opp_table: opp-table { 189 ddrc_opp_table: opp-table {
190 compatible = "operating-points 190 compatible = "operating-points-v2";
191 191
192 opp-25000000 { !! 192 opp-25M {
193 opp-hz = /bits/ 64 <25 193 opp-hz = /bits/ 64 <25000000>;
194 }; 194 };
195 195
196 opp-100000000 { !! 196 opp-100M {
197 opp-hz = /bits/ 64 <10 197 opp-hz = /bits/ 64 <100000000>;
198 }; 198 };
199 199
200 opp-750000000 { !! 200 opp-750M {
201 opp-hz = /bits/ 64 <75 201 opp-hz = /bits/ 64 <750000000>;
202 }; 202 };
203 }; 203 };
204 }; 204 };
205 205
206 &ecspi1 { 206 &ecspi1 {
207 pinctrl-names = "default"; 207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>; 208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210 status = "okay"; 210 status = "okay";
211 211
212 can@0 { 212 can@0 {
213 compatible = "microchip,mcp251 213 compatible = "microchip,mcp2515";
214 reg = <0>; 214 reg = <0>;
215 clocks = <&can20m>; 215 clocks = <&can20m>;
>> 216 oscillator-frequency = <20000000>;
216 interrupt-parent = <&gpio2>; 217 interrupt-parent = <&gpio2>;
217 interrupts = <3 IRQ_TYPE_LEVEL 218 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218 spi-max-frequency = <10000000> 219 spi-max-frequency = <10000000>;
219 }; 220 };
220 }; 221 };
221 222
222 &disp_blk_ctrl { 223 &disp_blk_ctrl {
223 status = "disabled"; 224 status = "disabled";
224 }; 225 };
225 226
226 /* off-board header */ 227 /* off-board header */
227 &ecspi2 { 228 &ecspi2 {
228 pinctrl-names = "default"; 229 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_spi2>; 230 pinctrl-0 = <&pinctrl_spi2>;
230 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 231 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
231 status = "okay"; 232 status = "okay";
232 }; 233 };
233 234
234 &fec1 { 235 &fec1 {
235 pinctrl-names = "default"; 236 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_fec1>; 237 pinctrl-0 = <&pinctrl_fec1>;
237 phy-mode = "rgmii-id"; 238 phy-mode = "rgmii-id";
238 phy-handle = <ðphy0>; 239 phy-handle = <ðphy0>;
239 local-mac-address = [00 00 00 00 00 00 240 local-mac-address = [00 00 00 00 00 00];
240 status = "okay"; 241 status = "okay";
241 242
242 mdio { 243 mdio {
243 #address-cells = <1>; 244 #address-cells = <1>;
244 #size-cells = <0>; 245 #size-cells = <0>;
245 246
246 ethphy0: ethernet-phy@0 { 247 ethphy0: ethernet-phy@0 {
247 compatible = "ethernet 248 compatible = "ethernet-phy-ieee802.3-c22";
248 reg = <0>; 249 reg = <0>;
249 ti,rx-internal-delay = 250 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
250 ti,tx-internal-delay = 251 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
251 tx-fifo-depth = <DP838 252 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
252 rx-fifo-depth = <DP838 253 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
253 }; 254 };
254 }; 255 };
255 }; 256 };
256 257
257 &gpio1 { 258 &gpio1 {
258 gpio-line-names = "", "", "", "", "", 259 gpio-line-names = "", "", "", "", "", "", "", "",
259 "m2_pwr_en", "", "", "", "", " !! 260 "", "", "", "", "", "m2_reset", "", "m2_wdis#",
260 "", "", "", "", "", "", "", "" 261 "", "", "", "", "", "", "", "",
261 "", "", "", "", "", "", "", "" 262 "", "", "", "", "", "", "", "";
262 }; 263 };
263 264
264 &gpio2 { 265 &gpio2 {
265 gpio-line-names = "", "", "", "", "", 266 gpio-line-names = "", "", "", "", "", "", "", "",
266 "uart2_en#", "", "", "", "", " 267 "uart2_en#", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "" 268 "", "", "", "", "", "", "", "",
268 "", "", "", "", "", "", "", "" 269 "", "", "", "", "", "", "", "";
269 }; 270 };
270 271
271 &gpio3 { 272 &gpio3 {
272 gpio-line-names = "", "m2_gdis#", "", 273 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
273 "", "", "", "", "", "", "", "" 274 "", "", "", "", "", "", "", "",
274 "", "", "", "", "", "", "", "" 275 "", "", "", "", "", "", "", "",
275 "", "", "", "", "", "", "", "" 276 "", "", "", "", "", "", "", "";
276 }; 277 };
277 278
278 &gpio4 { 279 &gpio4 {
279 gpio-line-names = "", "", "", "", "", 280 gpio-line-names = "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "" 281 "", "", "", "", "", "", "", "",
281 "", "", "", "", "", "app_gpio1 !! 282 "", "", "", "", "", "app_gpio1", "", "uart1_rs485",
282 "", "uart1_term", "uart1_half" 283 "", "uart1_term", "uart1_half", "app_gpio2",
283 "mipi_gpio1", "", "", ""; 284 "mipi_gpio1", "", "", "";
284 }; 285 };
285 286
286 &gpio5 { 287 &gpio5 {
287 gpio-line-names = "", "", "", "mipi_gp 288 gpio-line-names = "", "", "", "mipi_gpio4",
288 "mipi_gpio3", "mipi_gpio2", "" 289 "mipi_gpio3", "mipi_gpio2", "", "",
289 "", "", "", "", "", "", "", "" 290 "", "", "", "", "", "", "", "",
290 "", "", "", "", "", "", "", "" 291 "", "", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "" 292 "", "", "", "", "", "", "", "";
292 }; 293 };
293 294
294 &gpu { 295 &gpu {
295 status = "disabled"; 296 status = "disabled";
296 }; 297 };
297 298
298 &i2c1 { 299 &i2c1 {
299 clock-frequency = <100000>; 300 clock-frequency = <100000>;
300 pinctrl-names = "default", "gpio"; !! 301 pinctrl-names = "default";
301 pinctrl-0 = <&pinctrl_i2c1>; 302 pinctrl-0 = <&pinctrl_i2c1>;
302 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
303 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI <<
304 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI <<
305 status = "okay"; 303 status = "okay";
306 304
307 gsc: gsc@20 { 305 gsc: gsc@20 {
308 compatible = "gw,gsc"; 306 compatible = "gw,gsc";
309 reg = <0x20>; 307 reg = <0x20>;
310 pinctrl-0 = <&pinctrl_gsc>; 308 pinctrl-0 = <&pinctrl_gsc>;
311 interrupt-parent = <&gpio2>; 309 interrupt-parent = <&gpio2>;
312 interrupts = <6 IRQ_TYPE_EDGE_ 310 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
313 interrupt-controller; 311 interrupt-controller;
314 #interrupt-cells = <1>; 312 #interrupt-cells = <1>;
315 #address-cells = <1>; <<
316 #size-cells = <0>; <<
317 313
318 adc { 314 adc {
319 compatible = "gw,gsc-a 315 compatible = "gw,gsc-adc";
320 #address-cells = <1>; 316 #address-cells = <1>;
321 #size-cells = <0>; 317 #size-cells = <0>;
322 318
323 channel@6 { 319 channel@6 {
324 gw,mode = <0>; 320 gw,mode = <0>;
325 reg = <0x06>; 321 reg = <0x06>;
326 label = "temp" 322 label = "temp";
327 }; 323 };
328 324
329 channel@8 { 325 channel@8 {
330 gw,mode = <3>; !! 326 gw,mode = <1>;
331 reg = <0x08>; 327 reg = <0x08>;
332 label = "vdd_b 328 label = "vdd_bat";
333 }; 329 };
334 330
335 channel@82 { 331 channel@82 {
336 gw,mode = <2>; 332 gw,mode = <2>;
337 reg = <0x82>; 333 reg = <0x82>;
338 label = "vin"; 334 label = "vin";
339 gw,voltage-div 335 gw,voltage-divider-ohms = <22100 1000>;
340 gw,voltage-off 336 gw,voltage-offset-microvolt = <700000>;
341 }; 337 };
342 338
343 channel@84 { 339 channel@84 {
344 gw,mode = <2>; 340 gw,mode = <2>;
345 reg = <0x84>; 341 reg = <0x84>;
346 label = "vin_4 342 label = "vin_4p0";
347 gw,voltage-div 343 gw,voltage-divider-ohms = <10000 10000>;
348 }; 344 };
349 345
350 channel@86 { 346 channel@86 {
351 gw,mode = <2>; 347 gw,mode = <2>;
352 reg = <0x86>; 348 reg = <0x86>;
353 label = "vdd_3 349 label = "vdd_3p3";
354 gw,voltage-div 350 gw,voltage-divider-ohms = <10000 10000>;
355 }; 351 };
356 352
357 channel@88 { 353 channel@88 {
358 gw,mode = <2>; 354 gw,mode = <2>;
359 reg = <0x88>; 355 reg = <0x88>;
360 label = "vdd_0 356 label = "vdd_0p9";
361 }; 357 };
362 358
363 channel@8c { 359 channel@8c {
364 gw,mode = <2>; 360 gw,mode = <2>;
365 reg = <0x8c>; 361 reg = <0x8c>;
366 label = "vdd_s 362 label = "vdd_soc";
367 }; 363 };
368 364
369 channel@8e { 365 channel@8e {
370 gw,mode = <2>; 366 gw,mode = <2>;
371 reg = <0x8e>; 367 reg = <0x8e>;
372 label = "vdd_a 368 label = "vdd_arm";
373 }; 369 };
374 370
375 channel@90 { 371 channel@90 {
376 gw,mode = <2>; 372 gw,mode = <2>;
377 reg = <0x90>; 373 reg = <0x90>;
378 label = "vdd_1 374 label = "vdd_1p8";
379 }; 375 };
380 376
381 channel@92 { 377 channel@92 {
382 gw,mode = <2>; 378 gw,mode = <2>;
383 reg = <0x92>; 379 reg = <0x92>;
384 label = "vdd_d 380 label = "vdd_dram";
385 }; 381 };
386 382
387 channel@98 { 383 channel@98 {
388 gw,mode = <2>; 384 gw,mode = <2>;
389 reg = <0x98>; 385 reg = <0x98>;
390 label = "vdd_1 386 label = "vdd_1p0";
391 }; 387 };
392 388
393 channel@9a { 389 channel@9a {
394 gw,mode = <2>; 390 gw,mode = <2>;
395 reg = <0x9a>; 391 reg = <0x9a>;
396 label = "vdd_2 392 label = "vdd_2p5";
397 gw,voltage-div 393 gw,voltage-divider-ohms = <10000 10000>;
398 }; 394 };
399 395
400 channel@9c { <<
401 gw,mode = <2>; <<
402 reg = <0x9c>; <<
403 label = "vdd_5 <<
404 gw,voltage-div <<
405 }; <<
406 <<
407 channel@a2 { 396 channel@a2 {
408 gw,mode = <2>; 397 gw,mode = <2>;
409 reg = <0xa2>; 398 reg = <0xa2>;
410 label = "vdd_g 399 label = "vdd_gsc";
411 gw,voltage-div 400 gw,voltage-divider-ohms = <10000 10000>;
412 }; 401 };
413 }; 402 };
414 }; 403 };
415 404
416 gpio: gpio@23 { 405 gpio: gpio@23 {
417 compatible = "nxp,pca9555"; 406 compatible = "nxp,pca9555";
418 reg = <0x23>; 407 reg = <0x23>;
419 gpio-controller; 408 gpio-controller;
420 #gpio-cells = <2>; 409 #gpio-cells = <2>;
421 interrupt-parent = <&gsc>; 410 interrupt-parent = <&gsc>;
422 interrupts = <4>; 411 interrupts = <4>;
423 }; 412 };
424 413
425 pmic@4b { 414 pmic@4b {
426 compatible = "rohm,bd71847"; 415 compatible = "rohm,bd71847";
427 reg = <0x4b>; 416 reg = <0x4b>;
428 pinctrl-names = "default"; 417 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_pmic>; 418 pinctrl-0 = <&pinctrl_pmic>;
430 interrupt-parent = <&gpio3>; 419 interrupt-parent = <&gpio3>;
431 interrupts = <8 IRQ_TYPE_LEVEL 420 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
432 rohm,reset-snvs-powered; 421 rohm,reset-snvs-powered;
433 #clock-cells = <0>; 422 #clock-cells = <0>;
434 clocks = <&osc_32k>; !! 423 clocks = <&osc_32k 0>;
435 clock-output-names = "clk-32k- 424 clock-output-names = "clk-32k-out";
436 425
437 regulators { 426 regulators {
438 /* vdd_soc: 0.805-0.90 427 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
439 BUCK1 { 428 BUCK1 {
440 regulator-name 429 regulator-name = "buck1";
441 regulator-min- 430 regulator-min-microvolt = <700000>;
442 regulator-max- 431 regulator-max-microvolt = <1300000>;
443 regulator-boot 432 regulator-boot-on;
444 regulator-alwa 433 regulator-always-on;
445 regulator-ramp 434 regulator-ramp-delay = <1250>;
446 }; 435 };
447 436
448 /* vdd_arm: 0.805-1.0V 437 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
449 buck2: BUCK2 { 438 buck2: BUCK2 {
450 regulator-name 439 regulator-name = "buck2";
451 regulator-min- 440 regulator-min-microvolt = <700000>;
452 regulator-max- 441 regulator-max-microvolt = <1300000>;
453 regulator-boot 442 regulator-boot-on;
454 regulator-alwa 443 regulator-always-on;
455 regulator-ramp 444 regulator-ramp-delay = <1250>;
456 rohm,dvs-run-v 445 rohm,dvs-run-voltage = <1000000>;
457 rohm,dvs-idle- 446 rohm,dvs-idle-voltage = <900000>;
458 }; 447 };
459 448
460 /* vdd_0p9: 0.805-1.0V 449 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
461 BUCK3 { 450 BUCK3 {
462 regulator-name 451 regulator-name = "buck3";
463 regulator-min- 452 regulator-min-microvolt = <700000>;
464 regulator-max- 453 regulator-max-microvolt = <1350000>;
465 regulator-boot 454 regulator-boot-on;
466 regulator-alwa 455 regulator-always-on;
467 }; 456 };
468 457
469 /* vdd_3p3 */ 458 /* vdd_3p3 */
470 BUCK4 { 459 BUCK4 {
471 regulator-name 460 regulator-name = "buck4";
472 regulator-min- 461 regulator-min-microvolt = <3000000>;
473 regulator-max- 462 regulator-max-microvolt = <3300000>;
474 regulator-boot 463 regulator-boot-on;
475 regulator-alwa 464 regulator-always-on;
476 }; 465 };
477 466
478 /* vdd_1p8 */ 467 /* vdd_1p8 */
479 BUCK5 { 468 BUCK5 {
480 regulator-name 469 regulator-name = "buck5";
481 regulator-min- 470 regulator-min-microvolt = <1605000>;
482 regulator-max- 471 regulator-max-microvolt = <1995000>;
483 regulator-boot 472 regulator-boot-on;
484 regulator-alwa 473 regulator-always-on;
485 }; 474 };
486 475
487 /* vdd_dram */ 476 /* vdd_dram */
488 BUCK6 { 477 BUCK6 {
489 regulator-name 478 regulator-name = "buck6";
490 regulator-min- 479 regulator-min-microvolt = <800000>;
491 regulator-max- 480 regulator-max-microvolt = <1400000>;
492 regulator-boot 481 regulator-boot-on;
493 regulator-alwa 482 regulator-always-on;
494 }; 483 };
495 484
496 /* nvcc_snvs_1p8 */ 485 /* nvcc_snvs_1p8 */
497 LDO1 { 486 LDO1 {
498 regulator-name 487 regulator-name = "ldo1";
499 regulator-min- 488 regulator-min-microvolt = <1600000>;
500 regulator-max- 489 regulator-max-microvolt = <1900000>;
501 regulator-boot 490 regulator-boot-on;
502 regulator-alwa 491 regulator-always-on;
503 }; 492 };
504 493
505 /* vdd_snvs_0p8 */ 494 /* vdd_snvs_0p8 */
506 LDO2 { 495 LDO2 {
507 regulator-name 496 regulator-name = "ldo2";
508 regulator-min- 497 regulator-min-microvolt = <800000>;
509 regulator-max- 498 regulator-max-microvolt = <900000>;
510 regulator-boot 499 regulator-boot-on;
511 regulator-alwa 500 regulator-always-on;
512 }; 501 };
513 502
514 /* vdda_1p8 */ 503 /* vdda_1p8 */
515 LDO3 { 504 LDO3 {
516 regulator-name 505 regulator-name = "ldo3";
517 regulator-min- 506 regulator-min-microvolt = <1800000>;
518 regulator-max- 507 regulator-max-microvolt = <3300000>;
519 regulator-boot 508 regulator-boot-on;
520 regulator-alwa 509 regulator-always-on;
521 }; 510 };
522 511
523 LDO4 { 512 LDO4 {
524 regulator-name 513 regulator-name = "ldo4";
525 regulator-min- 514 regulator-min-microvolt = <900000>;
526 regulator-max- 515 regulator-max-microvolt = <1800000>;
527 regulator-boot 516 regulator-boot-on;
528 regulator-alwa 517 regulator-always-on;
529 }; 518 };
530 519
531 LDO6 { 520 LDO6 {
532 regulator-name 521 regulator-name = "ldo6";
533 regulator-min- 522 regulator-min-microvolt = <900000>;
534 regulator-max- 523 regulator-max-microvolt = <1800000>;
535 regulator-boot 524 regulator-boot-on;
536 regulator-alwa 525 regulator-always-on;
537 }; 526 };
538 }; 527 };
539 }; 528 };
540 529
541 eeprom@50 { 530 eeprom@50 {
542 compatible = "atmel,24c02"; 531 compatible = "atmel,24c02";
543 reg = <0x50>; 532 reg = <0x50>;
544 pagesize = <16>; 533 pagesize = <16>;
545 }; 534 };
546 535
547 eeprom@51 { 536 eeprom@51 {
548 compatible = "atmel,24c02"; 537 compatible = "atmel,24c02";
549 reg = <0x51>; 538 reg = <0x51>;
550 pagesize = <16>; 539 pagesize = <16>;
551 }; 540 };
552 541
553 eeprom@52 { 542 eeprom@52 {
554 compatible = "atmel,24c02"; 543 compatible = "atmel,24c02";
555 reg = <0x52>; 544 reg = <0x52>;
556 pagesize = <16>; 545 pagesize = <16>;
557 }; 546 };
558 547
559 eeprom@53 { 548 eeprom@53 {
560 compatible = "atmel,24c02"; 549 compatible = "atmel,24c02";
561 reg = <0x53>; 550 reg = <0x53>;
562 pagesize = <16>; 551 pagesize = <16>;
563 }; 552 };
564 553
565 rtc@68 { 554 rtc@68 {
566 compatible = "dallas,ds1672"; 555 compatible = "dallas,ds1672";
567 reg = <0x68>; 556 reg = <0x68>;
568 }; 557 };
569 }; 558 };
570 559
571 &i2c2 { 560 &i2c2 {
572 clock-frequency = <400000>; 561 clock-frequency = <400000>;
573 pinctrl-names = "default", "gpio"; !! 562 pinctrl-names = "default";
574 pinctrl-0 = <&pinctrl_i2c2>; 563 pinctrl-0 = <&pinctrl_i2c2>;
575 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
576 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
577 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
578 status = "okay"; 564 status = "okay";
579 565
580 accelerometer@19 { 566 accelerometer@19 {
581 compatible = "st,lis2de12"; 567 compatible = "st,lis2de12";
582 pinctrl-names = "default"; 568 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_accel>; 569 pinctrl-0 = <&pinctrl_accel>;
584 reg = <0x19>; 570 reg = <0x19>;
585 st,drdy-int-pin = <1>; 571 st,drdy-int-pin = <1>;
586 interrupt-parent = <&gpio1>; 572 interrupt-parent = <&gpio1>;
587 interrupts = <12 IRQ_TYPE_LEVE 573 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
>> 574 interrupt-names = "INT1";
588 }; 575 };
589 }; 576 };
590 577
591 /* off-board header */ 578 /* off-board header */
592 &i2c3 { 579 &i2c3 {
593 clock-frequency = <400000>; 580 clock-frequency = <400000>;
594 pinctrl-names = "default", "gpio"; !! 581 pinctrl-names = "default";
595 pinctrl-0 = <&pinctrl_i2c3>; 582 pinctrl-0 = <&pinctrl_i2c3>;
596 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
597 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI <<
598 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI <<
599 status = "okay"; 583 status = "okay";
600 }; 584 };
601 585
602 /* off-board header */ 586 /* off-board header */
603 &i2c4 { 587 &i2c4 {
604 clock-frequency = <400000>; 588 clock-frequency = <400000>;
605 pinctrl-names = "default", "gpio"; !! 589 pinctrl-names = "default";
606 pinctrl-0 = <&pinctrl_i2c4>; 590 pinctrl-0 = <&pinctrl_i2c4>;
607 pinctrl-1 = <&pinctrl_i2c4_gpio>; <<
608 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI <<
609 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI <<
610 status = "okay"; 591 status = "okay";
611 }; 592 };
612 593
613 &pgc_gpumix { 594 &pgc_gpumix {
614 status = "disabled"; 595 status = "disabled";
615 }; 596 };
616 597
617 /* off-board header */ 598 /* off-board header */
618 &sai3 { 599 &sai3 {
619 pinctrl-names = "default"; 600 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_sai3>; 601 pinctrl-0 = <&pinctrl_sai3>;
621 assigned-clocks = <&clk IMX8MN_CLK_SAI 602 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
622 assigned-clock-parents = <&clk IMX8MN_ 603 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
623 assigned-clock-rates = <24576000>; 604 assigned-clock-rates = <24576000>;
624 status = "okay"; 605 status = "okay";
625 }; 606 };
626 607
627 /* RS232/RS485/RS422 selectable */ 608 /* RS232/RS485/RS422 selectable */
628 &uart1 { 609 &uart1 {
629 pinctrl-names = "default"; 610 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 611 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
631 status = "okay"; 612 status = "okay";
632 }; 613 };
633 614
634 /* RS232 console */ 615 /* RS232 console */
635 &uart2 { 616 &uart2 {
636 pinctrl-names = "default"; 617 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_uart2>; 618 pinctrl-0 = <&pinctrl_uart2>;
638 status = "okay"; 619 status = "okay";
639 }; 620 };
640 621
641 /* bluetooth HCI */ 622 /* bluetooth HCI */
642 &uart3 { 623 &uart3 {
643 pinctrl-names = "default"; 624 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 625 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
645 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 626 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
646 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 627 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
647 status = "okay"; 628 status = "okay";
648 629
649 bluetooth { 630 bluetooth {
650 compatible = "brcm,bcm4330-bt" 631 compatible = "brcm,bcm4330-bt";
651 shutdown-gpios = <&gpio2 12 GP 632 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
652 }; 633 };
653 }; 634 };
654 635
655 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 636 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
656 &uart4 { 637 &uart4 {
657 pinctrl-names = "default"; 638 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart4>; 639 pinctrl-0 = <&pinctrl_uart4>;
659 status = "okay"; 640 status = "okay";
660 }; 641 };
661 642
662 &usbotg1 { 643 &usbotg1 {
663 dr_mode = "host"; 644 dr_mode = "host";
664 vbus-supply = <®_usb1_vbus>; 645 vbus-supply = <®_usb1_vbus>;
665 disable-over-current; 646 disable-over-current;
666 status = "okay"; 647 status = "okay";
667 }; 648 };
668 649
669 /* SDIO WiFi */ 650 /* SDIO WiFi */
670 &usdhc2 { 651 &usdhc2 {
671 pinctrl-names = "default", "state_100m !! 652 pinctrl-names = "default";
672 pinctrl-0 = <&pinctrl_usdhc2>; 653 pinctrl-0 = <&pinctrl_usdhc2>;
673 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; <<
674 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; <<
675 bus-width = <4>; 654 bus-width = <4>;
676 non-removable; 655 non-removable;
677 vmmc-supply = <®_wifi>; 656 vmmc-supply = <®_wifi>;
678 #address-cells = <1>; <<
679 #size-cells = <0>; <<
680 status = "okay"; 657 status = "okay";
681 <<
682 wifi@0 { <<
683 compatible = "brcm,bcm43455-fm <<
684 reg = <0>; <<
685 }; <<
686 }; 658 };
687 659
688 /* eMMC */ 660 /* eMMC */
689 &usdhc3 { 661 &usdhc3 {
690 pinctrl-names = "default", "state_100m 662 pinctrl-names = "default", "state_100mhz", "state_200mhz";
691 pinctrl-0 = <&pinctrl_usdhc3>; 663 pinctrl-0 = <&pinctrl_usdhc3>;
692 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 664 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
693 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 665 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
694 bus-width = <8>; 666 bus-width = <8>;
695 non-removable; 667 non-removable;
696 status = "okay"; 668 status = "okay";
697 }; 669 };
698 670
699 &wdog1 { 671 &wdog1 {
700 pinctrl-names = "default"; 672 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_wdog>; 673 pinctrl-0 = <&pinctrl_wdog>;
702 fsl,ext-reset-output; 674 fsl,ext-reset-output;
703 status = "okay"; 675 status = "okay";
704 }; 676 };
705 677
706 &iomuxc { 678 &iomuxc {
707 pinctrl-names = "default"; 679 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_hog>; 680 pinctrl-0 = <&pinctrl_hog>;
709 681
710 pinctrl_hog: hoggrp { 682 pinctrl_hog: hoggrp {
711 fsl,pins = < 683 fsl,pins = <
712 MX8MN_IOMUXC_NAND_CE0_ 684 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
713 MX8MN_IOMUXC_GPIO1_IO0 <<
714 MX8MN_IOMUXC_GPIO1_IO1 685 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
715 MX8MN_IOMUXC_NAND_DATA 686 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
716 MX8MN_IOMUXC_GPIO1_IO1 687 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
717 MX8MN_IOMUXC_SAI2_RXFS 688 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
718 MX8MN_IOMUXC_SAI2_RXC_ <<
719 MX8MN_IOMUXC_SAI2_MCLK 689 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
720 MX8MN_IOMUXC_SD1_DATA6 690 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
721 MX8MN_IOMUXC_SAI3_RXFS 691 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
722 MX8MN_IOMUXC_SPDIF_EXT 692 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
723 MX8MN_IOMUXC_SPDIF_RX_ 693 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
724 MX8MN_IOMUXC_SPDIF_TX_ 694 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
725 >; 695 >;
726 }; 696 };
727 697
728 pinctrl_accel: accelgrp { 698 pinctrl_accel: accelgrp {
729 fsl,pins = < 699 fsl,pins = <
730 MX8MN_IOMUXC_GPIO1_IO1 700 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
731 >; 701 >;
732 }; 702 };
733 703
734 pinctrl_fec1: fec1grp { 704 pinctrl_fec1: fec1grp {
735 fsl,pins = < 705 fsl,pins = <
736 MX8MN_IOMUXC_ENET_MDC_ 706 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
737 MX8MN_IOMUXC_ENET_MDIO 707 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
738 MX8MN_IOMUXC_ENET_TD3_ 708 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
739 MX8MN_IOMUXC_ENET_TD2_ 709 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
740 MX8MN_IOMUXC_ENET_TD1_ 710 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
741 MX8MN_IOMUXC_ENET_TD0_ 711 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
742 MX8MN_IOMUXC_ENET_RD3_ 712 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
743 MX8MN_IOMUXC_ENET_RD2_ 713 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
744 MX8MN_IOMUXC_ENET_RD1_ 714 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
745 MX8MN_IOMUXC_ENET_RD0_ 715 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
746 MX8MN_IOMUXC_ENET_TXC_ 716 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
747 MX8MN_IOMUXC_ENET_RXC_ 717 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
748 MX8MN_IOMUXC_ENET_RX_C 718 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
749 MX8MN_IOMUXC_ENET_TX_C 719 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
750 MX8MN_IOMUXC_GPIO1_IO1 720 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
751 MX8MN_IOMUXC_GPIO1_IO1 721 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
>> 722 MX8MN_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN 0x141
>> 723 MX8MN_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT 0x141
752 >; 724 >;
753 }; 725 };
754 726
755 pinctrl_gsc: gscgrp { 727 pinctrl_gsc: gscgrp {
756 fsl,pins = < 728 fsl,pins = <
757 MX8MN_IOMUXC_SD1_DATA4 729 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
758 >; 730 >;
759 }; 731 };
760 732
761 pinctrl_i2c1: i2c1grp { 733 pinctrl_i2c1: i2c1grp {
762 fsl,pins = < 734 fsl,pins = <
763 MX8MN_IOMUXC_I2C1_SCL_ 735 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
764 MX8MN_IOMUXC_I2C1_SDA_ 736 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
765 >; 737 >;
766 }; 738 };
767 739
768 pinctrl_i2c1_gpio: i2c1gpiogrp { <<
769 fsl,pins = < <<
770 MX8MN_IOMUXC_I2C1_SCL_ <<
771 MX8MN_IOMUXC_I2C1_SDA_ <<
772 >; <<
773 }; <<
774 <<
775 pinctrl_i2c2: i2c2grp { 740 pinctrl_i2c2: i2c2grp {
776 fsl,pins = < 741 fsl,pins = <
777 MX8MN_IOMUXC_I2C2_SCL_ 742 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
778 MX8MN_IOMUXC_I2C2_SDA_ 743 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
779 >; 744 >;
780 }; 745 };
781 746
782 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
783 fsl,pins = < <<
784 MX8MN_IOMUXC_I2C2_SCL_ <<
785 MX8MN_IOMUXC_I2C2_SDA_ <<
786 >; <<
787 }; <<
788 <<
789 pinctrl_i2c3: i2c3grp { 747 pinctrl_i2c3: i2c3grp {
790 fsl,pins = < 748 fsl,pins = <
791 MX8MN_IOMUXC_I2C3_SCL_ 749 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
792 MX8MN_IOMUXC_I2C3_SDA_ 750 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
793 >; 751 >;
794 }; 752 };
795 753
796 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
797 fsl,pins = < <<
798 MX8MN_IOMUXC_I2C3_SCL_ <<
799 MX8MN_IOMUXC_I2C3_SDA_ <<
800 >; <<
801 }; <<
802 <<
803 pinctrl_i2c4: i2c4grp { 754 pinctrl_i2c4: i2c4grp {
804 fsl,pins = < 755 fsl,pins = <
805 MX8MN_IOMUXC_I2C4_SCL_ 756 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
806 MX8MN_IOMUXC_I2C4_SDA_ 757 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
807 >; 758 >;
808 }; 759 };
809 760
810 pinctrl_i2c4_gpio: i2c4gpiogrp { <<
811 fsl,pins = < <<
812 MX8MN_IOMUXC_I2C4_SCL_ <<
813 MX8MN_IOMUXC_I2C4_SDA_ <<
814 >; <<
815 }; <<
816 <<
817 pinctrl_gpio_leds: gpioledgrp { 761 pinctrl_gpio_leds: gpioledgrp {
818 fsl,pins = < 762 fsl,pins = <
819 MX8MN_IOMUXC_SAI5_RXD0 763 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
820 MX8MN_IOMUXC_SAI5_RXD2 764 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
821 MX8MN_IOMUXC_SAI5_RXD1 765 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
822 MX8MN_IOMUXC_SAI5_RXC_ 766 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
823 MX8MN_IOMUXC_SAI5_MCLK 767 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
824 >; 768 >;
825 }; 769 };
826 770
827 pinctrl_pmic: pmicgrp { 771 pinctrl_pmic: pmicgrp {
828 fsl,pins = < 772 fsl,pins = <
829 MX8MN_IOMUXC_NAND_DATA 773 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
830 >; 774 >;
831 }; 775 };
832 776
833 pinctrl_pps: ppsgrp { 777 pinctrl_pps: ppsgrp {
834 fsl,pins = < 778 fsl,pins = <
835 MX8MN_IOMUXC_SAI5_RXD3 779 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
836 >; 780 >;
837 }; 781 };
838 782
839 pinctrl_reg_wl: regwlgrp { 783 pinctrl_reg_wl: regwlgrp {
840 fsl,pins = < 784 fsl,pins = <
841 MX8MN_IOMUXC_SD2_RESET 785 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
842 >; 786 >;
843 }; 787 };
844 788
845 pinctrl_reg_usb1: regusb1grp { 789 pinctrl_reg_usb1: regusb1grp {
846 fsl,pins = < 790 fsl,pins = <
847 MX8MN_IOMUXC_SD1_DATA5 791 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
848 >; 792 >;
849 }; 793 };
850 794
851 pinctrl_sai3: sai3grp { 795 pinctrl_sai3: sai3grp {
852 fsl,pins = < 796 fsl,pins = <
853 MX8MN_IOMUXC_SAI3_MCLK 797 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
854 MX8MN_IOMUXC_SAI3_RXD_ 798 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
855 MX8MN_IOMUXC_SAI3_TXC_ 799 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
856 MX8MN_IOMUXC_SAI3_TXD_ 800 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
857 MX8MN_IOMUXC_SAI3_TXFS 801 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
858 >; 802 >;
859 }; 803 };
860 804
861 pinctrl_spi1: spi1grp { 805 pinctrl_spi1: spi1grp {
862 fsl,pins = < 806 fsl,pins = <
863 MX8MN_IOMUXC_ECSPI1_SC 807 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
864 MX8MN_IOMUXC_ECSPI1_MO 808 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
865 MX8MN_IOMUXC_ECSPI1_MI 809 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
866 MX8MN_IOMUXC_ECSPI1_SS 810 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
867 MX8MN_IOMUXC_SD1_DATA1 811 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
868 >; 812 >;
869 }; 813 };
870 814
871 pinctrl_spi2: spi2grp { 815 pinctrl_spi2: spi2grp {
872 fsl,pins = < 816 fsl,pins = <
873 MX8MN_IOMUXC_ECSPI2_SC 817 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
874 MX8MN_IOMUXC_ECSPI2_MO 818 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
875 MX8MN_IOMUXC_ECSPI2_MI 819 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
876 MX8MN_IOMUXC_ECSPI2_SS 820 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
877 >; 821 >;
878 }; 822 };
879 823
880 pinctrl_uart1: uart1grp { 824 pinctrl_uart1: uart1grp {
881 fsl,pins = < 825 fsl,pins = <
882 MX8MN_IOMUXC_UART1_RXD 826 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
883 MX8MN_IOMUXC_UART1_TXD 827 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
884 >; 828 >;
885 }; 829 };
886 830
887 pinctrl_uart1_gpio: uart1gpiogrp { 831 pinctrl_uart1_gpio: uart1gpiogrp {
888 fsl,pins = < 832 fsl,pins = <
889 MX8MN_IOMUXC_SAI2_TXD0 833 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
890 MX8MN_IOMUXC_SAI2_TXC_ 834 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
891 MX8MN_IOMUXC_SAI2_RXD0 835 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
892 >; 836 >;
893 }; 837 };
894 838
895 pinctrl_uart2: uart2grp { 839 pinctrl_uart2: uart2grp {
896 fsl,pins = < 840 fsl,pins = <
897 MX8MN_IOMUXC_UART2_RXD 841 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
898 MX8MN_IOMUXC_UART2_TXD 842 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
899 >; 843 >;
900 }; 844 };
901 845
902 pinctrl_uart3_gpio: uart3_gpiogrp { 846 pinctrl_uart3_gpio: uart3_gpiogrp {
903 fsl,pins = < 847 fsl,pins = <
904 MX8MN_IOMUXC_SD2_CD_B_ 848 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
905 >; 849 >;
906 }; 850 };
907 851
908 pinctrl_uart3: uart3grp { 852 pinctrl_uart3: uart3grp {
909 fsl,pins = < 853 fsl,pins = <
910 MX8MN_IOMUXC_UART3_RXD 854 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
911 MX8MN_IOMUXC_UART3_TXD 855 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
912 MX8MN_IOMUXC_SD1_CLK_G 856 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
913 MX8MN_IOMUXC_SD1_CMD_G 857 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
914 >; 858 >;
915 }; 859 };
916 860
917 pinctrl_uart4: uart4grp { 861 pinctrl_uart4: uart4grp {
918 fsl,pins = < 862 fsl,pins = <
919 MX8MN_IOMUXC_UART4_RXD 863 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
920 MX8MN_IOMUXC_UART4_TXD 864 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
921 MX8MN_IOMUXC_GPIO1_IO0 865 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
922 >; 866 >;
923 }; 867 };
924 868
925 pinctrl_usdhc2: usdhc2grp { 869 pinctrl_usdhc2: usdhc2grp {
926 fsl,pins = < 870 fsl,pins = <
927 MX8MN_IOMUXC_SD2_CLK_U 871 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
928 MX8MN_IOMUXC_SD2_CMD_U 872 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
929 MX8MN_IOMUXC_SD2_DATA0 873 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
930 MX8MN_IOMUXC_SD2_DATA1 874 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
931 MX8MN_IOMUXC_SD2_DATA2 875 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
932 MX8MN_IOMUXC_SD2_DATA3 876 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
933 >; <<
934 }; <<
935 <<
936 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr <<
937 fsl,pins = < <<
938 MX8MN_IOMUXC_SD2_CLK_U <<
939 MX8MN_IOMUXC_SD2_CMD_U <<
940 MX8MN_IOMUXC_SD2_DATA0 <<
941 MX8MN_IOMUXC_SD2_DATA1 <<
942 MX8MN_IOMUXC_SD2_DATA2 <<
943 MX8MN_IOMUXC_SD2_DATA3 <<
944 >; <<
945 }; <<
946 <<
947 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr <<
948 fsl,pins = < <<
949 MX8MN_IOMUXC_SD2_CLK_U <<
950 MX8MN_IOMUXC_SD2_CMD_U <<
951 MX8MN_IOMUXC_SD2_DATA0 <<
952 MX8MN_IOMUXC_SD2_DATA1 <<
953 MX8MN_IOMUXC_SD2_DATA2 <<
954 MX8MN_IOMUXC_SD2_DATA3 <<
955 >; 877 >;
956 }; 878 };
957 879
958 pinctrl_usdhc3: usdhc3grp { 880 pinctrl_usdhc3: usdhc3grp {
959 fsl,pins = < 881 fsl,pins = <
960 MX8MN_IOMUXC_NAND_WE_B 882 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
961 MX8MN_IOMUXC_NAND_WP_B 883 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
962 MX8MN_IOMUXC_NAND_DATA 884 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
963 MX8MN_IOMUXC_NAND_DATA 885 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
964 MX8MN_IOMUXC_NAND_DATA 886 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
965 MX8MN_IOMUXC_NAND_DATA 887 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
966 MX8MN_IOMUXC_NAND_RE_B 888 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
967 MX8MN_IOMUXC_NAND_CE2_ 889 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
968 MX8MN_IOMUXC_NAND_CE3_ 890 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
969 MX8MN_IOMUXC_NAND_CLE_ 891 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
970 MX8MN_IOMUXC_NAND_CE1_ 892 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
971 >; 893 >;
972 }; 894 };
973 895
974 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 896 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
975 fsl,pins = < 897 fsl,pins = <
976 MX8MN_IOMUXC_NAND_WE_B 898 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
977 MX8MN_IOMUXC_NAND_WP_B 899 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
978 MX8MN_IOMUXC_NAND_DATA 900 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
979 MX8MN_IOMUXC_NAND_DATA 901 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
980 MX8MN_IOMUXC_NAND_DATA 902 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
981 MX8MN_IOMUXC_NAND_DATA 903 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
982 MX8MN_IOMUXC_NAND_RE_B 904 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
983 MX8MN_IOMUXC_NAND_CE2_ 905 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
984 MX8MN_IOMUXC_NAND_CE3_ 906 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
985 MX8MN_IOMUXC_NAND_CLE_ 907 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
986 MX8MN_IOMUXC_NAND_CE1_ 908 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
987 >; 909 >;
988 }; 910 };
989 911
990 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 912 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
991 fsl,pins = < 913 fsl,pins = <
992 MX8MN_IOMUXC_NAND_WE_B 914 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
993 MX8MN_IOMUXC_NAND_WP_B 915 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
994 MX8MN_IOMUXC_NAND_DATA 916 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
995 MX8MN_IOMUXC_NAND_DATA 917 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
996 MX8MN_IOMUXC_NAND_DATA 918 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
997 MX8MN_IOMUXC_NAND_DATA 919 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
998 MX8MN_IOMUXC_NAND_RE_B 920 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
999 MX8MN_IOMUXC_NAND_CE2_ 921 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1000 MX8MN_IOMUXC_NAND_CE3 922 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1001 MX8MN_IOMUXC_NAND_CLE 923 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1002 MX8MN_IOMUXC_NAND_CE1 924 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1003 >; 925 >;
1004 }; 926 };
1005 927
1006 pinctrl_wdog: wdoggrp { 928 pinctrl_wdog: wdoggrp {
1007 fsl,pins = < 929 fsl,pins = <
1008 MX8MN_IOMUXC_GPIO1_IO 930 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1009 >; 931 >;
1010 }; 932 };
1011 }; 933 };
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