1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 12
13 #include "imx8mn.dtsi" 13 #include "imx8mn.dtsi"
14 14
15 / { 15 / {
16 model = "Gateworks Venice GW7902 i.MX8 16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl, 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18 18
19 aliases { 19 aliases {
20 usb0 = &usbotg1; 20 usb0 = &usbotg1;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 stdout-path = &uart2; 24 stdout-path = &uart2;
25 }; 25 };
26 26
27 memory@40000000 { 27 memory@40000000 {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x8000 29 reg = <0x0 0x40000000 0 0x80000000>;
30 }; 30 };
31 31
32 can20m: can20m { 32 can20m: can20m {
33 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 clock-frequency = <20000000>; 35 clock-frequency = <20000000>;
36 clock-output-names = "can20m"; 36 clock-output-names = "can20m";
37 }; 37 };
38 38
39 gpio-keys { 39 gpio-keys {
40 compatible = "gpio-keys"; 40 compatible = "gpio-keys";
41 41
42 key-user-pb { 42 key-user-pb {
43 label = "user_pb"; 43 label = "user_pb";
44 gpios = <&gpio 2 GPIO_ 44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 linux,code = <BTN_0>; 45 linux,code = <BTN_0>;
46 }; 46 };
47 47
48 key-user-pb1x { 48 key-user-pb1x {
49 label = "user_pb1x"; 49 label = "user_pb1x";
50 linux,code = <BTN_1>; 50 linux,code = <BTN_1>;
51 interrupt-parent = <&g 51 interrupt-parent = <&gsc>;
52 interrupts = <0>; 52 interrupts = <0>;
53 }; 53 };
54 54
55 key-erased { 55 key-erased {
56 label = "key_erased"; 56 label = "key_erased";
57 linux,code = <BTN_2>; 57 linux,code = <BTN_2>;
58 interrupt-parent = <&g 58 interrupt-parent = <&gsc>;
59 interrupts = <1>; 59 interrupts = <1>;
60 }; 60 };
61 61
62 key-eeprom-wp { 62 key-eeprom-wp {
63 label = "eeprom_wp"; 63 label = "eeprom_wp";
64 linux,code = <BTN_3>; 64 linux,code = <BTN_3>;
65 interrupt-parent = <&g 65 interrupt-parent = <&gsc>;
66 interrupts = <2>; 66 interrupts = <2>;
67 }; 67 };
68 68
69 key-tamper { 69 key-tamper {
70 label = "tamper"; 70 label = "tamper";
71 linux,code = <BTN_4>; 71 linux,code = <BTN_4>;
72 interrupt-parent = <&g 72 interrupt-parent = <&gsc>;
73 interrupts = <5>; 73 interrupts = <5>;
74 }; 74 };
75 75
76 switch-hold { 76 switch-hold {
77 label = "switch_hold"; 77 label = "switch_hold";
78 linux,code = <BTN_5>; 78 linux,code = <BTN_5>;
79 interrupt-parent = <&g 79 interrupt-parent = <&gsc>;
80 interrupts = <7>; 80 interrupts = <7>;
81 }; 81 };
82 }; 82 };
83 83
84 led-controller { 84 led-controller {
85 compatible = "gpio-leds"; 85 compatible = "gpio-leds";
86 pinctrl-names = "default"; 86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_led 87 pinctrl-0 = <&pinctrl_gpio_leds>;
88 88
89 led-0 { 89 led-0 {
90 function = LED_FUNCTIO 90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_ 91 color = <LED_COLOR_ID_GREEN>;
92 label = "panel1"; 92 label = "panel1";
93 gpios = <&gpio3 21 GPI 93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off"; 94 default-state = "off";
95 }; 95 };
96 96
97 led-1 { 97 led-1 {
98 function = LED_FUNCTIO 98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_ 99 color = <LED_COLOR_ID_GREEN>;
100 label = "panel2"; 100 label = "panel2";
101 gpios = <&gpio3 23 GPI 101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off"; 102 default-state = "off";
103 }; 103 };
104 104
105 led-2 { 105 led-2 {
106 function = LED_FUNCTIO 106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_ 107 color = <LED_COLOR_ID_GREEN>;
108 label = "panel3"; 108 label = "panel3";
109 gpios = <&gpio3 22 GPI 109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off"; 110 default-state = "off";
111 }; 111 };
112 112
113 led-3 { 113 led-3 {
114 function = LED_FUNCTIO 114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_ 115 color = <LED_COLOR_ID_GREEN>;
116 label = "panel4"; 116 label = "panel4";
117 gpios = <&gpio3 20 GPI 117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off"; 118 default-state = "off";
119 }; 119 };
120 120
121 led-4 { 121 led-4 {
122 function = LED_FUNCTIO 122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_ 123 color = <LED_COLOR_ID_GREEN>;
124 label = "panel5"; 124 label = "panel5";
125 gpios = <&gpio3 25 GPI 125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off"; 126 default-state = "off";
127 }; 127 };
128 }; 128 };
129 129
130 pps { 130 pps {
131 compatible = "pps-gpio"; 131 compatible = "pps-gpio";
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>; 133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE 134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135 status = "okay"; 135 status = "okay";
136 }; 136 };
137 137
138 reg_3p3v: regulator-3p3v { 138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed" 139 compatible = "regulator-fixed";
140 regulator-name = "3P3V"; 140 regulator-name = "3P3V";
141 regulator-min-microvolt = <330 141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <330 142 regulator-max-microvolt = <3300000>;
143 regulator-always-on; 143 regulator-always-on;
144 }; 144 };
145 145
146 reg_usb1_vbus: regulator-usb1 { 146 reg_usb1_vbus: regulator-usb1 {
147 compatible = "regulator-fixed" 147 compatible = "regulator-fixed";
148 pinctrl-names = "default"; 148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_reg_usb1 149 pinctrl-0 = <&pinctrl_reg_usb1>;
150 regulator-name = "usb_usb1_vbu 150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_H 151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152 enable-active-high; 152 enable-active-high;
153 regulator-min-microvolt = <500 153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <500 154 regulator-max-microvolt = <5000000>;
155 }; 155 };
156 156
157 reg_wifi: regulator-wifi { 157 reg_wifi: regulator-wifi {
158 compatible = "regulator-fixed" 158 compatible = "regulator-fixed";
159 pinctrl-names = "default"; 159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_reg_wl>; 160 pinctrl-0 = <&pinctrl_reg_wl>;
161 regulator-name = "wifi"; 161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_ 162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high; 163 enable-active-high;
164 startup-delay-us = <100>; 164 startup-delay-us = <100>;
165 regulator-min-microvolt = <330 165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <330 166 regulator-max-microvolt = <3300000>;
167 }; 167 };
168 }; 168 };
169 169
170 &A53_0 { 170 &A53_0 {
171 cpu-supply = <&buck2>; 171 cpu-supply = <&buck2>;
172 }; 172 };
173 173
174 &A53_1 { 174 &A53_1 {
175 cpu-supply = <&buck2>; 175 cpu-supply = <&buck2>;
176 }; 176 };
177 177
178 &A53_2 { 178 &A53_2 {
179 cpu-supply = <&buck2>; 179 cpu-supply = <&buck2>;
180 }; 180 };
181 181
182 &A53_3 { 182 &A53_3 {
183 cpu-supply = <&buck2>; 183 cpu-supply = <&buck2>;
184 }; 184 };
185 185
186 &ddrc { 186 &ddrc {
187 operating-points-v2 = <&ddrc_opp_table 187 operating-points-v2 = <&ddrc_opp_table>;
188 188
189 ddrc_opp_table: opp-table { 189 ddrc_opp_table: opp-table {
190 compatible = "operating-points 190 compatible = "operating-points-v2";
191 191
192 opp-25000000 { 192 opp-25000000 {
193 opp-hz = /bits/ 64 <25 193 opp-hz = /bits/ 64 <25000000>;
194 }; 194 };
195 195
196 opp-100000000 { 196 opp-100000000 {
197 opp-hz = /bits/ 64 <10 197 opp-hz = /bits/ 64 <100000000>;
198 }; 198 };
199 199
200 opp-750000000 { 200 opp-750000000 {
201 opp-hz = /bits/ 64 <75 201 opp-hz = /bits/ 64 <750000000>;
202 }; 202 };
203 }; 203 };
204 }; 204 };
205 205
206 &ecspi1 { 206 &ecspi1 {
207 pinctrl-names = "default"; 207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>; 208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210 status = "okay"; 210 status = "okay";
211 211
212 can@0 { 212 can@0 {
213 compatible = "microchip,mcp251 213 compatible = "microchip,mcp2515";
214 reg = <0>; 214 reg = <0>;
215 clocks = <&can20m>; 215 clocks = <&can20m>;
216 interrupt-parent = <&gpio2>; 216 interrupt-parent = <&gpio2>;
217 interrupts = <3 IRQ_TYPE_LEVEL 217 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218 spi-max-frequency = <10000000> 218 spi-max-frequency = <10000000>;
219 }; 219 };
220 }; 220 };
221 221
222 &disp_blk_ctrl { 222 &disp_blk_ctrl {
223 status = "disabled"; 223 status = "disabled";
224 }; 224 };
225 225
226 /* off-board header */ 226 /* off-board header */
227 &ecspi2 { 227 &ecspi2 {
228 pinctrl-names = "default"; 228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_spi2>; 229 pinctrl-0 = <&pinctrl_spi2>;
230 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 230 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
231 status = "okay"; 231 status = "okay";
232 }; 232 };
233 233
234 &fec1 { 234 &fec1 {
235 pinctrl-names = "default"; 235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_fec1>; 236 pinctrl-0 = <&pinctrl_fec1>;
237 phy-mode = "rgmii-id"; 237 phy-mode = "rgmii-id";
238 phy-handle = <ðphy0>; 238 phy-handle = <ðphy0>;
239 local-mac-address = [00 00 00 00 00 00 239 local-mac-address = [00 00 00 00 00 00];
240 status = "okay"; 240 status = "okay";
241 241
242 mdio { 242 mdio {
243 #address-cells = <1>; 243 #address-cells = <1>;
244 #size-cells = <0>; 244 #size-cells = <0>;
245 245
246 ethphy0: ethernet-phy@0 { 246 ethphy0: ethernet-phy@0 {
247 compatible = "ethernet 247 compatible = "ethernet-phy-ieee802.3-c22";
248 reg = <0>; 248 reg = <0>;
249 ti,rx-internal-delay = 249 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
250 ti,tx-internal-delay = 250 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
251 tx-fifo-depth = <DP838 251 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
252 rx-fifo-depth = <DP838 252 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
253 }; 253 };
254 }; 254 };
255 }; 255 };
256 256
257 &gpio1 { 257 &gpio1 {
258 gpio-line-names = "", "", "", "", "", 258 gpio-line-names = "", "", "", "", "", "", "", "",
259 "m2_pwr_en", "", "", "", "", " 259 "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
260 "", "", "", "", "", "", "", "" 260 "", "", "", "", "", "", "", "",
261 "", "", "", "", "", "", "", "" 261 "", "", "", "", "", "", "", "";
262 }; 262 };
263 263
264 &gpio2 { 264 &gpio2 {
265 gpio-line-names = "", "", "", "", "", 265 gpio-line-names = "", "", "", "", "", "", "", "",
266 "uart2_en#", "", "", "", "", " 266 "uart2_en#", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "" 267 "", "", "", "", "", "", "", "",
268 "", "", "", "", "", "", "", "" 268 "", "", "", "", "", "", "", "";
269 }; 269 };
270 270
271 &gpio3 { 271 &gpio3 {
272 gpio-line-names = "", "m2_gdis#", "", 272 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
273 "", "", "", "", "", "", "", "" 273 "", "", "", "", "", "", "", "",
274 "", "", "", "", "", "", "", "" 274 "", "", "", "", "", "", "", "",
275 "", "", "", "", "", "", "", "" 275 "", "", "", "", "", "", "", "";
276 }; 276 };
277 277
278 &gpio4 { 278 &gpio4 {
279 gpio-line-names = "", "", "", "", "", 279 gpio-line-names = "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "" 280 "", "", "", "", "", "", "", "",
281 "", "", "", "", "", "app_gpio1 281 "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
282 "", "uart1_term", "uart1_half" 282 "", "uart1_term", "uart1_half", "app_gpio2",
283 "mipi_gpio1", "", "", ""; 283 "mipi_gpio1", "", "", "";
284 }; 284 };
285 285
286 &gpio5 { 286 &gpio5 {
287 gpio-line-names = "", "", "", "mipi_gp 287 gpio-line-names = "", "", "", "mipi_gpio4",
288 "mipi_gpio3", "mipi_gpio2", "" 288 "mipi_gpio3", "mipi_gpio2", "", "",
289 "", "", "", "", "", "", "", "" 289 "", "", "", "", "", "", "", "",
290 "", "", "", "", "", "", "", "" 290 "", "", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "" 291 "", "", "", "", "", "", "", "";
292 }; 292 };
293 293
294 &gpu { 294 &gpu {
295 status = "disabled"; 295 status = "disabled";
296 }; 296 };
297 297
298 &i2c1 { 298 &i2c1 {
299 clock-frequency = <100000>; 299 clock-frequency = <100000>;
300 pinctrl-names = "default", "gpio"; 300 pinctrl-names = "default", "gpio";
301 pinctrl-0 = <&pinctrl_i2c1>; 301 pinctrl-0 = <&pinctrl_i2c1>;
302 pinctrl-1 = <&pinctrl_i2c1_gpio>; 302 pinctrl-1 = <&pinctrl_i2c1_gpio>;
303 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 303 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
304 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 304 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
305 status = "okay"; 305 status = "okay";
306 306
307 gsc: gsc@20 { 307 gsc: gsc@20 {
308 compatible = "gw,gsc"; 308 compatible = "gw,gsc";
309 reg = <0x20>; 309 reg = <0x20>;
310 pinctrl-0 = <&pinctrl_gsc>; 310 pinctrl-0 = <&pinctrl_gsc>;
311 interrupt-parent = <&gpio2>; 311 interrupt-parent = <&gpio2>;
312 interrupts = <6 IRQ_TYPE_EDGE_ 312 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
313 interrupt-controller; 313 interrupt-controller;
314 #interrupt-cells = <1>; 314 #interrupt-cells = <1>;
315 #address-cells = <1>; <<
316 #size-cells = <0>; <<
317 315
318 adc { 316 adc {
319 compatible = "gw,gsc-a 317 compatible = "gw,gsc-adc";
320 #address-cells = <1>; 318 #address-cells = <1>;
321 #size-cells = <0>; 319 #size-cells = <0>;
322 320
323 channel@6 { 321 channel@6 {
324 gw,mode = <0>; 322 gw,mode = <0>;
325 reg = <0x06>; 323 reg = <0x06>;
326 label = "temp" 324 label = "temp";
327 }; 325 };
328 326
329 channel@8 { 327 channel@8 {
330 gw,mode = <3>; 328 gw,mode = <3>;
331 reg = <0x08>; 329 reg = <0x08>;
332 label = "vdd_b 330 label = "vdd_bat";
333 }; 331 };
334 332
335 channel@82 { 333 channel@82 {
336 gw,mode = <2>; 334 gw,mode = <2>;
337 reg = <0x82>; 335 reg = <0x82>;
338 label = "vin"; 336 label = "vin";
339 gw,voltage-div 337 gw,voltage-divider-ohms = <22100 1000>;
340 gw,voltage-off 338 gw,voltage-offset-microvolt = <700000>;
341 }; 339 };
342 340
343 channel@84 { 341 channel@84 {
344 gw,mode = <2>; 342 gw,mode = <2>;
345 reg = <0x84>; 343 reg = <0x84>;
346 label = "vin_4 344 label = "vin_4p0";
347 gw,voltage-div 345 gw,voltage-divider-ohms = <10000 10000>;
348 }; 346 };
349 347
350 channel@86 { 348 channel@86 {
351 gw,mode = <2>; 349 gw,mode = <2>;
352 reg = <0x86>; 350 reg = <0x86>;
353 label = "vdd_3 351 label = "vdd_3p3";
354 gw,voltage-div 352 gw,voltage-divider-ohms = <10000 10000>;
355 }; 353 };
356 354
357 channel@88 { 355 channel@88 {
358 gw,mode = <2>; 356 gw,mode = <2>;
359 reg = <0x88>; 357 reg = <0x88>;
360 label = "vdd_0 358 label = "vdd_0p9";
361 }; 359 };
362 360
363 channel@8c { 361 channel@8c {
364 gw,mode = <2>; 362 gw,mode = <2>;
365 reg = <0x8c>; 363 reg = <0x8c>;
366 label = "vdd_s 364 label = "vdd_soc";
367 }; 365 };
368 366
369 channel@8e { 367 channel@8e {
370 gw,mode = <2>; 368 gw,mode = <2>;
371 reg = <0x8e>; 369 reg = <0x8e>;
372 label = "vdd_a 370 label = "vdd_arm";
373 }; 371 };
374 372
375 channel@90 { 373 channel@90 {
376 gw,mode = <2>; 374 gw,mode = <2>;
377 reg = <0x90>; 375 reg = <0x90>;
378 label = "vdd_1 376 label = "vdd_1p8";
379 }; 377 };
380 378
381 channel@92 { 379 channel@92 {
382 gw,mode = <2>; 380 gw,mode = <2>;
383 reg = <0x92>; 381 reg = <0x92>;
384 label = "vdd_d 382 label = "vdd_dram";
385 }; 383 };
386 384
387 channel@98 { 385 channel@98 {
388 gw,mode = <2>; 386 gw,mode = <2>;
389 reg = <0x98>; 387 reg = <0x98>;
390 label = "vdd_1 388 label = "vdd_1p0";
391 }; 389 };
392 390
393 channel@9a { 391 channel@9a {
394 gw,mode = <2>; 392 gw,mode = <2>;
395 reg = <0x9a>; 393 reg = <0x9a>;
396 label = "vdd_2 394 label = "vdd_2p5";
397 gw,voltage-div 395 gw,voltage-divider-ohms = <10000 10000>;
398 }; 396 };
399 397
400 channel@9c { 398 channel@9c {
401 gw,mode = <2>; 399 gw,mode = <2>;
402 reg = <0x9c>; 400 reg = <0x9c>;
403 label = "vdd_5 401 label = "vdd_5p0";
404 gw,voltage-div 402 gw,voltage-divider-ohms = <10000 10000>;
405 }; 403 };
406 404
407 channel@a2 { 405 channel@a2 {
408 gw,mode = <2>; 406 gw,mode = <2>;
409 reg = <0xa2>; 407 reg = <0xa2>;
410 label = "vdd_g 408 label = "vdd_gsc";
411 gw,voltage-div 409 gw,voltage-divider-ohms = <10000 10000>;
412 }; 410 };
413 }; 411 };
414 }; 412 };
415 413
416 gpio: gpio@23 { 414 gpio: gpio@23 {
417 compatible = "nxp,pca9555"; 415 compatible = "nxp,pca9555";
418 reg = <0x23>; 416 reg = <0x23>;
419 gpio-controller; 417 gpio-controller;
420 #gpio-cells = <2>; 418 #gpio-cells = <2>;
421 interrupt-parent = <&gsc>; 419 interrupt-parent = <&gsc>;
422 interrupts = <4>; 420 interrupts = <4>;
423 }; 421 };
424 422
425 pmic@4b { 423 pmic@4b {
426 compatible = "rohm,bd71847"; 424 compatible = "rohm,bd71847";
427 reg = <0x4b>; 425 reg = <0x4b>;
428 pinctrl-names = "default"; 426 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_pmic>; 427 pinctrl-0 = <&pinctrl_pmic>;
430 interrupt-parent = <&gpio3>; 428 interrupt-parent = <&gpio3>;
431 interrupts = <8 IRQ_TYPE_LEVEL 429 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
432 rohm,reset-snvs-powered; 430 rohm,reset-snvs-powered;
433 #clock-cells = <0>; 431 #clock-cells = <0>;
434 clocks = <&osc_32k>; 432 clocks = <&osc_32k>;
435 clock-output-names = "clk-32k- 433 clock-output-names = "clk-32k-out";
436 434
437 regulators { 435 regulators {
438 /* vdd_soc: 0.805-0.90 436 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
439 BUCK1 { 437 BUCK1 {
440 regulator-name 438 regulator-name = "buck1";
441 regulator-min- 439 regulator-min-microvolt = <700000>;
442 regulator-max- 440 regulator-max-microvolt = <1300000>;
443 regulator-boot 441 regulator-boot-on;
444 regulator-alwa 442 regulator-always-on;
445 regulator-ramp 443 regulator-ramp-delay = <1250>;
446 }; 444 };
447 445
448 /* vdd_arm: 0.805-1.0V 446 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
449 buck2: BUCK2 { 447 buck2: BUCK2 {
450 regulator-name 448 regulator-name = "buck2";
451 regulator-min- 449 regulator-min-microvolt = <700000>;
452 regulator-max- 450 regulator-max-microvolt = <1300000>;
453 regulator-boot 451 regulator-boot-on;
454 regulator-alwa 452 regulator-always-on;
455 regulator-ramp 453 regulator-ramp-delay = <1250>;
456 rohm,dvs-run-v 454 rohm,dvs-run-voltage = <1000000>;
457 rohm,dvs-idle- 455 rohm,dvs-idle-voltage = <900000>;
458 }; 456 };
459 457
460 /* vdd_0p9: 0.805-1.0V 458 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
461 BUCK3 { 459 BUCK3 {
462 regulator-name 460 regulator-name = "buck3";
463 regulator-min- 461 regulator-min-microvolt = <700000>;
464 regulator-max- 462 regulator-max-microvolt = <1350000>;
465 regulator-boot 463 regulator-boot-on;
466 regulator-alwa 464 regulator-always-on;
467 }; 465 };
468 466
469 /* vdd_3p3 */ 467 /* vdd_3p3 */
470 BUCK4 { 468 BUCK4 {
471 regulator-name 469 regulator-name = "buck4";
472 regulator-min- 470 regulator-min-microvolt = <3000000>;
473 regulator-max- 471 regulator-max-microvolt = <3300000>;
474 regulator-boot 472 regulator-boot-on;
475 regulator-alwa 473 regulator-always-on;
476 }; 474 };
477 475
478 /* vdd_1p8 */ 476 /* vdd_1p8 */
479 BUCK5 { 477 BUCK5 {
480 regulator-name 478 regulator-name = "buck5";
481 regulator-min- 479 regulator-min-microvolt = <1605000>;
482 regulator-max- 480 regulator-max-microvolt = <1995000>;
483 regulator-boot 481 regulator-boot-on;
484 regulator-alwa 482 regulator-always-on;
485 }; 483 };
486 484
487 /* vdd_dram */ 485 /* vdd_dram */
488 BUCK6 { 486 BUCK6 {
489 regulator-name 487 regulator-name = "buck6";
490 regulator-min- 488 regulator-min-microvolt = <800000>;
491 regulator-max- 489 regulator-max-microvolt = <1400000>;
492 regulator-boot 490 regulator-boot-on;
493 regulator-alwa 491 regulator-always-on;
494 }; 492 };
495 493
496 /* nvcc_snvs_1p8 */ 494 /* nvcc_snvs_1p8 */
497 LDO1 { 495 LDO1 {
498 regulator-name 496 regulator-name = "ldo1";
499 regulator-min- 497 regulator-min-microvolt = <1600000>;
500 regulator-max- 498 regulator-max-microvolt = <1900000>;
501 regulator-boot 499 regulator-boot-on;
502 regulator-alwa 500 regulator-always-on;
503 }; 501 };
504 502
505 /* vdd_snvs_0p8 */ 503 /* vdd_snvs_0p8 */
506 LDO2 { 504 LDO2 {
507 regulator-name 505 regulator-name = "ldo2";
508 regulator-min- 506 regulator-min-microvolt = <800000>;
509 regulator-max- 507 regulator-max-microvolt = <900000>;
510 regulator-boot 508 regulator-boot-on;
511 regulator-alwa 509 regulator-always-on;
512 }; 510 };
513 511
514 /* vdda_1p8 */ 512 /* vdda_1p8 */
515 LDO3 { 513 LDO3 {
516 regulator-name 514 regulator-name = "ldo3";
517 regulator-min- 515 regulator-min-microvolt = <1800000>;
518 regulator-max- 516 regulator-max-microvolt = <3300000>;
519 regulator-boot 517 regulator-boot-on;
520 regulator-alwa 518 regulator-always-on;
521 }; 519 };
522 520
523 LDO4 { 521 LDO4 {
524 regulator-name 522 regulator-name = "ldo4";
525 regulator-min- 523 regulator-min-microvolt = <900000>;
526 regulator-max- 524 regulator-max-microvolt = <1800000>;
527 regulator-boot 525 regulator-boot-on;
528 regulator-alwa 526 regulator-always-on;
529 }; 527 };
530 528
531 LDO6 { 529 LDO6 {
532 regulator-name 530 regulator-name = "ldo6";
533 regulator-min- 531 regulator-min-microvolt = <900000>;
534 regulator-max- 532 regulator-max-microvolt = <1800000>;
535 regulator-boot 533 regulator-boot-on;
536 regulator-alwa 534 regulator-always-on;
537 }; 535 };
538 }; 536 };
539 }; 537 };
540 538
541 eeprom@50 { 539 eeprom@50 {
542 compatible = "atmel,24c02"; 540 compatible = "atmel,24c02";
543 reg = <0x50>; 541 reg = <0x50>;
544 pagesize = <16>; 542 pagesize = <16>;
545 }; 543 };
546 544
547 eeprom@51 { 545 eeprom@51 {
548 compatible = "atmel,24c02"; 546 compatible = "atmel,24c02";
549 reg = <0x51>; 547 reg = <0x51>;
550 pagesize = <16>; 548 pagesize = <16>;
551 }; 549 };
552 550
553 eeprom@52 { 551 eeprom@52 {
554 compatible = "atmel,24c02"; 552 compatible = "atmel,24c02";
555 reg = <0x52>; 553 reg = <0x52>;
556 pagesize = <16>; 554 pagesize = <16>;
557 }; 555 };
558 556
559 eeprom@53 { 557 eeprom@53 {
560 compatible = "atmel,24c02"; 558 compatible = "atmel,24c02";
561 reg = <0x53>; 559 reg = <0x53>;
562 pagesize = <16>; 560 pagesize = <16>;
563 }; 561 };
564 562
565 rtc@68 { 563 rtc@68 {
566 compatible = "dallas,ds1672"; 564 compatible = "dallas,ds1672";
567 reg = <0x68>; 565 reg = <0x68>;
568 }; 566 };
569 }; 567 };
570 568
571 &i2c2 { 569 &i2c2 {
572 clock-frequency = <400000>; 570 clock-frequency = <400000>;
573 pinctrl-names = "default", "gpio"; 571 pinctrl-names = "default", "gpio";
574 pinctrl-0 = <&pinctrl_i2c2>; 572 pinctrl-0 = <&pinctrl_i2c2>;
575 pinctrl-1 = <&pinctrl_i2c2_gpio>; 573 pinctrl-1 = <&pinctrl_i2c2_gpio>;
576 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 574 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
577 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 575 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
578 status = "okay"; 576 status = "okay";
579 577
580 accelerometer@19 { 578 accelerometer@19 {
581 compatible = "st,lis2de12"; 579 compatible = "st,lis2de12";
582 pinctrl-names = "default"; 580 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_accel>; 581 pinctrl-0 = <&pinctrl_accel>;
584 reg = <0x19>; 582 reg = <0x19>;
585 st,drdy-int-pin = <1>; 583 st,drdy-int-pin = <1>;
586 interrupt-parent = <&gpio1>; 584 interrupt-parent = <&gpio1>;
587 interrupts = <12 IRQ_TYPE_LEVE 585 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
>> 586 interrupt-names = "INT1";
588 }; 587 };
589 }; 588 };
590 589
591 /* off-board header */ 590 /* off-board header */
592 &i2c3 { 591 &i2c3 {
593 clock-frequency = <400000>; 592 clock-frequency = <400000>;
594 pinctrl-names = "default", "gpio"; 593 pinctrl-names = "default", "gpio";
595 pinctrl-0 = <&pinctrl_i2c3>; 594 pinctrl-0 = <&pinctrl_i2c3>;
596 pinctrl-1 = <&pinctrl_i2c3_gpio>; 595 pinctrl-1 = <&pinctrl_i2c3_gpio>;
597 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 596 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
598 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 597 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
599 status = "okay"; 598 status = "okay";
600 }; 599 };
601 600
602 /* off-board header */ 601 /* off-board header */
603 &i2c4 { 602 &i2c4 {
604 clock-frequency = <400000>; 603 clock-frequency = <400000>;
605 pinctrl-names = "default", "gpio"; 604 pinctrl-names = "default", "gpio";
606 pinctrl-0 = <&pinctrl_i2c4>; 605 pinctrl-0 = <&pinctrl_i2c4>;
607 pinctrl-1 = <&pinctrl_i2c4_gpio>; 606 pinctrl-1 = <&pinctrl_i2c4_gpio>;
608 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 607 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
609 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 608 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
610 status = "okay"; 609 status = "okay";
611 }; 610 };
612 611
613 &pgc_gpumix { 612 &pgc_gpumix {
614 status = "disabled"; 613 status = "disabled";
615 }; 614 };
616 615
617 /* off-board header */ 616 /* off-board header */
618 &sai3 { 617 &sai3 {
619 pinctrl-names = "default"; 618 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_sai3>; 619 pinctrl-0 = <&pinctrl_sai3>;
621 assigned-clocks = <&clk IMX8MN_CLK_SAI 620 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
622 assigned-clock-parents = <&clk IMX8MN_ 621 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
623 assigned-clock-rates = <24576000>; 622 assigned-clock-rates = <24576000>;
624 status = "okay"; 623 status = "okay";
625 }; 624 };
626 625
627 /* RS232/RS485/RS422 selectable */ 626 /* RS232/RS485/RS422 selectable */
628 &uart1 { 627 &uart1 {
629 pinctrl-names = "default"; 628 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 629 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
631 status = "okay"; 630 status = "okay";
632 }; 631 };
633 632
634 /* RS232 console */ 633 /* RS232 console */
635 &uart2 { 634 &uart2 {
636 pinctrl-names = "default"; 635 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_uart2>; 636 pinctrl-0 = <&pinctrl_uart2>;
638 status = "okay"; 637 status = "okay";
639 }; 638 };
640 639
641 /* bluetooth HCI */ 640 /* bluetooth HCI */
642 &uart3 { 641 &uart3 {
643 pinctrl-names = "default"; 642 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 643 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
645 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 644 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
646 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 645 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
647 status = "okay"; 646 status = "okay";
648 647
649 bluetooth { 648 bluetooth {
650 compatible = "brcm,bcm4330-bt" 649 compatible = "brcm,bcm4330-bt";
651 shutdown-gpios = <&gpio2 12 GP 650 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
652 }; 651 };
653 }; 652 };
654 653
655 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 654 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
656 &uart4 { 655 &uart4 {
657 pinctrl-names = "default"; 656 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart4>; 657 pinctrl-0 = <&pinctrl_uart4>;
659 status = "okay"; 658 status = "okay";
660 }; 659 };
661 660
662 &usbotg1 { 661 &usbotg1 {
663 dr_mode = "host"; 662 dr_mode = "host";
664 vbus-supply = <®_usb1_vbus>; 663 vbus-supply = <®_usb1_vbus>;
665 disable-over-current; 664 disable-over-current;
666 status = "okay"; 665 status = "okay";
667 }; 666 };
668 667
669 /* SDIO WiFi */ 668 /* SDIO WiFi */
670 &usdhc2 { 669 &usdhc2 {
671 pinctrl-names = "default", "state_100m 670 pinctrl-names = "default", "state_100mhz", "state_200mhz";
672 pinctrl-0 = <&pinctrl_usdhc2>; 671 pinctrl-0 = <&pinctrl_usdhc2>;
673 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 672 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
674 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 673 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
675 bus-width = <4>; 674 bus-width = <4>;
676 non-removable; 675 non-removable;
677 vmmc-supply = <®_wifi>; 676 vmmc-supply = <®_wifi>;
678 #address-cells = <1>; 677 #address-cells = <1>;
679 #size-cells = <0>; 678 #size-cells = <0>;
680 status = "okay"; 679 status = "okay";
681 680
682 wifi@0 { 681 wifi@0 {
683 compatible = "brcm,bcm43455-fm 682 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
684 reg = <0>; 683 reg = <0>;
685 }; 684 };
686 }; 685 };
687 686
688 /* eMMC */ 687 /* eMMC */
689 &usdhc3 { 688 &usdhc3 {
690 pinctrl-names = "default", "state_100m 689 pinctrl-names = "default", "state_100mhz", "state_200mhz";
691 pinctrl-0 = <&pinctrl_usdhc3>; 690 pinctrl-0 = <&pinctrl_usdhc3>;
692 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 691 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
693 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 692 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
694 bus-width = <8>; 693 bus-width = <8>;
695 non-removable; 694 non-removable;
696 status = "okay"; 695 status = "okay";
697 }; 696 };
698 697
699 &wdog1 { 698 &wdog1 {
700 pinctrl-names = "default"; 699 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_wdog>; 700 pinctrl-0 = <&pinctrl_wdog>;
702 fsl,ext-reset-output; 701 fsl,ext-reset-output;
703 status = "okay"; 702 status = "okay";
704 }; 703 };
705 704
706 &iomuxc { 705 &iomuxc {
707 pinctrl-names = "default"; 706 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_hog>; 707 pinctrl-0 = <&pinctrl_hog>;
709 708
710 pinctrl_hog: hoggrp { 709 pinctrl_hog: hoggrp {
711 fsl,pins = < 710 fsl,pins = <
712 MX8MN_IOMUXC_NAND_CE0_ 711 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
713 MX8MN_IOMUXC_GPIO1_IO0 712 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
714 MX8MN_IOMUXC_GPIO1_IO1 713 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
715 MX8MN_IOMUXC_NAND_DATA 714 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
716 MX8MN_IOMUXC_GPIO1_IO1 715 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
717 MX8MN_IOMUXC_SAI2_RXFS 716 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
718 MX8MN_IOMUXC_SAI2_RXC_ 717 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
719 MX8MN_IOMUXC_SAI2_MCLK 718 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
720 MX8MN_IOMUXC_SD1_DATA6 719 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
721 MX8MN_IOMUXC_SAI3_RXFS 720 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
722 MX8MN_IOMUXC_SPDIF_EXT 721 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
723 MX8MN_IOMUXC_SPDIF_RX_ 722 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
724 MX8MN_IOMUXC_SPDIF_TX_ 723 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
725 >; 724 >;
726 }; 725 };
727 726
728 pinctrl_accel: accelgrp { 727 pinctrl_accel: accelgrp {
729 fsl,pins = < 728 fsl,pins = <
730 MX8MN_IOMUXC_GPIO1_IO1 729 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
731 >; 730 >;
732 }; 731 };
733 732
734 pinctrl_fec1: fec1grp { 733 pinctrl_fec1: fec1grp {
735 fsl,pins = < 734 fsl,pins = <
736 MX8MN_IOMUXC_ENET_MDC_ 735 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
737 MX8MN_IOMUXC_ENET_MDIO 736 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
738 MX8MN_IOMUXC_ENET_TD3_ 737 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
739 MX8MN_IOMUXC_ENET_TD2_ 738 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
740 MX8MN_IOMUXC_ENET_TD1_ 739 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
741 MX8MN_IOMUXC_ENET_TD0_ 740 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
742 MX8MN_IOMUXC_ENET_RD3_ 741 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
743 MX8MN_IOMUXC_ENET_RD2_ 742 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
744 MX8MN_IOMUXC_ENET_RD1_ 743 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
745 MX8MN_IOMUXC_ENET_RD0_ 744 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
746 MX8MN_IOMUXC_ENET_TXC_ 745 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
747 MX8MN_IOMUXC_ENET_RXC_ 746 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
748 MX8MN_IOMUXC_ENET_RX_C 747 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
749 MX8MN_IOMUXC_ENET_TX_C 748 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
750 MX8MN_IOMUXC_GPIO1_IO1 749 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
751 MX8MN_IOMUXC_GPIO1_IO1 750 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
752 >; 751 >;
753 }; 752 };
754 753
755 pinctrl_gsc: gscgrp { 754 pinctrl_gsc: gscgrp {
756 fsl,pins = < 755 fsl,pins = <
757 MX8MN_IOMUXC_SD1_DATA4 756 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
758 >; 757 >;
759 }; 758 };
760 759
761 pinctrl_i2c1: i2c1grp { 760 pinctrl_i2c1: i2c1grp {
762 fsl,pins = < 761 fsl,pins = <
763 MX8MN_IOMUXC_I2C1_SCL_ 762 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
764 MX8MN_IOMUXC_I2C1_SDA_ 763 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
765 >; 764 >;
766 }; 765 };
767 766
768 pinctrl_i2c1_gpio: i2c1gpiogrp { 767 pinctrl_i2c1_gpio: i2c1gpiogrp {
769 fsl,pins = < 768 fsl,pins = <
770 MX8MN_IOMUXC_I2C1_SCL_ 769 MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
771 MX8MN_IOMUXC_I2C1_SDA_ 770 MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
772 >; 771 >;
773 }; 772 };
774 773
775 pinctrl_i2c2: i2c2grp { 774 pinctrl_i2c2: i2c2grp {
776 fsl,pins = < 775 fsl,pins = <
777 MX8MN_IOMUXC_I2C2_SCL_ 776 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
778 MX8MN_IOMUXC_I2C2_SDA_ 777 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
779 >; 778 >;
780 }; 779 };
781 780
782 pinctrl_i2c2_gpio: i2c2gpiogrp { 781 pinctrl_i2c2_gpio: i2c2gpiogrp {
783 fsl,pins = < 782 fsl,pins = <
784 MX8MN_IOMUXC_I2C2_SCL_ 783 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
785 MX8MN_IOMUXC_I2C2_SDA_ 784 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
786 >; 785 >;
787 }; 786 };
788 787
789 pinctrl_i2c3: i2c3grp { 788 pinctrl_i2c3: i2c3grp {
790 fsl,pins = < 789 fsl,pins = <
791 MX8MN_IOMUXC_I2C3_SCL_ 790 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
792 MX8MN_IOMUXC_I2C3_SDA_ 791 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
793 >; 792 >;
794 }; 793 };
795 794
796 pinctrl_i2c3_gpio: i2c3gpiogrp { 795 pinctrl_i2c3_gpio: i2c3gpiogrp {
797 fsl,pins = < 796 fsl,pins = <
798 MX8MN_IOMUXC_I2C3_SCL_ 797 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
799 MX8MN_IOMUXC_I2C3_SDA_ 798 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
800 >; 799 >;
801 }; 800 };
802 801
803 pinctrl_i2c4: i2c4grp { 802 pinctrl_i2c4: i2c4grp {
804 fsl,pins = < 803 fsl,pins = <
805 MX8MN_IOMUXC_I2C4_SCL_ 804 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
806 MX8MN_IOMUXC_I2C4_SDA_ 805 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
807 >; 806 >;
808 }; 807 };
809 808
810 pinctrl_i2c4_gpio: i2c4gpiogrp { 809 pinctrl_i2c4_gpio: i2c4gpiogrp {
811 fsl,pins = < 810 fsl,pins = <
812 MX8MN_IOMUXC_I2C4_SCL_ 811 MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
813 MX8MN_IOMUXC_I2C4_SDA_ 812 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
814 >; 813 >;
815 }; 814 };
816 815
817 pinctrl_gpio_leds: gpioledgrp { 816 pinctrl_gpio_leds: gpioledgrp {
818 fsl,pins = < 817 fsl,pins = <
819 MX8MN_IOMUXC_SAI5_RXD0 818 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
820 MX8MN_IOMUXC_SAI5_RXD2 819 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
821 MX8MN_IOMUXC_SAI5_RXD1 820 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
822 MX8MN_IOMUXC_SAI5_RXC_ 821 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
823 MX8MN_IOMUXC_SAI5_MCLK 822 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
824 >; 823 >;
825 }; 824 };
826 825
827 pinctrl_pmic: pmicgrp { 826 pinctrl_pmic: pmicgrp {
828 fsl,pins = < 827 fsl,pins = <
829 MX8MN_IOMUXC_NAND_DATA 828 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
830 >; 829 >;
831 }; 830 };
832 831
833 pinctrl_pps: ppsgrp { 832 pinctrl_pps: ppsgrp {
834 fsl,pins = < 833 fsl,pins = <
835 MX8MN_IOMUXC_SAI5_RXD3 834 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
836 >; 835 >;
837 }; 836 };
838 837
839 pinctrl_reg_wl: regwlgrp { 838 pinctrl_reg_wl: regwlgrp {
840 fsl,pins = < 839 fsl,pins = <
841 MX8MN_IOMUXC_SD2_RESET 840 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
842 >; 841 >;
843 }; 842 };
844 843
845 pinctrl_reg_usb1: regusb1grp { 844 pinctrl_reg_usb1: regusb1grp {
846 fsl,pins = < 845 fsl,pins = <
847 MX8MN_IOMUXC_SD1_DATA5 846 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
848 >; 847 >;
849 }; 848 };
850 849
851 pinctrl_sai3: sai3grp { 850 pinctrl_sai3: sai3grp {
852 fsl,pins = < 851 fsl,pins = <
853 MX8MN_IOMUXC_SAI3_MCLK 852 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
854 MX8MN_IOMUXC_SAI3_RXD_ 853 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
855 MX8MN_IOMUXC_SAI3_TXC_ 854 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
856 MX8MN_IOMUXC_SAI3_TXD_ 855 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
857 MX8MN_IOMUXC_SAI3_TXFS 856 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
858 >; 857 >;
859 }; 858 };
860 859
861 pinctrl_spi1: spi1grp { 860 pinctrl_spi1: spi1grp {
862 fsl,pins = < 861 fsl,pins = <
863 MX8MN_IOMUXC_ECSPI1_SC 862 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
864 MX8MN_IOMUXC_ECSPI1_MO 863 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
865 MX8MN_IOMUXC_ECSPI1_MI 864 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
866 MX8MN_IOMUXC_ECSPI1_SS 865 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
867 MX8MN_IOMUXC_SD1_DATA1 866 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
868 >; 867 >;
869 }; 868 };
870 869
871 pinctrl_spi2: spi2grp { 870 pinctrl_spi2: spi2grp {
872 fsl,pins = < 871 fsl,pins = <
873 MX8MN_IOMUXC_ECSPI2_SC 872 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
874 MX8MN_IOMUXC_ECSPI2_MO 873 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
875 MX8MN_IOMUXC_ECSPI2_MI 874 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
876 MX8MN_IOMUXC_ECSPI2_SS 875 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
877 >; 876 >;
878 }; 877 };
879 878
880 pinctrl_uart1: uart1grp { 879 pinctrl_uart1: uart1grp {
881 fsl,pins = < 880 fsl,pins = <
882 MX8MN_IOMUXC_UART1_RXD 881 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
883 MX8MN_IOMUXC_UART1_TXD 882 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
884 >; 883 >;
885 }; 884 };
886 885
887 pinctrl_uart1_gpio: uart1gpiogrp { 886 pinctrl_uart1_gpio: uart1gpiogrp {
888 fsl,pins = < 887 fsl,pins = <
889 MX8MN_IOMUXC_SAI2_TXD0 888 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
890 MX8MN_IOMUXC_SAI2_TXC_ 889 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
891 MX8MN_IOMUXC_SAI2_RXD0 890 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
892 >; 891 >;
893 }; 892 };
894 893
895 pinctrl_uart2: uart2grp { 894 pinctrl_uart2: uart2grp {
896 fsl,pins = < 895 fsl,pins = <
897 MX8MN_IOMUXC_UART2_RXD 896 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
898 MX8MN_IOMUXC_UART2_TXD 897 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
899 >; 898 >;
900 }; 899 };
901 900
902 pinctrl_uart3_gpio: uart3_gpiogrp { 901 pinctrl_uart3_gpio: uart3_gpiogrp {
903 fsl,pins = < 902 fsl,pins = <
904 MX8MN_IOMUXC_SD2_CD_B_ 903 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
905 >; 904 >;
906 }; 905 };
907 906
908 pinctrl_uart3: uart3grp { 907 pinctrl_uart3: uart3grp {
909 fsl,pins = < 908 fsl,pins = <
910 MX8MN_IOMUXC_UART3_RXD 909 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
911 MX8MN_IOMUXC_UART3_TXD 910 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
912 MX8MN_IOMUXC_SD1_CLK_G 911 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
913 MX8MN_IOMUXC_SD1_CMD_G 912 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
914 >; 913 >;
915 }; 914 };
916 915
917 pinctrl_uart4: uart4grp { 916 pinctrl_uart4: uart4grp {
918 fsl,pins = < 917 fsl,pins = <
919 MX8MN_IOMUXC_UART4_RXD 918 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
920 MX8MN_IOMUXC_UART4_TXD 919 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
921 MX8MN_IOMUXC_GPIO1_IO0 920 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
922 >; 921 >;
923 }; 922 };
924 923
925 pinctrl_usdhc2: usdhc2grp { 924 pinctrl_usdhc2: usdhc2grp {
926 fsl,pins = < 925 fsl,pins = <
927 MX8MN_IOMUXC_SD2_CLK_U 926 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
928 MX8MN_IOMUXC_SD2_CMD_U 927 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
929 MX8MN_IOMUXC_SD2_DATA0 928 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
930 MX8MN_IOMUXC_SD2_DATA1 929 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
931 MX8MN_IOMUXC_SD2_DATA2 930 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
932 MX8MN_IOMUXC_SD2_DATA3 931 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
933 >; 932 >;
934 }; 933 };
935 934
936 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 935 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
937 fsl,pins = < 936 fsl,pins = <
938 MX8MN_IOMUXC_SD2_CLK_U 937 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
939 MX8MN_IOMUXC_SD2_CMD_U 938 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
940 MX8MN_IOMUXC_SD2_DATA0 939 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
941 MX8MN_IOMUXC_SD2_DATA1 940 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
942 MX8MN_IOMUXC_SD2_DATA2 941 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
943 MX8MN_IOMUXC_SD2_DATA3 942 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
944 >; 943 >;
945 }; 944 };
946 945
947 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 946 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
948 fsl,pins = < 947 fsl,pins = <
949 MX8MN_IOMUXC_SD2_CLK_U 948 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
950 MX8MN_IOMUXC_SD2_CMD_U 949 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
951 MX8MN_IOMUXC_SD2_DATA0 950 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
952 MX8MN_IOMUXC_SD2_DATA1 951 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
953 MX8MN_IOMUXC_SD2_DATA2 952 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
954 MX8MN_IOMUXC_SD2_DATA3 953 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
955 >; 954 >;
956 }; 955 };
957 956
958 pinctrl_usdhc3: usdhc3grp { 957 pinctrl_usdhc3: usdhc3grp {
959 fsl,pins = < 958 fsl,pins = <
960 MX8MN_IOMUXC_NAND_WE_B 959 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
961 MX8MN_IOMUXC_NAND_WP_B 960 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
962 MX8MN_IOMUXC_NAND_DATA 961 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
963 MX8MN_IOMUXC_NAND_DATA 962 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
964 MX8MN_IOMUXC_NAND_DATA 963 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
965 MX8MN_IOMUXC_NAND_DATA 964 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
966 MX8MN_IOMUXC_NAND_RE_B 965 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
967 MX8MN_IOMUXC_NAND_CE2_ 966 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
968 MX8MN_IOMUXC_NAND_CE3_ 967 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
969 MX8MN_IOMUXC_NAND_CLE_ 968 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
970 MX8MN_IOMUXC_NAND_CE1_ 969 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
971 >; 970 >;
972 }; 971 };
973 972
974 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 973 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
975 fsl,pins = < 974 fsl,pins = <
976 MX8MN_IOMUXC_NAND_WE_B 975 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
977 MX8MN_IOMUXC_NAND_WP_B 976 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
978 MX8MN_IOMUXC_NAND_DATA 977 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
979 MX8MN_IOMUXC_NAND_DATA 978 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
980 MX8MN_IOMUXC_NAND_DATA 979 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
981 MX8MN_IOMUXC_NAND_DATA 980 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
982 MX8MN_IOMUXC_NAND_RE_B 981 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
983 MX8MN_IOMUXC_NAND_CE2_ 982 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
984 MX8MN_IOMUXC_NAND_CE3_ 983 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
985 MX8MN_IOMUXC_NAND_CLE_ 984 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
986 MX8MN_IOMUXC_NAND_CE1_ 985 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
987 >; 986 >;
988 }; 987 };
989 988
990 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 989 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
991 fsl,pins = < 990 fsl,pins = <
992 MX8MN_IOMUXC_NAND_WE_B 991 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
993 MX8MN_IOMUXC_NAND_WP_B 992 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
994 MX8MN_IOMUXC_NAND_DATA 993 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
995 MX8MN_IOMUXC_NAND_DATA 994 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
996 MX8MN_IOMUXC_NAND_DATA 995 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
997 MX8MN_IOMUXC_NAND_DATA 996 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
998 MX8MN_IOMUXC_NAND_RE_B 997 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
999 MX8MN_IOMUXC_NAND_CE2_ 998 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1000 MX8MN_IOMUXC_NAND_CE3 999 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1001 MX8MN_IOMUXC_NAND_CLE 1000 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1002 MX8MN_IOMUXC_NAND_CE1 1001 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1003 >; 1002 >;
1004 }; 1003 };
1005 1004
1006 pinctrl_wdog: wdoggrp { 1005 pinctrl_wdog: wdoggrp {
1007 fsl,pins = < 1006 fsl,pins = <
1008 MX8MN_IOMUXC_GPIO1_IO 1007 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1009 >; 1008 >;
1010 }; 1009 };
1011 }; 1010 };
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