1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/net/ti-dp83867.h> 11 #include <dt-bindings/net/ti-dp83867.h>
12 12
13 #include "imx8mn.dtsi" 13 #include "imx8mn.dtsi"
14 14
15 / { 15 / {
16 model = "Gateworks Venice GW7902 i.MX8 16 model = "Gateworks Venice GW7902 i.MX8MN board";
17 compatible = "gw,imx8mn-gw7902", "fsl, 17 compatible = "gw,imx8mn-gw7902", "fsl,imx8mn";
18 18
19 aliases { 19 aliases {
20 usb0 = &usbotg1; 20 usb0 = &usbotg1;
21 }; 21 };
22 22
23 chosen { 23 chosen {
24 stdout-path = &uart2; 24 stdout-path = &uart2;
25 }; 25 };
26 26
27 memory@40000000 { 27 memory@40000000 {
28 device_type = "memory"; 28 device_type = "memory";
29 reg = <0x0 0x40000000 0 0x8000 29 reg = <0x0 0x40000000 0 0x80000000>;
30 }; 30 };
31 31
32 can20m: can20m { 32 can20m: can20m {
33 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
34 #clock-cells = <0>; 34 #clock-cells = <0>;
35 clock-frequency = <20000000>; 35 clock-frequency = <20000000>;
36 clock-output-names = "can20m"; 36 clock-output-names = "can20m";
37 }; 37 };
38 38
39 gpio-keys { 39 gpio-keys {
40 compatible = "gpio-keys"; 40 compatible = "gpio-keys";
41 41
42 key-user-pb { 42 key-user-pb {
43 label = "user_pb"; 43 label = "user_pb";
44 gpios = <&gpio 2 GPIO_ 44 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
45 linux,code = <BTN_0>; 45 linux,code = <BTN_0>;
46 }; 46 };
47 47
48 key-user-pb1x { 48 key-user-pb1x {
49 label = "user_pb1x"; 49 label = "user_pb1x";
50 linux,code = <BTN_1>; 50 linux,code = <BTN_1>;
51 interrupt-parent = <&g 51 interrupt-parent = <&gsc>;
52 interrupts = <0>; 52 interrupts = <0>;
53 }; 53 };
54 54
55 key-erased { 55 key-erased {
56 label = "key_erased"; 56 label = "key_erased";
57 linux,code = <BTN_2>; 57 linux,code = <BTN_2>;
58 interrupt-parent = <&g 58 interrupt-parent = <&gsc>;
59 interrupts = <1>; 59 interrupts = <1>;
60 }; 60 };
61 61
62 key-eeprom-wp { 62 key-eeprom-wp {
63 label = "eeprom_wp"; 63 label = "eeprom_wp";
64 linux,code = <BTN_3>; 64 linux,code = <BTN_3>;
65 interrupt-parent = <&g 65 interrupt-parent = <&gsc>;
66 interrupts = <2>; 66 interrupts = <2>;
67 }; 67 };
68 68
69 key-tamper { 69 key-tamper {
70 label = "tamper"; 70 label = "tamper";
71 linux,code = <BTN_4>; 71 linux,code = <BTN_4>;
72 interrupt-parent = <&g 72 interrupt-parent = <&gsc>;
73 interrupts = <5>; 73 interrupts = <5>;
74 }; 74 };
75 75
76 switch-hold { 76 switch-hold {
77 label = "switch_hold"; 77 label = "switch_hold";
78 linux,code = <BTN_5>; 78 linux,code = <BTN_5>;
79 interrupt-parent = <&g 79 interrupt-parent = <&gsc>;
80 interrupts = <7>; 80 interrupts = <7>;
81 }; 81 };
82 }; 82 };
83 83
84 led-controller { 84 led-controller {
85 compatible = "gpio-leds"; 85 compatible = "gpio-leds";
86 pinctrl-names = "default"; 86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_gpio_led 87 pinctrl-0 = <&pinctrl_gpio_leds>;
88 88
89 led-0 { 89 led-0 {
90 function = LED_FUNCTIO 90 function = LED_FUNCTION_STATUS;
91 color = <LED_COLOR_ID_ 91 color = <LED_COLOR_ID_GREEN>;
92 label = "panel1"; 92 label = "panel1";
93 gpios = <&gpio3 21 GPI 93 gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
94 default-state = "off"; 94 default-state = "off";
95 }; 95 };
96 96
97 led-1 { 97 led-1 {
98 function = LED_FUNCTIO 98 function = LED_FUNCTION_STATUS;
99 color = <LED_COLOR_ID_ 99 color = <LED_COLOR_ID_GREEN>;
100 label = "panel2"; 100 label = "panel2";
101 gpios = <&gpio3 23 GPI 101 gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
102 default-state = "off"; 102 default-state = "off";
103 }; 103 };
104 104
105 led-2 { 105 led-2 {
106 function = LED_FUNCTIO 106 function = LED_FUNCTION_STATUS;
107 color = <LED_COLOR_ID_ 107 color = <LED_COLOR_ID_GREEN>;
108 label = "panel3"; 108 label = "panel3";
109 gpios = <&gpio3 22 GPI 109 gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
110 default-state = "off"; 110 default-state = "off";
111 }; 111 };
112 112
113 led-3 { 113 led-3 {
114 function = LED_FUNCTIO 114 function = LED_FUNCTION_STATUS;
115 color = <LED_COLOR_ID_ 115 color = <LED_COLOR_ID_GREEN>;
116 label = "panel4"; 116 label = "panel4";
117 gpios = <&gpio3 20 GPI 117 gpios = <&gpio3 20 GPIO_ACTIVE_LOW>;
118 default-state = "off"; 118 default-state = "off";
119 }; 119 };
120 120
121 led-4 { 121 led-4 {
122 function = LED_FUNCTIO 122 function = LED_FUNCTION_STATUS;
123 color = <LED_COLOR_ID_ 123 color = <LED_COLOR_ID_GREEN>;
124 label = "panel5"; 124 label = "panel5";
125 gpios = <&gpio3 25 GPI 125 gpios = <&gpio3 25 GPIO_ACTIVE_LOW>;
126 default-state = "off"; 126 default-state = "off";
127 }; 127 };
128 }; 128 };
129 129
130 pps { 130 pps {
131 compatible = "pps-gpio"; 131 compatible = "pps-gpio";
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_pps>; 133 pinctrl-0 = <&pinctrl_pps>;
134 gpios = <&gpio3 24 GPIO_ACTIVE 134 gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
135 status = "okay"; 135 status = "okay";
136 }; 136 };
137 137
138 reg_3p3v: regulator-3p3v { 138 reg_3p3v: regulator-3p3v {
139 compatible = "regulator-fixed" 139 compatible = "regulator-fixed";
140 regulator-name = "3P3V"; 140 regulator-name = "3P3V";
141 regulator-min-microvolt = <330 141 regulator-min-microvolt = <3300000>;
142 regulator-max-microvolt = <330 142 regulator-max-microvolt = <3300000>;
143 regulator-always-on; 143 regulator-always-on;
144 }; 144 };
145 145
146 reg_usb1_vbus: regulator-usb1 { 146 reg_usb1_vbus: regulator-usb1 {
147 compatible = "regulator-fixed" 147 compatible = "regulator-fixed";
148 pinctrl-names = "default"; 148 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_reg_usb1 149 pinctrl-0 = <&pinctrl_reg_usb1>;
150 regulator-name = "usb_usb1_vbu 150 regulator-name = "usb_usb1_vbus";
151 gpio = <&gpio2 7 GPIO_ACTIVE_H 151 gpio = <&gpio2 7 GPIO_ACTIVE_HIGH>;
152 enable-active-high; 152 enable-active-high;
153 regulator-min-microvolt = <500 153 regulator-min-microvolt = <5000000>;
154 regulator-max-microvolt = <500 154 regulator-max-microvolt = <5000000>;
155 }; 155 };
156 156
157 reg_wifi: regulator-wifi { 157 reg_wifi: regulator-wifi {
158 compatible = "regulator-fixed" 158 compatible = "regulator-fixed";
159 pinctrl-names = "default"; 159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_reg_wl>; 160 pinctrl-0 = <&pinctrl_reg_wl>;
161 regulator-name = "wifi"; 161 regulator-name = "wifi";
162 gpio = <&gpio2 19 GPIO_ACTIVE_ 162 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
163 enable-active-high; 163 enable-active-high;
164 startup-delay-us = <100>; 164 startup-delay-us = <100>;
165 regulator-min-microvolt = <330 165 regulator-min-microvolt = <3300000>;
166 regulator-max-microvolt = <330 166 regulator-max-microvolt = <3300000>;
167 }; 167 };
168 }; 168 };
169 169
170 &A53_0 { 170 &A53_0 {
171 cpu-supply = <&buck2>; 171 cpu-supply = <&buck2>;
172 }; 172 };
173 173
174 &A53_1 { 174 &A53_1 {
175 cpu-supply = <&buck2>; 175 cpu-supply = <&buck2>;
176 }; 176 };
177 177
178 &A53_2 { 178 &A53_2 {
179 cpu-supply = <&buck2>; 179 cpu-supply = <&buck2>;
180 }; 180 };
181 181
182 &A53_3 { 182 &A53_3 {
183 cpu-supply = <&buck2>; 183 cpu-supply = <&buck2>;
184 }; 184 };
185 185
186 &ddrc { 186 &ddrc {
187 operating-points-v2 = <&ddrc_opp_table 187 operating-points-v2 = <&ddrc_opp_table>;
188 188
189 ddrc_opp_table: opp-table { 189 ddrc_opp_table: opp-table {
190 compatible = "operating-points 190 compatible = "operating-points-v2";
191 191
192 opp-25000000 { 192 opp-25000000 {
193 opp-hz = /bits/ 64 <25 193 opp-hz = /bits/ 64 <25000000>;
194 }; 194 };
195 195
196 opp-100000000 { 196 opp-100000000 {
197 opp-hz = /bits/ 64 <10 197 opp-hz = /bits/ 64 <100000000>;
198 }; 198 };
199 199
200 opp-750000000 { 200 opp-750000000 {
201 opp-hz = /bits/ 64 <75 201 opp-hz = /bits/ 64 <750000000>;
202 }; 202 };
203 }; 203 };
204 }; 204 };
205 205
206 &ecspi1 { 206 &ecspi1 {
207 pinctrl-names = "default"; 207 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_spi1>; 208 pinctrl-0 = <&pinctrl_spi1>;
209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 209 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
210 status = "okay"; 210 status = "okay";
211 211
212 can@0 { 212 can@0 {
213 compatible = "microchip,mcp251 213 compatible = "microchip,mcp2515";
214 reg = <0>; 214 reg = <0>;
215 clocks = <&can20m>; 215 clocks = <&can20m>;
216 interrupt-parent = <&gpio2>; 216 interrupt-parent = <&gpio2>;
217 interrupts = <3 IRQ_TYPE_LEVEL 217 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
218 spi-max-frequency = <10000000> 218 spi-max-frequency = <10000000>;
219 }; 219 };
220 }; 220 };
221 221
222 &disp_blk_ctrl { 222 &disp_blk_ctrl {
223 status = "disabled"; 223 status = "disabled";
224 }; 224 };
225 225
226 /* off-board header */ 226 /* off-board header */
227 &ecspi2 { 227 &ecspi2 {
228 pinctrl-names = "default"; 228 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_spi2>; 229 pinctrl-0 = <&pinctrl_spi2>;
230 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 230 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
231 status = "okay"; 231 status = "okay";
232 }; 232 };
233 233
234 &fec1 { 234 &fec1 {
235 pinctrl-names = "default"; 235 pinctrl-names = "default";
236 pinctrl-0 = <&pinctrl_fec1>; 236 pinctrl-0 = <&pinctrl_fec1>;
237 phy-mode = "rgmii-id"; 237 phy-mode = "rgmii-id";
238 phy-handle = <ðphy0>; 238 phy-handle = <ðphy0>;
239 local-mac-address = [00 00 00 00 00 00 239 local-mac-address = [00 00 00 00 00 00];
240 status = "okay"; 240 status = "okay";
241 241
242 mdio { 242 mdio {
243 #address-cells = <1>; 243 #address-cells = <1>;
244 #size-cells = <0>; 244 #size-cells = <0>;
245 245
246 ethphy0: ethernet-phy@0 { 246 ethphy0: ethernet-phy@0 {
247 compatible = "ethernet 247 compatible = "ethernet-phy-ieee802.3-c22";
248 reg = <0>; 248 reg = <0>;
249 ti,rx-internal-delay = 249 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
250 ti,tx-internal-delay = 250 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
251 tx-fifo-depth = <DP838 251 tx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
252 rx-fifo-depth = <DP838 252 rx-fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
253 }; 253 };
254 }; 254 };
255 }; 255 };
256 256
257 &gpio1 { 257 &gpio1 {
258 gpio-line-names = "", "", "", "", "", 258 gpio-line-names = "", "", "", "", "", "", "", "",
259 "m2_pwr_en", "", "", "", "", " 259 "m2_pwr_en", "", "", "", "", "m2_reset", "", "m2_wdis#",
260 "", "", "", "", "", "", "", "" 260 "", "", "", "", "", "", "", "",
261 "", "", "", "", "", "", "", "" 261 "", "", "", "", "", "", "", "";
262 }; 262 };
263 263
264 &gpio2 { 264 &gpio2 {
265 gpio-line-names = "", "", "", "", "", 265 gpio-line-names = "", "", "", "", "", "", "", "",
266 "uart2_en#", "", "", "", "", " 266 "uart2_en#", "", "", "", "", "", "", "",
267 "", "", "", "", "", "", "", "" 267 "", "", "", "", "", "", "", "",
268 "", "", "", "", "", "", "", "" 268 "", "", "", "", "", "", "", "";
269 }; 269 };
270 270
271 &gpio3 { 271 &gpio3 {
272 gpio-line-names = "", "m2_gdis#", "", 272 gpio-line-names = "", "m2_gdis#", "", "", "", "", "", "m2_off#",
273 "", "", "", "", "", "", "", "" 273 "", "", "", "", "", "", "", "",
274 "", "", "", "", "", "", "", "" 274 "", "", "", "", "", "", "", "",
275 "", "", "", "", "", "", "", "" 275 "", "", "", "", "", "", "", "";
276 }; 276 };
277 277
278 &gpio4 { 278 &gpio4 {
279 gpio-line-names = "", "", "", "", "", 279 gpio-line-names = "", "", "", "", "", "", "", "",
280 "", "", "", "", "", "", "", "" 280 "", "", "", "", "", "", "", "",
281 "", "", "", "", "", "app_gpio1 281 "", "", "", "", "", "app_gpio1", "vdd_4p0_en", "uart1_rs485",
282 "", "uart1_term", "uart1_half" 282 "", "uart1_term", "uart1_half", "app_gpio2",
283 "mipi_gpio1", "", "", ""; 283 "mipi_gpio1", "", "", "";
284 }; 284 };
285 285
286 &gpio5 { 286 &gpio5 {
287 gpio-line-names = "", "", "", "mipi_gp 287 gpio-line-names = "", "", "", "mipi_gpio4",
288 "mipi_gpio3", "mipi_gpio2", "" 288 "mipi_gpio3", "mipi_gpio2", "", "",
289 "", "", "", "", "", "", "", "" 289 "", "", "", "", "", "", "", "",
290 "", "", "", "", "", "", "", "" 290 "", "", "", "", "", "", "", "",
291 "", "", "", "", "", "", "", "" 291 "", "", "", "", "", "", "", "";
292 }; 292 };
293 293
294 &gpu { 294 &gpu {
295 status = "disabled"; 295 status = "disabled";
296 }; 296 };
297 297
298 &i2c1 { 298 &i2c1 {
299 clock-frequency = <100000>; 299 clock-frequency = <100000>;
300 pinctrl-names = "default", "gpio"; 300 pinctrl-names = "default", "gpio";
301 pinctrl-0 = <&pinctrl_i2c1>; 301 pinctrl-0 = <&pinctrl_i2c1>;
302 pinctrl-1 = <&pinctrl_i2c1_gpio>; 302 pinctrl-1 = <&pinctrl_i2c1_gpio>;
303 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 303 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
304 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 304 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
305 status = "okay"; 305 status = "okay";
306 306
307 gsc: gsc@20 { 307 gsc: gsc@20 {
308 compatible = "gw,gsc"; 308 compatible = "gw,gsc";
309 reg = <0x20>; 309 reg = <0x20>;
310 pinctrl-0 = <&pinctrl_gsc>; 310 pinctrl-0 = <&pinctrl_gsc>;
311 interrupt-parent = <&gpio2>; 311 interrupt-parent = <&gpio2>;
312 interrupts = <6 IRQ_TYPE_EDGE_ 312 interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
313 interrupt-controller; 313 interrupt-controller;
314 #interrupt-cells = <1>; 314 #interrupt-cells = <1>;
315 #address-cells = <1>; 315 #address-cells = <1>;
316 #size-cells = <0>; 316 #size-cells = <0>;
317 317
318 adc { 318 adc {
319 compatible = "gw,gsc-a 319 compatible = "gw,gsc-adc";
320 #address-cells = <1>; 320 #address-cells = <1>;
321 #size-cells = <0>; 321 #size-cells = <0>;
322 322
323 channel@6 { 323 channel@6 {
324 gw,mode = <0>; 324 gw,mode = <0>;
325 reg = <0x06>; 325 reg = <0x06>;
326 label = "temp" 326 label = "temp";
327 }; 327 };
328 328
329 channel@8 { 329 channel@8 {
330 gw,mode = <3>; 330 gw,mode = <3>;
331 reg = <0x08>; 331 reg = <0x08>;
332 label = "vdd_b 332 label = "vdd_bat";
333 }; 333 };
334 334
335 channel@82 { 335 channel@82 {
336 gw,mode = <2>; 336 gw,mode = <2>;
337 reg = <0x82>; 337 reg = <0x82>;
338 label = "vin"; 338 label = "vin";
339 gw,voltage-div 339 gw,voltage-divider-ohms = <22100 1000>;
340 gw,voltage-off 340 gw,voltage-offset-microvolt = <700000>;
341 }; 341 };
342 342
343 channel@84 { 343 channel@84 {
344 gw,mode = <2>; 344 gw,mode = <2>;
345 reg = <0x84>; 345 reg = <0x84>;
346 label = "vin_4 346 label = "vin_4p0";
347 gw,voltage-div 347 gw,voltage-divider-ohms = <10000 10000>;
348 }; 348 };
349 349
350 channel@86 { 350 channel@86 {
351 gw,mode = <2>; 351 gw,mode = <2>;
352 reg = <0x86>; 352 reg = <0x86>;
353 label = "vdd_3 353 label = "vdd_3p3";
354 gw,voltage-div 354 gw,voltage-divider-ohms = <10000 10000>;
355 }; 355 };
356 356
357 channel@88 { 357 channel@88 {
358 gw,mode = <2>; 358 gw,mode = <2>;
359 reg = <0x88>; 359 reg = <0x88>;
360 label = "vdd_0 360 label = "vdd_0p9";
361 }; 361 };
362 362
363 channel@8c { 363 channel@8c {
364 gw,mode = <2>; 364 gw,mode = <2>;
365 reg = <0x8c>; 365 reg = <0x8c>;
366 label = "vdd_s 366 label = "vdd_soc";
367 }; 367 };
368 368
369 channel@8e { 369 channel@8e {
370 gw,mode = <2>; 370 gw,mode = <2>;
371 reg = <0x8e>; 371 reg = <0x8e>;
372 label = "vdd_a 372 label = "vdd_arm";
373 }; 373 };
374 374
375 channel@90 { 375 channel@90 {
376 gw,mode = <2>; 376 gw,mode = <2>;
377 reg = <0x90>; 377 reg = <0x90>;
378 label = "vdd_1 378 label = "vdd_1p8";
379 }; 379 };
380 380
381 channel@92 { 381 channel@92 {
382 gw,mode = <2>; 382 gw,mode = <2>;
383 reg = <0x92>; 383 reg = <0x92>;
384 label = "vdd_d 384 label = "vdd_dram";
385 }; 385 };
386 386
387 channel@98 { 387 channel@98 {
388 gw,mode = <2>; 388 gw,mode = <2>;
389 reg = <0x98>; 389 reg = <0x98>;
390 label = "vdd_1 390 label = "vdd_1p0";
391 }; 391 };
392 392
393 channel@9a { 393 channel@9a {
394 gw,mode = <2>; 394 gw,mode = <2>;
395 reg = <0x9a>; 395 reg = <0x9a>;
396 label = "vdd_2 396 label = "vdd_2p5";
397 gw,voltage-div 397 gw,voltage-divider-ohms = <10000 10000>;
398 }; 398 };
399 399
400 channel@9c { 400 channel@9c {
401 gw,mode = <2>; 401 gw,mode = <2>;
402 reg = <0x9c>; 402 reg = <0x9c>;
403 label = "vdd_5 403 label = "vdd_5p0";
404 gw,voltage-div 404 gw,voltage-divider-ohms = <10000 10000>;
405 }; 405 };
406 406
407 channel@a2 { 407 channel@a2 {
408 gw,mode = <2>; 408 gw,mode = <2>;
409 reg = <0xa2>; 409 reg = <0xa2>;
410 label = "vdd_g 410 label = "vdd_gsc";
411 gw,voltage-div 411 gw,voltage-divider-ohms = <10000 10000>;
412 }; 412 };
413 }; 413 };
414 }; 414 };
415 415
416 gpio: gpio@23 { 416 gpio: gpio@23 {
417 compatible = "nxp,pca9555"; 417 compatible = "nxp,pca9555";
418 reg = <0x23>; 418 reg = <0x23>;
419 gpio-controller; 419 gpio-controller;
420 #gpio-cells = <2>; 420 #gpio-cells = <2>;
421 interrupt-parent = <&gsc>; 421 interrupt-parent = <&gsc>;
422 interrupts = <4>; 422 interrupts = <4>;
423 }; 423 };
424 424
425 pmic@4b { 425 pmic@4b {
426 compatible = "rohm,bd71847"; 426 compatible = "rohm,bd71847";
427 reg = <0x4b>; 427 reg = <0x4b>;
428 pinctrl-names = "default"; 428 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_pmic>; 429 pinctrl-0 = <&pinctrl_pmic>;
430 interrupt-parent = <&gpio3>; 430 interrupt-parent = <&gpio3>;
431 interrupts = <8 IRQ_TYPE_LEVEL 431 interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
432 rohm,reset-snvs-powered; 432 rohm,reset-snvs-powered;
433 #clock-cells = <0>; 433 #clock-cells = <0>;
434 clocks = <&osc_32k>; 434 clocks = <&osc_32k>;
435 clock-output-names = "clk-32k- 435 clock-output-names = "clk-32k-out";
436 436
437 regulators { 437 regulators {
438 /* vdd_soc: 0.805-0.90 438 /* vdd_soc: 0.805-0.900V (typ=0.8V) */
439 BUCK1 { 439 BUCK1 {
440 regulator-name 440 regulator-name = "buck1";
441 regulator-min- 441 regulator-min-microvolt = <700000>;
442 regulator-max- 442 regulator-max-microvolt = <1300000>;
443 regulator-boot 443 regulator-boot-on;
444 regulator-alwa 444 regulator-always-on;
445 regulator-ramp 445 regulator-ramp-delay = <1250>;
446 }; 446 };
447 447
448 /* vdd_arm: 0.805-1.0V 448 /* vdd_arm: 0.805-1.0V (typ=0.9V) */
449 buck2: BUCK2 { 449 buck2: BUCK2 {
450 regulator-name 450 regulator-name = "buck2";
451 regulator-min- 451 regulator-min-microvolt = <700000>;
452 regulator-max- 452 regulator-max-microvolt = <1300000>;
453 regulator-boot 453 regulator-boot-on;
454 regulator-alwa 454 regulator-always-on;
455 regulator-ramp 455 regulator-ramp-delay = <1250>;
456 rohm,dvs-run-v 456 rohm,dvs-run-voltage = <1000000>;
457 rohm,dvs-idle- 457 rohm,dvs-idle-voltage = <900000>;
458 }; 458 };
459 459
460 /* vdd_0p9: 0.805-1.0V 460 /* vdd_0p9: 0.805-1.0V (typ=0.9V) */
461 BUCK3 { 461 BUCK3 {
462 regulator-name 462 regulator-name = "buck3";
463 regulator-min- 463 regulator-min-microvolt = <700000>;
464 regulator-max- 464 regulator-max-microvolt = <1350000>;
465 regulator-boot 465 regulator-boot-on;
466 regulator-alwa 466 regulator-always-on;
467 }; 467 };
468 468
469 /* vdd_3p3 */ 469 /* vdd_3p3 */
470 BUCK4 { 470 BUCK4 {
471 regulator-name 471 regulator-name = "buck4";
472 regulator-min- 472 regulator-min-microvolt = <3000000>;
473 regulator-max- 473 regulator-max-microvolt = <3300000>;
474 regulator-boot 474 regulator-boot-on;
475 regulator-alwa 475 regulator-always-on;
476 }; 476 };
477 477
478 /* vdd_1p8 */ 478 /* vdd_1p8 */
479 BUCK5 { 479 BUCK5 {
480 regulator-name 480 regulator-name = "buck5";
481 regulator-min- 481 regulator-min-microvolt = <1605000>;
482 regulator-max- 482 regulator-max-microvolt = <1995000>;
483 regulator-boot 483 regulator-boot-on;
484 regulator-alwa 484 regulator-always-on;
485 }; 485 };
486 486
487 /* vdd_dram */ 487 /* vdd_dram */
488 BUCK6 { 488 BUCK6 {
489 regulator-name 489 regulator-name = "buck6";
490 regulator-min- 490 regulator-min-microvolt = <800000>;
491 regulator-max- 491 regulator-max-microvolt = <1400000>;
492 regulator-boot 492 regulator-boot-on;
493 regulator-alwa 493 regulator-always-on;
494 }; 494 };
495 495
496 /* nvcc_snvs_1p8 */ 496 /* nvcc_snvs_1p8 */
497 LDO1 { 497 LDO1 {
498 regulator-name 498 regulator-name = "ldo1";
499 regulator-min- 499 regulator-min-microvolt = <1600000>;
500 regulator-max- 500 regulator-max-microvolt = <1900000>;
501 regulator-boot 501 regulator-boot-on;
502 regulator-alwa 502 regulator-always-on;
503 }; 503 };
504 504
505 /* vdd_snvs_0p8 */ 505 /* vdd_snvs_0p8 */
506 LDO2 { 506 LDO2 {
507 regulator-name 507 regulator-name = "ldo2";
508 regulator-min- 508 regulator-min-microvolt = <800000>;
509 regulator-max- 509 regulator-max-microvolt = <900000>;
510 regulator-boot 510 regulator-boot-on;
511 regulator-alwa 511 regulator-always-on;
512 }; 512 };
513 513
514 /* vdda_1p8 */ 514 /* vdda_1p8 */
515 LDO3 { 515 LDO3 {
516 regulator-name 516 regulator-name = "ldo3";
517 regulator-min- 517 regulator-min-microvolt = <1800000>;
518 regulator-max- 518 regulator-max-microvolt = <3300000>;
519 regulator-boot 519 regulator-boot-on;
520 regulator-alwa 520 regulator-always-on;
521 }; 521 };
522 522
523 LDO4 { 523 LDO4 {
524 regulator-name 524 regulator-name = "ldo4";
525 regulator-min- 525 regulator-min-microvolt = <900000>;
526 regulator-max- 526 regulator-max-microvolt = <1800000>;
527 regulator-boot 527 regulator-boot-on;
528 regulator-alwa 528 regulator-always-on;
529 }; 529 };
530 530
531 LDO6 { 531 LDO6 {
532 regulator-name 532 regulator-name = "ldo6";
533 regulator-min- 533 regulator-min-microvolt = <900000>;
534 regulator-max- 534 regulator-max-microvolt = <1800000>;
535 regulator-boot 535 regulator-boot-on;
536 regulator-alwa 536 regulator-always-on;
537 }; 537 };
538 }; 538 };
539 }; 539 };
540 540
541 eeprom@50 { 541 eeprom@50 {
542 compatible = "atmel,24c02"; 542 compatible = "atmel,24c02";
543 reg = <0x50>; 543 reg = <0x50>;
544 pagesize = <16>; 544 pagesize = <16>;
545 }; 545 };
546 546
547 eeprom@51 { 547 eeprom@51 {
548 compatible = "atmel,24c02"; 548 compatible = "atmel,24c02";
549 reg = <0x51>; 549 reg = <0x51>;
550 pagesize = <16>; 550 pagesize = <16>;
551 }; 551 };
552 552
553 eeprom@52 { 553 eeprom@52 {
554 compatible = "atmel,24c02"; 554 compatible = "atmel,24c02";
555 reg = <0x52>; 555 reg = <0x52>;
556 pagesize = <16>; 556 pagesize = <16>;
557 }; 557 };
558 558
559 eeprom@53 { 559 eeprom@53 {
560 compatible = "atmel,24c02"; 560 compatible = "atmel,24c02";
561 reg = <0x53>; 561 reg = <0x53>;
562 pagesize = <16>; 562 pagesize = <16>;
563 }; 563 };
564 564
565 rtc@68 { 565 rtc@68 {
566 compatible = "dallas,ds1672"; 566 compatible = "dallas,ds1672";
567 reg = <0x68>; 567 reg = <0x68>;
568 }; 568 };
569 }; 569 };
570 570
571 &i2c2 { 571 &i2c2 {
572 clock-frequency = <400000>; 572 clock-frequency = <400000>;
573 pinctrl-names = "default", "gpio"; 573 pinctrl-names = "default", "gpio";
574 pinctrl-0 = <&pinctrl_i2c2>; 574 pinctrl-0 = <&pinctrl_i2c2>;
575 pinctrl-1 = <&pinctrl_i2c2_gpio>; 575 pinctrl-1 = <&pinctrl_i2c2_gpio>;
576 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 576 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
577 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 577 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
578 status = "okay"; 578 status = "okay";
579 579
580 accelerometer@19 { 580 accelerometer@19 {
581 compatible = "st,lis2de12"; 581 compatible = "st,lis2de12";
582 pinctrl-names = "default"; 582 pinctrl-names = "default";
583 pinctrl-0 = <&pinctrl_accel>; 583 pinctrl-0 = <&pinctrl_accel>;
584 reg = <0x19>; 584 reg = <0x19>;
585 st,drdy-int-pin = <1>; 585 st,drdy-int-pin = <1>;
586 interrupt-parent = <&gpio1>; 586 interrupt-parent = <&gpio1>;
587 interrupts = <12 IRQ_TYPE_LEVE 587 interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
588 }; 588 };
589 }; 589 };
590 590
591 /* off-board header */ 591 /* off-board header */
592 &i2c3 { 592 &i2c3 {
593 clock-frequency = <400000>; 593 clock-frequency = <400000>;
594 pinctrl-names = "default", "gpio"; 594 pinctrl-names = "default", "gpio";
595 pinctrl-0 = <&pinctrl_i2c3>; 595 pinctrl-0 = <&pinctrl_i2c3>;
596 pinctrl-1 = <&pinctrl_i2c3_gpio>; 596 pinctrl-1 = <&pinctrl_i2c3_gpio>;
597 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 597 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
598 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 598 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
599 status = "okay"; 599 status = "okay";
600 }; 600 };
601 601
602 /* off-board header */ 602 /* off-board header */
603 &i2c4 { 603 &i2c4 {
604 clock-frequency = <400000>; 604 clock-frequency = <400000>;
605 pinctrl-names = "default", "gpio"; 605 pinctrl-names = "default", "gpio";
606 pinctrl-0 = <&pinctrl_i2c4>; 606 pinctrl-0 = <&pinctrl_i2c4>;
607 pinctrl-1 = <&pinctrl_i2c4_gpio>; 607 pinctrl-1 = <&pinctrl_i2c4_gpio>;
608 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 608 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
609 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 609 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
610 status = "okay"; 610 status = "okay";
611 }; 611 };
612 612
613 &pgc_gpumix { 613 &pgc_gpumix {
614 status = "disabled"; 614 status = "disabled";
615 }; 615 };
616 616
617 /* off-board header */ 617 /* off-board header */
618 &sai3 { 618 &sai3 {
619 pinctrl-names = "default"; 619 pinctrl-names = "default";
620 pinctrl-0 = <&pinctrl_sai3>; 620 pinctrl-0 = <&pinctrl_sai3>;
621 assigned-clocks = <&clk IMX8MN_CLK_SAI 621 assigned-clocks = <&clk IMX8MN_CLK_SAI3>;
622 assigned-clock-parents = <&clk IMX8MN_ 622 assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>;
623 assigned-clock-rates = <24576000>; 623 assigned-clock-rates = <24576000>;
624 status = "okay"; 624 status = "okay";
625 }; 625 };
626 626
627 /* RS232/RS485/RS422 selectable */ 627 /* RS232/RS485/RS422 selectable */
628 &uart1 { 628 &uart1 {
629 pinctrl-names = "default"; 629 pinctrl-names = "default";
630 pinctrl-0 = <&pinctrl_uart1>, <&pinctr 630 pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart1_gpio>;
631 status = "okay"; 631 status = "okay";
632 }; 632 };
633 633
634 /* RS232 console */ 634 /* RS232 console */
635 &uart2 { 635 &uart2 {
636 pinctrl-names = "default"; 636 pinctrl-names = "default";
637 pinctrl-0 = <&pinctrl_uart2>; 637 pinctrl-0 = <&pinctrl_uart2>;
638 status = "okay"; 638 status = "okay";
639 }; 639 };
640 640
641 /* bluetooth HCI */ 641 /* bluetooth HCI */
642 &uart3 { 642 &uart3 {
643 pinctrl-names = "default"; 643 pinctrl-names = "default";
644 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 644 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
645 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW> 645 rts-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
646 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW> 646 cts-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
647 status = "okay"; 647 status = "okay";
648 648
649 bluetooth { 649 bluetooth {
650 compatible = "brcm,bcm4330-bt" 650 compatible = "brcm,bcm4330-bt";
651 shutdown-gpios = <&gpio2 12 GP 651 shutdown-gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
652 }; 652 };
653 }; 653 };
654 654
655 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading 655 /* LTE Cat M1/NB1/EGPRS modem or GPS (loading option) */
656 &uart4 { 656 &uart4 {
657 pinctrl-names = "default"; 657 pinctrl-names = "default";
658 pinctrl-0 = <&pinctrl_uart4>; 658 pinctrl-0 = <&pinctrl_uart4>;
659 status = "okay"; 659 status = "okay";
660 }; 660 };
661 661
662 &usbotg1 { 662 &usbotg1 {
663 dr_mode = "host"; 663 dr_mode = "host";
664 vbus-supply = <®_usb1_vbus>; 664 vbus-supply = <®_usb1_vbus>;
665 disable-over-current; 665 disable-over-current;
666 status = "okay"; 666 status = "okay";
667 }; 667 };
668 668
669 /* SDIO WiFi */ 669 /* SDIO WiFi */
670 &usdhc2 { 670 &usdhc2 {
671 pinctrl-names = "default", "state_100m 671 pinctrl-names = "default", "state_100mhz", "state_200mhz";
672 pinctrl-0 = <&pinctrl_usdhc2>; 672 pinctrl-0 = <&pinctrl_usdhc2>;
673 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 673 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
674 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 674 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
675 bus-width = <4>; 675 bus-width = <4>;
676 non-removable; 676 non-removable;
677 vmmc-supply = <®_wifi>; 677 vmmc-supply = <®_wifi>;
678 #address-cells = <1>; 678 #address-cells = <1>;
679 #size-cells = <0>; 679 #size-cells = <0>;
680 status = "okay"; 680 status = "okay";
681 681
682 wifi@0 { 682 wifi@0 {
683 compatible = "brcm,bcm43455-fm 683 compatible = "brcm,bcm43455-fmac", "brcm,bcm4329-fmac";
684 reg = <0>; 684 reg = <0>;
685 }; 685 };
686 }; 686 };
687 687
688 /* eMMC */ 688 /* eMMC */
689 &usdhc3 { 689 &usdhc3 {
690 pinctrl-names = "default", "state_100m 690 pinctrl-names = "default", "state_100mhz", "state_200mhz";
691 pinctrl-0 = <&pinctrl_usdhc3>; 691 pinctrl-0 = <&pinctrl_usdhc3>;
692 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 692 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
693 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 693 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
694 bus-width = <8>; 694 bus-width = <8>;
695 non-removable; 695 non-removable;
696 status = "okay"; 696 status = "okay";
697 }; 697 };
698 698
699 &wdog1 { 699 &wdog1 {
700 pinctrl-names = "default"; 700 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_wdog>; 701 pinctrl-0 = <&pinctrl_wdog>;
702 fsl,ext-reset-output; 702 fsl,ext-reset-output;
703 status = "okay"; 703 status = "okay";
704 }; 704 };
705 705
706 &iomuxc { 706 &iomuxc {
707 pinctrl-names = "default"; 707 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_hog>; 708 pinctrl-0 = <&pinctrl_hog>;
709 709
710 pinctrl_hog: hoggrp { 710 pinctrl_hog: hoggrp {
711 fsl,pins = < 711 fsl,pins = <
712 MX8MN_IOMUXC_NAND_CE0_ 712 MX8MN_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x40000159 /* M2_GDIS# */
713 MX8MN_IOMUXC_GPIO1_IO0 713 MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x40000041 /* M2_PWR_EN */
714 MX8MN_IOMUXC_GPIO1_IO1 714 MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x40000041 /* M2_RESET */
715 MX8MN_IOMUXC_NAND_DATA 715 MX8MN_IOMUXC_NAND_DATA01_GPIO3_IO7 0x40000119 /* M2_OFF# */
716 MX8MN_IOMUXC_GPIO1_IO1 716 MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x40000159 /* M2_WDIS# */
717 MX8MN_IOMUXC_SAI2_RXFS 717 MX8MN_IOMUXC_SAI2_RXFS_GPIO4_IO21 0x40000041 /* APP GPIO1 */
718 MX8MN_IOMUXC_SAI2_RXC_ 718 MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22 0x40000041 /* VDD_4P0_EN */
719 MX8MN_IOMUXC_SAI2_MCLK 719 MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x40000041 /* APP GPIO2 */
720 MX8MN_IOMUXC_SD1_DATA6 720 MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8 0x40000041 /* UART2_EN# */
721 MX8MN_IOMUXC_SAI3_RXFS 721 MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x40000041 /* MIPI_GPIO1 */
722 MX8MN_IOMUXC_SPDIF_EXT 722 MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x40000041 /* MIPI_GPIO2 */
723 MX8MN_IOMUXC_SPDIF_RX_ 723 MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4 0x40000041 /* MIPI_GPIO3/PWM2 */
724 MX8MN_IOMUXC_SPDIF_TX_ 724 MX8MN_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* MIPI_GPIO4/PWM3 */
725 >; 725 >;
726 }; 726 };
727 727
728 pinctrl_accel: accelgrp { 728 pinctrl_accel: accelgrp {
729 fsl,pins = < 729 fsl,pins = <
730 MX8MN_IOMUXC_GPIO1_IO1 730 MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x159
731 >; 731 >;
732 }; 732 };
733 733
734 pinctrl_fec1: fec1grp { 734 pinctrl_fec1: fec1grp {
735 fsl,pins = < 735 fsl,pins = <
736 MX8MN_IOMUXC_ENET_MDC_ 736 MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
737 MX8MN_IOMUXC_ENET_MDIO 737 MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
738 MX8MN_IOMUXC_ENET_TD3_ 738 MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
739 MX8MN_IOMUXC_ENET_TD2_ 739 MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
740 MX8MN_IOMUXC_ENET_TD1_ 740 MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
741 MX8MN_IOMUXC_ENET_TD0_ 741 MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
742 MX8MN_IOMUXC_ENET_RD3_ 742 MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
743 MX8MN_IOMUXC_ENET_RD2_ 743 MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
744 MX8MN_IOMUXC_ENET_RD1_ 744 MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
745 MX8MN_IOMUXC_ENET_RD0_ 745 MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
746 MX8MN_IOMUXC_ENET_TXC_ 746 MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
747 MX8MN_IOMUXC_ENET_RXC_ 747 MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
748 MX8MN_IOMUXC_ENET_RX_C 748 MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
749 MX8MN_IOMUXC_ENET_TX_C 749 MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
750 MX8MN_IOMUXC_GPIO1_IO1 750 MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* RST# */
751 MX8MN_IOMUXC_GPIO1_IO1 751 MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x19 /* IRQ# */
752 >; 752 >;
753 }; 753 };
754 754
755 pinctrl_gsc: gscgrp { 755 pinctrl_gsc: gscgrp {
756 fsl,pins = < 756 fsl,pins = <
757 MX8MN_IOMUXC_SD1_DATA4 757 MX8MN_IOMUXC_SD1_DATA4_GPIO2_IO6 0x40
758 >; 758 >;
759 }; 759 };
760 760
761 pinctrl_i2c1: i2c1grp { 761 pinctrl_i2c1: i2c1grp {
762 fsl,pins = < 762 fsl,pins = <
763 MX8MN_IOMUXC_I2C1_SCL_ 763 MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
764 MX8MN_IOMUXC_I2C1_SDA_ 764 MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
765 >; 765 >;
766 }; 766 };
767 767
768 pinctrl_i2c1_gpio: i2c1gpiogrp { 768 pinctrl_i2c1_gpio: i2c1gpiogrp {
769 fsl,pins = < 769 fsl,pins = <
770 MX8MN_IOMUXC_I2C1_SCL_ 770 MX8MN_IOMUXC_I2C1_SCL_GPIO5_IO14 0x400001c3
771 MX8MN_IOMUXC_I2C1_SDA_ 771 MX8MN_IOMUXC_I2C1_SDA_GPIO5_IO15 0x400001c3
772 >; 772 >;
773 }; 773 };
774 774
775 pinctrl_i2c2: i2c2grp { 775 pinctrl_i2c2: i2c2grp {
776 fsl,pins = < 776 fsl,pins = <
777 MX8MN_IOMUXC_I2C2_SCL_ 777 MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
778 MX8MN_IOMUXC_I2C2_SDA_ 778 MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
779 >; 779 >;
780 }; 780 };
781 781
782 pinctrl_i2c2_gpio: i2c2gpiogrp { 782 pinctrl_i2c2_gpio: i2c2gpiogrp {
783 fsl,pins = < 783 fsl,pins = <
784 MX8MN_IOMUXC_I2C2_SCL_ 784 MX8MN_IOMUXC_I2C2_SCL_GPIO5_IO16 0x400001c3
785 MX8MN_IOMUXC_I2C2_SDA_ 785 MX8MN_IOMUXC_I2C2_SDA_GPIO5_IO17 0x400001c3
786 >; 786 >;
787 }; 787 };
788 788
789 pinctrl_i2c3: i2c3grp { 789 pinctrl_i2c3: i2c3grp {
790 fsl,pins = < 790 fsl,pins = <
791 MX8MN_IOMUXC_I2C3_SCL_ 791 MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
792 MX8MN_IOMUXC_I2C3_SDA_ 792 MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
793 >; 793 >;
794 }; 794 };
795 795
796 pinctrl_i2c3_gpio: i2c3gpiogrp { 796 pinctrl_i2c3_gpio: i2c3gpiogrp {
797 fsl,pins = < 797 fsl,pins = <
798 MX8MN_IOMUXC_I2C3_SCL_ 798 MX8MN_IOMUXC_I2C3_SCL_GPIO5_IO18 0x400001c3
799 MX8MN_IOMUXC_I2C3_SDA_ 799 MX8MN_IOMUXC_I2C3_SDA_GPIO5_IO19 0x400001c3
800 >; 800 >;
801 }; 801 };
802 802
803 pinctrl_i2c4: i2c4grp { 803 pinctrl_i2c4: i2c4grp {
804 fsl,pins = < 804 fsl,pins = <
805 MX8MN_IOMUXC_I2C4_SCL_ 805 MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
806 MX8MN_IOMUXC_I2C4_SDA_ 806 MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
807 >; 807 >;
808 }; 808 };
809 809
810 pinctrl_i2c4_gpio: i2c4gpiogrp { 810 pinctrl_i2c4_gpio: i2c4gpiogrp {
811 fsl,pins = < 811 fsl,pins = <
812 MX8MN_IOMUXC_I2C4_SCL_ 812 MX8MN_IOMUXC_I2C4_SCL_GPIO5_IO20 0x400001c3
813 MX8MN_IOMUXC_I2C4_SDA_ 813 MX8MN_IOMUXC_I2C4_SDA_GPIO5_IO21 0x400001c3
814 >; 814 >;
815 }; 815 };
816 816
817 pinctrl_gpio_leds: gpioledgrp { 817 pinctrl_gpio_leds: gpioledgrp {
818 fsl,pins = < 818 fsl,pins = <
819 MX8MN_IOMUXC_SAI5_RXD0 819 MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x19
820 MX8MN_IOMUXC_SAI5_RXD2 820 MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x19
821 MX8MN_IOMUXC_SAI5_RXD1 821 MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x19
822 MX8MN_IOMUXC_SAI5_RXC_ 822 MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x19
823 MX8MN_IOMUXC_SAI5_MCLK 823 MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x19
824 >; 824 >;
825 }; 825 };
826 826
827 pinctrl_pmic: pmicgrp { 827 pinctrl_pmic: pmicgrp {
828 fsl,pins = < 828 fsl,pins = <
829 MX8MN_IOMUXC_NAND_DATA 829 MX8MN_IOMUXC_NAND_DATA02_GPIO3_IO8 0x41
830 >; 830 >;
831 }; 831 };
832 832
833 pinctrl_pps: ppsgrp { 833 pinctrl_pps: ppsgrp {
834 fsl,pins = < 834 fsl,pins = <
835 MX8MN_IOMUXC_SAI5_RXD3 835 MX8MN_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x141 /* PPS */
836 >; 836 >;
837 }; 837 };
838 838
839 pinctrl_reg_wl: regwlgrp { 839 pinctrl_reg_wl: regwlgrp {
840 fsl,pins = < 840 fsl,pins = <
841 MX8MN_IOMUXC_SD2_RESET 841 MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 /* WLAN_WLON */
842 >; 842 >;
843 }; 843 };
844 844
845 pinctrl_reg_usb1: regusb1grp { 845 pinctrl_reg_usb1: regusb1grp {
846 fsl,pins = < 846 fsl,pins = <
847 MX8MN_IOMUXC_SD1_DATA5 847 MX8MN_IOMUXC_SD1_DATA5_GPIO2_IO7 0x41
848 >; 848 >;
849 }; 849 };
850 850
851 pinctrl_sai3: sai3grp { 851 pinctrl_sai3: sai3grp {
852 fsl,pins = < 852 fsl,pins = <
853 MX8MN_IOMUXC_SAI3_MCLK 853 MX8MN_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
854 MX8MN_IOMUXC_SAI3_RXD_ 854 MX8MN_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
855 MX8MN_IOMUXC_SAI3_TXC_ 855 MX8MN_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
856 MX8MN_IOMUXC_SAI3_TXD_ 856 MX8MN_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
857 MX8MN_IOMUXC_SAI3_TXFS 857 MX8MN_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
858 >; 858 >;
859 }; 859 };
860 860
861 pinctrl_spi1: spi1grp { 861 pinctrl_spi1: spi1grp {
862 fsl,pins = < 862 fsl,pins = <
863 MX8MN_IOMUXC_ECSPI1_SC 863 MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82
864 MX8MN_IOMUXC_ECSPI1_MO 864 MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82
865 MX8MN_IOMUXC_ECSPI1_MI 865 MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82
866 MX8MN_IOMUXC_ECSPI1_SS 866 MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x40
867 MX8MN_IOMUXC_SD1_DATA1 867 MX8MN_IOMUXC_SD1_DATA1_GPIO2_IO3 0x140 /* CAN_IRQ# */
868 >; 868 >;
869 }; 869 };
870 870
871 pinctrl_spi2: spi2grp { 871 pinctrl_spi2: spi2grp {
872 fsl,pins = < 872 fsl,pins = <
873 MX8MN_IOMUXC_ECSPI2_SC 873 MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x82
874 MX8MN_IOMUXC_ECSPI2_MO 874 MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x82
875 MX8MN_IOMUXC_ECSPI2_MI 875 MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x82
876 MX8MN_IOMUXC_ECSPI2_SS 876 MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x40 /* SS0 */
877 >; 877 >;
878 }; 878 };
879 879
880 pinctrl_uart1: uart1grp { 880 pinctrl_uart1: uart1grp {
881 fsl,pins = < 881 fsl,pins = <
882 MX8MN_IOMUXC_UART1_RXD 882 MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
883 MX8MN_IOMUXC_UART1_TXD 883 MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
884 >; 884 >;
885 }; 885 };
886 886
887 pinctrl_uart1_gpio: uart1gpiogrp { 887 pinctrl_uart1_gpio: uart1gpiogrp {
888 fsl,pins = < 888 fsl,pins = <
889 MX8MN_IOMUXC_SAI2_TXD0 889 MX8MN_IOMUXC_SAI2_TXD0_GPIO4_IO26 0x40000110 /* HALF */
890 MX8MN_IOMUXC_SAI2_TXC_ 890 MX8MN_IOMUXC_SAI2_TXC_GPIO4_IO25 0x40000110 /* TERM */
891 MX8MN_IOMUXC_SAI2_RXD0 891 MX8MN_IOMUXC_SAI2_RXD0_GPIO4_IO23 0x40000110 /* RS485 */
892 >; 892 >;
893 }; 893 };
894 894
895 pinctrl_uart2: uart2grp { 895 pinctrl_uart2: uart2grp {
896 fsl,pins = < 896 fsl,pins = <
897 MX8MN_IOMUXC_UART2_RXD 897 MX8MN_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
898 MX8MN_IOMUXC_UART2_TXD 898 MX8MN_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
899 >; 899 >;
900 }; 900 };
901 901
902 pinctrl_uart3_gpio: uart3_gpiogrp { 902 pinctrl_uart3_gpio: uart3_gpiogrp {
903 fsl,pins = < 903 fsl,pins = <
904 MX8MN_IOMUXC_SD2_CD_B_ 904 MX8MN_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 /* BT_EN# */
905 >; 905 >;
906 }; 906 };
907 907
908 pinctrl_uart3: uart3grp { 908 pinctrl_uart3: uart3grp {
909 fsl,pins = < 909 fsl,pins = <
910 MX8MN_IOMUXC_UART3_RXD 910 MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140
911 MX8MN_IOMUXC_UART3_TXD 911 MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140
912 MX8MN_IOMUXC_SD1_CLK_G 912 MX8MN_IOMUXC_SD1_CLK_GPIO2_IO0 0x140 /* CTS */
913 MX8MN_IOMUXC_SD1_CMD_G 913 MX8MN_IOMUXC_SD1_CMD_GPIO2_IO1 0x140 /* RTS */
914 >; 914 >;
915 }; 915 };
916 916
917 pinctrl_uart4: uart4grp { 917 pinctrl_uart4: uart4grp {
918 fsl,pins = < 918 fsl,pins = <
919 MX8MN_IOMUXC_UART4_RXD 919 MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX 0x140
920 MX8MN_IOMUXC_UART4_TXD 920 MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX 0x140
921 MX8MN_IOMUXC_GPIO1_IO0 921 MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x141 /* GNSS_GASP */
922 >; 922 >;
923 }; 923 };
924 924
925 pinctrl_usdhc2: usdhc2grp { 925 pinctrl_usdhc2: usdhc2grp {
926 fsl,pins = < 926 fsl,pins = <
927 MX8MN_IOMUXC_SD2_CLK_U 927 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
928 MX8MN_IOMUXC_SD2_CMD_U 928 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
929 MX8MN_IOMUXC_SD2_DATA0 929 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
930 MX8MN_IOMUXC_SD2_DATA1 930 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
931 MX8MN_IOMUXC_SD2_DATA2 931 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
932 MX8MN_IOMUXC_SD2_DATA3 932 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
933 >; 933 >;
934 }; 934 };
935 935
936 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 936 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
937 fsl,pins = < 937 fsl,pins = <
938 MX8MN_IOMUXC_SD2_CLK_U 938 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
939 MX8MN_IOMUXC_SD2_CMD_U 939 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
940 MX8MN_IOMUXC_SD2_DATA0 940 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
941 MX8MN_IOMUXC_SD2_DATA1 941 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
942 MX8MN_IOMUXC_SD2_DATA2 942 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
943 MX8MN_IOMUXC_SD2_DATA3 943 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
944 >; 944 >;
945 }; 945 };
946 946
947 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 947 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
948 fsl,pins = < 948 fsl,pins = <
949 MX8MN_IOMUXC_SD2_CLK_U 949 MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
950 MX8MN_IOMUXC_SD2_CMD_U 950 MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
951 MX8MN_IOMUXC_SD2_DATA0 951 MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
952 MX8MN_IOMUXC_SD2_DATA1 952 MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
953 MX8MN_IOMUXC_SD2_DATA2 953 MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
954 MX8MN_IOMUXC_SD2_DATA3 954 MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
955 >; 955 >;
956 }; 956 };
957 957
958 pinctrl_usdhc3: usdhc3grp { 958 pinctrl_usdhc3: usdhc3grp {
959 fsl,pins = < 959 fsl,pins = <
960 MX8MN_IOMUXC_NAND_WE_B 960 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
961 MX8MN_IOMUXC_NAND_WP_B 961 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
962 MX8MN_IOMUXC_NAND_DATA 962 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
963 MX8MN_IOMUXC_NAND_DATA 963 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
964 MX8MN_IOMUXC_NAND_DATA 964 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
965 MX8MN_IOMUXC_NAND_DATA 965 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
966 MX8MN_IOMUXC_NAND_RE_B 966 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
967 MX8MN_IOMUXC_NAND_CE2_ 967 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
968 MX8MN_IOMUXC_NAND_CE3_ 968 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
969 MX8MN_IOMUXC_NAND_CLE_ 969 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
970 MX8MN_IOMUXC_NAND_CE1_ 970 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
971 >; 971 >;
972 }; 972 };
973 973
974 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 974 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
975 fsl,pins = < 975 fsl,pins = <
976 MX8MN_IOMUXC_NAND_WE_B 976 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
977 MX8MN_IOMUXC_NAND_WP_B 977 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
978 MX8MN_IOMUXC_NAND_DATA 978 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
979 MX8MN_IOMUXC_NAND_DATA 979 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
980 MX8MN_IOMUXC_NAND_DATA 980 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
981 MX8MN_IOMUXC_NAND_DATA 981 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
982 MX8MN_IOMUXC_NAND_RE_B 982 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
983 MX8MN_IOMUXC_NAND_CE2_ 983 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
984 MX8MN_IOMUXC_NAND_CE3_ 984 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
985 MX8MN_IOMUXC_NAND_CLE_ 985 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
986 MX8MN_IOMUXC_NAND_CE1_ 986 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
987 >; 987 >;
988 }; 988 };
989 989
990 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 990 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
991 fsl,pins = < 991 fsl,pins = <
992 MX8MN_IOMUXC_NAND_WE_B 992 MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
993 MX8MN_IOMUXC_NAND_WP_B 993 MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
994 MX8MN_IOMUXC_NAND_DATA 994 MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
995 MX8MN_IOMUXC_NAND_DATA 995 MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
996 MX8MN_IOMUXC_NAND_DATA 996 MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
997 MX8MN_IOMUXC_NAND_DATA 997 MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
998 MX8MN_IOMUXC_NAND_RE_B 998 MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
999 MX8MN_IOMUXC_NAND_CE2_ 999 MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
1000 MX8MN_IOMUXC_NAND_CE3 1000 MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
1001 MX8MN_IOMUXC_NAND_CLE 1001 MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
1002 MX8MN_IOMUXC_NAND_CE1 1002 MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
1003 >; 1003 >;
1004 }; 1004 };
1005 1005
1006 pinctrl_wdog: wdoggrp { 1006 pinctrl_wdog: wdoggrp {
1007 fsl,pins = < 1007 fsl,pins = <
1008 MX8MN_IOMUXC_GPIO1_IO 1008 MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
1009 >; 1009 >;
1010 }; 1010 };
1011 }; 1011 };
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