1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 * Copyright (C) 2023 Pengutronix, Marco Felsc< 4 * Copyright (C) 2023 Pengutronix, Marco Felsch <kernel@pengutronix.de>
5 */ 5 */
6 6
7 #include "imx8mp.dtsi" 7 #include "imx8mp.dtsi"
8 8
9 #include <dt-bindings/leds/common.h> 9 #include <dt-bindings/leds/common.h>
10 10
11 / { 11 / {
12 model = "Polyhex i.MX8MPlus Debix SOM 12 model = "Polyhex i.MX8MPlus Debix SOM A";
13 compatible = "polyhex,imx8mp-debix-som 13 compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp";
14 14
15 reg_usdhc2_vmmc: regulator-usdhc2 { 15 reg_usdhc2_vmmc: regulator-usdhc2 {
16 compatible = "regulator-fixed" 16 compatible = "regulator-fixed";
17 pinctrl-names = "default"; 17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_reg_usdh 18 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
19 regulator-name = "VSD_3V3"; 19 regulator-name = "VSD_3V3";
20 regulator-min-microvolt = <330 20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <330 21 regulator-max-microvolt = <3300000>;
22 gpio = <&gpio2 19 GPIO_ACTIVE_ 22 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
23 enable-active-high; 23 enable-active-high;
24 }; 24 };
25 25
26 gpio-leds { 26 gpio-leds {
27 compatible = "gpio-leds"; 27 compatible = "gpio-leds";
28 pinctrl-names = "default"; 28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_gpio_led 29 pinctrl-0 = <&pinctrl_gpio_led>;
30 30
31 led-0 { 31 led-0 {
32 gpios = <&gpio3 16 GPI 32 gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
33 default-state = "on"; 33 default-state = "on";
34 linux,default-trigger 34 linux,default-trigger = "heartbeat";
35 function = LED_FUNCTIO 35 function = LED_FUNCTION_STATUS;
36 color = <LED_COLOR_ID_ 36 color = <LED_COLOR_ID_GREEN>;
37 }; 37 };
38 }; 38 };
39 }; 39 };
40 40
41 &A53_0 { 41 &A53_0 {
42 cpu-supply = <&buck2>; 42 cpu-supply = <&buck2>;
43 }; 43 };
44 44
45 &A53_1 { 45 &A53_1 {
46 cpu-supply = <&buck2>; 46 cpu-supply = <&buck2>;
47 }; 47 };
48 48
49 &A53_2 { 49 &A53_2 {
50 cpu-supply = <&buck2>; 50 cpu-supply = <&buck2>;
51 }; 51 };
52 52
53 &A53_3 { 53 &A53_3 {
54 cpu-supply = <&buck2>; 54 cpu-supply = <&buck2>;
55 }; 55 };
56 56
57 &i2c1 { 57 &i2c1 {
58 clock-frequency = <400000>; 58 clock-frequency = <400000>;
59 pinctrl-names = "default"; 59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_i2c1>; 60 pinctrl-0 = <&pinctrl_i2c1>;
61 status = "okay"; 61 status = "okay";
62 62
63 pmic@25 { 63 pmic@25 {
64 compatible = "nxp,pca9450c"; 64 compatible = "nxp,pca9450c";
65 reg = <0x25>; 65 reg = <0x25>;
66 pinctrl-names = "default"; 66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_pmic>; 67 pinctrl-0 = <&pinctrl_pmic>;
68 interrupt-parent = <&gpio1>; 68 interrupt-parent = <&gpio1>;
69 interrupts = <3 IRQ_TYPE_LEVEL 69 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
70 70
71 regulators { 71 regulators {
72 buck1: BUCK1 { 72 buck1: BUCK1 {
73 regulator-name 73 regulator-name = "BUCK1";
74 regulator-min- 74 regulator-min-microvolt = <600000>;
75 regulator-max- 75 regulator-max-microvolt = <2187500>;
76 regulator-boot 76 regulator-boot-on;
77 regulator-alwa 77 regulator-always-on;
78 regulator-ramp 78 regulator-ramp-delay = <3125>;
79 }; 79 };
80 80
81 buck2: BUCK2 { 81 buck2: BUCK2 {
82 regulator-name 82 regulator-name = "BUCK2";
83 regulator-min- 83 regulator-min-microvolt = <600000>;
84 regulator-max- 84 regulator-max-microvolt = <2187500>;
85 regulator-boot 85 regulator-boot-on;
86 regulator-alwa 86 regulator-always-on;
87 regulator-ramp 87 regulator-ramp-delay = <3125>;
88 nxp,dvs-run-vo 88 nxp,dvs-run-voltage = <950000>;
89 nxp,dvs-standb 89 nxp,dvs-standby-voltage = <850000>;
90 }; 90 };
91 91
92 buck4: BUCK4 { 92 buck4: BUCK4 {
93 regulator-name 93 regulator-name = "BUCK4";
94 regulator-min- 94 regulator-min-microvolt = <600000>;
95 regulator-max- 95 regulator-max-microvolt = <3400000>;
96 regulator-boot 96 regulator-boot-on;
97 regulator-alwa 97 regulator-always-on;
98 }; 98 };
99 99
100 buck5: BUCK5 { 100 buck5: BUCK5 {
101 regulator-name 101 regulator-name = "BUCK5";
102 regulator-min- 102 regulator-min-microvolt = <600000>;
103 regulator-max- 103 regulator-max-microvolt = <3400000>;
104 regulator-boot 104 regulator-boot-on;
105 regulator-alwa 105 regulator-always-on;
106 }; 106 };
107 107
108 buck6: BUCK6 { 108 buck6: BUCK6 {
109 regulator-name 109 regulator-name = "BUCK6";
110 regulator-min- 110 regulator-min-microvolt = <600000>;
111 regulator-max- 111 regulator-max-microvolt = <3400000>;
112 regulator-boot 112 regulator-boot-on;
113 regulator-alwa 113 regulator-always-on;
114 }; 114 };
115 115
116 ldo1: LDO1 { 116 ldo1: LDO1 {
117 regulator-name 117 regulator-name = "LDO1";
118 regulator-min- 118 regulator-min-microvolt = <1600000>;
119 regulator-max- 119 regulator-max-microvolt = <3300000>;
120 regulator-boot 120 regulator-boot-on;
121 regulator-alwa 121 regulator-always-on;
122 }; 122 };
123 123
124 ldo2: LDO2 { 124 ldo2: LDO2 {
125 regulator-name 125 regulator-name = "LDO2";
126 regulator-min- 126 regulator-min-microvolt = <800000>;
127 regulator-max- 127 regulator-max-microvolt = <1150000>;
128 regulator-boot 128 regulator-boot-on;
129 regulator-alwa 129 regulator-always-on;
130 }; 130 };
131 131
132 ldo3: LDO3 { 132 ldo3: LDO3 {
133 regulator-name 133 regulator-name = "LDO3";
134 regulator-min- 134 regulator-min-microvolt = <800000>;
135 regulator-max- 135 regulator-max-microvolt = <3300000>;
136 regulator-boot 136 regulator-boot-on;
137 regulator-alwa 137 regulator-always-on;
138 }; 138 };
139 139
140 ldo4: LDO4 { 140 ldo4: LDO4 {
141 regulator-name 141 regulator-name = "LDO4";
142 regulator-min- 142 regulator-min-microvolt = <800000>;
143 regulator-max- 143 regulator-max-microvolt = <3300000>;
144 regulator-boot 144 regulator-boot-on;
145 regulator-alwa 145 regulator-always-on;
146 }; 146 };
147 147
148 ldo5: LDO5 { 148 ldo5: LDO5 {
149 regulator-name 149 regulator-name = "LDO5";
150 regulator-min- 150 regulator-min-microvolt = <1800000>;
151 regulator-max- 151 regulator-max-microvolt = <3300000>;
152 regulator-boot 152 regulator-boot-on;
153 regulator-alwa 153 regulator-always-on;
154 }; 154 };
155 }; 155 };
156 }; 156 };
157 }; 157 };
158 158
159 &i2c4 { 159 &i2c4 {
160 clock-frequency = <400000>; 160 clock-frequency = <400000>;
161 pinctrl-names = "default"; 161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_i2c4>; 162 pinctrl-0 = <&pinctrl_i2c4>;
163 status = "okay"; 163 status = "okay";
164 164
165 adc@48 { 165 adc@48 {
166 compatible = "ti,ads1115"; 166 compatible = "ti,ads1115";
167 reg = <0x48>; 167 reg = <0x48>;
168 #address-cells = <1>; 168 #address-cells = <1>;
169 #size-cells = <0>; 169 #size-cells = <0>;
170 170
171 channel@4 { 171 channel@4 {
172 reg = <4>; 172 reg = <4>;
173 ti,gain = <1>; 173 ti,gain = <1>;
174 ti,datarate = <7>; 174 ti,datarate = <7>;
175 }; 175 };
176 176
177 channel@5 { 177 channel@5 {
178 reg = <5>; 178 reg = <5>;
179 ti,gain = <1>; 179 ti,gain = <1>;
180 ti,datarate = <7>; 180 ti,datarate = <7>;
181 }; 181 };
182 182
183 channel@6 { 183 channel@6 {
184 reg = <6>; 184 reg = <6>;
185 ti,gain = <1>; 185 ti,gain = <1>;
186 ti,datarate = <7>; 186 ti,datarate = <7>;
187 }; 187 };
188 188
189 channel@7 { 189 channel@7 {
190 reg = <7>; 190 reg = <7>;
191 ti,gain = <1>; 191 ti,gain = <1>;
192 ti,datarate = <7>; 192 ti,datarate = <7>;
193 }; 193 };
194 }; 194 };
195 }; 195 };
196 196
197 &snvs_pwrkey { 197 &snvs_pwrkey {
198 status = "okay"; 198 status = "okay";
199 }; 199 };
200 200
201 /* eMMC */ 201 /* eMMC */
202 &usdhc3 { 202 &usdhc3 {
203 pinctrl-names = "default", "state_100m 203 pinctrl-names = "default", "state_100mhz", "state_200mhz";
204 pinctrl-0 = <&pinctrl_usdhc3>; 204 pinctrl-0 = <&pinctrl_usdhc3>;
205 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 205 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
206 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 206 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
207 assigned-clocks = <&clk IMX8MP_CLK_USD 207 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
208 assigned-clock-rates = <400000000>; 208 assigned-clock-rates = <400000000>;
209 bus-width = <8>; 209 bus-width = <8>;
210 non-removable; 210 non-removable;
211 status = "okay"; 211 status = "okay";
212 }; 212 };
213 213
214 &wdog1 { 214 &wdog1 {
215 pinctrl-names = "default"; 215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_wdog>; 216 pinctrl-0 = <&pinctrl_wdog>;
217 fsl,ext-reset-output; 217 fsl,ext-reset-output;
218 status = "okay"; 218 status = "okay";
219 }; 219 };
220 220
221 &iomuxc { 221 &iomuxc {
222 pinctrl_gpio_led: gpioledgrp { 222 pinctrl_gpio_led: gpioledgrp {
223 fsl,pins = < 223 fsl,pins = <
224 MX8MP_IOMUXC_NAND_READ 224 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19
225 >; 225 >;
226 }; 226 };
227 227
228 pinctrl_i2c1: i2c1grp { 228 pinctrl_i2c1: i2c1grp {
229 fsl,pins = < 229 fsl,pins = <
230 MX8MP_IOMUXC_I2C1_SCL_ 230 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
231 MX8MP_IOMUXC_I2C1_SDA_ 231 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
232 >; 232 >;
233 }; 233 };
234 234
235 pinctrl_i2c4: i2c4grp { 235 pinctrl_i2c4: i2c4grp {
236 fsl,pins = < 236 fsl,pins = <
237 MX8MP_IOMUXC_I2C4_SCL_ 237 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3
238 MX8MP_IOMUXC_I2C4_SDA_ 238 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3
239 >; 239 >;
240 }; 240 };
241 241
242 pinctrl_pmic: pmicgrp { 242 pinctrl_pmic: pmicgrp {
243 fsl,pins = < 243 fsl,pins = <
244 MX8MP_IOMUXC_GPIO1_IO0 244 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41
245 >; 245 >;
246 }; 246 };
247 247
248 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 248 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
249 fsl,pins = < 249 fsl,pins = <
250 MX8MP_IOMUXC_SD2_RESET 250 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41
251 >; 251 >;
252 }; 252 };
253 253
254 pinctrl_usdhc3: usdhc3grp { 254 pinctrl_usdhc3: usdhc3grp {
255 fsl,pins = < 255 fsl,pins = <
256 MX8MP_IOMUXC_NAND_WE_B 256 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
257 MX8MP_IOMUXC_NAND_WP_B 257 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
258 MX8MP_IOMUXC_NAND_DATA 258 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
259 MX8MP_IOMUXC_NAND_DATA 259 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
260 MX8MP_IOMUXC_NAND_DATA 260 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
261 MX8MP_IOMUXC_NAND_DATA 261 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
262 MX8MP_IOMUXC_NAND_RE_B 262 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
263 MX8MP_IOMUXC_NAND_CE2_ 263 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
264 MX8MP_IOMUXC_NAND_CE3_ 264 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
265 MX8MP_IOMUXC_NAND_CLE_ 265 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
266 MX8MP_IOMUXC_NAND_CE1_ 266 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
267 >; 267 >;
268 }; 268 };
269 269
270 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr 270 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
271 fsl,pins = < 271 fsl,pins = <
272 MX8MP_IOMUXC_NAND_WE_B 272 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
273 MX8MP_IOMUXC_NAND_WP_B 273 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
274 MX8MP_IOMUXC_NAND_DATA 274 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
275 MX8MP_IOMUXC_NAND_DATA 275 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
276 MX8MP_IOMUXC_NAND_DATA 276 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
277 MX8MP_IOMUXC_NAND_DATA 277 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
278 MX8MP_IOMUXC_NAND_RE_B 278 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
279 MX8MP_IOMUXC_NAND_CE2_ 279 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
280 MX8MP_IOMUXC_NAND_CE3_ 280 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
281 MX8MP_IOMUXC_NAND_CLE_ 281 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
282 MX8MP_IOMUXC_NAND_CE1_ 282 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
283 >; 283 >;
284 }; 284 };
285 285
286 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr 286 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
287 fsl,pins = < 287 fsl,pins = <
288 MX8MP_IOMUXC_NAND_WE_B 288 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
289 MX8MP_IOMUXC_NAND_WP_B 289 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
290 MX8MP_IOMUXC_NAND_DATA 290 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
291 MX8MP_IOMUXC_NAND_DATA 291 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
292 MX8MP_IOMUXC_NAND_DATA 292 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
293 MX8MP_IOMUXC_NAND_DATA 293 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
294 MX8MP_IOMUXC_NAND_RE_B 294 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
295 MX8MP_IOMUXC_NAND_CE2_ 295 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
296 MX8MP_IOMUXC_NAND_CE3_ 296 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
297 MX8MP_IOMUXC_NAND_CLE_ 297 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
298 MX8MP_IOMUXC_NAND_CE1_ 298 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
299 >; 299 >;
300 }; 300 };
301 301
302 pinctrl_wdog: wdoggrp { 302 pinctrl_wdog: wdoggrp {
303 fsl,pins = < 303 fsl,pins = <
304 MX8MP_IOMUXC_GPIO1_IO0 304 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6
305 >; 305 >;
306 }; 306 };
307 }; 307 };
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