1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2019 NXP
4 * Copyright (C) 2023 Pengutronix, Marco Felsc<
5 */
6
7 #include "imx8mp.dtsi"
8
9 #include <dt-bindings/leds/common.h>
10
11 / {
12 model = "Polyhex i.MX8MPlus Debix SOM
13 compatible = "polyhex,imx8mp-debix-som
14
15 reg_usdhc2_vmmc: regulator-usdhc2 {
16 compatible = "regulator-fixed"
17 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_reg_usdh
19 regulator-name = "VSD_3V3";
20 regulator-min-microvolt = <330
21 regulator-max-microvolt = <330
22 gpio = <&gpio2 19 GPIO_ACTIVE_
23 enable-active-high;
24 };
25
26 gpio-leds {
27 compatible = "gpio-leds";
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_gpio_led
30
31 led-0 {
32 gpios = <&gpio3 16 GPI
33 default-state = "on";
34 linux,default-trigger
35 function = LED_FUNCTIO
36 color = <LED_COLOR_ID_
37 };
38 };
39 };
40
41 &A53_0 {
42 cpu-supply = <&buck2>;
43 };
44
45 &A53_1 {
46 cpu-supply = <&buck2>;
47 };
48
49 &A53_2 {
50 cpu-supply = <&buck2>;
51 };
52
53 &A53_3 {
54 cpu-supply = <&buck2>;
55 };
56
57 &i2c1 {
58 clock-frequency = <400000>;
59 pinctrl-names = "default";
60 pinctrl-0 = <&pinctrl_i2c1>;
61 status = "okay";
62
63 pmic@25 {
64 compatible = "nxp,pca9450c";
65 reg = <0x25>;
66 pinctrl-names = "default";
67 pinctrl-0 = <&pinctrl_pmic>;
68 interrupt-parent = <&gpio1>;
69 interrupts = <3 IRQ_TYPE_LEVEL
70
71 regulators {
72 buck1: BUCK1 {
73 regulator-name
74 regulator-min-
75 regulator-max-
76 regulator-boot
77 regulator-alwa
78 regulator-ramp
79 };
80
81 buck2: BUCK2 {
82 regulator-name
83 regulator-min-
84 regulator-max-
85 regulator-boot
86 regulator-alwa
87 regulator-ramp
88 nxp,dvs-run-vo
89 nxp,dvs-standb
90 };
91
92 buck4: BUCK4 {
93 regulator-name
94 regulator-min-
95 regulator-max-
96 regulator-boot
97 regulator-alwa
98 };
99
100 buck5: BUCK5 {
101 regulator-name
102 regulator-min-
103 regulator-max-
104 regulator-boot
105 regulator-alwa
106 };
107
108 buck6: BUCK6 {
109 regulator-name
110 regulator-min-
111 regulator-max-
112 regulator-boot
113 regulator-alwa
114 };
115
116 ldo1: LDO1 {
117 regulator-name
118 regulator-min-
119 regulator-max-
120 regulator-boot
121 regulator-alwa
122 };
123
124 ldo2: LDO2 {
125 regulator-name
126 regulator-min-
127 regulator-max-
128 regulator-boot
129 regulator-alwa
130 };
131
132 ldo3: LDO3 {
133 regulator-name
134 regulator-min-
135 regulator-max-
136 regulator-boot
137 regulator-alwa
138 };
139
140 ldo4: LDO4 {
141 regulator-name
142 regulator-min-
143 regulator-max-
144 regulator-boot
145 regulator-alwa
146 };
147
148 ldo5: LDO5 {
149 regulator-name
150 regulator-min-
151 regulator-max-
152 regulator-boot
153 regulator-alwa
154 };
155 };
156 };
157 };
158
159 &i2c4 {
160 clock-frequency = <400000>;
161 pinctrl-names = "default";
162 pinctrl-0 = <&pinctrl_i2c4>;
163 status = "okay";
164
165 adc@48 {
166 compatible = "ti,ads1115";
167 reg = <0x48>;
168 #address-cells = <1>;
169 #size-cells = <0>;
170
171 channel@4 {
172 reg = <4>;
173 ti,gain = <1>;
174 ti,datarate = <7>;
175 };
176
177 channel@5 {
178 reg = <5>;
179 ti,gain = <1>;
180 ti,datarate = <7>;
181 };
182
183 channel@6 {
184 reg = <6>;
185 ti,gain = <1>;
186 ti,datarate = <7>;
187 };
188
189 channel@7 {
190 reg = <7>;
191 ti,gain = <1>;
192 ti,datarate = <7>;
193 };
194 };
195 };
196
197 &snvs_pwrkey {
198 status = "okay";
199 };
200
201 /* eMMC */
202 &usdhc3 {
203 pinctrl-names = "default", "state_100m
204 pinctrl-0 = <&pinctrl_usdhc3>;
205 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
206 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
207 assigned-clocks = <&clk IMX8MP_CLK_USD
208 assigned-clock-rates = <400000000>;
209 bus-width = <8>;
210 non-removable;
211 status = "okay";
212 };
213
214 &wdog1 {
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_wdog>;
217 fsl,ext-reset-output;
218 status = "okay";
219 };
220
221 &iomuxc {
222 pinctrl_gpio_led: gpioledgrp {
223 fsl,pins = <
224 MX8MP_IOMUXC_NAND_READ
225 >;
226 };
227
228 pinctrl_i2c1: i2c1grp {
229 fsl,pins = <
230 MX8MP_IOMUXC_I2C1_SCL_
231 MX8MP_IOMUXC_I2C1_SDA_
232 >;
233 };
234
235 pinctrl_i2c4: i2c4grp {
236 fsl,pins = <
237 MX8MP_IOMUXC_I2C4_SCL_
238 MX8MP_IOMUXC_I2C4_SDA_
239 >;
240 };
241
242 pinctrl_pmic: pmicgrp {
243 fsl,pins = <
244 MX8MP_IOMUXC_GPIO1_IO0
245 >;
246 };
247
248 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc
249 fsl,pins = <
250 MX8MP_IOMUXC_SD2_RESET
251 >;
252 };
253
254 pinctrl_usdhc3: usdhc3grp {
255 fsl,pins = <
256 MX8MP_IOMUXC_NAND_WE_B
257 MX8MP_IOMUXC_NAND_WP_B
258 MX8MP_IOMUXC_NAND_DATA
259 MX8MP_IOMUXC_NAND_DATA
260 MX8MP_IOMUXC_NAND_DATA
261 MX8MP_IOMUXC_NAND_DATA
262 MX8MP_IOMUXC_NAND_RE_B
263 MX8MP_IOMUXC_NAND_CE2_
264 MX8MP_IOMUXC_NAND_CE3_
265 MX8MP_IOMUXC_NAND_CLE_
266 MX8MP_IOMUXC_NAND_CE1_
267 >;
268 };
269
270 pinctrl_usdhc3_100mhz: usdhc3-100mhzgr
271 fsl,pins = <
272 MX8MP_IOMUXC_NAND_WE_B
273 MX8MP_IOMUXC_NAND_WP_B
274 MX8MP_IOMUXC_NAND_DATA
275 MX8MP_IOMUXC_NAND_DATA
276 MX8MP_IOMUXC_NAND_DATA
277 MX8MP_IOMUXC_NAND_DATA
278 MX8MP_IOMUXC_NAND_RE_B
279 MX8MP_IOMUXC_NAND_CE2_
280 MX8MP_IOMUXC_NAND_CE3_
281 MX8MP_IOMUXC_NAND_CLE_
282 MX8MP_IOMUXC_NAND_CE1_
283 >;
284 };
285
286 pinctrl_usdhc3_200mhz: usdhc3-200mhzgr
287 fsl,pins = <
288 MX8MP_IOMUXC_NAND_WE_B
289 MX8MP_IOMUXC_NAND_WP_B
290 MX8MP_IOMUXC_NAND_DATA
291 MX8MP_IOMUXC_NAND_DATA
292 MX8MP_IOMUXC_NAND_DATA
293 MX8MP_IOMUXC_NAND_DATA
294 MX8MP_IOMUXC_NAND_RE_B
295 MX8MP_IOMUXC_NAND_CE2_
296 MX8MP_IOMUXC_NAND_CE3_
297 MX8MP_IOMUXC_NAND_CLE_
298 MX8MP_IOMUXC_NAND_CE1_
299 >;
300 };
301
302 pinctrl_wdog: wdoggrp {
303 fsl,pins = <
304 MX8MP_IOMUXC_GPIO1_IO0
305 >;
306 };
307 };
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