1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2022 Avnet Embedded GmbH
4 */
5
6 /dts-v1/;
7
8 #include "imx8mp-msc-sm2s-14N0600E.dtsi"
9 #include <dt-bindings/clock/imx8mp-clock.h>
10 #include <dt-bindings/gpio/gpio.h>
11
12 / {
13 model = "MSC SM2-MB-EP1 Carrier Board
14 compatible = "avnet,sm2s-imx8mp-14N060
15 "avnet,sm2s-imx8mp-14N060
16 "fsl,imx8mp";
17
18 reg_vcc_3v3_audio: 3v3-audio-regulator
19 compatible = "regulator-fixed"
20 regulator-name = "VCC_3V3_AUD"
21 regulator-min-microvolt = <330
22 regulator-max-microvolt = <330
23 };
24
25 reg_vcc_1v8_audio: 1v8-audio-regulator
26 compatible = "regulator-fixed"
27 regulator-name = "VCC_1V8_AUD"
28 regulator-min-microvolt = <180
29 regulator-max-microvolt = <180
30 };
31
32 sound {
33 compatible = "simple-audio-car
34 simple-audio-card,name = "sgtl
35 simple-audio-card,format = "i2
36 simple-audio-card,frame-master
37 simple-audio-card,bitclock-mas
38
39 simple-audio-card,cpu {
40 sound-dai = <&sai2>;
41 };
42
43 codec_dai: simple-audio-card,c
44 sound-dai = <&sgtl5000
45 };
46 };
47 };
48
49 &hdmi_pvi {
50 status = "okay";
51 };
52
53 &hdmi_tx {
54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_hdmi>;
56 status = "okay";
57 };
58
59 &hdmi_tx_phy {
60 status = "okay";
61 };
62
63 &lcdif3 {
64 status = "okay";
65 };
66
67 &i2c1 {
68 sgtl5000: audio-codec@a {
69 compatible = "fsl,sgtl5000";
70 reg = <0x0a>;
71
72 assigned-clocks = <&clk IMX8MP
73 assigned-clock-parents = <&clk
74 assigned-clock-rates = <240000
75 clocks = <&clk IMX8MP_CLK_CLKO
76 #sound-dai-cells = <0>;
77
78 VDDA-supply = <®_vcc_3v3_au
79 VDDD-supply = <®_vcc_1v8_au
80 VDDIO-supply = <®_vcc_1v8_a
81 };
82 };
83
84 /* I2S-0 = sai2 */
85 &sai2 {
86 pinctrl-names = "default";
87 pinctrl-0 = <&pinctrl_sai2>;
88
89 assigned-clocks = <&clk IMX8MP_CLK_SAI
90 assigned-clock-parents = <&clk IMX8MP_
91 assigned-clock-rates = <12288000>;
92
93 fsl,sai-mclk-direction-output;
94 status = "okay";
95 };
96
97 &flexcan1 {
98 status = "okay";
99 };
100
101 &flexcan2 {
102 status = "okay";
103 };
104
105 &usdhc2 {
106 no-1-8-v;
107 };
108
109 &iomuxc {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_smarc_gpio>;
112
113 pinctrl_hdmi: hdmigrp {
114 fsl,pins = <
115 MX8MP_IOMUXC_HDMI_DDC_
116 MX8MP_IOMUXC_HDMI_DDC_
117 MX8MP_IOMUXC_HDMI_CEC_
118 MX8MP_IOMUXC_HDMI_HPD_
119 >;
120 };
121
122 pinctrl_sai2: sai2grp {
123 fsl,pins = <
124 MX8MP_IOMUXC_SAI2_TXFS
125 MX8MP_IOMUXC_SAI2_TXC_
126 MX8MP_IOMUXC_SAI2_RXD0
127 MX8MP_IOMUXC_SAI2_TXD0
128 >;
129 };
130
131 pinctrl_smarc_gpio: smarcgpiosgrp {
132 fsl,pins =
133 <MX8MP_IOMUXC_GPIO1_IO
134 <MX8MP_IOMUXC_SAI1_RXC
135 <MX8MP_IOMUXC_SAI1_RXD
136 <MX8MP_IOMUXC_SAI1_RXD
137 <MX8MP_IOMUXC_SAI3_RXC
138 <MX8MP_IOMUXC_SAI3_MCL
139 <MX8MP_IOMUXC_SAI1_TXD
140 <MX8MP_IOMUXC_GPIO1_IO
141 <MX8MP_IOMUXC_SAI1_MCL
142 <MX8MP_IOMUXC_SAI2_RXF
143 <MX8MP_IOMUXC_SAI2_RXC
144 <MX8MP_IOMUXC_SAI3_RXF
145 <MX8MP_IOMUXC_SAI1_TXD
146 <MX8MP_IOMUXC_SAI1_RXF
147 };
148 };
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