1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de> 4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/phy/phy-imx8-pcie.h> <<
10 #include <dt-bindings/leds/leds-pca9532.h> 9 #include <dt-bindings/leds/leds-pca9532.h>
11 #include <dt-bindings/pwm/pwm.h> 10 #include <dt-bindings/pwm/pwm.h>
12 #include "imx8mp-phycore-som.dtsi" 11 #include "imx8mp-phycore-som.dtsi"
13 12
14 / { 13 / {
15 model = "PHYTEC phyBOARD-Pollux i.MX8M 14 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
16 compatible = "phytec,imx8mp-phyboard-p 15 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
17 "phytec,imx8mp-phycore-so 16 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
18 17
19 chosen { 18 chosen {
20 stdout-path = &uart1; 19 stdout-path = &uart1;
21 }; 20 };
22 21
23 backlight_lvds: backlight { 22 backlight_lvds: backlight {
24 compatible = "pwm-backlight"; 23 compatible = "pwm-backlight";
25 pinctrl-names = "default"; 24 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_lvds1>; 25 pinctrl-0 = <&pinctrl_lvds1>;
27 brightness-levels = <0 4 8 16 26 brightness-levels = <0 4 8 16 32 64 128 255>;
28 default-brightness-level = <11 27 default-brightness-level = <11>;
29 enable-gpios = <&gpio2 20 GPIO 28 enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
30 num-interpolated-steps = <2>; 29 num-interpolated-steps = <2>;
31 power-supply = <®_lvds1_reg 30 power-supply = <®_lvds1_reg_en>;
32 pwms = <&pwm3 0 50000 0>; 31 pwms = <&pwm3 0 50000 0>;
33 }; 32 };
34 33
35 panel1_lvds: panel-lvds { 34 panel1_lvds: panel-lvds {
36 compatible = "edt,etml1010g3dr 35 compatible = "edt,etml1010g3dra";
37 backlight = <&backlight_lvds>; 36 backlight = <&backlight_lvds>;
38 power-supply = <®_vcc_3v3_s 37 power-supply = <®_vcc_3v3_sw>;
39 38
40 port { 39 port {
41 panel1_in: endpoint { 40 panel1_in: endpoint {
42 remote-endpoin 41 remote-endpoint = <&ldb_lvds_ch1>;
43 }; 42 };
44 }; 43 };
45 }; 44 };
46 45
47 reg_vcc_5v_sw: regulator-vcc-5v-sw { <<
48 compatible = "regulator-fixed" <<
49 regulator-always-on; <<
50 regulator-boot-on; <<
51 regulator-max-microvolt = <500 <<
52 regulator-min-microvolt = <500 <<
53 regulator-name = "VCC_5V_SW"; <<
54 }; <<
55 <<
56 reg_can1_stby: regulator-can1-stby { 46 reg_can1_stby: regulator-can1-stby {
57 compatible = "regulator-fixed" 47 compatible = "regulator-fixed";
58 pinctrl-names = "default"; 48 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexcan1 49 pinctrl-0 = <&pinctrl_flexcan1_reg>;
60 gpio = <&gpio3 20 GPIO_ACTIVE_ 50 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
61 regulator-max-microvolt = <330 51 regulator-max-microvolt = <3300000>;
62 regulator-min-microvolt = <330 52 regulator-min-microvolt = <3300000>;
63 regulator-name = "can1-stby"; 53 regulator-name = "can1-stby";
64 }; 54 };
65 55
66 reg_can2_stby: regulator-can2-stby { 56 reg_can2_stby: regulator-can2-stby {
67 compatible = "regulator-fixed" 57 compatible = "regulator-fixed";
68 pinctrl-names = "default"; 58 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_flexcan2 59 pinctrl-0 = <&pinctrl_flexcan2_reg>;
70 gpio = <&gpio3 21 GPIO_ACTIVE_ 60 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
71 regulator-max-microvolt = <330 61 regulator-max-microvolt = <3300000>;
72 regulator-min-microvolt = <330 62 regulator-min-microvolt = <3300000>;
73 regulator-name = "can2-stby"; 63 regulator-name = "can2-stby";
74 }; 64 };
75 65
76 reg_lvds1_reg_en: regulator-lvds1 { 66 reg_lvds1_reg_en: regulator-lvds1 {
77 compatible = "regulator-fixed" 67 compatible = "regulator-fixed";
78 enable-active-high; 68 enable-active-high;
79 gpio = <&gpio1 9 GPIO_ACTIVE_H 69 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
80 regulator-max-microvolt = <120 70 regulator-max-microvolt = <1200000>;
81 regulator-min-microvolt = <120 71 regulator-min-microvolt = <1200000>;
82 regulator-name = "lvds1_reg_en 72 regulator-name = "lvds1_reg_en";
83 }; 73 };
84 74
85 reg_usb1_vbus: regulator-usb1-vbus { 75 reg_usb1_vbus: regulator-usb1-vbus {
86 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
87 pinctrl-names = "default"; 77 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_usb1_vbu 78 pinctrl-0 = <&pinctrl_usb1_vbus>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_ 79 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
90 regulator-max-microvolt = <500 80 regulator-max-microvolt = <5000000>;
91 regulator-min-microvolt = <500 81 regulator-min-microvolt = <5000000>;
92 regulator-name = "usb1_host_vb 82 regulator-name = "usb1_host_vbus";
93 }; 83 };
94 84
95 reg_usdhc2_vmmc: regulator-usdhc2 { 85 reg_usdhc2_vmmc: regulator-usdhc2 {
96 compatible = "regulator-fixed" 86 compatible = "regulator-fixed";
97 pinctrl-names = "default"; 87 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_reg_usdh 88 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
99 regulator-name = "VSD_3V3"; 89 regulator-name = "VSD_3V3";
100 regulator-min-microvolt = <330 90 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <330 91 regulator-max-microvolt = <3300000>;
102 gpio = <&gpio2 19 GPIO_ACTIVE_ 92 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
103 enable-active-high; 93 enable-active-high;
104 startup-delay-us = <100>; 94 startup-delay-us = <100>;
105 off-on-delay-us = <12000>; 95 off-on-delay-us = <12000>;
106 }; 96 };
107 97
108 reg_vcc_3v3_sw: regulator-vcc-3v3-sw { 98 reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
109 compatible = "regulator-fixed" 99 compatible = "regulator-fixed";
110 regulator-name = "VCC_3V3_SW"; 100 regulator-name = "VCC_3V3_SW";
111 regulator-min-microvolt = <330 101 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <330 102 regulator-max-microvolt = <3300000>;
113 }; 103 };
114 }; 104 };
115 105
116 /* TPM */ <<
117 &ecspi1 { <<
118 #address-cells = <1>; <<
119 #size-cells = <0>; <<
120 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; <<
121 pinctrl-names = "default"; <<
122 pinctrl-0 = <&pinctrl_ecspi1>; <<
123 status = "okay"; <<
124 <<
125 tpm: tpm@0 { <<
126 compatible = "infineon,slb9670 <<
127 reg = <0>; <<
128 spi-max-frequency = <38000000> <<
129 }; <<
130 }; <<
131 <<
132 &eqos { 106 &eqos {
133 pinctrl-names = "default"; 107 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_eqos>; 108 pinctrl-0 = <&pinctrl_eqos>;
135 phy-mode = "rgmii-id"; 109 phy-mode = "rgmii-id";
136 phy-handle = <ðphy0>; 110 phy-handle = <ðphy0>;
137 status = "okay"; 111 status = "okay";
138 112
139 mdio { 113 mdio {
140 compatible = "snps,dwmac-mdio" 114 compatible = "snps,dwmac-mdio";
141 #address-cells = <1>; 115 #address-cells = <1>;
142 #size-cells = <0>; 116 #size-cells = <0>;
143 117
144 ethphy0: ethernet-phy@1 { 118 ethphy0: ethernet-phy@1 {
145 compatible = "ethernet 119 compatible = "ethernet-phy-ieee802.3-c22";
146 reg = <0x1>; 120 reg = <0x1>;
147 ti,rx-internal-delay = 121 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
148 ti,tx-internal-delay = 122 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
149 ti,fifo-depth = <DP838 123 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
150 ti,clk-output-sel = <D 124 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
151 enet-phy-lane-no-swap; 125 enet-phy-lane-no-swap;
152 }; 126 };
153 }; 127 };
154 }; 128 };
155 129
156 /* CAN FD */ 130 /* CAN FD */
157 &flexcan1 { 131 &flexcan1 {
158 pinctrl-names = "default"; 132 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_flexcan1>; 133 pinctrl-0 = <&pinctrl_flexcan1>;
160 xceiver-supply = <®_can1_stby>; 134 xceiver-supply = <®_can1_stby>;
161 status = "okay"; 135 status = "okay";
162 }; 136 };
163 137
164 &flexcan2 { 138 &flexcan2 {
165 pinctrl-names = "default"; 139 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_flexcan2>; 140 pinctrl-0 = <&pinctrl_flexcan2>;
167 xceiver-supply = <®_can2_stby>; 141 xceiver-supply = <®_can2_stby>;
168 status = "okay"; 142 status = "okay";
169 }; 143 };
170 144
171 &i2c2 { 145 &i2c2 {
172 clock-frequency = <400000>; 146 clock-frequency = <400000>;
173 pinctrl-names = "default", "gpio"; 147 pinctrl-names = "default", "gpio";
174 pinctrl-0 = <&pinctrl_i2c2>; 148 pinctrl-0 = <&pinctrl_i2c2>;
175 pinctrl-1 = <&pinctrl_i2c2_gpio>; 149 pinctrl-1 = <&pinctrl_i2c2_gpio>;
176 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 150 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
177 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 151 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
178 status = "okay"; 152 status = "okay";
179 153
180 eeprom@51 { 154 eeprom@51 {
181 compatible = "atmel,24c02"; 155 compatible = "atmel,24c02";
182 reg = <0x51>; 156 reg = <0x51>;
183 pagesize = <16>; 157 pagesize = <16>;
184 vcc-supply = <®_vcc_3v3_sw> <<
185 }; 158 };
186 159
187 leds@62 { 160 leds@62 {
188 compatible = "nxp,pca9533"; 161 compatible = "nxp,pca9533";
189 reg = <0x62>; 162 reg = <0x62>;
190 163
191 led-1 { 164 led-1 {
192 type = <PCA9532_TYPE_L 165 type = <PCA9532_TYPE_LED>;
193 }; 166 };
194 167
195 led-2 { 168 led-2 {
196 type = <PCA9532_TYPE_L 169 type = <PCA9532_TYPE_LED>;
197 }; 170 };
198 171
199 led-3 { 172 led-3 {
200 type = <PCA9532_TYPE_L 173 type = <PCA9532_TYPE_LED>;
201 }; 174 };
202 }; 175 };
203 }; 176 };
204 177
205 &lcdif2 { 178 &lcdif2 {
206 status = "okay"; 179 status = "okay";
207 }; 180 };
208 181
209 &lvds_bridge { 182 &lvds_bridge {
210 status = "okay"; 183 status = "okay";
211 184
212 ports { 185 ports {
213 port@2 { 186 port@2 {
214 ldb_lvds_ch1: endpoint 187 ldb_lvds_ch1: endpoint {
215 remote-endpoin 188 remote-endpoint = <&panel1_in>;
216 }; 189 };
217 }; 190 };
218 }; 191 };
219 }; 192 };
220 193
221 &media_blk_ctrl { <<
222 /* <<
223 * The LVDS panel on this device uses <<
224 * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = <<
225 * serializer and LCDIFv3 scanout engi <<
226 * pixel clock of exactly 72.4 MHz. <<
227 */ <<
228 assigned-clock-rates = <500000000>, <2 <<
229 <0>, <0>, <5000 <<
230 <506800000>; <<
231 }; <<
232 <<
233 &snvs_pwrkey { 194 &snvs_pwrkey {
234 status = "okay"; 195 status = "okay";
235 }; 196 };
236 197
237 &pcie_phy { <<
238 clocks = <&hsio_blk_ctrl>; <<
239 clock-names = "ref"; <<
240 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
241 fsl,clkreq-unsupported; <<
242 status = "okay"; <<
243 }; <<
244 <<
245 /* Mini PCIe */ <<
246 &pcie { <<
247 pinctrl-names = "default"; <<
248 pinctrl-0 = <&pinctrl_pcie0>; <<
249 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW <<
250 vpcie-supply = <®_vcc_3v3_sw>; <<
251 status = "okay"; <<
252 }; <<
253 <<
254 &pwm3 { 198 &pwm3 {
255 status = "okay"; 199 status = "okay";
256 pinctrl-names = "default"; 200 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_pwm3>; 201 pinctrl-0 = <&pinctrl_pwm3>;
258 }; 202 };
259 203
260 &rv3028 { 204 &rv3028 {
261 pinctrl-names = "default"; 205 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_rtc>; 206 pinctrl-0 = <&pinctrl_rtc>;
263 interrupt-parent = <&gpio4>; 207 interrupt-parent = <&gpio4>;
264 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 208 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
265 aux-voltage-chargeable = <1>; <<
266 wakeup-source; 209 wakeup-source;
267 trickle-resistor-ohms = <3000>; 210 trickle-resistor-ohms = <3000>;
268 }; 211 };
269 212
270 /* debug console */ 213 /* debug console */
271 &uart1 { 214 &uart1 {
272 pinctrl-names = "default"; 215 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_uart1>; 216 pinctrl-0 = <&pinctrl_uart1>;
274 status = "okay"; 217 status = "okay";
275 }; 218 };
276 219
277 /* USB1 Host mode Type-A */ 220 /* USB1 Host mode Type-A */
278 &usb3_phy0 { 221 &usb3_phy0 {
279 vbus-supply = <®_usb1_vbus>; 222 vbus-supply = <®_usb1_vbus>;
280 status = "okay"; 223 status = "okay";
281 }; 224 };
282 225
283 &usb3_0 { 226 &usb3_0 {
284 status = "okay"; 227 status = "okay";
285 }; 228 };
286 229
287 &usb_dwc3_0 { 230 &usb_dwc3_0 {
288 dr_mode = "host"; 231 dr_mode = "host";
289 status = "okay"; 232 status = "okay";
290 }; 233 };
291 234
292 /* USB2 4-port USB3.0 HUB */ 235 /* USB2 4-port USB3.0 HUB */
293 &usb3_phy1 { 236 &usb3_phy1 {
294 vbus-supply = <®_vcc_5v_sw>; <<
295 status = "okay"; 237 status = "okay";
296 }; 238 };
297 239
298 &usb3_1 { 240 &usb3_1 {
299 fsl,permanently-attached; 241 fsl,permanently-attached;
300 fsl,disable-port-power-control; 242 fsl,disable-port-power-control;
301 status = "okay"; 243 status = "okay";
302 }; 244 };
303 245
304 &usb_dwc3_1 { 246 &usb_dwc3_1 {
305 dr_mode = "host"; 247 dr_mode = "host";
306 status = "okay"; 248 status = "okay";
307 }; 249 };
308 250
309 /* RS232/RS485 */ 251 /* RS232/RS485 */
310 &uart2 { 252 &uart2 {
311 assigned-clocks = <&clk IMX8MP_CLK_UAR 253 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
312 assigned-clock-parents = <&clk IMX8MP_ 254 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
313 pinctrl-names = "default"; 255 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_uart2>; 256 pinctrl-0 = <&pinctrl_uart2>;
315 uart-has-rtscts; 257 uart-has-rtscts;
316 status = "okay"; 258 status = "okay";
317 }; 259 };
318 260
319 /* SD-Card */ 261 /* SD-Card */
320 &usdhc2 { 262 &usdhc2 {
321 assigned-clocks = <&clk IMX8MP_CLK_USD 263 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
322 assigned-clock-rates = <200000000>; 264 assigned-clock-rates = <200000000>;
323 pinctrl-names = "default", "state_100m 265 pinctrl-names = "default", "state_100mhz", "state_200mhz";
324 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 266 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
325 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 267 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
326 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 268 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
327 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 269 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
328 disable-wp; <<
329 vmmc-supply = <®_usdhc2_vmmc>; 270 vmmc-supply = <®_usdhc2_vmmc>;
330 vqmmc-supply = <&ldo5>; <<
331 bus-width = <4>; 271 bus-width = <4>;
332 status = "okay"; 272 status = "okay";
333 }; 273 };
334 274
335 &gpio1 { 275 &gpio1 {
336 gpio-line-names = "", "", "X_PMIC_WDOG 276 gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
337 "PMIC_SD_VSEL", "", "", "", "" 277 "PMIC_SD_VSEL", "", "", "", "", "",
338 "", "", "USB1_OTG_PWR", "", "" 278 "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
339 }; 279 };
340 280
341 &gpio2 { 281 &gpio2 {
342 gpio-line-names = "", "", "", "", 282 gpio-line-names = "", "", "", "",
343 "", "", "", "", "", "", 283 "", "", "", "", "", "",
344 "", "", "X_SD2_CD_B", "", "", 284 "", "", "X_SD2_CD_B", "", "", "",
345 "", "", "", "SD2_RESET_B"; 285 "", "", "", "SD2_RESET_B";
346 }; 286 };
347 287
348 &gpio3 { 288 &gpio3 {
349 gpio-line-names = "", "", "", "", 289 gpio-line-names = "", "", "", "",
350 "", "", "", "", "", "", 290 "", "", "", "", "", "",
351 "", "", "", "", "", "", 291 "", "", "", "", "", "",
352 "", "", "", "", "nCAN1_EN", "n 292 "", "", "", "", "nCAN1_EN", "nCAN2_EN";
353 }; 293 };
354 294
355 &gpio4 { 295 &gpio4 {
356 gpio-line-names = "", "", "", "", 296 gpio-line-names = "", "", "", "",
357 "", "", "", "", "", "", 297 "", "", "", "", "", "",
358 "", "", "", "", "", "", 298 "", "", "", "", "", "",
359 "", "", "X_PMIC_IRQ_B", "", "n 299 "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
360 }; 300 };
361 301
362 &iomuxc { 302 &iomuxc {
363 pinctrl_ecspi1: ecspi1grp { <<
364 fsl,pins = < <<
365 MX8MP_IOMUXC_ECSPI1_MI <<
366 MX8MP_IOMUXC_ECSPI1_MO <<
367 MX8MP_IOMUXC_ECSPI1_SC <<
368 MX8MP_IOMUXC_ECSPI1_SS <<
369 >; <<
370 }; <<
371 <<
372 pinctrl_eqos: eqosgrp { 303 pinctrl_eqos: eqosgrp {
373 fsl,pins = < 304 fsl,pins = <
374 MX8MP_IOMUXC_ENET_MDC_ 305 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
375 MX8MP_IOMUXC_ENET_MDIO 306 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
376 MX8MP_IOMUXC_ENET_RD0_ 307 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
377 MX8MP_IOMUXC_ENET_RD1_ 308 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
378 MX8MP_IOMUXC_ENET_RD2_ 309 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
379 MX8MP_IOMUXC_ENET_RD3_ 310 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
380 MX8MP_IOMUXC_ENET_RXC_ 311 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
381 MX8MP_IOMUXC_ENET_RX_C 312 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
382 MX8MP_IOMUXC_ENET_TD0_ 313 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12
383 MX8MP_IOMUXC_ENET_TD1_ 314 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12
384 MX8MP_IOMUXC_ENET_TD2_ 315 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12
385 MX8MP_IOMUXC_ENET_TD3_ 316 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12
386 MX8MP_IOMUXC_ENET_TX_C 317 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
387 MX8MP_IOMUXC_ENET_TXC_ 318 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12
388 MX8MP_IOMUXC_SAI1_MCLK 319 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
389 >; 320 >;
390 }; 321 };
391 322
392 pinctrl_flexcan1: flexcan1grp { 323 pinctrl_flexcan1: flexcan1grp {
393 fsl,pins = < 324 fsl,pins = <
394 MX8MP_IOMUXC_SAI5_RXD2 325 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
395 MX8MP_IOMUXC_SAI5_RXD1 326 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
396 >; 327 >;
397 }; 328 };
398 329
399 pinctrl_flexcan2: flexcan2grp { 330 pinctrl_flexcan2: flexcan2grp {
400 fsl,pins = < 331 fsl,pins = <
401 MX8MP_IOMUXC_SAI5_MCLK 332 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
402 MX8MP_IOMUXC_SAI5_RXD3 333 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
403 >; 334 >;
404 }; 335 };
405 336
406 pinctrl_flexcan1_reg: flexcan1reggrp { 337 pinctrl_flexcan1_reg: flexcan1reggrp {
407 fsl,pins = < 338 fsl,pins = <
408 MX8MP_IOMUXC_SAI5_RXC_ 339 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
409 >; 340 >;
410 }; 341 };
411 342
412 pinctrl_flexcan2_reg: flexcan2reggrp { 343 pinctrl_flexcan2_reg: flexcan2reggrp {
413 fsl,pins = < 344 fsl,pins = <
414 MX8MP_IOMUXC_SAI5_RXD0 345 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
415 >; 346 >;
416 }; 347 };
417 348
418 pinctrl_i2c2: i2c2grp { 349 pinctrl_i2c2: i2c2grp {
419 fsl,pins = < 350 fsl,pins = <
420 MX8MP_IOMUXC_I2C2_SCL_ 351 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
421 MX8MP_IOMUXC_I2C2_SDA_ 352 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
422 >; 353 >;
423 }; 354 };
424 355
425 pinctrl_i2c2_gpio: i2c2gpiogrp { 356 pinctrl_i2c2_gpio: i2c2gpiogrp {
426 fsl,pins = < 357 fsl,pins = <
427 MX8MP_IOMUXC_I2C2_SCL_ 358 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
428 MX8MP_IOMUXC_I2C2_SDA_ 359 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
429 >; 360 >;
430 }; 361 };
431 362
432 pinctrl_lvds1: lvds1grp { 363 pinctrl_lvds1: lvds1grp {
433 fsl,pins = < 364 fsl,pins = <
434 MX8MP_IOMUXC_SD2_WP__G 365 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
435 >; <<
436 }; <<
437 <<
438 pinctrl_pcie0: pcie0grp { <<
439 fsl,pins = < <<
440 MX8MP_IOMUXC_GPIO1_IO0 <<
441 MX8MP_IOMUXC_GPIO1_IO1 <<
442 MX8MP_IOMUXC_GPIO1_IO1 <<
443 MX8MP_IOMUXC_GPIO1_IO1 <<
444 >; 366 >;
445 }; 367 };
446 368
447 pinctrl_pwm3: pwm3grp { 369 pinctrl_pwm3: pwm3grp {
448 fsl,pins = < 370 fsl,pins = <
449 MX8MP_IOMUXC_SPDIF_TX_ 371 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
450 >; 372 >;
451 }; 373 };
452 374
453 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 375 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
454 fsl,pins = < 376 fsl,pins = <
455 MX8MP_IOMUXC_SD2_RESET 377 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
456 >; 378 >;
457 }; 379 };
458 380
459 pinctrl_rtc: rtcgrp { 381 pinctrl_rtc: rtcgrp {
460 fsl,pins = < 382 fsl,pins = <
461 MX8MP_IOMUXC_SAI1_TXD7 383 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
462 >; 384 >;
463 }; 385 };
464 386
465 pinctrl_uart1: uart1grp { 387 pinctrl_uart1: uart1grp {
466 fsl,pins = < 388 fsl,pins = <
467 MX8MP_IOMUXC_UART1_RXD 389 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
468 MX8MP_IOMUXC_UART1_TXD 390 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
469 >; 391 >;
470 }; 392 };
471 393
472 pinctrl_usb1_vbus: usb1vbusgrp { 394 pinctrl_usb1_vbus: usb1vbusgrp {
473 fsl,pins = < 395 fsl,pins = <
474 MX8MP_IOMUXC_GPIO1_IO1 396 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
475 >; 397 >;
476 }; 398 };
477 399
478 pinctrl_uart2: uart2grp { 400 pinctrl_uart2: uart2grp {
479 fsl,pins = < 401 fsl,pins = <
480 MX8MP_IOMUXC_UART2_RXD 402 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
481 MX8MP_IOMUXC_UART2_TXD 403 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
482 MX8MP_IOMUXC_SAI3_RXC_ 404 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
483 MX8MP_IOMUXC_SAI3_RXD_ 405 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
484 >; 406 >;
485 }; 407 };
486 408
487 pinctrl_usdhc2_pins: usdhc2-gpiogrp { 409 pinctrl_usdhc2_pins: usdhc2-gpiogrp {
488 fsl,pins = < 410 fsl,pins = <
489 MX8MP_IOMUXC_SD2_CD_B_ 411 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40
490 >; 412 >;
491 }; 413 };
492 414
493 pinctrl_usdhc2: usdhc2grp { 415 pinctrl_usdhc2: usdhc2grp {
494 fsl,pins = < 416 fsl,pins = <
495 MX8MP_IOMUXC_SD2_CLK__ 417 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
496 MX8MP_IOMUXC_SD2_CMD__ 418 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
497 MX8MP_IOMUXC_SD2_DATA0 419 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
498 MX8MP_IOMUXC_SD2_DATA1 420 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
499 MX8MP_IOMUXC_SD2_DATA2 421 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
500 MX8MP_IOMUXC_SD2_DATA3 422 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
501 MX8MP_IOMUXC_GPIO1_IO0 423 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
502 >; 424 >;
503 }; 425 };
504 426
505 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 427 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
506 fsl,pins = < 428 fsl,pins = <
507 MX8MP_IOMUXC_SD2_CLK__ 429 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
508 MX8MP_IOMUXC_SD2_CMD__ 430 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
509 MX8MP_IOMUXC_SD2_DATA0 431 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
510 MX8MP_IOMUXC_SD2_DATA1 432 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
511 MX8MP_IOMUXC_SD2_DATA2 433 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
512 MX8MP_IOMUXC_SD2_DATA3 434 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
513 MX8MP_IOMUXC_GPIO1_IO0 435 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
514 >; 436 >;
515 }; 437 };
516 438
517 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 439 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
518 fsl,pins = < 440 fsl,pins = <
519 MX8MP_IOMUXC_SD2_CLK__ 441 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
520 MX8MP_IOMUXC_SD2_CMD__ 442 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
521 MX8MP_IOMUXC_SD2_DATA0 443 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
522 MX8MP_IOMUXC_SD2_DATA1 444 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
523 MX8MP_IOMUXC_SD2_DATA2 445 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
524 MX8MP_IOMUXC_SD2_DATA3 446 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
525 MX8MP_IOMUXC_GPIO1_IO0 447 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
526 >; 448 >;
527 }; 449 };
528 }; 450 };
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