1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de> 4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/phy/phy-imx8-pcie.h> <<
10 #include <dt-bindings/leds/leds-pca9532.h> 9 #include <dt-bindings/leds/leds-pca9532.h>
11 #include <dt-bindings/pwm/pwm.h> 10 #include <dt-bindings/pwm/pwm.h>
12 #include "imx8mp-phycore-som.dtsi" 11 #include "imx8mp-phycore-som.dtsi"
13 12
14 / { 13 / {
15 model = "PHYTEC phyBOARD-Pollux i.MX8M 14 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
16 compatible = "phytec,imx8mp-phyboard-p 15 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
17 "phytec,imx8mp-phycore-so 16 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
18 17
19 chosen { 18 chosen {
20 stdout-path = &uart1; 19 stdout-path = &uart1;
21 }; 20 };
22 21
23 backlight_lvds: backlight { <<
24 compatible = "pwm-backlight"; <<
25 pinctrl-names = "default"; <<
26 pinctrl-0 = <&pinctrl_lvds1>; <<
27 brightness-levels = <0 4 8 16 <<
28 default-brightness-level = <11 <<
29 enable-gpios = <&gpio2 20 GPIO <<
30 num-interpolated-steps = <2>; <<
31 power-supply = <®_lvds1_reg <<
32 pwms = <&pwm3 0 50000 0>; <<
33 }; <<
34 <<
35 panel1_lvds: panel-lvds { <<
36 compatible = "edt,etml1010g3dr <<
37 backlight = <&backlight_lvds>; <<
38 power-supply = <®_vcc_3v3_s <<
39 <<
40 port { <<
41 panel1_in: endpoint { <<
42 remote-endpoin <<
43 }; <<
44 }; <<
45 }; <<
46 <<
47 reg_vcc_5v_sw: regulator-vcc-5v-sw { <<
48 compatible = "regulator-fixed" <<
49 regulator-always-on; <<
50 regulator-boot-on; <<
51 regulator-max-microvolt = <500 <<
52 regulator-min-microvolt = <500 <<
53 regulator-name = "VCC_5V_SW"; <<
54 }; <<
55 <<
56 reg_can1_stby: regulator-can1-stby { 22 reg_can1_stby: regulator-can1-stby {
57 compatible = "regulator-fixed" 23 compatible = "regulator-fixed";
58 pinctrl-names = "default"; 24 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexcan1 25 pinctrl-0 = <&pinctrl_flexcan1_reg>;
60 gpio = <&gpio3 20 GPIO_ACTIVE_ 26 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
61 regulator-max-microvolt = <330 27 regulator-max-microvolt = <3300000>;
62 regulator-min-microvolt = <330 28 regulator-min-microvolt = <3300000>;
63 regulator-name = "can1-stby"; 29 regulator-name = "can1-stby";
64 }; 30 };
65 31
66 reg_can2_stby: regulator-can2-stby { 32 reg_can2_stby: regulator-can2-stby {
67 compatible = "regulator-fixed" 33 compatible = "regulator-fixed";
68 pinctrl-names = "default"; 34 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_flexcan2 35 pinctrl-0 = <&pinctrl_flexcan2_reg>;
70 gpio = <&gpio3 21 GPIO_ACTIVE_ 36 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
71 regulator-max-microvolt = <330 37 regulator-max-microvolt = <3300000>;
72 regulator-min-microvolt = <330 38 regulator-min-microvolt = <3300000>;
73 regulator-name = "can2-stby"; 39 regulator-name = "can2-stby";
74 }; 40 };
75 41
76 reg_lvds1_reg_en: regulator-lvds1 { <<
77 compatible = "regulator-fixed" <<
78 enable-active-high; <<
79 gpio = <&gpio1 9 GPIO_ACTIVE_H <<
80 regulator-max-microvolt = <120 <<
81 regulator-min-microvolt = <120 <<
82 regulator-name = "lvds1_reg_en <<
83 }; <<
84 <<
85 reg_usb1_vbus: regulator-usb1-vbus { 42 reg_usb1_vbus: regulator-usb1-vbus {
86 compatible = "regulator-fixed" 43 compatible = "regulator-fixed";
87 pinctrl-names = "default"; 44 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_usb1_vbu 45 pinctrl-0 = <&pinctrl_usb1_vbus>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_ 46 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
90 regulator-max-microvolt = <500 47 regulator-max-microvolt = <5000000>;
91 regulator-min-microvolt = <500 48 regulator-min-microvolt = <5000000>;
92 regulator-name = "usb1_host_vb 49 regulator-name = "usb1_host_vbus";
93 }; 50 };
94 51
95 reg_usdhc2_vmmc: regulator-usdhc2 { 52 reg_usdhc2_vmmc: regulator-usdhc2 {
96 compatible = "regulator-fixed" 53 compatible = "regulator-fixed";
97 pinctrl-names = "default"; 54 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_reg_usdh 55 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
99 regulator-name = "VSD_3V3"; 56 regulator-name = "VSD_3V3";
100 regulator-min-microvolt = <330 57 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <330 58 regulator-max-microvolt = <3300000>;
102 gpio = <&gpio2 19 GPIO_ACTIVE_ 59 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
103 enable-active-high; 60 enable-active-high;
104 startup-delay-us = <100>; 61 startup-delay-us = <100>;
105 off-on-delay-us = <12000>; 62 off-on-delay-us = <12000>;
106 }; 63 };
107 <<
108 reg_vcc_3v3_sw: regulator-vcc-3v3-sw { <<
109 compatible = "regulator-fixed" <<
110 regulator-name = "VCC_3V3_SW"; <<
111 regulator-min-microvolt = <330 <<
112 regulator-max-microvolt = <330 <<
113 }; <<
114 }; <<
115 <<
116 /* TPM */ <<
117 &ecspi1 { <<
118 #address-cells = <1>; <<
119 #size-cells = <0>; <<
120 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; <<
121 pinctrl-names = "default"; <<
122 pinctrl-0 = <&pinctrl_ecspi1>; <<
123 status = "okay"; <<
124 <<
125 tpm: tpm@0 { <<
126 compatible = "infineon,slb9670 <<
127 reg = <0>; <<
128 spi-max-frequency = <38000000> <<
129 }; <<
130 }; 64 };
131 65
132 &eqos { 66 &eqos {
133 pinctrl-names = "default"; 67 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_eqos>; 68 pinctrl-0 = <&pinctrl_eqos>;
135 phy-mode = "rgmii-id"; 69 phy-mode = "rgmii-id";
136 phy-handle = <ðphy0>; 70 phy-handle = <ðphy0>;
137 status = "okay"; 71 status = "okay";
138 72
139 mdio { 73 mdio {
140 compatible = "snps,dwmac-mdio" 74 compatible = "snps,dwmac-mdio";
141 #address-cells = <1>; 75 #address-cells = <1>;
142 #size-cells = <0>; 76 #size-cells = <0>;
143 77
144 ethphy0: ethernet-phy@1 { 78 ethphy0: ethernet-phy@1 {
145 compatible = "ethernet 79 compatible = "ethernet-phy-ieee802.3-c22";
146 reg = <0x1>; 80 reg = <0x1>;
147 ti,rx-internal-delay = 81 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
148 ti,tx-internal-delay = 82 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
149 ti,fifo-depth = <DP838 83 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
150 ti,clk-output-sel = <D 84 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
151 enet-phy-lane-no-swap; 85 enet-phy-lane-no-swap;
152 }; 86 };
153 }; 87 };
154 }; 88 };
155 89
156 /* CAN FD */ 90 /* CAN FD */
157 &flexcan1 { 91 &flexcan1 {
158 pinctrl-names = "default"; 92 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_flexcan1>; 93 pinctrl-0 = <&pinctrl_flexcan1>;
160 xceiver-supply = <®_can1_stby>; 94 xceiver-supply = <®_can1_stby>;
161 status = "okay"; 95 status = "okay";
162 }; 96 };
163 97
164 &flexcan2 { 98 &flexcan2 {
165 pinctrl-names = "default"; 99 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_flexcan2>; 100 pinctrl-0 = <&pinctrl_flexcan2>;
167 xceiver-supply = <®_can2_stby>; 101 xceiver-supply = <®_can2_stby>;
168 status = "okay"; 102 status = "okay";
169 }; 103 };
170 104
171 &i2c2 { 105 &i2c2 {
172 clock-frequency = <400000>; 106 clock-frequency = <400000>;
173 pinctrl-names = "default", "gpio"; 107 pinctrl-names = "default", "gpio";
174 pinctrl-0 = <&pinctrl_i2c2>; 108 pinctrl-0 = <&pinctrl_i2c2>;
175 pinctrl-1 = <&pinctrl_i2c2_gpio>; 109 pinctrl-1 = <&pinctrl_i2c2_gpio>;
176 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 110 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
177 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 111 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
178 status = "okay"; 112 status = "okay";
179 113
180 eeprom@51 { 114 eeprom@51 {
181 compatible = "atmel,24c02"; 115 compatible = "atmel,24c02";
182 reg = <0x51>; 116 reg = <0x51>;
183 pagesize = <16>; 117 pagesize = <16>;
184 vcc-supply = <®_vcc_3v3_sw> <<
185 }; 118 };
186 119
187 leds@62 { 120 leds@62 {
188 compatible = "nxp,pca9533"; 121 compatible = "nxp,pca9533";
189 reg = <0x62>; 122 reg = <0x62>;
190 123
191 led-1 { 124 led-1 {
192 type = <PCA9532_TYPE_L 125 type = <PCA9532_TYPE_LED>;
193 }; 126 };
194 127
195 led-2 { 128 led-2 {
196 type = <PCA9532_TYPE_L 129 type = <PCA9532_TYPE_LED>;
197 }; 130 };
198 131
199 led-3 { 132 led-3 {
200 type = <PCA9532_TYPE_L 133 type = <PCA9532_TYPE_LED>;
201 }; 134 };
202 }; 135 };
203 }; 136 };
204 137
205 &lcdif2 { <<
206 status = "okay"; <<
207 }; <<
208 <<
209 &lvds_bridge { <<
210 status = "okay"; <<
211 <<
212 ports { <<
213 port@2 { <<
214 ldb_lvds_ch1: endpoint <<
215 remote-endpoin <<
216 }; <<
217 }; <<
218 }; <<
219 }; <<
220 <<
221 &media_blk_ctrl { <<
222 /* <<
223 * The LVDS panel on this device uses <<
224 * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = <<
225 * serializer and LCDIFv3 scanout engi <<
226 * pixel clock of exactly 72.4 MHz. <<
227 */ <<
228 assigned-clock-rates = <500000000>, <2 <<
229 <0>, <0>, <5000 <<
230 <506800000>; <<
231 }; <<
232 <<
233 &snvs_pwrkey { 138 &snvs_pwrkey {
234 status = "okay"; 139 status = "okay";
235 }; 140 };
236 141
237 &pcie_phy { <<
238 clocks = <&hsio_blk_ctrl>; <<
239 clock-names = "ref"; <<
240 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
241 fsl,clkreq-unsupported; <<
242 status = "okay"; <<
243 }; <<
244 <<
245 /* Mini PCIe */ <<
246 &pcie { <<
247 pinctrl-names = "default"; <<
248 pinctrl-0 = <&pinctrl_pcie0>; <<
249 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW <<
250 vpcie-supply = <®_vcc_3v3_sw>; <<
251 status = "okay"; <<
252 }; <<
253 <<
254 &pwm3 { <<
255 status = "okay"; <<
256 pinctrl-names = "default"; <<
257 pinctrl-0 = <&pinctrl_pwm3>; <<
258 }; <<
259 <<
260 &rv3028 { <<
261 pinctrl-names = "default"; <<
262 pinctrl-0 = <&pinctrl_rtc>; <<
263 interrupt-parent = <&gpio4>; <<
264 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; <<
265 aux-voltage-chargeable = <1>; <<
266 wakeup-source; <<
267 trickle-resistor-ohms = <3000>; <<
268 }; <<
269 <<
270 /* debug console */ 142 /* debug console */
271 &uart1 { 143 &uart1 {
272 pinctrl-names = "default"; 144 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_uart1>; 145 pinctrl-0 = <&pinctrl_uart1>;
274 status = "okay"; 146 status = "okay";
275 }; 147 };
276 148
277 /* USB1 Host mode Type-A */ 149 /* USB1 Host mode Type-A */
278 &usb3_phy0 { 150 &usb3_phy0 {
279 vbus-supply = <®_usb1_vbus>; 151 vbus-supply = <®_usb1_vbus>;
280 status = "okay"; 152 status = "okay";
281 }; 153 };
282 154
283 &usb3_0 { 155 &usb3_0 {
284 status = "okay"; 156 status = "okay";
285 }; 157 };
286 158
287 &usb_dwc3_0 { 159 &usb_dwc3_0 {
288 dr_mode = "host"; 160 dr_mode = "host";
289 status = "okay"; 161 status = "okay";
290 }; 162 };
291 163
292 /* USB2 4-port USB3.0 HUB */ 164 /* USB2 4-port USB3.0 HUB */
293 &usb3_phy1 { 165 &usb3_phy1 {
294 vbus-supply = <®_vcc_5v_sw>; <<
295 status = "okay"; 166 status = "okay";
296 }; 167 };
297 168
298 &usb3_1 { 169 &usb3_1 {
299 fsl,permanently-attached; 170 fsl,permanently-attached;
300 fsl,disable-port-power-control; 171 fsl,disable-port-power-control;
301 status = "okay"; 172 status = "okay";
302 }; 173 };
303 174
304 &usb_dwc3_1 { 175 &usb_dwc3_1 {
305 dr_mode = "host"; 176 dr_mode = "host";
306 status = "okay"; 177 status = "okay";
307 }; 178 };
308 179
309 /* RS232/RS485 */ 180 /* RS232/RS485 */
310 &uart2 { 181 &uart2 {
311 assigned-clocks = <&clk IMX8MP_CLK_UAR 182 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
312 assigned-clock-parents = <&clk IMX8MP_ 183 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
313 pinctrl-names = "default"; 184 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_uart2>; 185 pinctrl-0 = <&pinctrl_uart2>;
315 uart-has-rtscts; 186 uart-has-rtscts;
316 status = "okay"; 187 status = "okay";
317 }; 188 };
318 189
319 /* SD-Card */ 190 /* SD-Card */
320 &usdhc2 { 191 &usdhc2 {
321 assigned-clocks = <&clk IMX8MP_CLK_USD 192 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
322 assigned-clock-rates = <200000000>; 193 assigned-clock-rates = <200000000>;
323 pinctrl-names = "default", "state_100m 194 pinctrl-names = "default", "state_100mhz", "state_200mhz";
324 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 195 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
325 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 196 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
326 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 197 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
327 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 198 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
328 disable-wp; <<
329 vmmc-supply = <®_usdhc2_vmmc>; 199 vmmc-supply = <®_usdhc2_vmmc>;
330 vqmmc-supply = <&ldo5>; <<
331 bus-width = <4>; 200 bus-width = <4>;
332 status = "okay"; 201 status = "okay";
333 }; 202 };
334 203
335 &gpio1 { 204 &gpio1 {
336 gpio-line-names = "", "", "X_PMIC_WDOG 205 gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
337 "PMIC_SD_VSEL", "", "", "", "" 206 "PMIC_SD_VSEL", "", "", "", "", "",
338 "", "", "USB1_OTG_PWR", "", "" 207 "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
339 }; 208 };
340 209
341 &gpio2 { 210 &gpio2 {
342 gpio-line-names = "", "", "", "", 211 gpio-line-names = "", "", "", "",
343 "", "", "", "", "", "", 212 "", "", "", "", "", "",
344 "", "", "X_SD2_CD_B", "", "", 213 "", "", "X_SD2_CD_B", "", "", "",
345 "", "", "", "SD2_RESET_B"; 214 "", "", "", "SD2_RESET_B";
346 }; 215 };
347 216
348 &gpio3 { 217 &gpio3 {
349 gpio-line-names = "", "", "", "", 218 gpio-line-names = "", "", "", "",
350 "", "", "", "", "", "", 219 "", "", "", "", "", "",
351 "", "", "", "", "", "", 220 "", "", "", "", "", "",
352 "", "", "", "", "nCAN1_EN", "n 221 "", "", "", "", "nCAN1_EN", "nCAN2_EN";
353 }; 222 };
354 223
355 &gpio4 { 224 &gpio4 {
356 gpio-line-names = "", "", "", "", 225 gpio-line-names = "", "", "", "",
357 "", "", "", "", "", "", 226 "", "", "", "", "", "",
358 "", "", "", "", "", "", 227 "", "", "", "", "", "",
359 "", "", "X_PMIC_IRQ_B", "", "n 228 "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
360 }; 229 };
361 230
362 &iomuxc { 231 &iomuxc {
363 pinctrl_ecspi1: ecspi1grp { <<
364 fsl,pins = < <<
365 MX8MP_IOMUXC_ECSPI1_MI <<
366 MX8MP_IOMUXC_ECSPI1_MO <<
367 MX8MP_IOMUXC_ECSPI1_SC <<
368 MX8MP_IOMUXC_ECSPI1_SS <<
369 >; <<
370 }; <<
371 <<
372 pinctrl_eqos: eqosgrp { 232 pinctrl_eqos: eqosgrp {
373 fsl,pins = < 233 fsl,pins = <
374 MX8MP_IOMUXC_ENET_MDC_ 234 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
375 MX8MP_IOMUXC_ENET_MDIO 235 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
376 MX8MP_IOMUXC_ENET_RD0_ 236 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
377 MX8MP_IOMUXC_ENET_RD1_ 237 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
378 MX8MP_IOMUXC_ENET_RD2_ 238 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
379 MX8MP_IOMUXC_ENET_RD3_ 239 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
380 MX8MP_IOMUXC_ENET_RXC_ 240 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
381 MX8MP_IOMUXC_ENET_RX_C 241 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
382 MX8MP_IOMUXC_ENET_TD0_ !! 242 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
383 MX8MP_IOMUXC_ENET_TD1_ !! 243 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
384 MX8MP_IOMUXC_ENET_TD2_ !! 244 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
385 MX8MP_IOMUXC_ENET_TD3_ !! 245 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
386 MX8MP_IOMUXC_ENET_TX_C !! 246 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
387 MX8MP_IOMUXC_ENET_TXC_ !! 247 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
388 MX8MP_IOMUXC_SAI1_MCLK 248 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
389 >; 249 >;
390 }; 250 };
391 251
392 pinctrl_flexcan1: flexcan1grp { 252 pinctrl_flexcan1: flexcan1grp {
393 fsl,pins = < 253 fsl,pins = <
394 MX8MP_IOMUXC_SAI5_RXD2 254 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
395 MX8MP_IOMUXC_SAI5_RXD1 255 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
396 >; 256 >;
397 }; 257 };
398 258
399 pinctrl_flexcan2: flexcan2grp { 259 pinctrl_flexcan2: flexcan2grp {
400 fsl,pins = < 260 fsl,pins = <
401 MX8MP_IOMUXC_SAI5_MCLK 261 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
402 MX8MP_IOMUXC_SAI5_RXD3 262 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
403 >; 263 >;
404 }; 264 };
405 265
406 pinctrl_flexcan1_reg: flexcan1reggrp { 266 pinctrl_flexcan1_reg: flexcan1reggrp {
407 fsl,pins = < 267 fsl,pins = <
408 MX8MP_IOMUXC_SAI5_RXC_ 268 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
409 >; 269 >;
410 }; 270 };
411 271
412 pinctrl_flexcan2_reg: flexcan2reggrp { 272 pinctrl_flexcan2_reg: flexcan2reggrp {
413 fsl,pins = < 273 fsl,pins = <
414 MX8MP_IOMUXC_SAI5_RXD0 274 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
415 >; 275 >;
416 }; 276 };
417 277
418 pinctrl_i2c2: i2c2grp { 278 pinctrl_i2c2: i2c2grp {
419 fsl,pins = < 279 fsl,pins = <
420 MX8MP_IOMUXC_I2C2_SCL_ 280 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
421 MX8MP_IOMUXC_I2C2_SDA_ 281 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
422 >; 282 >;
423 }; 283 };
424 284
425 pinctrl_i2c2_gpio: i2c2gpiogrp { 285 pinctrl_i2c2_gpio: i2c2gpiogrp {
426 fsl,pins = < 286 fsl,pins = <
427 MX8MP_IOMUXC_I2C2_SCL_ 287 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
428 MX8MP_IOMUXC_I2C2_SDA_ 288 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
429 >; 289 >;
430 }; 290 };
431 291
432 pinctrl_lvds1: lvds1grp { <<
433 fsl,pins = < <<
434 MX8MP_IOMUXC_SD2_WP__G <<
435 >; <<
436 }; <<
437 <<
438 pinctrl_pcie0: pcie0grp { <<
439 fsl,pins = < <<
440 MX8MP_IOMUXC_GPIO1_IO0 <<
441 MX8MP_IOMUXC_GPIO1_IO1 <<
442 MX8MP_IOMUXC_GPIO1_IO1 <<
443 MX8MP_IOMUXC_GPIO1_IO1 <<
444 >; <<
445 }; <<
446 <<
447 pinctrl_pwm3: pwm3grp { <<
448 fsl,pins = < <<
449 MX8MP_IOMUXC_SPDIF_TX_ <<
450 >; <<
451 }; <<
452 <<
453 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 292 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
454 fsl,pins = < 293 fsl,pins = <
455 MX8MP_IOMUXC_SD2_RESET 294 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
456 >; 295 >;
457 }; 296 };
458 297
459 pinctrl_rtc: rtcgrp { <<
460 fsl,pins = < <<
461 MX8MP_IOMUXC_SAI1_TXD7 <<
462 >; <<
463 }; <<
464 <<
465 pinctrl_uart1: uart1grp { 298 pinctrl_uart1: uart1grp {
466 fsl,pins = < 299 fsl,pins = <
467 MX8MP_IOMUXC_UART1_RXD !! 300 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
468 MX8MP_IOMUXC_UART1_TXD !! 301 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
469 >; 302 >;
470 }; 303 };
471 304
472 pinctrl_usb1_vbus: usb1vbusgrp { 305 pinctrl_usb1_vbus: usb1vbusgrp {
473 fsl,pins = < 306 fsl,pins = <
474 MX8MP_IOMUXC_GPIO1_IO1 307 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
475 >; 308 >;
476 }; 309 };
477 310
478 pinctrl_uart2: uart2grp { 311 pinctrl_uart2: uart2grp {
479 fsl,pins = < 312 fsl,pins = <
480 MX8MP_IOMUXC_UART2_RXD 313 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
481 MX8MP_IOMUXC_UART2_TXD 314 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
482 MX8MP_IOMUXC_SAI3_RXC_ 315 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
483 MX8MP_IOMUXC_SAI3_RXD_ 316 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
484 >; 317 >;
485 }; 318 };
486 319
487 pinctrl_usdhc2_pins: usdhc2-gpiogrp { 320 pinctrl_usdhc2_pins: usdhc2-gpiogrp {
488 fsl,pins = < 321 fsl,pins = <
489 MX8MP_IOMUXC_SD2_CD_B_ !! 322 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
490 >; 323 >;
491 }; 324 };
492 325
493 pinctrl_usdhc2: usdhc2grp { 326 pinctrl_usdhc2: usdhc2grp {
494 fsl,pins = < 327 fsl,pins = <
495 MX8MP_IOMUXC_SD2_CLK__ 328 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
496 MX8MP_IOMUXC_SD2_CMD__ 329 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
497 MX8MP_IOMUXC_SD2_DATA0 330 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
498 MX8MP_IOMUXC_SD2_DATA1 331 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
499 MX8MP_IOMUXC_SD2_DATA2 332 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
500 MX8MP_IOMUXC_SD2_DATA3 333 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
501 MX8MP_IOMUXC_GPIO1_IO0 334 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
502 >; 335 >;
503 }; 336 };
504 337
505 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 338 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
506 fsl,pins = < 339 fsl,pins = <
507 MX8MP_IOMUXC_SD2_CLK__ 340 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
508 MX8MP_IOMUXC_SD2_CMD__ 341 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
509 MX8MP_IOMUXC_SD2_DATA0 342 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
510 MX8MP_IOMUXC_SD2_DATA1 343 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
511 MX8MP_IOMUXC_SD2_DATA2 344 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
512 MX8MP_IOMUXC_SD2_DATA3 345 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
513 MX8MP_IOMUXC_GPIO1_IO0 346 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
514 >; 347 >;
515 }; 348 };
516 349
517 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 350 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
518 fsl,pins = < 351 fsl,pins = <
519 MX8MP_IOMUXC_SD2_CLK__ 352 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
520 MX8MP_IOMUXC_SD2_CMD__ 353 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
521 MX8MP_IOMUXC_SD2_DATA0 354 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
522 MX8MP_IOMUXC_SD2_DATA1 355 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
523 MX8MP_IOMUXC_SD2_DATA2 356 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
524 MX8MP_IOMUXC_SD2_DATA3 357 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
525 MX8MP_IOMUXC_GPIO1_IO0 358 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
526 >; 359 >;
527 }; 360 };
528 }; 361 };
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