1 // SPDX-License-Identifier: GPL-2.0 1 // SPDX-License-Identifier: GPL-2.0
2 /* 2 /*
3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH 3 * Copyright (C) 2020 PHYTEC Messtechnik GmbH
4 * Author: Teresa Remmet <t.remmet@phytec.de> 4 * Author: Teresa Remmet <t.remmet@phytec.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include <dt-bindings/phy/phy-imx8-pcie.h> 9 #include <dt-bindings/phy/phy-imx8-pcie.h>
10 #include <dt-bindings/leds/leds-pca9532.h> 10 #include <dt-bindings/leds/leds-pca9532.h>
11 #include <dt-bindings/pwm/pwm.h> 11 #include <dt-bindings/pwm/pwm.h>
12 #include "imx8mp-phycore-som.dtsi" 12 #include "imx8mp-phycore-som.dtsi"
13 13
14 / { 14 / {
15 model = "PHYTEC phyBOARD-Pollux i.MX8M 15 model = "PHYTEC phyBOARD-Pollux i.MX8MP";
16 compatible = "phytec,imx8mp-phyboard-p 16 compatible = "phytec,imx8mp-phyboard-pollux-rdk",
17 "phytec,imx8mp-phycore-so 17 "phytec,imx8mp-phycore-som", "fsl,imx8mp";
18 18
19 chosen { 19 chosen {
20 stdout-path = &uart1; 20 stdout-path = &uart1;
21 }; 21 };
22 22
23 backlight_lvds: backlight { 23 backlight_lvds: backlight {
24 compatible = "pwm-backlight"; 24 compatible = "pwm-backlight";
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_lvds1>; 26 pinctrl-0 = <&pinctrl_lvds1>;
27 brightness-levels = <0 4 8 16 27 brightness-levels = <0 4 8 16 32 64 128 255>;
28 default-brightness-level = <11 28 default-brightness-level = <11>;
29 enable-gpios = <&gpio2 20 GPIO 29 enable-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>;
30 num-interpolated-steps = <2>; 30 num-interpolated-steps = <2>;
31 power-supply = <®_lvds1_reg 31 power-supply = <®_lvds1_reg_en>;
32 pwms = <&pwm3 0 50000 0>; 32 pwms = <&pwm3 0 50000 0>;
33 }; 33 };
34 34
35 panel1_lvds: panel-lvds { 35 panel1_lvds: panel-lvds {
36 compatible = "edt,etml1010g3dr 36 compatible = "edt,etml1010g3dra";
37 backlight = <&backlight_lvds>; 37 backlight = <&backlight_lvds>;
38 power-supply = <®_vcc_3v3_s 38 power-supply = <®_vcc_3v3_sw>;
39 39
40 port { 40 port {
41 panel1_in: endpoint { 41 panel1_in: endpoint {
42 remote-endpoin 42 remote-endpoint = <&ldb_lvds_ch1>;
43 }; 43 };
44 }; 44 };
45 }; 45 };
46 46
47 reg_vcc_5v_sw: regulator-vcc-5v-sw { 47 reg_vcc_5v_sw: regulator-vcc-5v-sw {
48 compatible = "regulator-fixed" 48 compatible = "regulator-fixed";
49 regulator-always-on; 49 regulator-always-on;
50 regulator-boot-on; 50 regulator-boot-on;
51 regulator-max-microvolt = <500 51 regulator-max-microvolt = <5000000>;
52 regulator-min-microvolt = <500 52 regulator-min-microvolt = <5000000>;
53 regulator-name = "VCC_5V_SW"; 53 regulator-name = "VCC_5V_SW";
54 }; 54 };
55 55
56 reg_can1_stby: regulator-can1-stby { 56 reg_can1_stby: regulator-can1-stby {
57 compatible = "regulator-fixed" 57 compatible = "regulator-fixed";
58 pinctrl-names = "default"; 58 pinctrl-names = "default";
59 pinctrl-0 = <&pinctrl_flexcan1 59 pinctrl-0 = <&pinctrl_flexcan1_reg>;
60 gpio = <&gpio3 20 GPIO_ACTIVE_ 60 gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
61 regulator-max-microvolt = <330 61 regulator-max-microvolt = <3300000>;
62 regulator-min-microvolt = <330 62 regulator-min-microvolt = <3300000>;
63 regulator-name = "can1-stby"; 63 regulator-name = "can1-stby";
64 }; 64 };
65 65
66 reg_can2_stby: regulator-can2-stby { 66 reg_can2_stby: regulator-can2-stby {
67 compatible = "regulator-fixed" 67 compatible = "regulator-fixed";
68 pinctrl-names = "default"; 68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_flexcan2 69 pinctrl-0 = <&pinctrl_flexcan2_reg>;
70 gpio = <&gpio3 21 GPIO_ACTIVE_ 70 gpio = <&gpio3 21 GPIO_ACTIVE_LOW>;
71 regulator-max-microvolt = <330 71 regulator-max-microvolt = <3300000>;
72 regulator-min-microvolt = <330 72 regulator-min-microvolt = <3300000>;
73 regulator-name = "can2-stby"; 73 regulator-name = "can2-stby";
74 }; 74 };
75 75
76 reg_lvds1_reg_en: regulator-lvds1 { 76 reg_lvds1_reg_en: regulator-lvds1 {
77 compatible = "regulator-fixed" 77 compatible = "regulator-fixed";
78 enable-active-high; 78 enable-active-high;
79 gpio = <&gpio1 9 GPIO_ACTIVE_H 79 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
80 regulator-max-microvolt = <120 80 regulator-max-microvolt = <1200000>;
81 regulator-min-microvolt = <120 81 regulator-min-microvolt = <1200000>;
82 regulator-name = "lvds1_reg_en 82 regulator-name = "lvds1_reg_en";
83 }; 83 };
84 84
85 reg_usb1_vbus: regulator-usb1-vbus { 85 reg_usb1_vbus: regulator-usb1-vbus {
86 compatible = "regulator-fixed" 86 compatible = "regulator-fixed";
87 pinctrl-names = "default"; 87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_usb1_vbu 88 pinctrl-0 = <&pinctrl_usb1_vbus>;
89 gpio = <&gpio1 12 GPIO_ACTIVE_ 89 gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
90 regulator-max-microvolt = <500 90 regulator-max-microvolt = <5000000>;
91 regulator-min-microvolt = <500 91 regulator-min-microvolt = <5000000>;
92 regulator-name = "usb1_host_vb 92 regulator-name = "usb1_host_vbus";
93 }; 93 };
94 94
95 reg_usdhc2_vmmc: regulator-usdhc2 { 95 reg_usdhc2_vmmc: regulator-usdhc2 {
96 compatible = "regulator-fixed" 96 compatible = "regulator-fixed";
97 pinctrl-names = "default"; 97 pinctrl-names = "default";
98 pinctrl-0 = <&pinctrl_reg_usdh 98 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
99 regulator-name = "VSD_3V3"; 99 regulator-name = "VSD_3V3";
100 regulator-min-microvolt = <330 100 regulator-min-microvolt = <3300000>;
101 regulator-max-microvolt = <330 101 regulator-max-microvolt = <3300000>;
102 gpio = <&gpio2 19 GPIO_ACTIVE_ 102 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
103 enable-active-high; 103 enable-active-high;
104 startup-delay-us = <100>; 104 startup-delay-us = <100>;
105 off-on-delay-us = <12000>; 105 off-on-delay-us = <12000>;
106 }; 106 };
107 107
108 reg_vcc_3v3_sw: regulator-vcc-3v3-sw { 108 reg_vcc_3v3_sw: regulator-vcc-3v3-sw {
109 compatible = "regulator-fixed" 109 compatible = "regulator-fixed";
110 regulator-name = "VCC_3V3_SW"; 110 regulator-name = "VCC_3V3_SW";
111 regulator-min-microvolt = <330 111 regulator-min-microvolt = <3300000>;
112 regulator-max-microvolt = <330 112 regulator-max-microvolt = <3300000>;
113 }; 113 };
114 }; 114 };
115 115
116 /* TPM */ 116 /* TPM */
117 &ecspi1 { 117 &ecspi1 {
118 #address-cells = <1>; 118 #address-cells = <1>;
119 #size-cells = <0>; 119 #size-cells = <0>;
120 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 120 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
121 pinctrl-names = "default"; 121 pinctrl-names = "default";
122 pinctrl-0 = <&pinctrl_ecspi1>; 122 pinctrl-0 = <&pinctrl_ecspi1>;
123 status = "okay"; 123 status = "okay";
124 124
125 tpm: tpm@0 { 125 tpm: tpm@0 {
126 compatible = "infineon,slb9670 126 compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
127 reg = <0>; 127 reg = <0>;
128 spi-max-frequency = <38000000> 128 spi-max-frequency = <38000000>;
129 }; 129 };
130 }; 130 };
131 131
132 &eqos { 132 &eqos {
133 pinctrl-names = "default"; 133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_eqos>; 134 pinctrl-0 = <&pinctrl_eqos>;
135 phy-mode = "rgmii-id"; 135 phy-mode = "rgmii-id";
136 phy-handle = <ðphy0>; 136 phy-handle = <ðphy0>;
137 status = "okay"; 137 status = "okay";
138 138
139 mdio { 139 mdio {
140 compatible = "snps,dwmac-mdio" 140 compatible = "snps,dwmac-mdio";
141 #address-cells = <1>; 141 #address-cells = <1>;
142 #size-cells = <0>; 142 #size-cells = <0>;
143 143
144 ethphy0: ethernet-phy@1 { 144 ethphy0: ethernet-phy@1 {
145 compatible = "ethernet 145 compatible = "ethernet-phy-ieee802.3-c22";
146 reg = <0x1>; 146 reg = <0x1>;
147 ti,rx-internal-delay = 147 ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
148 ti,tx-internal-delay = 148 ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>;
149 ti,fifo-depth = <DP838 149 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
150 ti,clk-output-sel = <D 150 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
151 enet-phy-lane-no-swap; 151 enet-phy-lane-no-swap;
152 }; 152 };
153 }; 153 };
154 }; 154 };
155 155
156 /* CAN FD */ 156 /* CAN FD */
157 &flexcan1 { 157 &flexcan1 {
158 pinctrl-names = "default"; 158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_flexcan1>; 159 pinctrl-0 = <&pinctrl_flexcan1>;
160 xceiver-supply = <®_can1_stby>; 160 xceiver-supply = <®_can1_stby>;
161 status = "okay"; 161 status = "okay";
162 }; 162 };
163 163
164 &flexcan2 { 164 &flexcan2 {
165 pinctrl-names = "default"; 165 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_flexcan2>; 166 pinctrl-0 = <&pinctrl_flexcan2>;
167 xceiver-supply = <®_can2_stby>; 167 xceiver-supply = <®_can2_stby>;
168 status = "okay"; 168 status = "okay";
169 }; 169 };
170 170
171 &i2c2 { 171 &i2c2 {
172 clock-frequency = <400000>; 172 clock-frequency = <400000>;
173 pinctrl-names = "default", "gpio"; 173 pinctrl-names = "default", "gpio";
174 pinctrl-0 = <&pinctrl_i2c2>; 174 pinctrl-0 = <&pinctrl_i2c2>;
175 pinctrl-1 = <&pinctrl_i2c2_gpio>; 175 pinctrl-1 = <&pinctrl_i2c2_gpio>;
176 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 176 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
177 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 177 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
178 status = "okay"; 178 status = "okay";
179 179
180 eeprom@51 { 180 eeprom@51 {
181 compatible = "atmel,24c02"; 181 compatible = "atmel,24c02";
182 reg = <0x51>; 182 reg = <0x51>;
183 pagesize = <16>; 183 pagesize = <16>;
184 vcc-supply = <®_vcc_3v3_sw> 184 vcc-supply = <®_vcc_3v3_sw>;
185 }; 185 };
186 186
187 leds@62 { 187 leds@62 {
188 compatible = "nxp,pca9533"; 188 compatible = "nxp,pca9533";
189 reg = <0x62>; 189 reg = <0x62>;
190 190
191 led-1 { 191 led-1 {
192 type = <PCA9532_TYPE_L 192 type = <PCA9532_TYPE_LED>;
193 }; 193 };
194 194
195 led-2 { 195 led-2 {
196 type = <PCA9532_TYPE_L 196 type = <PCA9532_TYPE_LED>;
197 }; 197 };
198 198
199 led-3 { 199 led-3 {
200 type = <PCA9532_TYPE_L 200 type = <PCA9532_TYPE_LED>;
201 }; 201 };
202 }; 202 };
203 }; 203 };
204 204
205 &lcdif2 { 205 &lcdif2 {
206 status = "okay"; 206 status = "okay";
207 }; 207 };
208 208
209 &lvds_bridge { 209 &lvds_bridge {
210 status = "okay"; 210 status = "okay";
211 211
212 ports { 212 ports {
213 port@2 { 213 port@2 {
214 ldb_lvds_ch1: endpoint 214 ldb_lvds_ch1: endpoint {
215 remote-endpoin 215 remote-endpoint = <&panel1_in>;
216 }; 216 };
217 }; 217 };
218 }; 218 };
219 }; 219 };
220 220
221 &media_blk_ctrl { 221 &media_blk_ctrl {
222 /* 222 /*
223 * The LVDS panel on this device uses 223 * The LVDS panel on this device uses 72.4 MHz pixel clock,
224 * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 224 * set IMX8MP_VIDEO_PLL1 to 72.4 * 7 = 506.8 MHz so the LDB
225 * serializer and LCDIFv3 scanout engi 225 * serializer and LCDIFv3 scanout engine can reach accurate
226 * pixel clock of exactly 72.4 MHz. 226 * pixel clock of exactly 72.4 MHz.
227 */ 227 */
228 assigned-clock-rates = <500000000>, <2 228 assigned-clock-rates = <500000000>, <200000000>,
229 <0>, <0>, <5000 229 <0>, <0>, <500000000>,
230 <506800000>; 230 <506800000>;
231 }; 231 };
232 232
233 &snvs_pwrkey { 233 &snvs_pwrkey {
234 status = "okay"; 234 status = "okay";
235 }; 235 };
236 236
237 &pcie_phy { 237 &pcie_phy {
238 clocks = <&hsio_blk_ctrl>; 238 clocks = <&hsio_blk_ctrl>;
239 clock-names = "ref"; 239 clock-names = "ref";
240 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 240 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>;
241 fsl,clkreq-unsupported; 241 fsl,clkreq-unsupported;
242 status = "okay"; 242 status = "okay";
243 }; 243 };
244 244
245 /* Mini PCIe */ 245 /* Mini PCIe */
246 &pcie { 246 &pcie {
247 pinctrl-names = "default"; 247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_pcie0>; 248 pinctrl-0 = <&pinctrl_pcie0>;
249 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW 249 reset-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
250 vpcie-supply = <®_vcc_3v3_sw>; 250 vpcie-supply = <®_vcc_3v3_sw>;
251 status = "okay"; 251 status = "okay";
252 }; 252 };
253 253
254 &pwm3 { 254 &pwm3 {
255 status = "okay"; 255 status = "okay";
256 pinctrl-names = "default"; 256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_pwm3>; 257 pinctrl-0 = <&pinctrl_pwm3>;
258 }; 258 };
259 259
260 &rv3028 { 260 &rv3028 {
261 pinctrl-names = "default"; 261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_rtc>; 262 pinctrl-0 = <&pinctrl_rtc>;
263 interrupt-parent = <&gpio4>; 263 interrupt-parent = <&gpio4>;
264 interrupts = <19 IRQ_TYPE_LEVEL_LOW>; 264 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
265 aux-voltage-chargeable = <1>; 265 aux-voltage-chargeable = <1>;
266 wakeup-source; 266 wakeup-source;
267 trickle-resistor-ohms = <3000>; 267 trickle-resistor-ohms = <3000>;
268 }; 268 };
269 269
270 /* debug console */ 270 /* debug console */
271 &uart1 { 271 &uart1 {
272 pinctrl-names = "default"; 272 pinctrl-names = "default";
273 pinctrl-0 = <&pinctrl_uart1>; 273 pinctrl-0 = <&pinctrl_uart1>;
274 status = "okay"; 274 status = "okay";
275 }; 275 };
276 276
277 /* USB1 Host mode Type-A */ 277 /* USB1 Host mode Type-A */
278 &usb3_phy0 { 278 &usb3_phy0 {
279 vbus-supply = <®_usb1_vbus>; 279 vbus-supply = <®_usb1_vbus>;
280 status = "okay"; 280 status = "okay";
281 }; 281 };
282 282
283 &usb3_0 { 283 &usb3_0 {
284 status = "okay"; 284 status = "okay";
285 }; 285 };
286 286
287 &usb_dwc3_0 { 287 &usb_dwc3_0 {
288 dr_mode = "host"; 288 dr_mode = "host";
289 status = "okay"; 289 status = "okay";
290 }; 290 };
291 291
292 /* USB2 4-port USB3.0 HUB */ 292 /* USB2 4-port USB3.0 HUB */
293 &usb3_phy1 { 293 &usb3_phy1 {
294 vbus-supply = <®_vcc_5v_sw>; 294 vbus-supply = <®_vcc_5v_sw>;
295 status = "okay"; 295 status = "okay";
296 }; 296 };
297 297
298 &usb3_1 { 298 &usb3_1 {
299 fsl,permanently-attached; 299 fsl,permanently-attached;
300 fsl,disable-port-power-control; 300 fsl,disable-port-power-control;
301 status = "okay"; 301 status = "okay";
302 }; 302 };
303 303
304 &usb_dwc3_1 { 304 &usb_dwc3_1 {
305 dr_mode = "host"; 305 dr_mode = "host";
306 status = "okay"; 306 status = "okay";
307 }; 307 };
308 308
309 /* RS232/RS485 */ 309 /* RS232/RS485 */
310 &uart2 { 310 &uart2 {
311 assigned-clocks = <&clk IMX8MP_CLK_UAR 311 assigned-clocks = <&clk IMX8MP_CLK_UART2>;
312 assigned-clock-parents = <&clk IMX8MP_ 312 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
313 pinctrl-names = "default"; 313 pinctrl-names = "default";
314 pinctrl-0 = <&pinctrl_uart2>; 314 pinctrl-0 = <&pinctrl_uart2>;
315 uart-has-rtscts; 315 uart-has-rtscts;
316 status = "okay"; 316 status = "okay";
317 }; 317 };
318 318
319 /* SD-Card */ 319 /* SD-Card */
320 &usdhc2 { 320 &usdhc2 {
321 assigned-clocks = <&clk IMX8MP_CLK_USD 321 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
322 assigned-clock-rates = <200000000>; 322 assigned-clock-rates = <200000000>;
323 pinctrl-names = "default", "state_100m 323 pinctrl-names = "default", "state_100mhz", "state_200mhz";
324 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 324 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_pins>;
325 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 325 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_pins>;
326 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 326 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_pins>;
327 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 327 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
328 disable-wp; 328 disable-wp;
329 vmmc-supply = <®_usdhc2_vmmc>; 329 vmmc-supply = <®_usdhc2_vmmc>;
330 vqmmc-supply = <&ldo5>; 330 vqmmc-supply = <&ldo5>;
331 bus-width = <4>; 331 bus-width = <4>;
332 status = "okay"; 332 status = "okay";
333 }; 333 };
334 334
335 &gpio1 { 335 &gpio1 {
336 gpio-line-names = "", "", "X_PMIC_WDOG 336 gpio-line-names = "", "", "X_PMIC_WDOG_B", "",
337 "PMIC_SD_VSEL", "", "", "", "" 337 "PMIC_SD_VSEL", "", "", "", "", "",
338 "", "", "USB1_OTG_PWR", "", "" 338 "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT";
339 }; 339 };
340 340
341 &gpio2 { 341 &gpio2 {
342 gpio-line-names = "", "", "", "", 342 gpio-line-names = "", "", "", "",
343 "", "", "", "", "", "", 343 "", "", "", "", "", "",
344 "", "", "X_SD2_CD_B", "", "", 344 "", "", "X_SD2_CD_B", "", "", "",
345 "", "", "", "SD2_RESET_B"; 345 "", "", "", "SD2_RESET_B";
346 }; 346 };
347 347
348 &gpio3 { 348 &gpio3 {
349 gpio-line-names = "", "", "", "", 349 gpio-line-names = "", "", "", "",
350 "", "", "", "", "", "", 350 "", "", "", "", "", "",
351 "", "", "", "", "", "", 351 "", "", "", "", "", "",
352 "", "", "", "", "nCAN1_EN", "n 352 "", "", "", "", "nCAN1_EN", "nCAN2_EN";
353 }; 353 };
354 354
355 &gpio4 { 355 &gpio4 {
356 gpio-line-names = "", "", "", "", 356 gpio-line-names = "", "", "", "",
357 "", "", "", "", "", "", 357 "", "", "", "", "", "",
358 "", "", "", "", "", "", 358 "", "", "", "", "", "",
359 "", "", "X_PMIC_IRQ_B", "", "n 359 "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN";
360 }; 360 };
361 361
362 &iomuxc { 362 &iomuxc {
363 pinctrl_ecspi1: ecspi1grp { 363 pinctrl_ecspi1: ecspi1grp {
364 fsl,pins = < 364 fsl,pins = <
365 MX8MP_IOMUXC_ECSPI1_MI 365 MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80
366 MX8MP_IOMUXC_ECSPI1_MO 366 MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80
367 MX8MP_IOMUXC_ECSPI1_SC 367 MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80
368 MX8MP_IOMUXC_ECSPI1_SS 368 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00
369 >; 369 >;
370 }; 370 };
371 371
372 pinctrl_eqos: eqosgrp { 372 pinctrl_eqos: eqosgrp {
373 fsl,pins = < 373 fsl,pins = <
374 MX8MP_IOMUXC_ENET_MDC_ 374 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
375 MX8MP_IOMUXC_ENET_MDIO 375 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
376 MX8MP_IOMUXC_ENET_RD0_ 376 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
377 MX8MP_IOMUXC_ENET_RD1_ 377 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
378 MX8MP_IOMUXC_ENET_RD2_ 378 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
379 MX8MP_IOMUXC_ENET_RD3_ 379 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
380 MX8MP_IOMUXC_ENET_RXC_ 380 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
381 MX8MP_IOMUXC_ENET_RX_C 381 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
382 MX8MP_IOMUXC_ENET_TD0_ 382 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12
383 MX8MP_IOMUXC_ENET_TD1_ 383 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12
384 MX8MP_IOMUXC_ENET_TD2_ 384 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x12
385 MX8MP_IOMUXC_ENET_TD3_ 385 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x12
386 MX8MP_IOMUXC_ENET_TX_C 386 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12
387 MX8MP_IOMUXC_ENET_TXC_ 387 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x12
388 MX8MP_IOMUXC_SAI1_MCLK 388 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
389 >; 389 >;
390 }; 390 };
391 391
392 pinctrl_flexcan1: flexcan1grp { 392 pinctrl_flexcan1: flexcan1grp {
393 fsl,pins = < 393 fsl,pins = <
394 MX8MP_IOMUXC_SAI5_RXD2 394 MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154
395 MX8MP_IOMUXC_SAI5_RXD1 395 MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154
396 >; 396 >;
397 }; 397 };
398 398
399 pinctrl_flexcan2: flexcan2grp { 399 pinctrl_flexcan2: flexcan2grp {
400 fsl,pins = < 400 fsl,pins = <
401 MX8MP_IOMUXC_SAI5_MCLK 401 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
402 MX8MP_IOMUXC_SAI5_RXD3 402 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
403 >; 403 >;
404 }; 404 };
405 405
406 pinctrl_flexcan1_reg: flexcan1reggrp { 406 pinctrl_flexcan1_reg: flexcan1reggrp {
407 fsl,pins = < 407 fsl,pins = <
408 MX8MP_IOMUXC_SAI5_RXC_ 408 MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154
409 >; 409 >;
410 }; 410 };
411 411
412 pinctrl_flexcan2_reg: flexcan2reggrp { 412 pinctrl_flexcan2_reg: flexcan2reggrp {
413 fsl,pins = < 413 fsl,pins = <
414 MX8MP_IOMUXC_SAI5_RXD0 414 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154
415 >; 415 >;
416 }; 416 };
417 417
418 pinctrl_i2c2: i2c2grp { 418 pinctrl_i2c2: i2c2grp {
419 fsl,pins = < 419 fsl,pins = <
420 MX8MP_IOMUXC_I2C2_SCL_ 420 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
421 MX8MP_IOMUXC_I2C2_SDA_ 421 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
422 >; 422 >;
423 }; 423 };
424 424
425 pinctrl_i2c2_gpio: i2c2gpiogrp { 425 pinctrl_i2c2_gpio: i2c2gpiogrp {
426 fsl,pins = < 426 fsl,pins = <
427 MX8MP_IOMUXC_I2C2_SCL_ 427 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
428 MX8MP_IOMUXC_I2C2_SDA_ 428 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
429 >; 429 >;
430 }; 430 };
431 431
432 pinctrl_lvds1: lvds1grp { 432 pinctrl_lvds1: lvds1grp {
433 fsl,pins = < 433 fsl,pins = <
434 MX8MP_IOMUXC_SD2_WP__G 434 MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x12
435 >; 435 >;
436 }; 436 };
437 437
438 pinctrl_pcie0: pcie0grp { 438 pinctrl_pcie0: pcie0grp {
439 fsl,pins = < 439 fsl,pins = <
440 MX8MP_IOMUXC_GPIO1_IO0 440 MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x40
441 MX8MP_IOMUXC_GPIO1_IO1 441 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x60
442 MX8MP_IOMUXC_GPIO1_IO1 442 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x60 /* open drain, pull up */
443 MX8MP_IOMUXC_GPIO1_IO1 443 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x40
444 >; 444 >;
445 }; 445 };
446 446
447 pinctrl_pwm3: pwm3grp { 447 pinctrl_pwm3: pwm3grp {
448 fsl,pins = < 448 fsl,pins = <
449 MX8MP_IOMUXC_SPDIF_TX_ 449 MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x12
450 >; 450 >;
451 }; 451 };
452 452
453 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc 453 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
454 fsl,pins = < 454 fsl,pins = <
455 MX8MP_IOMUXC_SD2_RESET 455 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
456 >; 456 >;
457 }; 457 };
458 458
459 pinctrl_rtc: rtcgrp { 459 pinctrl_rtc: rtcgrp {
460 fsl,pins = < 460 fsl,pins = <
461 MX8MP_IOMUXC_SAI1_TXD7 461 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x1C0
462 >; 462 >;
463 }; 463 };
464 464
465 pinctrl_uart1: uart1grp { 465 pinctrl_uart1: uart1grp {
466 fsl,pins = < 466 fsl,pins = <
467 MX8MP_IOMUXC_UART1_RXD 467 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
468 MX8MP_IOMUXC_UART1_TXD 468 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
469 >; 469 >;
470 }; 470 };
471 471
472 pinctrl_usb1_vbus: usb1vbusgrp { 472 pinctrl_usb1_vbus: usb1vbusgrp {
473 fsl,pins = < 473 fsl,pins = <
474 MX8MP_IOMUXC_GPIO1_IO1 474 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10
475 >; 475 >;
476 }; 476 };
477 477
478 pinctrl_uart2: uart2grp { 478 pinctrl_uart2: uart2grp {
479 fsl,pins = < 479 fsl,pins = <
480 MX8MP_IOMUXC_UART2_RXD 480 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
481 MX8MP_IOMUXC_UART2_TXD 481 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
482 MX8MP_IOMUXC_SAI3_RXC_ 482 MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140
483 MX8MP_IOMUXC_SAI3_RXD_ 483 MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140
484 >; 484 >;
485 }; 485 };
486 486
487 pinctrl_usdhc2_pins: usdhc2-gpiogrp { 487 pinctrl_usdhc2_pins: usdhc2-gpiogrp {
488 fsl,pins = < 488 fsl,pins = <
489 MX8MP_IOMUXC_SD2_CD_B_ 489 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x40
490 >; 490 >;
491 }; 491 };
492 492
493 pinctrl_usdhc2: usdhc2grp { 493 pinctrl_usdhc2: usdhc2grp {
494 fsl,pins = < 494 fsl,pins = <
495 MX8MP_IOMUXC_SD2_CLK__ 495 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
496 MX8MP_IOMUXC_SD2_CMD__ 496 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
497 MX8MP_IOMUXC_SD2_DATA0 497 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
498 MX8MP_IOMUXC_SD2_DATA1 498 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
499 MX8MP_IOMUXC_SD2_DATA2 499 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
500 MX8MP_IOMUXC_SD2_DATA3 500 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
501 MX8MP_IOMUXC_GPIO1_IO0 501 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
502 >; 502 >;
503 }; 503 };
504 504
505 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 505 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
506 fsl,pins = < 506 fsl,pins = <
507 MX8MP_IOMUXC_SD2_CLK__ 507 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
508 MX8MP_IOMUXC_SD2_CMD__ 508 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
509 MX8MP_IOMUXC_SD2_DATA0 509 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
510 MX8MP_IOMUXC_SD2_DATA1 510 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
511 MX8MP_IOMUXC_SD2_DATA2 511 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
512 MX8MP_IOMUXC_SD2_DATA3 512 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
513 MX8MP_IOMUXC_GPIO1_IO0 513 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
514 >; 514 >;
515 }; 515 };
516 516
517 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 517 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
518 fsl,pins = < 518 fsl,pins = <
519 MX8MP_IOMUXC_SD2_CLK__ 519 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
520 MX8MP_IOMUXC_SD2_CMD__ 520 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
521 MX8MP_IOMUXC_SD2_DATA0 521 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
522 MX8MP_IOMUXC_SD2_DATA1 522 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
523 MX8MP_IOMUXC_SD2_DATA2 523 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
524 MX8MP_IOMUXC_SD2_DATA3 524 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
525 MX8MP_IOMUXC_GPIO1_IO0 525 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
526 >; 526 >;
527 }; 527 };
528 }; 528 };
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