~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

TOMOYO Linux Cross Reference
Linux/scripts/dtc/include-prefixes/arm64/freescale/imx8mp-pinfunc.h

Version: ~ [ linux-6.12-rc7 ] ~ [ linux-6.11.7 ] ~ [ linux-6.10.14 ] ~ [ linux-6.9.12 ] ~ [ linux-6.8.12 ] ~ [ linux-6.7.12 ] ~ [ linux-6.6.60 ] ~ [ linux-6.5.13 ] ~ [ linux-6.4.16 ] ~ [ linux-6.3.13 ] ~ [ linux-6.2.16 ] ~ [ linux-6.1.116 ] ~ [ linux-6.0.19 ] ~ [ linux-5.19.17 ] ~ [ linux-5.18.19 ] ~ [ linux-5.17.15 ] ~ [ linux-5.16.20 ] ~ [ linux-5.15.171 ] ~ [ linux-5.14.21 ] ~ [ linux-5.13.19 ] ~ [ linux-5.12.19 ] ~ [ linux-5.11.22 ] ~ [ linux-5.10.229 ] ~ [ linux-5.9.16 ] ~ [ linux-5.8.18 ] ~ [ linux-5.7.19 ] ~ [ linux-5.6.19 ] ~ [ linux-5.5.19 ] ~ [ linux-5.4.285 ] ~ [ linux-5.3.18 ] ~ [ linux-5.2.21 ] ~ [ linux-5.1.21 ] ~ [ linux-5.0.21 ] ~ [ linux-4.20.17 ] ~ [ linux-4.19.323 ] ~ [ linux-4.18.20 ] ~ [ linux-4.17.19 ] ~ [ linux-4.16.18 ] ~ [ linux-4.15.18 ] ~ [ linux-4.14.336 ] ~ [ linux-4.13.16 ] ~ [ linux-4.12.14 ] ~ [ linux-4.11.12 ] ~ [ linux-4.10.17 ] ~ [ linux-4.9.337 ] ~ [ linux-4.4.302 ] ~ [ linux-3.10.108 ] ~ [ linux-2.6.32.71 ] ~ [ linux-2.6.0 ] ~ [ linux-2.4.37.11 ] ~ [ unix-v6-master ] ~ [ ccs-tools-1.8.12 ] ~ [ policy-sample ] ~
Architecture: ~ [ i386 ] ~ [ alpha ] ~ [ m68k ] ~ [ mips ] ~ [ ppc ] ~ [ sparc ] ~ [ sparc64 ] ~

Diff markup

Differences between /scripts/dtc/include-prefixes/arm64/freescale/imx8mp-pinfunc.h (Version linux-6.12-rc7) and /scripts/dtc/include-prefixes/arm64/freescale/imx8mp-pinfunc.h (Version linux-4.18.20)


  1 /* SPDX-License-Identifier: GPL-2.0+ */             1 
  2 /*                                                
  3  * Copyright 2019 NXP                             
  4  */                                               
  5                                                   
  6 #ifndef __DTS_IMX8MP_PINFUNC_H                    
  7 #define __DTS_IMX8MP_PINFUNC_H                    
  8                                                   
  9 /*                                                
 10  * The pin function ID is a tuple of              
 11  * <mux_reg conf_reg input_reg mux_mode input_    
 12  */                                               
 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00       
 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_    
 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0    
 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1     
 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01       
 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT         
 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_T    
 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2     
 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02       
 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B     
 23 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRI    
 24 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_AN    
 25 #define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B         
 26 #define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03       
 27 #define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELEC    
 28 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_    
 29 #define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVE    
 30 #define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04       
 31 #define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELEC    
 32 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_O    
 33 #define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVE    
 34 #define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05       
 35 #define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI           
 36 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1    
 37 #define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READ    
 38 #define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06       
 39 #define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC     
 40 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_T    
 41 #define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B      
 42 #define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3     
 43 #define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07       
 44 #define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO    
 45 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRI    
 46 #define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP        
 47 #define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4     
 48 #define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08       
 49 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588    
 50 #define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT         
 51 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_    
 52 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588    
 53 #define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_    
 54 #define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09       
 55 #define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588    
 56 #define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT         
 57 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_O    
 58 #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_    
 59 #define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVE    
 60 #define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10       
 61 #define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID      
 62 #define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT         
 63 #define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11       
 64 #define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID      
 65 #define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT         
 66 #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELEC    
 67 #define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READ    
 68 #define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12       
 69 #define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR     
 70 #define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVE    
 71 #define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13       
 72 #define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC      
 73 #define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT         
 74 #define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14       
 75 #define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR     
 76 #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B      
 77 #define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT         
 78 #define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1        
 79 #define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15       
 80 #define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC      
 81 #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP        
 82 #define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT         
 83 #define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2        
 84 #define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC       
 85 #define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_T    
 86 #define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16         
 87 #define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE      
 88 #define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO     
 89 #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_    
 90 #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_B    
 91 #define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17        
 92 #define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5      
 93 #define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_    
 94 #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_T    
 95 #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BI    
 96 #define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18         
 97 #define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6       
 98 #define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_    
 99 #define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CL    
100 #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_R    
101 #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BI    
102 #define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19         
103 #define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7       
104 #define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_    
105 #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_R    
106 #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BI    
107 #define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20         
108 #define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B        
109 #define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_    
110 #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_R    
111 #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CL    
112 #define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21         
113 #define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP          
114 #define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGM    
115 #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI    
116 #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPD    
117 #define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22      
118 #define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0    
119 #define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CL    
120 #define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER     
121 #define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_T    
122 #define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23         
123 #define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1       
124 #define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGM    
125 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI    
126 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM    
127 #define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24      
128 #define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2    
129 #define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CL    
130 #define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER     
131 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_T    
132 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BI    
133 #define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25         
134 #define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3       
135 #define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_    
136 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_R    
137 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BI    
138 #define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26         
139 #define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4       
140 #define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_    
141 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_R    
142 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BI    
143 #define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27         
144 #define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B     
145 #define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_    
146 #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_R    
147 #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CL    
148 #define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28         
149 #define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK         
150 #define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_    
151 #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_M    
152 #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1    
153 #define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29         
154 #define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD         
155 #define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK          
156 #define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC           
157 #define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL            
158 #define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX        
159 #define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX        
160 #define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00          
161 #define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD          
162 #define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO          
163 #define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA            
164 #define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX        
165 #define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX        
166 #define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01          
167 #define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0      
168 #define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD    
169 #define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL          
170 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS     
171 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS     
172 #define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02        
173 #define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1      
174 #define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD    
175 #define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA          
176 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS     
177 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS     
178 #define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03        
179 #define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2      
180 #define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD    
181 #define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL          
182 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX      
183 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX      
184 #define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04        
185 #define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3      
186 #define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD    
187 #define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA          
188 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX      
189 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX      
190 #define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05        
191 #define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4      
192 #define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX    
193 #define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL          
194 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS     
195 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS     
196 #define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06        
197 #define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5      
198 #define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER       
199 #define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA          
200 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS     
201 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS     
202 #define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07        
203 #define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6      
204 #define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX    
205 #define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL          
206 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX      
207 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX      
208 #define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08        
209 #define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7      
210 #define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER       
211 #define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA          
212 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX      
213 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX      
214 #define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09        
215 #define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET    
216 #define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK    
217 #define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL        
218 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RT    
219 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CT    
220 #define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10      
221 #define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE    
222 #define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA         
223 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS    
224 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS    
225 #define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11       
226 #define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B        
227 #define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12         
228 #define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK          
229 #define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK         
230 #define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX        
231 #define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX        
232 #define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13          
233 #define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD          
234 #define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI         
235 #define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX        
236 #define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX        
237 #define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK    
238 #define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14          
239 #define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0      
240 #define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA          
241 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX      
242 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX      
243 #define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_B    
244 #define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15        
245 #define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1      
246 #define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL          
247 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX      
248 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX      
249 #define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_B    
250 #define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16        
251 #define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2      
252 #define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0        
253 #define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF    
254 #define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_B    
255 #define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17        
256 #define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3      
257 #define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO       
258 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF    
259 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_B    
260 #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18        
261 #define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESE    
262 #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET    
263 #define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19      
264 #define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_R    
265 #define MX8MP_IOMUXC_SD2_WP__USDHC2_WP            
266 #define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20           
267 #define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI     
268 #define MX8MP_IOMUXC_NAND_ALE__NAND_ALE           
269 #define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK     
270 #define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_T    
271 #define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0      
272 #define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX       
273 #define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX       
274 #define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00         
275 #define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE    
276 #define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B       
277 #define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0    
278 #define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3    
279 #define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_T    
280 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX     
281 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX     
282 #define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01       
283 #define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRA    
284 #define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B       
285 #define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1    
286 #define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE    
287 #define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL         
288 #define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02       
289 #define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRA    
290 #define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B       
291 #define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0    
292 #define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5     
293 #define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA         
294 #define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03       
295 #define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRA    
296 #define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B       
297 #define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1    
298 #define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6     
299 #define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA         
300 #define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04       
301 #define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRA    
302 #define MX8MP_IOMUXC_NAND_CLE__NAND_CLE           
303 #define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK     
304 #define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7       
305 #define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX       
306 #define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX       
307 #define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05         
308 #define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE    
309 #define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00     
310 #define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DA    
311 #define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI    
312 #define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TR    
313 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX    
314 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX    
315 #define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06      
316 #define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TR    
317 #define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01     
318 #define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DA    
319 #define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI    
320 #define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT    
321 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX    
322 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX    
323 #define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07      
324 #define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TR    
325 #define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02     
326 #define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DA    
327 #define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B     
328 #define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CT    
329 #define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RT    
330 #define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA        
331 #define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08      
332 #define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TR    
333 #define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03     
334 #define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DA    
335 #define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP       
336 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RT    
337 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CT    
338 #define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_    
339 #define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09      
340 #define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TR    
341 #define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04     
342 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DA    
343 #define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0    
344 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DA    
345 #define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_    
346 #define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10      
347 #define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TR    
348 #define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05     
349 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DA    
350 #define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1    
351 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DA    
352 #define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TR    
353 #define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11      
354 #define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TR    
355 #define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06     
356 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DA    
357 #define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2    
358 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DA    
359 #define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT    
360 #define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12      
361 #define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TR    
362 #define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07     
363 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DA    
364 #define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3    
365 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DA    
366 #define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_    
367 #define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13      
368 #define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TR    
369 #define MX8MP_IOMUXC_NAND_DQS__NAND_DQS           
370 #define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS      
371 #define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_M    
372 #define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPE    
373 #define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL           
374 #define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14         
375 #define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE    
376 #define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B         
377 #define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS     
378 #define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4      
379 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX      
380 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX      
381 #define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15        
382 #define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRAC    
383 #define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_    
384 #define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESE    
385 #define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL       
386 #define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16     
387 #define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_T    
388 #define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B         
389 #define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK        
390 #define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA          
391 #define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17        
392 #define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRAC    
393 #define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B         
394 #define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD        
395 #define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL          
396 #define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18        
397 #define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVEN    
398 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_    
399 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_    
400 #define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT          
401 #define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL          
402 #define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19        
403 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_R    
404 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_T    
405 #define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT           
406 #define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA           
407 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CL    
408 #define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20         
409 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_    
410 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_    
411 #define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT          
412 #define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL          
413 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_B    
414 #define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21        
415 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_    
416 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_    
417 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_    
418 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_    
419 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_B    
420 #define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22        
421 #define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX           
422 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_    
423 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_    
424 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_    
425 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_    
426 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_B    
427 #define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23        
428 #define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX           
429 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_    
430 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_    
431 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_    
432 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_    
433 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_B    
434 #define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24        
435 #define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX           
436 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_    
437 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_    
438 #define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT          
439 #define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA          
440 #define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25        
441 #define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX           
442 #define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_    
443 #define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVE    
444 #define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00        
445 #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_R    
446 #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CL    
447 #define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVEN    
448 #define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01         
449 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_    
450 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_    
451 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_B    
452 #define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVE    
453 #define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02        
454 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_    
455 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_B    
456 #define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVE    
457 #define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03        
458 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_    
459 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_B    
460 #define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC         
461 #define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04        
462 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_    
463 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_B    
464 #define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO        
465 #define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05        
466 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_    
467 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_    
468 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_    
469 #define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD    
470 #define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06        
471 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_    
472 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_    
473 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_    
474 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_    
475 #define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD    
476 #define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07        
477 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_    
478 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_    
479 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_    
480 #define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD    
481 #define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08        
482 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_    
483 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_    
484 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_    
485 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_    
486 #define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD    
487 #define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09        
488 #define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_    
489 #define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX    
490 #define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10        
491 #define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_T    
492 #define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC    
493 #define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11         
494 #define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_    
495 #define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD    
496 #define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12        
497 #define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_    
498 #define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD    
499 #define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13        
500 #define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_    
501 #define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD    
502 #define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14        
503 #define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_    
504 #define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD    
505 #define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15        
506 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_    
507 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_    
508 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_    
509 #define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX    
510 #define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16        
511 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_    
512 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_    
513 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_    
514 #define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TX    
515 #define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17        
516 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_    
517 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_    
518 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_    
519 #define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER       
520 #define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18        
521 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_    
522 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_    
523 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_C    
524 #define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER       
525 #define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19        
526 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_    
527 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_    
528 #define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK      
529 #define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20        
530 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_    
531 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_    
532 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_    
533 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_    
534 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX      
535 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX      
536 #define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21        
537 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_B    
538 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_R    
539 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_T    
540 #define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX            
541 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX       
542 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX       
543 #define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22         
544 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BI    
545 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_    
546 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_    
547 #define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_    
548 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_    
549 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS     
550 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS     
551 #define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23        
552 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_B    
553 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_    
554 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_    
555 #define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_    
556 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_    
557 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS     
558 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS     
559 #define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24        
560 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_B    
561 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_T    
562 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_T    
563 #define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX            
564 #define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25         
565 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BI    
566 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_    
567 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_    
568 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_    
569 #define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX           
570 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_    
571 #define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26        
572 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_    
573 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_    
574 #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_    
575 #define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX           
576 #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_    
577 #define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27        
578 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_    
579 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_    
580 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_    
581 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_    
582 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_    
583 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF    
584 #define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28        
585 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_B    
586 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_R    
587 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_R    
588 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_R    
589 #define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK           
590 #define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS      
591 #define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS      
592 #define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29         
593 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CL    
594 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_R    
595 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_R    
596 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_R    
597 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS      
598 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS      
599 #define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30         
600 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BI    
601 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_    
602 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_    
603 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_    
604 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_    
605 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX      
606 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX      
607 #define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31        
608 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_B    
609 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_T    
610 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_T    
611 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_R    
612 #define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1      
613 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX       
614 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX       
615 #define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00         
616 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BI    
617 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_T    
618 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_T    
619 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_R    
620 #define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2      
621 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1    
622 #define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01         
623 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_    
624 #define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT          
625 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_    
626 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF    
627 #define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02        
628 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF    
629 #define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1    
630 #define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT           
631 #define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL           
632 #define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1      
633 #define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX            
634 #define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03         
635 #define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1    
636 #define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT           
637 #define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA           
638 #define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2      
639 #define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX            
640 #define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04         
641 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPA    
642 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05    
643 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_S    
644 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT      
645 #define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK     
646 #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX    
647 #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX    
648 #define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL        
649 #define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI    
650 #define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06      
651 #define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI     
652 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX    
653 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX    
654 #define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA        
655 #define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI    
656 #define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07      
657 #define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO     
658 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CT    
659 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RT    
660 #define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL        
661 #define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI    
662 #define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08      
663 #define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0       
664 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS    
665 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS    
666 #define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA         
667 #define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7    
668 #define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09       
669 #define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK     
670 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX    
671 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX    
672 #define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL        
673 #define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI    
674 #define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10      
675 #define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI     
676 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX    
677 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX    
678 #define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA        
679 #define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI    
680 #define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11      
681 #define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12      
682 #define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO     
683 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CT    
684 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RT    
685 #define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL        
686 #define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI    
687 #define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1       
688 #define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0       
689 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS    
690 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS    
691 #define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA         
692 #define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2        
693 #define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13       
694 #define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL           
695 #define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC       
696 #define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK        
697 #define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14         
698 #define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA           
699 #define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO      
700 #define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI        
701 #define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15         
702 #define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL           
703 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_E    
704 #define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B        
705 #define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO        
706 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_E    
707 #define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16         
708 #define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA           
709 #define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_E    
710 #define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP          
711 #define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0         
712 #define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17         
713 #define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL           
714 #define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT           
715 #define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK           
716 #define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK        
717 #define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18         
718 #define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA           
719 #define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT           
720 #define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK           
721 #define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI        
722 #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19         
723 #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL           
724 #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT           
725 #define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B      
726 #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO        
727 #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20         
728 #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA           
729 #define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT           
730 #define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0         
731 #define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21         
732 #define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX      
733 #define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX      
734 #define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK       
735 #define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22        
736 #define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX      
737 #define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX      
738 #define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI       
739 #define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23        
740 #define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX      
741 #define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX      
742 #define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO       
743 #define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3     
744 #define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24        
745 #define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX      
746 #define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX      
747 #define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0        
748 #define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2     
749 #define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25        
750 #define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX      
751 #define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX      
752 #define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS     
753 #define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS     
754 #define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B    
755 #define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2     
756 #define MX8MP_IOMUXC_UART3_RXD__CAN2_TX           
757 #define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26        
758 #define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX      
759 #define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX      
760 #define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS     
761 #define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS     
762 #define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT    
763 #define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK          
764 #define MX8MP_IOMUXC_UART3_TXD__CAN2_RX           
765 #define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27        
766 #define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX      
767 #define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX      
768 #define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS     
769 #define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS     
770 #define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B     
771 #define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1     
772 #define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL          
773 #define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28        
774 #define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX      
775 #define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX      
776 #define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS     
777 #define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS     
778 #define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1     
779 #define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA          
780 #define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29        
781 #define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDM    
782 #define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL       
783 #define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX        
784 #define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26     
785 #define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDM    
786 #define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA       
787 #define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX        
788 #define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27     
789 #define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CE    
790 #define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL           
791 #define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX            
792 #define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28         
793 #define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HP    
794 #define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_H    
795 #define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA           
796 #define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX            
797 #define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29         
798                                                   
799 #endif /* __DTS_IMX8MP_PINFUNC_H */               
800                                                   

~ [ source navigation ] ~ [ diff markup ] ~ [ identifier search ] ~

kernel.org | git.kernel.org | LWN.net | Project Home | SVN repository | Mail admin

Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.

sflogo.php