1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 2 /* 3 * Copyright 2019 NXP 3 * Copyright 2019 NXP 4 */ 4 */ 5 5 6 #ifndef __DTS_IMX8MP_PINFUNC_H 6 #ifndef __DTS_IMX8MP_PINFUNC_H 7 #define __DTS_IMX8MP_PINFUNC_H 7 #define __DTS_IMX8MP_PINFUNC_H 8 8 9 /* 9 /* 10 * The pin function ID is a tuple of 10 * The pin function ID is a tuple of 11 * <mux_reg conf_reg input_reg mux_mode input_ 11 * <mux_reg conf_reg input_reg mux_mode input_val> 12 */ 12 */ 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 13 #define MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x014 0x274 0x000 0x0 0x0 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_ 14 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_ENET_PHY_REF_CLK_ROOT 0x014 0x274 0x000 0x1 0x0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 15 #define MX8MP_IOMUXC_GPIO1_IO00__ISP_FL_TRIG_0 0x014 0x274 0x5D4 0x3 0x0 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 16 #define MX8MP_IOMUXC_GPIO1_IO00__CCM_EXT_CLK1 0x014 0x274 0x000 0x6 0x0 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 17 #define MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x018 0x278 0x000 0x0 0x0 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 18 #define MX8MP_IOMUXC_GPIO1_IO01__PWM1_OUT 0x018 0x278 0x000 0x1 0x0 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_T 19 #define MX8MP_IOMUXC_GPIO1_IO01__ISP_SHUTTER_TRIG_0 0x018 0x278 0x5DC 0x3 0x0 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 20 #define MX8MP_IOMUXC_GPIO1_IO01__CCM_EXT_CLK2 0x018 0x278 0x000 0x6 0x0 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 21 #define MX8MP_IOMUXC_GPIO1_IO02__GPIO1_IO02 0x01C 0x27C 0x000 0x0 0x0 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 22 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x01C 0x27C 0x000 0x1 0x0 23 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRI 23 #define MX8MP_IOMUXC_GPIO1_IO02__ISP_FLASH_TRIG_0 0x01C 0x27C 0x000 0x3 0x0 24 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_AN 24 #define MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_ANY 0x01C 0x27C 0x000 0x5 0x0 25 #define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 25 #define MX8MP_IOMUXC_GPIO1_IO02__SJC_DE_B 0x01C 0x27C 0x000 0x7 0x0 26 #define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 26 #define MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x020 0x280 0x000 0x0 0x0 27 #define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELEC 27 #define MX8MP_IOMUXC_GPIO1_IO03__USDHC1_VSELECT 0x020 0x280 0x000 0x1 0x0 28 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_ 28 #define MX8MP_IOMUXC_GPIO1_IO03__ISP_PRELIGHT_TRIG_0 0x020 0x280 0x000 0x3 0x0 29 #define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVE 29 #define MX8MP_IOMUXC_GPIO1_IO03__SDMA1_EXT_EVENT00 0x020 0x280 0x000 0x5 0x0 30 #define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 30 #define MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x024 0x284 0x000 0x0 0x0 31 #define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELEC 31 #define MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x024 0x284 0x000 0x1 0x0 32 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_O 32 #define MX8MP_IOMUXC_GPIO1_IO04__ISP_SHUTTER_OPEN_0 0x024 0x284 0x000 0x3 0x0 33 #define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVE 33 #define MX8MP_IOMUXC_GPIO1_IO04__SDMA1_EXT_EVENT01 0x024 0x284 0x000 0x5 0x0 34 #define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 34 #define MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x028 0x288 0x000 0x0 0x0 35 #define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 35 #define MX8MP_IOMUXC_GPIO1_IO05__M7_NMI 0x028 0x288 0x000 0x1 0x0 36 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 36 #define MX8MP_IOMUXC_GPIO1_IO05__ISP_FL_TRIG_1 0x028 0x288 0x5D8 0x3 0x0 37 #define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READ 37 #define MX8MP_IOMUXC_GPIO1_IO05__CCM_PMIC_READY 0x028 0x288 0x554 0x5 0x0 38 #define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 38 #define MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x02C 0x28C 0x000 0x0 0x0 39 #define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 39 #define MX8MP_IOMUXC_GPIO1_IO06__ENET_QOS_MDC 0x02C 0x28C 0x000 0x1 0x0 40 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_T 40 #define MX8MP_IOMUXC_GPIO1_IO06__ISP_SHUTTER_TRIG_1 0x02C 0x28C 0x5E0 0x3 0x0 41 #define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 41 #define MX8MP_IOMUXC_GPIO1_IO06__USDHC1_CD_B 0x02C 0x28C 0x000 0x5 0x0 42 #define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 42 #define MX8MP_IOMUXC_GPIO1_IO06__CCM_EXT_CLK3 0x02C 0x28C 0x000 0x6 0x0 43 #define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 43 #define MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x030 0x290 0x000 0x0 0x0 44 #define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 44 #define MX8MP_IOMUXC_GPIO1_IO07__ENET_QOS_MDIO 0x030 0x290 0x590 0x1 0x0 45 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRI 45 #define MX8MP_IOMUXC_GPIO1_IO07__ISP_FLASH_TRIG_1 0x030 0x290 0x000 0x3 0x0 46 #define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 46 #define MX8MP_IOMUXC_GPIO1_IO07__USDHC1_WP 0x030 0x290 0x000 0x5 0x0 47 #define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 47 #define MX8MP_IOMUXC_GPIO1_IO07__CCM_EXT_CLK4 0x030 0x290 0x000 0x6 0x0 48 #define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 48 #define MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x034 0x294 0x000 0x0 0x0 49 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588 49 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_IN 0x034 0x294 0x000 0x1 0x0 50 #define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 50 #define MX8MP_IOMUXC_GPIO1_IO08__PWM1_OUT 0x034 0x294 0x000 0x2 0x0 51 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_ 51 #define MX8MP_IOMUXC_GPIO1_IO08__ISP_PRELIGHT_TRIG_1 0x034 0x294 0x000 0x3 0x0 52 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588 52 #define MX8MP_IOMUXC_GPIO1_IO08__ENET_QOS_1588_EVENT0_AUX_IN 0x034 0x294 0x000 0x4 0x0 53 #define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_ 53 #define MX8MP_IOMUXC_GPIO1_IO08__USDHC2_RESET_B 0x034 0x294 0x000 0x5 0x0 54 #define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 54 #define MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x038 0x298 0x000 0x0 0x0 55 #define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588 55 #define MX8MP_IOMUXC_GPIO1_IO09__ENET_QOS_1588_EVENT0_OUT 0x038 0x298 0x000 0x1 0x0 56 #define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 56 #define MX8MP_IOMUXC_GPIO1_IO09__PWM2_OUT 0x038 0x298 0x000 0x2 0x0 57 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_O 57 #define MX8MP_IOMUXC_GPIO1_IO09__ISP_SHUTTER_OPEN_1 0x038 0x298 0x000 0x3 0x0 58 #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_ 58 #define MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x038 0x298 0x000 0x4 0x0 59 #define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVE 59 #define MX8MP_IOMUXC_GPIO1_IO09__SDMA2_EXT_EVENT00 0x038 0x298 0x000 0x5 0x0 60 #define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 60 #define MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x03C 0x29C 0x000 0x0 0x0 61 #define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 61 #define MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x03C 0x29C 0x000 0x1 0x0 62 #define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 62 #define MX8MP_IOMUXC_GPIO1_IO10__PWM3_OUT 0x03C 0x29C 0x000 0x2 0x0 63 #define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 63 #define MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x040 0x2A0 0x000 0x0 0x0 64 #define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 64 #define MX8MP_IOMUXC_GPIO1_IO11__USB2_OTG_ID 0x040 0x2A0 0x000 0x1 0x0 65 #define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 65 #define MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x040 0x2A0 0x000 0x2 0x0 66 #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELEC 66 #define MX8MP_IOMUXC_GPIO1_IO11__USDHC3_VSELECT 0x040 0x2A0 0x000 0x4 0x0 67 #define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READ 67 #define MX8MP_IOMUXC_GPIO1_IO11__CCM_PMIC_READY 0x040 0x2A0 0x554 0x5 0x1 68 #define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 68 #define MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x044 0x2A4 0x000 0x0 0x0 69 #define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 69 #define MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x044 0x2A4 0x000 0x1 0x0 70 #define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVE 70 #define MX8MP_IOMUXC_GPIO1_IO12__SDMA2_EXT_EVENT01 0x044 0x2A4 0x000 0x5 0x0 71 #define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 71 #define MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x048 0x2A8 0x000 0x0 0x0 72 #define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 72 #define MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x048 0x2A8 0x000 0x1 0x0 73 #define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 73 #define MX8MP_IOMUXC_GPIO1_IO13__PWM2_OUT 0x048 0x2A8 0x000 0x5 0x0 74 #define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 74 #define MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x04C 0x2AC 0x000 0x0 0x0 75 #define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 75 #define MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x04C 0x2AC 0x000 0x1 0x0 76 #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 76 #define MX8MP_IOMUXC_GPIO1_IO14__USDHC3_CD_B 0x04C 0x2AC 0x608 0x4 0x0 77 #define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 77 #define MX8MP_IOMUXC_GPIO1_IO14__PWM3_OUT 0x04C 0x2AC 0x000 0x5 0x0 78 #define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 78 #define MX8MP_IOMUXC_GPIO1_IO14__CCM_CLKO1 0x04C 0x2AC 0x000 0x6 0x0 79 #define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 79 #define MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x050 0x2B0 0x000 0x0 0x0 80 #define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 80 #define MX8MP_IOMUXC_GPIO1_IO15__USB2_OTG_OC 0x050 0x2B0 0x000 0x1 0x0 81 #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 81 #define MX8MP_IOMUXC_GPIO1_IO15__USDHC3_WP 0x050 0x2B0 0x634 0x4 0x0 82 #define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 82 #define MX8MP_IOMUXC_GPIO1_IO15__PWM4_OUT 0x050 0x2B0 0x000 0x5 0x0 83 #define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 83 #define MX8MP_IOMUXC_GPIO1_IO15__CCM_CLKO2 0x050 0x2B0 0x000 0x6 0x0 84 #define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 84 #define MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x054 0x2B4 0x000 0x0 0x0 85 #define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_T 85 #define MX8MP_IOMUXC_ENET_MDC__AUDIOMIX_SAI6_TX_DATA00 0x054 0x2B4 0x000 0x2 0x0 86 #define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 86 #define MX8MP_IOMUXC_ENET_MDC__GPIO1_IO16 0x054 0x2B4 0x000 0x5 0x0 87 #define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 87 #define MX8MP_IOMUXC_ENET_MDC__USDHC3_STROBE 0x054 0x2B4 0x630 0x6 0x0 88 #define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 88 #define MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x058 0x2B8 0x590 0x0 0x1 89 #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_ 89 #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_SAI6_TX_SYNC 0x058 0x2B8 0x528 0x2 0x0 90 #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_B 90 #define MX8MP_IOMUXC_ENET_MDIO__AUDIOMIX_PDM_BIT_STREAM03 0x058 0x2B8 0x4CC 0x3 0x0 91 #define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 91 #define MX8MP_IOMUXC_ENET_MDIO__GPIO1_IO17 0x058 0x2B8 0x000 0x5 0x0 92 #define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 92 #define MX8MP_IOMUXC_ENET_MDIO__USDHC3_DATA5 0x058 0x2B8 0x624 0x6 0x0 93 #define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_ 93 #define MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x05C 0x2BC 0x000 0x0 0x0 94 #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_T 94 #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_SAI6_TX_BCLK 0x05C 0x2BC 0x524 0x2 0x0 95 #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BI 95 #define MX8MP_IOMUXC_ENET_TD3__AUDIOMIX_PDM_BIT_STREAM02 0x05C 0x2BC 0x4C8 0x3 0x0 96 #define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 96 #define MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x05C 0x2BC 0x000 0x5 0x0 97 #define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 97 #define MX8MP_IOMUXC_ENET_TD3__USDHC3_DATA6 0x05C 0x2BC 0x628 0x6 0x0 98 #define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_ 98 #define MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x060 0x2C0 0x000 0x0 0x0 99 #define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CL 99 #define MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x060 0x2C0 0x000 0x1 0x0 100 #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_R 100 #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_SAI6_RX_DATA00 0x060 0x2C0 0x51C 0x2 0x0 101 #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BI 101 #define MX8MP_IOMUXC_ENET_TD2__AUDIOMIX_PDM_BIT_STREAM01 0x060 0x2C0 0x4C4 0x3 0x0 102 #define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 102 #define MX8MP_IOMUXC_ENET_TD2__GPIO1_IO19 0x060 0x2C0 0x000 0x5 0x0 103 #define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 103 #define MX8MP_IOMUXC_ENET_TD2__USDHC3_DATA7 0x060 0x2C0 0x62C 0x6 0x0 104 #define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_ 104 #define MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x064 0x2C4 0x000 0x0 0x0 105 #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_R 105 #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_SAI6_RX_SYNC 0x064 0x2C4 0x520 0x2 0x0 106 #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BI 106 #define MX8MP_IOMUXC_ENET_TD1__AUDIOMIX_PDM_BIT_STREAM00 0x064 0x2C4 0x4C0 0x3 0x0 107 #define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 107 #define MX8MP_IOMUXC_ENET_TD1__GPIO1_IO20 0x064 0x2C4 0x000 0x5 0x0 108 #define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 108 #define MX8MP_IOMUXC_ENET_TD1__USDHC3_CD_B 0x064 0x2C4 0x608 0x6 0x1 109 #define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_ 109 #define MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x068 0x2C8 0x000 0x0 0x0 110 #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_R 110 #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_SAI6_RX_BCLK 0x068 0x2C8 0x518 0x2 0x0 111 #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CL 111 #define MX8MP_IOMUXC_ENET_TD0__AUDIOMIX_PDM_CLK 0x068 0x2C8 0x000 0x3 0x0 112 #define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 112 #define MX8MP_IOMUXC_ENET_TD0__GPIO1_IO21 0x068 0x2C8 0x000 0x5 0x0 113 #define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 113 #define MX8MP_IOMUXC_ENET_TD0__USDHC3_WP 0x068 0x2C8 0x634 0x6 0x1 114 #define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGM 114 #define MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x06C 0x2CC 0x000 0x0 0x0 115 #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI 115 #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SAI6_MCLK 0x06C 0x2CC 0x514 0x2 0x0 116 #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPD 116 #define MX8MP_IOMUXC_ENET_TX_CTL__AUDIOMIX_SPDIF1_OUT 0x06C 0x2CC 0x000 0x3 0x0 117 #define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 117 #define MX8MP_IOMUXC_ENET_TX_CTL__GPIO1_IO22 0x06C 0x2CC 0x000 0x5 0x0 118 #define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 118 #define MX8MP_IOMUXC_ENET_TX_CTL__USDHC3_DATA0 0x06C 0x2CC 0x610 0x6 0x0 119 #define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CL 119 #define MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x070 0x2D0 0x000 0x0 0x0 120 #define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 120 #define MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x070 0x2D0 0x000 0x1 0x0 121 #define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_T 121 #define MX8MP_IOMUXC_ENET_TXC__AUDIOMIX_SAI7_TX_DATA00 0x070 0x2D0 0x000 0x2 0x0 122 #define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 122 #define MX8MP_IOMUXC_ENET_TXC__GPIO1_IO23 0x070 0x2D0 0x000 0x5 0x0 123 #define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 123 #define MX8MP_IOMUXC_ENET_TXC__USDHC3_DATA1 0x070 0x2D0 0x614 0x6 0x0 124 #define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGM 124 #define MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x074 0x2D4 0x000 0x0 0x0 125 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI 125 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_SAI7_TX_SYNC 0x074 0x2D4 0x540 0x2 0x0 126 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM 126 #define MX8MP_IOMUXC_ENET_RX_CTL__AUDIOMIX_PDM_BIT_STREAM03 0x074 0x2D4 0x4CC 0x3 0x1 127 #define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 127 #define MX8MP_IOMUXC_ENET_RX_CTL__GPIO1_IO24 0x074 0x2D4 0x000 0x5 0x0 128 #define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 128 #define MX8MP_IOMUXC_ENET_RX_CTL__USDHC3_DATA2 0x074 0x2D4 0x618 0x6 0x0 129 #define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CL 129 #define MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x078 0x2D8 0x000 0x0 0x0 130 #define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 130 #define MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x078 0x2D8 0x000 0x1 0x0 131 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_T 131 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_SAI7_TX_BCLK 0x078 0x2D8 0x53C 0x2 0x0 132 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BI 132 #define MX8MP_IOMUXC_ENET_RXC__AUDIOMIX_PDM_BIT_STREAM02 0x078 0x2D8 0x4C8 0x3 0x1 133 #define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 133 #define MX8MP_IOMUXC_ENET_RXC__GPIO1_IO25 0x078 0x2D8 0x000 0x5 0x0 134 #define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 134 #define MX8MP_IOMUXC_ENET_RXC__USDHC3_DATA3 0x078 0x2D8 0x61C 0x6 0x0 135 #define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_ 135 #define MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x07C 0x2DC 0x000 0x0 0x0 136 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_R 136 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_SAI7_RX_DATA00 0x07C 0x2DC 0x534 0x2 0x0 137 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BI 137 #define MX8MP_IOMUXC_ENET_RD0__AUDIOMIX_PDM_BIT_STREAM01 0x07C 0x2DC 0x4C4 0x3 0x1 138 #define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 138 #define MX8MP_IOMUXC_ENET_RD0__GPIO1_IO26 0x07C 0x2DC 0x000 0x5 0x0 139 #define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 139 #define MX8MP_IOMUXC_ENET_RD0__USDHC3_DATA4 0x07C 0x2DC 0x620 0x6 0x0 140 #define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_ 140 #define MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x080 0x2E0 0x000 0x0 0x0 141 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_R 141 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_SAI7_RX_SYNC 0x080 0x2E0 0x538 0x2 0x0 142 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BI 142 #define MX8MP_IOMUXC_ENET_RD1__AUDIOMIX_PDM_BIT_STREAM00 0x080 0x2E0 0x4C0 0x3 0x1 143 #define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 143 #define MX8MP_IOMUXC_ENET_RD1__GPIO1_IO27 0x080 0x2E0 0x000 0x5 0x0 144 #define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 144 #define MX8MP_IOMUXC_ENET_RD1__USDHC3_RESET_B 0x080 0x2E0 0x000 0x6 0x0 145 #define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_ 145 #define MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x084 0x2E4 0x000 0x0 0x0 146 #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_R 146 #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_SAI7_RX_BCLK 0x084 0x2E4 0x530 0x2 0x0 147 #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CL 147 #define MX8MP_IOMUXC_ENET_RD2__AUDIOMIX_PDM_CLK 0x084 0x2E4 0x000 0x3 0x0 148 #define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 148 #define MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x084 0x2E4 0x000 0x5 0x0 149 #define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 149 #define MX8MP_IOMUXC_ENET_RD2__USDHC3_CLK 0x084 0x2E4 0x604 0x6 0x0 150 #define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_ 150 #define MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x088 0x2E8 0x000 0x0 0x0 151 #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_M 151 #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SAI7_MCLK 0x088 0x2E8 0x52C 0x2 0x0 152 #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1 152 #define MX8MP_IOMUXC_ENET_RD3__AUDIOMIX_SPDIF1_IN 0x088 0x2E8 0x544 0x3 0x0 153 #define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 153 #define MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x088 0x2E8 0x000 0x5 0x0 154 #define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 154 #define MX8MP_IOMUXC_ENET_RD3__USDHC3_CMD 0x088 0x2E8 0x60C 0x6 0x0 155 #define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 155 #define MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x08C 0x2EC 0x000 0x0 0x0 156 #define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 156 #define MX8MP_IOMUXC_SD1_CLK__ENET1_MDC 0x08C 0x2EC 0x000 0x1 0x0 157 #define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 157 #define MX8MP_IOMUXC_SD1_CLK__I2C5_SCL 0x08C 0x2EC 0x5C4 0x3 0x0 158 #define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 158 #define MX8MP_IOMUXC_SD1_CLK__UART1_DCE_TX 0x08C 0x2EC 0x000 0x4 0x0 159 #define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 159 #define MX8MP_IOMUXC_SD1_CLK__UART1_DTE_RX 0x08C 0x2EC 0x5E8 0x4 0x0 160 #define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 160 #define MX8MP_IOMUXC_SD1_CLK__GPIO2_IO00 0x08C 0x2EC 0x000 0x5 0x0 161 #define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 161 #define MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x090 0x2F0 0x000 0x0 0x0 162 #define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 162 #define MX8MP_IOMUXC_SD1_CMD__ENET1_MDIO 0x090 0x2F0 0x57C 0x1 0x0 163 #define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 163 #define MX8MP_IOMUXC_SD1_CMD__I2C5_SDA 0x090 0x2F0 0x5C8 0x3 0x0 164 #define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 164 #define MX8MP_IOMUXC_SD1_CMD__UART1_DCE_RX 0x090 0x2F0 0x5E8 0x4 0x1 165 #define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 165 #define MX8MP_IOMUXC_SD1_CMD__UART1_DTE_TX 0x090 0x2F0 0x000 0x4 0x0 166 #define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 166 #define MX8MP_IOMUXC_SD1_CMD__GPIO2_IO01 0x090 0x2F0 0x000 0x5 0x0 167 #define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 167 #define MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x094 0x2F4 0x000 0x0 0x0 168 #define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD 168 #define MX8MP_IOMUXC_SD1_DATA0__ENET1_RGMII_TD1 0x094 0x2F4 0x000 0x1 0x0 169 #define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 169 #define MX8MP_IOMUXC_SD1_DATA0__I2C6_SCL 0x094 0x2F4 0x5CC 0x3 0x0 170 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 170 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DCE_RTS 0x094 0x2F4 0x5E4 0x4 0x0 171 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 171 #define MX8MP_IOMUXC_SD1_DATA0__UART1_DTE_CTS 0x094 0x2F4 0x000 0x4 0x0 172 #define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 172 #define MX8MP_IOMUXC_SD1_DATA0__GPIO2_IO02 0x094 0x2F4 0x000 0x5 0x0 173 #define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 173 #define MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x098 0x2F8 0x000 0x0 0x0 174 #define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD 174 #define MX8MP_IOMUXC_SD1_DATA1__ENET1_RGMII_TD0 0x098 0x2F8 0x000 0x1 0x0 175 #define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 175 #define MX8MP_IOMUXC_SD1_DATA1__I2C6_SDA 0x098 0x2F8 0x5D0 0x3 0x0 176 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 176 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DCE_CTS 0x098 0x2F8 0x000 0x4 0x0 177 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 177 #define MX8MP_IOMUXC_SD1_DATA1__UART1_DTE_RTS 0x098 0x2F8 0x5E4 0x4 0x1 178 #define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 178 #define MX8MP_IOMUXC_SD1_DATA1__GPIO2_IO03 0x098 0x2F8 0x000 0x5 0x0 179 #define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 179 #define MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x09C 0x2FC 0x000 0x0 0x0 180 #define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD 180 #define MX8MP_IOMUXC_SD1_DATA2__ENET1_RGMII_RD0 0x09C 0x2FC 0x580 0x1 0x0 181 #define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 181 #define MX8MP_IOMUXC_SD1_DATA2__I2C4_SCL 0x09C 0x2FC 0x5BC 0x3 0x0 182 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 182 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DCE_TX 0x09C 0x2FC 0x000 0x4 0x0 183 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 183 #define MX8MP_IOMUXC_SD1_DATA2__UART2_DTE_RX 0x09C 0x2FC 0x5F0 0x4 0x0 184 #define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 184 #define MX8MP_IOMUXC_SD1_DATA2__GPIO2_IO04 0x09C 0x2FC 0x000 0x5 0x0 185 #define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 185 #define MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x0A0 0x300 0x000 0x0 0x0 186 #define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD 186 #define MX8MP_IOMUXC_SD1_DATA3__ENET1_RGMII_RD1 0x0A0 0x300 0x584 0x1 0x0 187 #define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 187 #define MX8MP_IOMUXC_SD1_DATA3__I2C4_SDA 0x0A0 0x300 0x5C0 0x3 0x0 188 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 188 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DCE_RX 0x0A0 0x300 0x5F0 0x4 0x1 189 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 189 #define MX8MP_IOMUXC_SD1_DATA3__UART2_DTE_TX 0x0A0 0x300 0x000 0x4 0x0 190 #define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 190 #define MX8MP_IOMUXC_SD1_DATA3__GPIO2_IO05 0x0A0 0x300 0x000 0x5 0x0 191 #define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 191 #define MX8MP_IOMUXC_SD1_DATA4__USDHC1_DATA4 0x0A4 0x304 0x000 0x0 0x0 192 #define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX 192 #define MX8MP_IOMUXC_SD1_DATA4__ENET1_RGMII_TX_CTL 0x0A4 0x304 0x000 0x1 0x0 193 #define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 193 #define MX8MP_IOMUXC_SD1_DATA4__I2C1_SCL 0x0A4 0x304 0x5A4 0x3 0x0 194 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 194 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x0A4 0x304 0x5EC 0x4 0x0 195 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 195 #define MX8MP_IOMUXC_SD1_DATA4__UART2_DTE_CTS 0x0A4 0x304 0x000 0x4 0x0 196 #define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 196 #define MX8MP_IOMUXC_SD1_DATA4__GPIO2_IO06 0x0A4 0x304 0x000 0x5 0x0 197 #define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 197 #define MX8MP_IOMUXC_SD1_DATA5__USDHC1_DATA5 0x0A8 0x308 0x000 0x0 0x0 198 #define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 198 #define MX8MP_IOMUXC_SD1_DATA5__ENET1_TX_ER 0x0A8 0x308 0x000 0x1 0x0 199 #define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 199 #define MX8MP_IOMUXC_SD1_DATA5__I2C1_SDA 0x0A8 0x308 0x5A8 0x3 0x0 200 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 200 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x0A8 0x308 0x000 0x4 0x0 201 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 201 #define MX8MP_IOMUXC_SD1_DATA5__UART2_DTE_RTS 0x0A8 0x308 0x5EC 0x4 0x1 202 #define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 202 #define MX8MP_IOMUXC_SD1_DATA5__GPIO2_IO07 0x0A8 0x308 0x000 0x5 0x0 203 #define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 203 #define MX8MP_IOMUXC_SD1_DATA6__USDHC1_DATA6 0x0AC 0x30C 0x000 0x0 0x0 204 #define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX 204 #define MX8MP_IOMUXC_SD1_DATA6__ENET1_RGMII_RX_CTL 0x0AC 0x30C 0x588 0x1 0x0 205 #define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 205 #define MX8MP_IOMUXC_SD1_DATA6__I2C2_SCL 0x0AC 0x30C 0x5AC 0x3 0x0 206 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 206 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DCE_TX 0x0AC 0x30C 0x000 0x4 0x0 207 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 207 #define MX8MP_IOMUXC_SD1_DATA6__UART3_DTE_RX 0x0AC 0x30C 0x5F8 0x4 0x0 208 #define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 208 #define MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x0AC 0x30C 0x000 0x5 0x0 209 #define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 209 #define MX8MP_IOMUXC_SD1_DATA7__USDHC1_DATA7 0x0B0 0x310 0x000 0x0 0x0 210 #define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 210 #define MX8MP_IOMUXC_SD1_DATA7__ENET1_RX_ER 0x0B0 0x310 0x58C 0x1 0x0 211 #define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 211 #define MX8MP_IOMUXC_SD1_DATA7__I2C2_SDA 0x0B0 0x310 0x5B0 0x3 0x0 212 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 212 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DCE_RX 0x0B0 0x310 0x5F8 0x4 0x1 213 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 213 #define MX8MP_IOMUXC_SD1_DATA7__UART3_DTE_TX 0x0B0 0x310 0x000 0x4 0x0 214 #define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 214 #define MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x0B0 0x310 0x000 0x5 0x0 215 #define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET 215 #define MX8MP_IOMUXC_SD1_RESET_B__USDHC1_RESET_B 0x0B4 0x314 0x000 0x0 0x0 216 #define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 216 #define MX8MP_IOMUXC_SD1_RESET_B__ENET1_TX_CLK 0x0B4 0x314 0x578 0x1 0x0 217 #define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 217 #define MX8MP_IOMUXC_SD1_RESET_B__I2C3_SCL 0x0B4 0x314 0x5B4 0x3 0x0 218 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RT 218 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DCE_RTS 0x0B4 0x314 0x5F4 0x4 0x0 219 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CT 219 #define MX8MP_IOMUXC_SD1_RESET_B__UART3_DTE_CTS 0x0B4 0x314 0x000 0x4 0x0 220 #define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 220 #define MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x0B4 0x314 0x000 0x5 0x0 221 #define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 221 #define MX8MP_IOMUXC_SD1_STROBE__USDHC1_STROBE 0x0B8 0x318 0x000 0x0 0x0 222 #define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 222 #define MX8MP_IOMUXC_SD1_STROBE__I2C3_SDA 0x0B8 0x318 0x5B8 0x3 0x0 223 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 223 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DCE_CTS 0x0B8 0x318 0x000 0x4 0x0 224 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 224 #define MX8MP_IOMUXC_SD1_STROBE__UART3_DTE_RTS 0x0B8 0x318 0x5F4 0x4 0x1 225 #define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 225 #define MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x0B8 0x318 0x000 0x5 0x0 226 #define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 226 #define MX8MP_IOMUXC_SD2_CD_B__USDHC2_CD_B 0x0BC 0x31C 0x000 0x0 0x0 227 #define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 227 #define MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0BC 0x31C 0x000 0x5 0x0 228 #define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 228 #define MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x0C0 0x320 0x000 0x0 0x0 229 #define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 229 #define MX8MP_IOMUXC_SD2_CLK__ECSPI2_SCLK 0x0C0 0x320 0x568 0x2 0x0 230 #define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 230 #define MX8MP_IOMUXC_SD2_CLK__UART4_DCE_RX 0x0C0 0x320 0x600 0x3 0x0 231 #define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 231 #define MX8MP_IOMUXC_SD2_CLK__UART4_DTE_TX 0x0C0 0x320 0x000 0x3 0x0 232 #define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 232 #define MX8MP_IOMUXC_SD2_CLK__GPIO2_IO13 0x0C0 0x320 0x000 0x5 0x0 233 #define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 233 #define MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x0C4 0x324 0x000 0x0 0x0 234 #define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 234 #define MX8MP_IOMUXC_SD2_CMD__ECSPI2_MOSI 0x0C4 0x324 0x570 0x2 0x0 235 #define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 235 #define MX8MP_IOMUXC_SD2_CMD__UART4_DCE_TX 0x0C4 0x324 0x000 0x3 0x0 236 #define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 236 #define MX8MP_IOMUXC_SD2_CMD__UART4_DTE_RX 0x0C4 0x324 0x600 0x3 0x1 237 #define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 237 #define MX8MP_IOMUXC_SD2_CMD__AUDIOMIX_PDM_CLK 0x0C4 0x324 0x000 0x4 0x0 238 #define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 238 #define MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x0C4 0x324 0x000 0x5 0x0 239 #define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 239 #define MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x0C8 0x328 0x000 0x0 0x0 240 #define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 240 #define MX8MP_IOMUXC_SD2_DATA0__I2C4_SDA 0x0C8 0x328 0x5C0 0x2 0x1 241 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 241 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DCE_RX 0x0C8 0x328 0x5F0 0x3 0x2 242 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 242 #define MX8MP_IOMUXC_SD2_DATA0__UART2_DTE_TX 0x0C8 0x328 0x000 0x3 0x0 243 #define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_B 243 #define MX8MP_IOMUXC_SD2_DATA0__AUDIOMIX_PDM_BIT_STREAM00 0x0C8 0x328 0x4C0 0x4 0x2 244 #define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 244 #define MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x0C8 0x328 0x000 0x5 0x0 245 #define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 245 #define MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x0CC 0x32C 0x000 0x0 0x0 246 #define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 246 #define MX8MP_IOMUXC_SD2_DATA1__I2C4_SCL 0x0CC 0x32C 0x5BC 0x2 0x1 247 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 247 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DCE_TX 0x0CC 0x32C 0x000 0x3 0x0 248 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 248 #define MX8MP_IOMUXC_SD2_DATA1__UART2_DTE_RX 0x0CC 0x32C 0x5F0 0x3 0x3 249 #define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_B 249 #define MX8MP_IOMUXC_SD2_DATA1__AUDIOMIX_PDM_BIT_STREAM01 0x0CC 0x32C 0x4C4 0x4 0x2 250 #define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 250 #define MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x0CC 0x32C 0x000 0x5 0x0 251 #define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 251 #define MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x0D0 0x330 0x000 0x0 0x0 252 #define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 252 #define MX8MP_IOMUXC_SD2_DATA2__ECSPI2_SS0 0x0D0 0x330 0x574 0x2 0x0 253 #define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF 253 #define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_SPDIF1_OUT 0x0D0 0x330 0x000 0x3 0x0 254 #define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_B 254 #define MX8MP_IOMUXC_SD2_DATA2__AUDIOMIX_PDM_BIT_STREAM02 0x0D0 0x330 0x4C8 0x4 0x2 255 #define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 255 #define MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x0D0 0x330 0x000 0x5 0x0 256 #define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 256 #define MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x0D4 0x334 0x000 0x0 0x0 257 #define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 257 #define MX8MP_IOMUXC_SD2_DATA3__ECSPI2_MISO 0x0D4 0x334 0x56C 0x2 0x0 258 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF 258 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_SPDIF1_IN 0x0D4 0x334 0x544 0x3 0x1 259 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_B 259 #define MX8MP_IOMUXC_SD2_DATA3__AUDIOMIX_PDM_BIT_STREAM03 0x0D4 0x334 0x4CC 0x4 0x2 260 #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 260 #define MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x0D4 0x334 0x000 0x5 0x0 261 #define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESE 261 #define MX8MP_IOMUXC_SD2_DATA3__SRC_EARLY_RESET 0x0D4 0x334 0x000 0x6 0x0 262 #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET 262 #define MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x0D8 0x338 0x000 0x0 0x0 263 #define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 263 #define MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x0D8 0x338 0x000 0x5 0x0 264 #define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_R 264 #define MX8MP_IOMUXC_SD2_RESET_B__SRC_SYSTEM_RESET 0x0D8 0x338 0x000 0x6 0x0 265 #define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 265 #define MX8MP_IOMUXC_SD2_WP__USDHC2_WP 0x0DC 0x33C 0x000 0x0 0x0 266 #define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 266 #define MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x0DC 0x33C 0x000 0x5 0x0 267 #define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 267 #define MX8MP_IOMUXC_SD2_WP__CORESIGHT_EVENTI 0x0DC 0x33C 0x000 0x6 0x0 268 #define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 268 #define MX8MP_IOMUXC_NAND_ALE__NAND_ALE 0x0E0 0x340 0x000 0x0 0x0 269 #define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 269 #define MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x0E0 0x340 0x000 0x1 0x0 270 #define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_T 270 #define MX8MP_IOMUXC_NAND_ALE__AUDIOMIX_SAI3_TX_BCLK 0x0E0 0x340 0x4E8 0x2 0x0 271 #define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 271 #define MX8MP_IOMUXC_NAND_ALE__ISP_FL_TRIG_0 0x0E0 0x340 0x5D4 0x3 0x1 272 #define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 272 #define MX8MP_IOMUXC_NAND_ALE__UART3_DCE_RX 0x0E0 0x340 0x5F8 0x4 0x2 273 #define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 273 #define MX8MP_IOMUXC_NAND_ALE__UART3_DTE_TX 0x0E0 0x340 0x000 0x4 0x0 274 #define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 274 #define MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x0E0 0x340 0x000 0x5 0x0 275 #define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE 275 #define MX8MP_IOMUXC_NAND_ALE__CORESIGHT_TRACE_CLK 0x0E0 0x340 0x000 0x6 0x0 276 #define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 276 #define MX8MP_IOMUXC_NAND_CE0_B__NAND_CE0_B 0x0E4 0x344 0x000 0x0 0x0 277 #define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0 277 #define MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x0E4 0x344 0x000 0x1 0x0 278 #define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3 278 #define MX8MP_IOMUXC_NAND_CE0_B__AUDIOMIX_SAI3_TX_DATA00 0x0E4 0x344 0x000 0x2 0x0 279 #define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_T 279 #define MX8MP_IOMUXC_NAND_CE0_B__ISP_SHUTTER_TRIG_0 0x0E4 0x344 0x5DC 0x3 0x1 280 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 280 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DCE_TX 0x0E4 0x344 0x000 0x4 0x0 281 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 281 #define MX8MP_IOMUXC_NAND_CE0_B__UART3_DTE_RX 0x0E4 0x344 0x5F8 0x4 0x3 282 #define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 282 #define MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x0E4 0x344 0x000 0x5 0x0 283 #define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRA 283 #define MX8MP_IOMUXC_NAND_CE0_B__CORESIGHT_TRACE_CTL 0x0E4 0x344 0x000 0x6 0x0 284 #define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 284 #define MX8MP_IOMUXC_NAND_CE1_B__NAND_CE1_B 0x0E8 0x348 0x000 0x0 0x0 285 #define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1 285 #define MX8MP_IOMUXC_NAND_CE1_B__FLEXSPI_A_SS1_B 0x0E8 0x348 0x000 0x1 0x0 286 #define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 286 #define MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x0E8 0x348 0x630 0x2 0x1 287 #define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 287 #define MX8MP_IOMUXC_NAND_CE1_B__I2C4_SCL 0x0E8 0x348 0x5BC 0x4 0x2 288 #define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 288 #define MX8MP_IOMUXC_NAND_CE1_B__GPIO3_IO02 0x0E8 0x348 0x000 0x5 0x0 289 #define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRA 289 #define MX8MP_IOMUXC_NAND_CE1_B__CORESIGHT_TRACE00 0x0E8 0x348 0x000 0x6 0x0 290 #define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 290 #define MX8MP_IOMUXC_NAND_CE2_B__NAND_CE2_B 0x0EC 0x34C 0x000 0x0 0x0 291 #define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0 291 #define MX8MP_IOMUXC_NAND_CE2_B__FLEXSPI_B_SS0_B 0x0EC 0x34C 0x000 0x1 0x0 292 #define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 292 #define MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x0EC 0x34C 0x624 0x2 0x1 293 #define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 293 #define MX8MP_IOMUXC_NAND_CE2_B__I2C4_SDA 0x0EC 0x34C 0x5C0 0x4 0x2 294 #define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 294 #define MX8MP_IOMUXC_NAND_CE2_B__GPIO3_IO03 0x0EC 0x34C 0x000 0x5 0x0 295 #define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRA 295 #define MX8MP_IOMUXC_NAND_CE2_B__CORESIGHT_TRACE01 0x0EC 0x34C 0x000 0x6 0x0 296 #define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 296 #define MX8MP_IOMUXC_NAND_CE3_B__NAND_CE3_B 0x0F0 0x350 0x000 0x0 0x0 297 #define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1 297 #define MX8MP_IOMUXC_NAND_CE3_B__FLEXSPI_B_SS1_B 0x0F0 0x350 0x000 0x1 0x0 298 #define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 298 #define MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x0F0 0x350 0x628 0x2 0x1 299 #define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 299 #define MX8MP_IOMUXC_NAND_CE3_B__I2C3_SDA 0x0F0 0x350 0x5B8 0x4 0x1 300 #define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 300 #define MX8MP_IOMUXC_NAND_CE3_B__GPIO3_IO04 0x0F0 0x350 0x000 0x5 0x0 301 #define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRA 301 #define MX8MP_IOMUXC_NAND_CE3_B__CORESIGHT_TRACE02 0x0F0 0x350 0x000 0x6 0x0 302 #define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 302 #define MX8MP_IOMUXC_NAND_CLE__NAND_CLE 0x0F4 0x354 0x000 0x0 0x0 303 #define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 303 #define MX8MP_IOMUXC_NAND_CLE__FLEXSPI_B_SCLK 0x0F4 0x354 0x000 0x1 0x0 304 #define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 304 #define MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x0F4 0x354 0x62C 0x2 0x1 305 #define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 305 #define MX8MP_IOMUXC_NAND_CLE__UART4_DCE_RX 0x0F4 0x354 0x600 0x4 0x2 306 #define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 306 #define MX8MP_IOMUXC_NAND_CLE__UART4_DTE_TX 0x0F4 0x354 0x000 0x4 0x0 307 #define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 307 #define MX8MP_IOMUXC_NAND_CLE__GPIO3_IO05 0x0F4 0x354 0x000 0x5 0x0 308 #define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE 308 #define MX8MP_IOMUXC_NAND_CLE__CORESIGHT_TRACE03 0x0F4 0x354 0x000 0x6 0x0 309 #define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 309 #define MX8MP_IOMUXC_NAND_DATA00__NAND_DATA00 0x0F8 0x358 0x000 0x0 0x0 310 #define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DA 310 #define MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x0F8 0x358 0x000 0x1 0x0 311 #define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI 311 #define MX8MP_IOMUXC_NAND_DATA00__AUDIOMIX_SAI3_RX_DATA00 0x0F8 0x358 0x4E4 0x2 0x0 312 #define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TR 312 #define MX8MP_IOMUXC_NAND_DATA00__ISP_FLASH_TRIG_0 0x0F8 0x358 0x000 0x3 0x0 313 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 313 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DCE_RX 0x0F8 0x358 0x600 0x4 0x3 314 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 314 #define MX8MP_IOMUXC_NAND_DATA00__UART4_DTE_TX 0x0F8 0x358 0x000 0x4 0x0 315 #define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 315 #define MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x0F8 0x358 0x000 0x5 0x0 316 #define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TR 316 #define MX8MP_IOMUXC_NAND_DATA00__CORESIGHT_TRACE04 0x0F8 0x358 0x000 0x6 0x0 317 #define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 317 #define MX8MP_IOMUXC_NAND_DATA01__NAND_DATA01 0x0FC 0x35C 0x000 0x0 0x0 318 #define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DA 318 #define MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x0FC 0x35C 0x000 0x1 0x0 319 #define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI 319 #define MX8MP_IOMUXC_NAND_DATA01__AUDIOMIX_SAI3_TX_SYNC 0x0FC 0x35C 0x4EC 0x2 0x0 320 #define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT 320 #define MX8MP_IOMUXC_NAND_DATA01__ISP_PRELIGHT_TRIG_0 0x0FC 0x35C 0x000 0x3 0x0 321 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 321 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DCE_TX 0x0FC 0x35C 0x000 0x4 0x0 322 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 322 #define MX8MP_IOMUXC_NAND_DATA01__UART4_DTE_RX 0x0FC 0x35C 0x600 0x4 0x4 323 #define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 323 #define MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x0FC 0x35C 0x000 0x5 0x0 324 #define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TR 324 #define MX8MP_IOMUXC_NAND_DATA01__CORESIGHT_TRACE05 0x0FC 0x35C 0x000 0x6 0x0 325 #define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 325 #define MX8MP_IOMUXC_NAND_DATA02__NAND_DATA02 0x100 0x360 0x000 0x0 0x0 326 #define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DA 326 #define MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x100 0x360 0x000 0x1 0x0 327 #define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 327 #define MX8MP_IOMUXC_NAND_DATA02__USDHC3_CD_B 0x100 0x360 0x608 0x2 0x2 328 #define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CT 328 #define MX8MP_IOMUXC_NAND_DATA02__UART4_DCE_CTS 0x100 0x360 0x000 0x3 0x0 329 #define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RT 329 #define MX8MP_IOMUXC_NAND_DATA02__UART4_DTE_RTS 0x100 0x360 0x5FC 0x3 0x0 330 #define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 330 #define MX8MP_IOMUXC_NAND_DATA02__I2C4_SDA 0x100 0x360 0x5C0 0x4 0x3 331 #define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 331 #define MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x100 0x360 0x000 0x5 0x0 332 #define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TR 332 #define MX8MP_IOMUXC_NAND_DATA02__CORESIGHT_TRACE06 0x100 0x360 0x000 0x6 0x0 333 #define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 333 #define MX8MP_IOMUXC_NAND_DATA03__NAND_DATA03 0x104 0x364 0x000 0x0 0x0 334 #define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DA 334 #define MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x104 0x364 0x000 0x1 0x0 335 #define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 335 #define MX8MP_IOMUXC_NAND_DATA03__USDHC3_WP 0x104 0x364 0x634 0x2 0x2 336 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RT 336 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DCE_RTS 0x104 0x364 0x5FC 0x3 0x1 337 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CT 337 #define MX8MP_IOMUXC_NAND_DATA03__UART4_DTE_CTS 0x104 0x364 0x000 0x3 0x0 338 #define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_ 338 #define MX8MP_IOMUXC_NAND_DATA03__ISP_FL_TRIG_1 0x104 0x364 0x5D8 0x4 0x1 339 #define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 339 #define MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x104 0x364 0x000 0x5 0x0 340 #define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TR 340 #define MX8MP_IOMUXC_NAND_DATA03__CORESIGHT_TRACE07 0x104 0x364 0x000 0x6 0x0 341 #define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 341 #define MX8MP_IOMUXC_NAND_DATA04__NAND_DATA04 0x108 0x368 0x000 0x0 0x0 342 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DA 342 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_B_DATA00 0x108 0x368 0x000 0x1 0x0 343 #define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 343 #define MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x108 0x368 0x610 0x2 0x1 344 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DA 344 #define MX8MP_IOMUXC_NAND_DATA04__FLEXSPI_A_DATA04 0x108 0x368 0x000 0x3 0x0 345 #define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_ 345 #define MX8MP_IOMUXC_NAND_DATA04__ISP_SHUTTER_TRIG_1 0x108 0x368 0x5E0 0x4 0x1 346 #define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 346 #define MX8MP_IOMUXC_NAND_DATA04__GPIO3_IO10 0x108 0x368 0x000 0x5 0x0 347 #define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TR 347 #define MX8MP_IOMUXC_NAND_DATA04__CORESIGHT_TRACE08 0x108 0x368 0x000 0x6 0x0 348 #define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 348 #define MX8MP_IOMUXC_NAND_DATA05__NAND_DATA05 0x10C 0x36C 0x000 0x0 0x0 349 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DA 349 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_B_DATA01 0x10C 0x36C 0x000 0x1 0x0 350 #define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 350 #define MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x10C 0x36C 0x614 0x2 0x1 351 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DA 351 #define MX8MP_IOMUXC_NAND_DATA05__FLEXSPI_A_DATA05 0x10C 0x36C 0x000 0x3 0x0 352 #define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TR 352 #define MX8MP_IOMUXC_NAND_DATA05__ISP_FLASH_TRIG_1 0x10C 0x36C 0x000 0x4 0x0 353 #define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 353 #define MX8MP_IOMUXC_NAND_DATA05__GPIO3_IO11 0x10C 0x36C 0x000 0x5 0x0 354 #define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TR 354 #define MX8MP_IOMUXC_NAND_DATA05__CORESIGHT_TRACE09 0x10C 0x36C 0x000 0x6 0x0 355 #define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 355 #define MX8MP_IOMUXC_NAND_DATA06__NAND_DATA06 0x110 0x370 0x000 0x0 0x0 356 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DA 356 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_B_DATA02 0x110 0x370 0x000 0x1 0x0 357 #define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 357 #define MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x110 0x370 0x618 0x2 0x1 358 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DA 358 #define MX8MP_IOMUXC_NAND_DATA06__FLEXSPI_A_DATA06 0x110 0x370 0x000 0x3 0x0 359 #define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT 359 #define MX8MP_IOMUXC_NAND_DATA06__ISP_PRELIGHT_TRIG_1 0x110 0x370 0x000 0x4 0x0 360 #define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 360 #define MX8MP_IOMUXC_NAND_DATA06__GPIO3_IO12 0x110 0x370 0x000 0x5 0x0 361 #define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TR 361 #define MX8MP_IOMUXC_NAND_DATA06__CORESIGHT_TRACE10 0x110 0x370 0x000 0x6 0x0 362 #define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 362 #define MX8MP_IOMUXC_NAND_DATA07__NAND_DATA07 0x114 0x374 0x000 0x0 0x0 363 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DA 363 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_B_DATA03 0x114 0x374 0x000 0x1 0x0 364 #define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 364 #define MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x114 0x374 0x61C 0x2 0x1 365 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DA 365 #define MX8MP_IOMUXC_NAND_DATA07__FLEXSPI_A_DATA07 0x114 0x374 0x000 0x3 0x0 366 #define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_ 366 #define MX8MP_IOMUXC_NAND_DATA07__ISP_SHUTTER_OPEN_1 0x114 0x374 0x000 0x4 0x0 367 #define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 367 #define MX8MP_IOMUXC_NAND_DATA07__GPIO3_IO13 0x114 0x374 0x000 0x5 0x0 368 #define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TR 368 #define MX8MP_IOMUXC_NAND_DATA07__CORESIGHT_TRACE11 0x114 0x374 0x000 0x6 0x0 369 #define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 369 #define MX8MP_IOMUXC_NAND_DQS__NAND_DQS 0x118 0x378 0x000 0x0 0x0 370 #define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 370 #define MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x118 0x378 0x000 0x1 0x0 371 #define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_M 371 #define MX8MP_IOMUXC_NAND_DQS__AUDIOMIX_SAI3_MCLK 0x118 0x378 0x4E0 0x2 0x0 372 #define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPE 372 #define MX8MP_IOMUXC_NAND_DQS__ISP_SHUTTER_OPEN_0 0x118 0x378 0x000 0x3 0x0 373 #define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 373 #define MX8MP_IOMUXC_NAND_DQS__I2C3_SCL 0x118 0x378 0x5B4 0x4 0x1 374 #define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 374 #define MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x118 0x378 0x000 0x5 0x0 375 #define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE 375 #define MX8MP_IOMUXC_NAND_DQS__CORESIGHT_TRACE12 0x118 0x378 0x000 0x6 0x0 376 #define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 376 #define MX8MP_IOMUXC_NAND_RE_B__NAND_RE_B 0x11C 0x37C 0x000 0x0 0x0 377 #define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 377 #define MX8MP_IOMUXC_NAND_RE_B__FLEXSPI_B_DQS 0x11C 0x37C 0x000 0x1 0x0 378 #define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 378 #define MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x11C 0x37C 0x620 0x2 0x1 379 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 379 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DCE_TX 0x11C 0x37C 0x000 0x4 0x0 380 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 380 #define MX8MP_IOMUXC_NAND_RE_B__UART4_DTE_RX 0x11C 0x37C 0x600 0x4 0x5 381 #define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 381 #define MX8MP_IOMUXC_NAND_RE_B__GPIO3_IO15 0x11C 0x37C 0x000 0x5 0x0 382 #define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRAC 382 #define MX8MP_IOMUXC_NAND_RE_B__CORESIGHT_TRACE13 0x11C 0x37C 0x000 0x6 0x0 383 #define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_ 383 #define MX8MP_IOMUXC_NAND_READY_B__NAND_READY_B 0x120 0x380 0x000 0x0 0x0 384 #define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESE 384 #define MX8MP_IOMUXC_NAND_READY_B__USDHC3_RESET_B 0x120 0x380 0x000 0x2 0x0 385 #define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 385 #define MX8MP_IOMUXC_NAND_READY_B__I2C3_SCL 0x120 0x380 0x5B4 0x4 0x2 386 #define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 386 #define MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x120 0x380 0x000 0x5 0x0 387 #define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_T 387 #define MX8MP_IOMUXC_NAND_READY_B__CORESIGHT_TRACE14 0x120 0x380 0x000 0x6 0x0 388 #define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 388 #define MX8MP_IOMUXC_NAND_WE_B__NAND_WE_B 0x124 0x384 0x000 0x0 0x0 389 #define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 389 #define MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x124 0x384 0x604 0x2 0x1 390 #define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 390 #define MX8MP_IOMUXC_NAND_WE_B__I2C3_SDA 0x124 0x384 0x5B8 0x4 0x2 391 #define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 391 #define MX8MP_IOMUXC_NAND_WE_B__GPIO3_IO17 0x124 0x384 0x000 0x5 0x0 392 #define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRAC 392 #define MX8MP_IOMUXC_NAND_WE_B__CORESIGHT_TRACE15 0x124 0x384 0x000 0x6 0x0 393 #define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 393 #define MX8MP_IOMUXC_NAND_WP_B__NAND_WP_B 0x128 0x388 0x000 0x0 0x0 394 #define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 394 #define MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x128 0x388 0x60C 0x2 0x1 395 #define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 395 #define MX8MP_IOMUXC_NAND_WP_B__I2C4_SCL 0x128 0x388 0x5BC 0x4 0x3 396 #define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 396 #define MX8MP_IOMUXC_NAND_WP_B__GPIO3_IO18 0x128 0x388 0x000 0x5 0x0 397 #define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVEN 397 #define MX8MP_IOMUXC_NAND_WP_B__CORESIGHT_EVENTO 0x128 0x388 0x000 0x6 0x0 398 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_ 398 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x12C 0x38C 0x508 0x0 0x0 399 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_ 399 #define MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x12C 0x38C 0x000 0x1 0x0 400 #define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 400 #define MX8MP_IOMUXC_SAI5_RXFS__PWM4_OUT 0x12C 0x38C 0x000 0x2 0x0 401 #define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 401 #define MX8MP_IOMUXC_SAI5_RXFS__I2C6_SCL 0x12C 0x38C 0x5CC 0x3 0x1 402 #define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 402 #define MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x12C 0x38C 0x000 0x5 0x0 403 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_R 403 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI5_RX_BCLK 0x130 0x390 0x4F4 0x0 0x0 404 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_T 404 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_SAI1_TX_DATA01 0x130 0x390 0x000 0x1 0x0 405 #define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 405 #define MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x130 0x390 0x000 0x2 0x0 406 #define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 406 #define MX8MP_IOMUXC_SAI5_RXC__I2C6_SDA 0x130 0x390 0x5D0 0x3 0x1 407 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CL 407 #define MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0x130 0x390 0x000 0x4 0x0 408 #define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 408 #define MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x130 0x390 0x000 0x5 0x0 409 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_ 409 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI5_RX_DATA00 0x134 0x394 0x4F8 0x0 0x0 410 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_ 410 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_SAI1_TX_DATA02 0x134 0x394 0x000 0x1 0x0 411 #define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 411 #define MX8MP_IOMUXC_SAI5_RXD0__PWM2_OUT 0x134 0x394 0x000 0x2 0x0 412 #define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 412 #define MX8MP_IOMUXC_SAI5_RXD0__I2C5_SCL 0x134 0x394 0x5C4 0x3 0x1 413 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_B 413 #define MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x134 0x394 0x4C0 0x4 0x3 414 #define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 414 #define MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x134 0x394 0x000 0x5 0x0 415 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_ 415 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_RX_DATA01 0x138 0x398 0x4FC 0x0 0x0 416 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_ 416 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_DATA03 0x138 0x398 0x000 0x1 0x0 417 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_ 417 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x138 0x398 0x4D8 0x2 0x0 418 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_ 418 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0x138 0x398 0x510 0x3 0x0 419 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_B 419 #define MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x138 0x398 0x4C4 0x4 0x3 420 #define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 420 #define MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x138 0x398 0x000 0x5 0x0 421 #define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 421 #define MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x138 0x398 0x000 0x6 0x0 422 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_ 422 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_RX_DATA02 0x13C 0x39C 0x500 0x0 0x0 423 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_ 423 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_DATA04 0x13C 0x39C 0x000 0x1 0x0 424 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_ 424 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI1_TX_SYNC 0x13C 0x39C 0x4D8 0x2 0x1 425 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_ 425 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0x13C 0x39C 0x50C 0x3 0x0 426 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_B 426 #define MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x13C 0x39C 0x4C8 0x4 0x3 427 #define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 427 #define MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x13C 0x39C 0x000 0x5 0x0 428 #define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 428 #define MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x13C 0x39C 0x54C 0x6 0x0 429 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_ 429 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_RX_DATA03 0x140 0x3A0 0x504 0x0 0x0 430 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_ 430 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_DATA05 0x140 0x3A0 0x000 0x1 0x0 431 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_ 431 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI1_TX_SYNC 0x140 0x3A0 0x4D8 0x2 0x2 432 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_ 432 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0x140 0x3A0 0x000 0x3 0x0 433 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_B 433 #define MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x140 0x3A0 0x4CC 0x4 0x3 434 #define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 434 #define MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x140 0x3A0 0x000 0x5 0x0 435 #define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 435 #define MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x140 0x3A0 0x000 0x6 0x0 436 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_ 436 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI5_MCLK 0x144 0x3A4 0x4F0 0x0 0x0 437 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_ 437 #define MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x144 0x3A4 0x4D4 0x1 0x0 438 #define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 438 #define MX8MP_IOMUXC_SAI5_MCLK__PWM1_OUT 0x144 0x3A4 0x000 0x2 0x0 439 #define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 439 #define MX8MP_IOMUXC_SAI5_MCLK__I2C5_SDA 0x144 0x3A4 0x5C8 0x3 0x1 440 #define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 440 #define MX8MP_IOMUXC_SAI5_MCLK__GPIO3_IO25 0x144 0x3A4 0x000 0x5 0x0 441 #define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 441 #define MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x144 0x3A4 0x550 0x6 0x0 442 #define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_ 442 #define MX8MP_IOMUXC_SAI1_RXFS__AUDIOMIX_SAI1_RX_SYNC 0x148 0x3A8 0x4D0 0x0 0x0 443 #define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVE 443 #define MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x148 0x3A8 0x000 0x4 0x0 444 #define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 444 #define MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x148 0x3A8 0x000 0x5 0x0 445 #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_R 445 #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_SAI1_RX_BCLK 0x14C 0x3AC 0x000 0x0 0x0 446 #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CL 446 #define MX8MP_IOMUXC_SAI1_RXC__AUDIOMIX_PDM_CLK 0x14C 0x3AC 0x000 0x3 0x0 447 #define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVEN 447 #define MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x14C 0x3AC 0x000 0x4 0x0 448 #define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 448 #define MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x14C 0x3AC 0x000 0x5 0x0 449 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_ 449 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x150 0x3B0 0x000 0x0 0x0 450 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_ 450 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_TX_DATA01 0x150 0x3B0 0x000 0x2 0x0 451 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_B 451 #define MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0x150 0x3B0 0x4C0 0x3 0x4 452 #define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVE 452 #define MX8MP_IOMUXC_SAI1_RXD0__ENET1_1588_EVENT1_IN 0x150 0x3B0 0x000 0x4 0x0 453 #define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 453 #define MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x150 0x3B0 0x000 0x5 0x0 454 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_ 454 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_SAI1_RX_DATA01 0x154 0x3B4 0x000 0x0 0x0 455 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_B 455 #define MX8MP_IOMUXC_SAI1_RXD1__AUDIOMIX_PDM_BIT_STREAM01 0x154 0x3B4 0x4C4 0x3 0x4 456 #define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVE 456 #define MX8MP_IOMUXC_SAI1_RXD1__ENET1_1588_EVENT1_OUT 0x154 0x3B4 0x000 0x4 0x0 457 #define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 457 #define MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x154 0x3B4 0x000 0x5 0x0 458 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_ 458 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_SAI1_RX_DATA02 0x158 0x3B8 0x000 0x0 0x0 459 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_B 459 #define MX8MP_IOMUXC_SAI1_RXD2__AUDIOMIX_PDM_BIT_STREAM02 0x158 0x3B8 0x4C8 0x3 0x4 460 #define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 460 #define MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x158 0x3B8 0x000 0x4 0x0 461 #define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 461 #define MX8MP_IOMUXC_SAI1_RXD2__GPIO4_IO04 0x158 0x3B8 0x000 0x5 0x0 462 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_ 462 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_SAI1_RX_DATA03 0x15C 0x3BC 0x000 0x0 0x0 463 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_B 463 #define MX8MP_IOMUXC_SAI1_RXD3__AUDIOMIX_PDM_BIT_STREAM03 0x15C 0x3BC 0x4CC 0x3 0x4 464 #define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 464 #define MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x15C 0x3BC 0x57C 0x4 0x1 465 #define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 465 #define MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x15C 0x3BC 0x000 0x5 0x0 466 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_ 466 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI1_RX_DATA04 0x160 0x3C0 0x000 0x0 0x0 467 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_ 467 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_TX_BCLK 0x160 0x3C0 0x524 0x1 0x1 468 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_ 468 #define MX8MP_IOMUXC_SAI1_RXD4__AUDIOMIX_SAI6_RX_BCLK 0x160 0x3C0 0x518 0x2 0x1 469 #define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD 469 #define MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x160 0x3C0 0x580 0x4 0x1 470 #define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 470 #define MX8MP_IOMUXC_SAI1_RXD4__GPIO4_IO06 0x160 0x3C0 0x000 0x5 0x0 471 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_ 471 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_DATA05 0x164 0x3C4 0x000 0x0 0x0 472 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_ 472 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_TX_DATA00 0x164 0x3C4 0x000 0x1 0x0 473 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_ 473 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI6_RX_DATA00 0x164 0x3C4 0x51C 0x2 0x1 474 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_ 474 #define MX8MP_IOMUXC_SAI1_RXD5__AUDIOMIX_SAI1_RX_SYNC 0x164 0x3C4 0x4D0 0x3 0x1 475 #define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD 475 #define MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x164 0x3C4 0x584 0x4 0x1 476 #define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 476 #define MX8MP_IOMUXC_SAI1_RXD5__GPIO4_IO07 0x164 0x3C4 0x000 0x5 0x0 477 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_ 477 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI1_RX_DATA06 0x168 0x3C8 0x000 0x0 0x0 478 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_ 478 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_TX_SYNC 0x168 0x3C8 0x528 0x1 0x1 479 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_ 479 #define MX8MP_IOMUXC_SAI1_RXD6__AUDIOMIX_SAI6_RX_SYNC 0x168 0x3C8 0x520 0x2 0x1 480 #define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD 480 #define MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x168 0x3C8 0x000 0x4 0x0 481 #define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 481 #define MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x168 0x3C8 0x000 0x5 0x0 482 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_ 482 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_RX_DATA07 0x16C 0x3CC 0x000 0x0 0x0 483 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_ 483 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI6_MCLK 0x16C 0x3CC 0x514 0x1 0x1 484 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_ 484 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_SYNC 0x16C 0x3CC 0x4D8 0x2 0x3 485 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_ 485 #define MX8MP_IOMUXC_SAI1_RXD7__AUDIOMIX_SAI1_TX_DATA04 0x16C 0x3CC 0x000 0x3 0x0 486 #define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD 486 #define MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x16C 0x3CC 0x000 0x4 0x0 487 #define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 487 #define MX8MP_IOMUXC_SAI1_RXD7__GPIO4_IO09 0x16C 0x3CC 0x000 0x5 0x0 488 #define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_ 488 #define MX8MP_IOMUXC_SAI1_TXFS__AUDIOMIX_SAI1_TX_SYNC 0x170 0x3D0 0x4D8 0x0 0x4 489 #define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX 489 #define MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x170 0x3D0 0x588 0x4 0x1 490 #define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 490 #define MX8MP_IOMUXC_SAI1_TXFS__GPIO4_IO10 0x170 0x3D0 0x000 0x5 0x0 491 #define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_T 491 #define MX8MP_IOMUXC_SAI1_TXC__AUDIOMIX_SAI1_TX_BCLK 0x174 0x3D4 0x4D4 0x0 0x1 492 #define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 492 #define MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x174 0x3D4 0x000 0x4 0x0 493 #define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 493 #define MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x174 0x3D4 0x000 0x5 0x0 494 #define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_ 494 #define MX8MP_IOMUXC_SAI1_TXD0__AUDIOMIX_SAI1_TX_DATA00 0x178 0x3D8 0x000 0x0 0x0 495 #define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD 495 #define MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x178 0x3D8 0x000 0x4 0x0 496 #define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 496 #define MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x178 0x3D8 0x000 0x5 0x0 497 #define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_ 497 #define MX8MP_IOMUXC_SAI1_TXD1__AUDIOMIX_SAI1_TX_DATA01 0x17C 0x3DC 0x000 0x0 0x0 498 #define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD 498 #define MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x17C 0x3DC 0x000 0x4 0x0 499 #define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 499 #define MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x17C 0x3DC 0x000 0x5 0x0 500 #define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_ 500 #define MX8MP_IOMUXC_SAI1_TXD2__AUDIOMIX_SAI1_TX_DATA02 0x180 0x3E0 0x000 0x0 0x0 501 #define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD 501 #define MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x180 0x3E0 0x000 0x4 0x0 502 #define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 502 #define MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x180 0x3E0 0x000 0x5 0x0 503 #define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_ 503 #define MX8MP_IOMUXC_SAI1_TXD3__AUDIOMIX_SAI1_TX_DATA03 0x184 0x3E4 0x000 0x0 0x0 504 #define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD 504 #define MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x184 0x3E4 0x000 0x4 0x0 505 #define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 505 #define MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x184 0x3E4 0x000 0x5 0x0 506 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_ 506 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI1_TX_DATA04 0x188 0x3E8 0x000 0x0 0x0 507 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_ 507 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_RX_BCLK 0x188 0x3E8 0x518 0x1 0x2 508 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_ 508 #define MX8MP_IOMUXC_SAI1_TXD4__AUDIOMIX_SAI6_TX_BCLK 0x188 0x3E8 0x524 0x2 0x2 509 #define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX 509 #define MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x188 0x3E8 0x000 0x4 0x0 510 #define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 510 #define MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x188 0x3E8 0x000 0x5 0x0 511 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_ 511 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI1_TX_DATA05 0x18C 0x3EC 0x000 0x0 0x0 512 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_ 512 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_RX_DATA00 0x18C 0x3EC 0x51C 0x1 0x2 513 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_ 513 #define MX8MP_IOMUXC_SAI1_TXD5__AUDIOMIX_SAI6_TX_DATA00 0x18C 0x3EC 0x000 0x2 0x0 514 #define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TX 514 #define MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x18C 0x3EC 0x000 0x4 0x0 515 #define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 515 #define MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x18C 0x3EC 0x000 0x5 0x0 516 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_ 516 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI1_TX_DATA06 0x190 0x3F0 0x000 0x0 0x0 517 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_ 517 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_RX_SYNC 0x190 0x3F0 0x520 0x1 0x2 518 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_ 518 #define MX8MP_IOMUXC_SAI1_TXD6__AUDIOMIX_SAI6_TX_SYNC 0x190 0x3F0 0x528 0x2 0x2 519 #define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 519 #define MX8MP_IOMUXC_SAI1_TXD6__ENET1_RX_ER 0x190 0x3F0 0x58C 0x4 0x1 520 #define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 520 #define MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x190 0x3F0 0x000 0x5 0x0 521 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_ 521 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI1_TX_DATA07 0x194 0x3F4 0x000 0x0 0x0 522 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_ 522 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_SAI6_MCLK 0x194 0x3F4 0x514 0x1 0x2 523 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_C 523 #define MX8MP_IOMUXC_SAI1_TXD7__AUDIOMIX_PDM_CLK 0x194 0x3F4 0x000 0x3 0x0 524 #define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 524 #define MX8MP_IOMUXC_SAI1_TXD7__ENET1_TX_ER 0x194 0x3F4 0x000 0x4 0x0 525 #define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 525 #define MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x194 0x3F4 0x000 0x5 0x0 526 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_ 526 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x198 0x3F8 0x000 0x0 0x0 527 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_ 527 #define MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x198 0x3F8 0x4D4 0x2 0x2 528 #define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 528 #define MX8MP_IOMUXC_SAI1_MCLK__ENET1_TX_CLK 0x198 0x3F8 0x578 0x4 0x1 529 #define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 529 #define MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x198 0x3F8 0x000 0x5 0x0 530 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_ 530 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_SYNC 0x19C 0x3FC 0x000 0x0 0x0 531 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_ 531 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_SYNC 0x19C 0x3FC 0x510 0x1 0x2 532 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_ 532 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI5_TX_DATA01 0x19C 0x3FC 0x000 0x2 0x0 533 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_ 533 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x19C 0x3FC 0x4DC 0x3 0x0 534 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 534 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DCE_TX 0x19C 0x3FC 0x000 0x4 0x0 535 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 535 #define MX8MP_IOMUXC_SAI2_RXFS__UART1_DTE_RX 0x19C 0x3FC 0x5E8 0x4 0x2 536 #define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 536 #define MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x19C 0x3FC 0x000 0x5 0x0 537 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_B 537 #define MX8MP_IOMUXC_SAI2_RXFS__AUDIOMIX_PDM_BIT_STREAM02 0x19C 0x3FC 0x4C8 0x6 0x5 538 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_R 538 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI2_RX_BCLK 0x1A0 0x400 0x000 0x0 0x0 539 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_T 539 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_SAI5_TX_BCLK 0x1A0 0x400 0x50C 0x1 0x2 540 #define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 540 #define MX8MP_IOMUXC_SAI2_RXC__CAN1_TX 0x1A0 0x400 0x000 0x3 0x0 541 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 541 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DCE_RX 0x1A0 0x400 0x5E8 0x4 0x3 542 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 542 #define MX8MP_IOMUXC_SAI2_RXC__UART1_DTE_TX 0x1A0 0x400 0x000 0x4 0x0 543 #define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 543 #define MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x1A0 0x400 0x000 0x5 0x0 544 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BI 544 #define MX8MP_IOMUXC_SAI2_RXC__AUDIOMIX_PDM_BIT_STREAM01 0x1A0 0x400 0x4C4 0x6 0x5 545 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_ 545 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_RX_DATA00 0x1A4 0x404 0x000 0x0 0x0 546 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_ 546 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI5_TX_DATA00 0x1A4 0x404 0x000 0x1 0x0 547 #define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_ 547 #define MX8MP_IOMUXC_SAI2_RXD0__ENET_QOS_1588_EVENT2_OUT 0x1A4 0x404 0x000 0x2 0x0 548 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_ 548 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_SAI2_TX_DATA01 0x1A4 0x404 0x000 0x3 0x0 549 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 549 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1A4 0x404 0x5E4 0x4 0x2 550 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 550 #define MX8MP_IOMUXC_SAI2_RXD0__UART1_DTE_CTS 0x1A4 0x404 0x000 0x4 0x0 551 #define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 551 #define MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x1A4 0x404 0x000 0x5 0x0 552 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_B 552 #define MX8MP_IOMUXC_SAI2_RXD0__AUDIOMIX_PDM_BIT_STREAM03 0x1A4 0x404 0x4CC 0x6 0x5 553 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_ 553 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0x1A8 0x408 0x000 0x0 0x0 554 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_ 554 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI5_TX_DATA01 0x1A8 0x408 0x000 0x1 0x0 555 #define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_ 555 #define MX8MP_IOMUXC_SAI2_TXFS__ENET_QOS_1588_EVENT3_OUT 0x1A8 0x408 0x000 0x2 0x0 556 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_ 556 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1A8 0x408 0x000 0x3 0x0 557 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 557 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1A8 0x408 0x000 0x4 0x0 558 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 558 #define MX8MP_IOMUXC_SAI2_TXFS__UART1_DTE_RTS 0x1A8 0x408 0x5E4 0x4 0x3 559 #define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 559 #define MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x1A8 0x408 0x000 0x5 0x0 560 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_B 560 #define MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_PDM_BIT_STREAM02 0x1A8 0x408 0x4C8 0x6 0x6 561 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_T 561 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0x1AC 0x40C 0x000 0x0 0x0 562 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_T 562 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI5_TX_DATA02 0x1AC 0x40C 0x000 0x1 0x0 563 #define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 563 #define MX8MP_IOMUXC_SAI2_TXC__CAN1_RX 0x1AC 0x40C 0x54C 0x3 0x1 564 #define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 564 #define MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1AC 0x40C 0x000 0x5 0x0 565 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BI 565 #define MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_PDM_BIT_STREAM01 0x1AC 0x40C 0x4C4 0x6 0x6 566 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_ 566 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0x1B0 0x410 0x000 0x0 0x0 567 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_ 567 #define MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI5_TX_DATA03 0x1B0 0x410 0x000 0x1 0x0 568 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_ 568 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_IN 0x1B0 0x410 0x000 0x2 0x0 569 #define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 569 #define MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x1B0 0x410 0x000 0x3 0x0 570 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_ 570 #define MX8MP_IOMUXC_SAI2_TXD0__ENET_QOS_1588_EVENT2_AUX_IN 0x1B0 0x410 0x000 0x4 0x0 571 #define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 571 #define MX8MP_IOMUXC_SAI2_TXD0__GPIO4_IO26 0x1B0 0x410 0x000 0x5 0x0 572 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_ 572 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0x1B4 0x414 0x000 0x0 0x0 573 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_ 573 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI5_MCLK 0x1B4 0x414 0x4F0 0x1 0x2 574 #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_ 574 #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_IN 0x1B4 0x414 0x000 0x2 0x0 575 #define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 575 #define MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x1B4 0x414 0x550 0x3 0x1 576 #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_ 576 #define MX8MP_IOMUXC_SAI2_MCLK__ENET_QOS_1588_EVENT3_AUX_IN 0x1B4 0x414 0x000 0x4 0x0 577 #define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 577 #define MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x1B4 0x414 0x000 0x5 0x0 578 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_ 578 #define MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI3_MCLK 0x1B4 0x414 0x4E0 0x6 0x1 579 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_ 579 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_SYNC 0x1B8 0x418 0x000 0x0 0x0 580 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_ 580 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI2_RX_DATA01 0x1B8 0x418 0x4DC 0x1 0x1 581 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_ 581 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI5_RX_SYNC 0x1B8 0x418 0x508 0x2 0x2 582 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_ 582 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SAI3_RX_DATA01 0x1B8 0x418 0x000 0x3 0x0 583 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF 583 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_SPDIF1_IN 0x1B8 0x418 0x544 0x4 0x2 584 #define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 584 #define MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1B8 0x418 0x000 0x5 0x0 585 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_B 585 #define MX8MP_IOMUXC_SAI3_RXFS__AUDIOMIX_PDM_BIT_STREAM00 0x1B8 0x418 0x4C0 0x6 0x5 586 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_R 586 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI3_RX_BCLK 0x1BC 0x41C 0x000 0x0 0x0 587 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_R 587 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI2_RX_DATA02 0x1BC 0x41C 0x000 0x1 0x0 588 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_R 588 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_SAI5_RX_BCLK 0x1BC 0x41C 0x4F4 0x2 0x2 589 #define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 589 #define MX8MP_IOMUXC_SAI3_RXC__GPT1_CLK 0x1BC 0x41C 0x59C 0x3 0x0 590 #define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 590 #define MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x1BC 0x41C 0x000 0x4 0x0 591 #define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 591 #define MX8MP_IOMUXC_SAI3_RXC__UART2_DTE_RTS 0x1BC 0x41C 0x5EC 0x4 0x2 592 #define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 592 #define MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1BC 0x41C 0x000 0x5 0x0 593 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CL 593 #define MX8MP_IOMUXC_SAI3_RXC__AUDIOMIX_PDM_CLK 0x1BC 0x41C 0x000 0x6 0x0 594 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_R 594 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1C0 0x420 0x4E4 0x0 0x1 595 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_R 595 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI2_RX_DATA03 0x1C0 0x420 0x000 0x1 0x0 596 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_R 596 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI5_RX_DATA00 0x1C0 0x420 0x4F8 0x2 0x2 597 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 597 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x1C0 0x420 0x5EC 0x4 0x3 598 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 598 #define MX8MP_IOMUXC_SAI3_RXD__UART2_DTE_CTS 0x1C0 0x420 0x000 0x4 0x0 599 #define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 599 #define MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x1C0 0x420 0x000 0x5 0x0 600 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BI 600 #define MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_PDM_BIT_STREAM01 0x1C0 0x420 0x4C4 0x6 0x7 601 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_ 601 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1C4 0x424 0x4EC 0x0 0x1 602 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_ 602 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI2_TX_DATA01 0x1C4 0x424 0x000 0x1 0x0 603 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_ 603 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI5_RX_DATA01 0x1C4 0x424 0x4FC 0x2 0x2 604 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_ 604 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_DATA01 0x1C4 0x424 0x000 0x3 0x0 605 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 605 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DCE_RX 0x1C4 0x424 0x5F0 0x4 0x4 606 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 606 #define MX8MP_IOMUXC_SAI3_TXFS__UART2_DTE_TX 0x1C4 0x424 0x000 0x4 0x0 607 #define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 607 #define MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x1C4 0x424 0x000 0x5 0x0 608 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_B 608 #define MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_PDM_BIT_STREAM03 0x1C4 0x424 0x4CC 0x6 0x6 609 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_T 609 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1C8 0x428 0x4E8 0x0 0x1 610 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_T 610 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI2_TX_DATA02 0x1C8 0x428 0x000 0x1 0x0 611 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_R 611 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI5_RX_DATA02 0x1C8 0x428 0x500 0x2 0x2 612 #define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 612 #define MX8MP_IOMUXC_SAI3_TXC__GPT1_CAPTURE1 0x1C8 0x428 0x594 0x3 0x0 613 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 613 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DCE_TX 0x1C8 0x428 0x000 0x4 0x0 614 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 614 #define MX8MP_IOMUXC_SAI3_TXC__UART2_DTE_RX 0x1C8 0x428 0x5F0 0x4 0x5 615 #define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 615 #define MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x1C8 0x428 0x000 0x5 0x0 616 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BI 616 #define MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_PDM_BIT_STREAM02 0x1C8 0x428 0x4C8 0x6 0x7 617 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_T 617 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x1CC 0x42C 0x000 0x0 0x0 618 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_T 618 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI2_TX_DATA03 0x1CC 0x42C 0x000 0x1 0x0 619 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_R 619 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI5_RX_DATA03 0x1CC 0x42C 0x504 0x2 0x2 620 #define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 620 #define MX8MP_IOMUXC_SAI3_TXD__GPT1_CAPTURE2 0x1CC 0x42C 0x598 0x3 0x0 621 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1 621 #define MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SPDIF1_EXT_CLK 0x1CC 0x42C 0x548 0x4 0x0 622 #define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 622 #define MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x1CC 0x42C 0x000 0x5 0x0 623 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_ 623 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI3_MCLK 0x1D0 0x430 0x4E0 0x0 0x2 624 #define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 624 #define MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x1D0 0x430 0x000 0x1 0x0 625 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_ 625 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SAI5_MCLK 0x1D0 0x430 0x4F0 0x2 0x3 626 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF 626 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_OUT 0x1D0 0x430 0x000 0x4 0x0 627 #define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 627 #define MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1D0 0x430 0x000 0x5 0x0 628 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF 628 #define MX8MP_IOMUXC_SAI3_MCLK__AUDIOMIX_SPDIF1_IN 0x1D0 0x430 0x544 0x6 0x3 629 #define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1 629 #define MX8MP_IOMUXC_SPDIF_TX__AUDIOMIX_SPDIF1_OUT 0x1D4 0x434 0x000 0x0 0x0 630 #define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 630 #define MX8MP_IOMUXC_SPDIF_TX__PWM3_OUT 0x1D4 0x434 0x000 0x1 0x0 631 #define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 631 #define MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x1D4 0x434 0x5C4 0x2 0x2 632 #define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 632 #define MX8MP_IOMUXC_SPDIF_TX__GPT1_COMPARE1 0x1D4 0x434 0x000 0x3 0x0 633 #define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 633 #define MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x1D4 0x434 0x000 0x4 0x0 634 #define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 634 #define MX8MP_IOMUXC_SPDIF_TX__GPIO5_IO03 0x1D4 0x434 0x000 0x5 0x0 635 #define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1 635 #define MX8MP_IOMUXC_SPDIF_RX__AUDIOMIX_SPDIF1_IN 0x1D8 0x438 0x544 0x0 0x4 636 #define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 636 #define MX8MP_IOMUXC_SPDIF_RX__PWM2_OUT 0x1D8 0x438 0x000 0x1 0x0 637 #define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 637 #define MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x1D8 0x438 0x5C8 0x2 0x2 638 #define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 638 #define MX8MP_IOMUXC_SPDIF_RX__GPT1_COMPARE2 0x1D8 0x438 0x000 0x3 0x0 639 #define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 639 #define MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x1D8 0x438 0x54C 0x4 0x2 640 #define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 640 #define MX8MP_IOMUXC_SPDIF_RX__GPIO5_IO04 0x1D8 0x438 0x000 0x5 0x0 641 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPA 641 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPT1_COMPARE3 0x1DC 0x43C 0x000 0x3 0x0 642 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 642 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x1DC 0x43C 0x000 0x5 0x0 643 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_S 643 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__AUDIOMIX_SPDIF1_EXT_CLK 0x1DC 0x43C 0x548 0x0 0x1 644 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 644 #define MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x1DC 0x43C 0x000 0x1 0x0 645 #define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 645 #define MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x1E0 0x440 0x558 0x0 0x0 646 #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 646 #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x1E0 0x440 0x5F8 0x1 0x4 647 #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 647 #define MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DTE_TX 0x1E0 0x440 0x000 0x1 0x0 648 #define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 648 #define MX8MP_IOMUXC_ECSPI1_SCLK__I2C1_SCL 0x1E0 0x440 0x5A4 0x2 0x1 649 #define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI 649 #define MX8MP_IOMUXC_ECSPI1_SCLK__AUDIOMIX_SAI7_RX_SYNC 0x1E0 0x440 0x538 0x3 0x1 650 #define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 650 #define MX8MP_IOMUXC_ECSPI1_SCLK__GPIO5_IO06 0x1E0 0x440 0x000 0x5 0x0 651 #define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 651 #define MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x1E4 0x444 0x560 0x0 0x0 652 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 652 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x1E4 0x444 0x000 0x1 0x0 653 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 653 #define MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DTE_RX 0x1E4 0x444 0x5F8 0x1 0x5 654 #define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 654 #define MX8MP_IOMUXC_ECSPI1_MOSI__I2C1_SDA 0x1E4 0x444 0x5A8 0x2 0x1 655 #define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI 655 #define MX8MP_IOMUXC_ECSPI1_MOSI__AUDIOMIX_SAI7_RX_BCLK 0x1E4 0x444 0x530 0x3 0x1 656 #define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 656 #define MX8MP_IOMUXC_ECSPI1_MOSI__GPIO5_IO07 0x1E4 0x444 0x000 0x5 0x0 657 #define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 657 #define MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1E8 0x448 0x55C 0x0 0x0 658 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CT 658 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x1E8 0x448 0x000 0x1 0x0 659 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RT 659 #define MX8MP_IOMUXC_ECSPI1_MISO__UART3_DTE_RTS 0x1E8 0x448 0x5F4 0x1 0x2 660 #define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 660 #define MX8MP_IOMUXC_ECSPI1_MISO__I2C2_SCL 0x1E8 0x448 0x5AC 0x2 0x1 661 #define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI 661 #define MX8MP_IOMUXC_ECSPI1_MISO__AUDIOMIX_SAI7_RX_DATA00 0x1E8 0x448 0x534 0x3 0x1 662 #define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 662 #define MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x1E8 0x448 0x000 0x5 0x0 663 #define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 663 #define MX8MP_IOMUXC_ECSPI1_SS0__ECSPI1_SS0 0x1EC 0x44C 0x564 0x0 0x0 664 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 664 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x1EC 0x44C 0x5F4 0x1 0x3 665 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 665 #define MX8MP_IOMUXC_ECSPI1_SS0__UART3_DTE_CTS 0x1EC 0x44C 0x000 0x1 0x0 666 #define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 666 #define MX8MP_IOMUXC_ECSPI1_SS0__I2C2_SDA 0x1EC 0x44C 0x5B0 0x2 0x1 667 #define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7 667 #define MX8MP_IOMUXC_ECSPI1_SS0__AUDIOMIX_SAI7_TX_SYNC 0x1EC 0x44C 0x540 0x3 0x1 668 #define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 668 #define MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1EC 0x44C 0x000 0x5 0x0 669 #define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 669 #define MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x1F0 0x450 0x568 0x0 0x1 670 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 670 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1F0 0x450 0x600 0x1 0x6 671 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 671 #define MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DTE_TX 0x1F0 0x450 0x000 0x1 0x0 672 #define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 672 #define MX8MP_IOMUXC_ECSPI2_SCLK__I2C3_SCL 0x1F0 0x450 0x5B4 0x2 0x3 673 #define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI 673 #define MX8MP_IOMUXC_ECSPI2_SCLK__AUDIOMIX_SAI7_TX_BCLK 0x1F0 0x450 0x53C 0x3 0x1 674 #define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 674 #define MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1F0 0x450 0x000 0x5 0x0 675 #define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 675 #define MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x1F4 0x454 0x570 0x0 0x1 676 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 676 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1F4 0x454 0x000 0x1 0x0 677 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 677 #define MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DTE_RX 0x1F4 0x454 0x600 0x1 0x7 678 #define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 678 #define MX8MP_IOMUXC_ECSPI2_MOSI__I2C3_SDA 0x1F4 0x454 0x5B8 0x2 0x3 679 #define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI 679 #define MX8MP_IOMUXC_ECSPI2_MOSI__AUDIOMIX_SAI7_TX_DATA00 0x1F4 0x454 0x000 0x3 0x0 680 #define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 680 #define MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1F4 0x454 0x000 0x5 0x0 681 #define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 681 #define MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1F8 0x458 0x000 0x5 0x0 682 #define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 682 #define MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x1F8 0x458 0x56C 0x0 0x1 683 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CT 683 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1F8 0x458 0x000 0x1 0x0 684 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RT 684 #define MX8MP_IOMUXC_ECSPI2_MISO__UART4_DTE_RTS 0x1F8 0x458 0x5FC 0x1 0x2 685 #define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 685 #define MX8MP_IOMUXC_ECSPI2_MISO__I2C4_SCL 0x1F8 0x458 0x5BC 0x2 0x4 686 #define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI 686 #define MX8MP_IOMUXC_ECSPI2_MISO__AUDIOMIX_SAI7_MCLK 0x1F8 0x458 0x52C 0x3 0x1 687 #define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 687 #define MX8MP_IOMUXC_ECSPI2_MISO__CCM_CLKO1 0x1F8 0x458 0x000 0x4 0x0 688 #define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 688 #define MX8MP_IOMUXC_ECSPI2_SS0__ECSPI2_SS0 0x1FC 0x45C 0x574 0x0 0x1 689 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 689 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1FC 0x45C 0x5FC 0x1 0x3 690 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 690 #define MX8MP_IOMUXC_ECSPI2_SS0__UART4_DTE_CTS 0x1FC 0x45C 0x000 0x1 0x0 691 #define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 691 #define MX8MP_IOMUXC_ECSPI2_SS0__I2C4_SDA 0x1FC 0x45C 0x5C0 0x2 0x4 692 #define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 692 #define MX8MP_IOMUXC_ECSPI2_SS0__CCM_CLKO2 0x1FC 0x45C 0x000 0x4 0x0 693 #define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 693 #define MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1FC 0x45C 0x000 0x5 0x0 694 #define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 694 #define MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x200 0x460 0x5A4 0x0 0x2 695 #define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 695 #define MX8MP_IOMUXC_I2C1_SCL__ENET_QOS_MDC 0x200 0x460 0x000 0x1 0x0 696 #define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 696 #define MX8MP_IOMUXC_I2C1_SCL__ECSPI1_SCLK 0x200 0x460 0x558 0x3 0x1 697 #define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 697 #define MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x200 0x460 0x000 0x5 0x0 698 #define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 698 #define MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x204 0x464 0x5A8 0x0 0x2 699 #define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 699 #define MX8MP_IOMUXC_I2C1_SDA__ENET_QOS_MDIO 0x204 0x464 0x590 0x1 0x2 700 #define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 700 #define MX8MP_IOMUXC_I2C1_SDA__ECSPI1_MOSI 0x204 0x464 0x560 0x3 0x1 701 #define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 701 #define MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x204 0x464 0x000 0x5 0x0 702 #define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 702 #define MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x208 0x468 0x5AC 0x0 0x2 703 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_E 703 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_IN 0x208 0x468 0x000 0x1 0x0 704 #define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 704 #define MX8MP_IOMUXC_I2C2_SCL__USDHC3_CD_B 0x208 0x468 0x608 0x2 0x3 705 #define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 705 #define MX8MP_IOMUXC_I2C2_SCL__ECSPI1_MISO 0x208 0x468 0x55C 0x3 0x1 706 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_E 706 #define MX8MP_IOMUXC_I2C2_SCL__ENET_QOS_1588_EVENT1_AUX_IN 0x208 0x468 0x000 0x4 0x0 707 #define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 707 #define MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x208 0x468 0x000 0x5 0x0 708 #define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 708 #define MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x20C 0x46C 0x5B0 0x0 0x2 709 #define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_E 709 #define MX8MP_IOMUXC_I2C2_SDA__ENET_QOS_1588_EVENT1_OUT 0x20C 0x46C 0x000 0x1 0x0 710 #define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 710 #define MX8MP_IOMUXC_I2C2_SDA__USDHC3_WP 0x20C 0x46C 0x634 0x2 0x3 711 #define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 711 #define MX8MP_IOMUXC_I2C2_SDA__ECSPI1_SS0 0x20C 0x46C 0x564 0x3 0x1 712 #define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 712 #define MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x20C 0x46C 0x000 0x5 0x0 713 #define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 713 #define MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x210 0x470 0x5B4 0x0 0x4 714 #define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 714 #define MX8MP_IOMUXC_I2C3_SCL__PWM4_OUT 0x210 0x470 0x000 0x1 0x0 715 #define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 715 #define MX8MP_IOMUXC_I2C3_SCL__GPT2_CLK 0x210 0x470 0x000 0x2 0x0 716 #define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 716 #define MX8MP_IOMUXC_I2C3_SCL__ECSPI2_SCLK 0x210 0x470 0x568 0x3 0x2 717 #define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 717 #define MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x210 0x470 0x000 0x5 0x0 718 #define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 718 #define MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x214 0x474 0x5B8 0x0 0x4 719 #define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 719 #define MX8MP_IOMUXC_I2C3_SDA__PWM3_OUT 0x214 0x474 0x000 0x1 0x0 720 #define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 720 #define MX8MP_IOMUXC_I2C3_SDA__GPT3_CLK 0x214 0x474 0x000 0x2 0x0 721 #define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 721 #define MX8MP_IOMUXC_I2C3_SDA__ECSPI2_MOSI 0x214 0x474 0x570 0x3 0x2 722 #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 722 #define MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x214 0x474 0x000 0x5 0x0 723 #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 723 #define MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x218 0x478 0x5BC 0x0 0x5 724 #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 724 #define MX8MP_IOMUXC_I2C4_SCL__PWM2_OUT 0x218 0x478 0x000 0x1 0x0 725 #define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 725 #define MX8MP_IOMUXC_I2C4_SCL__PCIE_CLKREQ_B 0x218 0x478 0x5A0 0x2 0x0 726 #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 726 #define MX8MP_IOMUXC_I2C4_SCL__ECSPI2_MISO 0x218 0x478 0x56C 0x3 0x2 727 #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 727 #define MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x218 0x478 0x000 0x5 0x0 728 #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 728 #define MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x21C 0x47C 0x5C0 0x0 0x5 729 #define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 729 #define MX8MP_IOMUXC_I2C4_SDA__PWM1_OUT 0x21C 0x47C 0x000 0x1 0x0 730 #define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 730 #define MX8MP_IOMUXC_I2C4_SDA__ECSPI2_SS0 0x21C 0x47C 0x574 0x3 0x2 731 #define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 731 #define MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x21C 0x47C 0x000 0x5 0x0 732 #define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 732 #define MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x220 0x480 0x5E8 0x0 0x4 733 #define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 733 #define MX8MP_IOMUXC_UART1_RXD__UART1_DTE_TX 0x220 0x480 0x000 0x0 0x0 734 #define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 734 #define MX8MP_IOMUXC_UART1_RXD__ECSPI3_SCLK 0x220 0x480 0x000 0x1 0x0 735 #define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 735 #define MX8MP_IOMUXC_UART1_RXD__GPIO5_IO22 0x220 0x480 0x000 0x5 0x0 736 #define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 736 #define MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x224 0x484 0x000 0x0 0x0 737 #define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 737 #define MX8MP_IOMUXC_UART1_TXD__UART1_DTE_RX 0x224 0x484 0x5E8 0x0 0x5 738 #define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 738 #define MX8MP_IOMUXC_UART1_TXD__ECSPI3_MOSI 0x224 0x484 0x000 0x1 0x0 739 #define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 739 #define MX8MP_IOMUXC_UART1_TXD__GPIO5_IO23 0x224 0x484 0x000 0x5 0x0 740 #define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 740 #define MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x228 0x488 0x5F0 0x0 0x6 741 #define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 741 #define MX8MP_IOMUXC_UART2_RXD__UART2_DTE_TX 0x228 0x488 0x000 0x0 0x0 742 #define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 742 #define MX8MP_IOMUXC_UART2_RXD__ECSPI3_MISO 0x228 0x488 0x000 0x1 0x0 743 #define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 743 #define MX8MP_IOMUXC_UART2_RXD__GPT1_COMPARE3 0x228 0x488 0x000 0x3 0x0 744 #define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 744 #define MX8MP_IOMUXC_UART2_RXD__GPIO5_IO24 0x228 0x488 0x000 0x5 0x0 745 #define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 745 #define MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x22C 0x48C 0x000 0x0 0x0 746 #define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 746 #define MX8MP_IOMUXC_UART2_TXD__UART2_DTE_RX 0x22C 0x48C 0x5F0 0x0 0x7 747 #define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 747 #define MX8MP_IOMUXC_UART2_TXD__ECSPI3_SS0 0x22C 0x48C 0x000 0x1 0x0 748 #define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 748 #define MX8MP_IOMUXC_UART2_TXD__GPT1_COMPARE2 0x22C 0x48C 0x000 0x3 0x0 749 #define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 749 #define MX8MP_IOMUXC_UART2_TXD__GPIO5_IO25 0x22C 0x48C 0x000 0x5 0x0 750 #define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 750 #define MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x230 0x490 0x5F8 0x0 0x6 751 #define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 751 #define MX8MP_IOMUXC_UART3_RXD__UART3_DTE_TX 0x230 0x490 0x000 0x0 0x0 752 #define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 752 #define MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x230 0x490 0x000 0x1 0x0 753 #define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 753 #define MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x230 0x490 0x5E4 0x1 0x4 754 #define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 754 #define MX8MP_IOMUXC_UART3_RXD__USDHC3_RESET_B 0x230 0x490 0x000 0x2 0x0 755 #define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 755 #define MX8MP_IOMUXC_UART3_RXD__GPT1_CAPTURE2 0x230 0x490 0x598 0x3 0x1 756 #define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 756 #define MX8MP_IOMUXC_UART3_RXD__CAN2_TX 0x230 0x490 0x000 0x4 0x0 757 #define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 757 #define MX8MP_IOMUXC_UART3_RXD__GPIO5_IO26 0x230 0x490 0x000 0x5 0x0 758 #define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 758 #define MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x234 0x494 0x000 0x0 0x0 759 #define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 759 #define MX8MP_IOMUXC_UART3_TXD__UART3_DTE_RX 0x234 0x494 0x5F8 0x0 0x7 760 #define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 760 #define MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x234 0x494 0x5E4 0x1 0x5 761 #define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 761 #define MX8MP_IOMUXC_UART3_TXD__UART1_DTE_CTS 0x234 0x494 0x000 0x1 0x0 762 #define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 762 #define MX8MP_IOMUXC_UART3_TXD__USDHC3_VSELECT 0x234 0x494 0x000 0x2 0x0 763 #define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 763 #define MX8MP_IOMUXC_UART3_TXD__GPT1_CLK 0x234 0x494 0x59C 0x3 0x1 764 #define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 764 #define MX8MP_IOMUXC_UART3_TXD__CAN2_RX 0x234 0x494 0x550 0x4 0x2 765 #define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 765 #define MX8MP_IOMUXC_UART3_TXD__GPIO5_IO27 0x234 0x494 0x000 0x5 0x0 766 #define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 766 #define MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x238 0x498 0x600 0x0 0x8 767 #define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 767 #define MX8MP_IOMUXC_UART4_RXD__UART4_DTE_TX 0x238 0x498 0x000 0x0 0x0 768 #define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 768 #define MX8MP_IOMUXC_UART4_RXD__UART2_DCE_CTS 0x238 0x498 0x000 0x1 0x0 769 #define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 769 #define MX8MP_IOMUXC_UART4_RXD__UART2_DTE_RTS 0x238 0x498 0x5EC 0x1 0x4 770 #define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 770 #define MX8MP_IOMUXC_UART4_RXD__PCIE_CLKREQ_B 0x238 0x498 0x5A0 0x2 0x1 771 #define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 771 #define MX8MP_IOMUXC_UART4_RXD__GPT1_COMPARE1 0x238 0x498 0x000 0x3 0x0 772 #define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 772 #define MX8MP_IOMUXC_UART4_RXD__I2C6_SCL 0x238 0x498 0x5CC 0x4 0x2 773 #define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 773 #define MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x238 0x498 0x000 0x5 0x0 774 #define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 774 #define MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x23C 0x49C 0x000 0x0 0x0 775 #define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 775 #define MX8MP_IOMUXC_UART4_TXD__UART4_DTE_RX 0x23C 0x49C 0x600 0x0 0x9 776 #define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 776 #define MX8MP_IOMUXC_UART4_TXD__UART2_DCE_RTS 0x23C 0x49C 0x5EC 0x1 0x5 777 #define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 777 #define MX8MP_IOMUXC_UART4_TXD__UART2_DTE_CTS 0x23C 0x49C 0x000 0x1 0x0 778 #define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 778 #define MX8MP_IOMUXC_UART4_TXD__GPT1_CAPTURE1 0x23C 0x49C 0x594 0x3 0x1 779 #define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 779 #define MX8MP_IOMUXC_UART4_TXD__I2C6_SDA 0x23C 0x49C 0x5D0 0x4 0x2 780 #define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 780 #define MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x23C 0x49C 0x000 0x5 0x0 781 #define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDM 781 #define MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x240 0x4A0 0x000 0x0 0x0 782 #define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 782 #define MX8MP_IOMUXC_HDMI_DDC_SCL__I2C5_SCL 0x240 0x4A0 0x5C4 0x3 0x3 783 #define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 783 #define MX8MP_IOMUXC_HDMI_DDC_SCL__CAN1_TX 0x240 0x4A0 0x000 0x4 0x0 784 #define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 784 #define MX8MP_IOMUXC_HDMI_DDC_SCL__GPIO3_IO26 0x240 0x4A0 0x000 0x5 0x0 785 #define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDM 785 #define MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x244 0x4A4 0x000 0x0 0x0 786 #define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 786 #define MX8MP_IOMUXC_HDMI_DDC_SDA__I2C5_SDA 0x244 0x4A4 0x5C8 0x3 0x3 787 #define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 787 #define MX8MP_IOMUXC_HDMI_DDC_SDA__CAN1_RX 0x244 0x4A4 0x54C 0x4 0x3 788 #define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 788 #define MX8MP_IOMUXC_HDMI_DDC_SDA__GPIO3_IO27 0x244 0x4A4 0x000 0x5 0x0 789 #define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CE 789 #define MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x248 0x4A8 0x000 0x0 0x0 790 #define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 790 #define MX8MP_IOMUXC_HDMI_CEC__I2C6_SCL 0x248 0x4A8 0x5CC 0x3 0x3 791 #define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 791 #define MX8MP_IOMUXC_HDMI_CEC__CAN2_TX 0x248 0x4A8 0x000 0x4 0x0 792 #define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 792 #define MX8MP_IOMUXC_HDMI_CEC__GPIO3_IO28 0x248 0x4A8 0x000 0x5 0x0 793 #define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HP 793 #define MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x24C 0x4AC 0x000 0x0 0x0 794 #define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_H 794 #define MX8MP_IOMUXC_HDMI_HPD__AUDIOMIX_HDMI_HPD_O 0x24C 0x4AC 0x000 0x1 0x0 795 #define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 795 #define MX8MP_IOMUXC_HDMI_HPD__I2C6_SDA 0x24C 0x4AC 0x5D0 0x3 0x3 796 #define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 796 #define MX8MP_IOMUXC_HDMI_HPD__CAN2_RX 0x24C 0x4AC 0x550 0x4 0x3 797 #define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 797 #define MX8MP_IOMUXC_HDMI_HPD__GPIO3_IO29 0x24C 0x4AC 0x000 0x5 0x0 798 798 799 #endif /* __DTS_IMX8MP_PINFUNC_H */ 799 #endif /* __DTS_IMX8MP_PINFUNC_H */ 800 800
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