1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2023 Gateworks Corporation 3 * Copyright 2023 Gateworks Corporation
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 9
10 / { 10 / {
11 aliases { <<
12 ethernet1 = ð1; <<
13 }; <<
14 <<
15 connector { <<
16 compatible = "gpio-usb-b-conne <<
17 pinctrl-names = "default"; <<
18 pinctrl-0 = <&pinctrl_usbcon1> <<
19 type = "micro"; <<
20 label = "otg"; <<
21 vbus-supply = <®_usb1_vbus> <<
22 id-gpios = <&gpio3 21 GPIO_ACT <<
23 <<
24 port { <<
25 usb_dr_connector: endp <<
26 remote-endpoin <<
27 }; <<
28 }; <<
29 }; <<
30 <<
31 led-controller { 11 led-controller {
32 compatible = "gpio-leds"; 12 compatible = "gpio-leds";
33 pinctrl-names = "default"; 13 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_led 14 pinctrl-0 = <&pinctrl_gpio_leds>;
35 15
36 led-0 { 16 led-0 {
37 function = LED_FUNCTIO 17 function = LED_FUNCTION_STATUS;
38 color = <LED_COLOR_ID_ 18 color = <LED_COLOR_ID_GREEN>;
39 gpios = <&gpio4 1 GPIO 19 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
40 default-state = "on"; 20 default-state = "on";
41 linux,default-trigger 21 linux,default-trigger = "heartbeat";
42 }; 22 };
43 23
44 led-1 { 24 led-1 {
45 function = LED_FUNCTIO 25 function = LED_FUNCTION_STATUS;
46 color = <LED_COLOR_ID_ 26 color = <LED_COLOR_ID_RED>;
47 gpios = <&gpio4 5 GPIO 27 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
48 default-state = "off"; 28 default-state = "off";
49 }; 29 };
50 }; 30 };
51 31
52 pcie0_refclk: clock-pcie0 { 32 pcie0_refclk: clock-pcie0 {
53 compatible = "fixed-clock"; 33 compatible = "fixed-clock";
54 #clock-cells = <0>; 34 #clock-cells = <0>;
55 clock-frequency = <100000000>; 35 clock-frequency = <100000000>;
56 }; 36 };
57 37
58 pps { 38 pps {
59 compatible = "pps-gpio"; 39 compatible = "pps-gpio";
60 pinctrl-names = "default"; 40 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pps>; 41 pinctrl-0 = <&pinctrl_pps>;
62 gpios = <&gpio4 3 GPIO_ACTIVE_ 42 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
63 status = "okay"; 43 status = "okay";
64 }; 44 };
65 45
66 reg_usb1_vbus: regulator-usb1 { 46 reg_usb1_vbus: regulator-usb1 {
67 compatible = "regulator-fixed" 47 compatible = "regulator-fixed";
68 pinctrl-names = "default"; 48 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_reg_usb1 49 pinctrl-0 = <&pinctrl_reg_usb1_en>;
70 regulator-name = "usb1_vbus"; 50 regulator-name = "usb1_vbus";
71 gpio = <&gpio1 12 GPIO_ACTIVE_ 51 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
72 enable-active-high; 52 enable-active-high;
73 regulator-min-microvolt = <500 53 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <500 54 regulator-max-microvolt = <5000000>;
75 }; 55 };
76 56
77 reg_usb2_vbus: regulator-usb2 { 57 reg_usb2_vbus: regulator-usb2 {
78 compatible = "regulator-fixed" 58 compatible = "regulator-fixed";
79 pinctrl-names = "default"; 59 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_reg_usb2 60 pinctrl-0 = <&pinctrl_reg_usb2_en>;
81 regulator-name = "usb2_vbus"; 61 regulator-name = "usb2_vbus";
82 gpio = <&gpio4 12 GPIO_ACTIVE_ 62 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
83 enable-active-high; 63 enable-active-high;
84 regulator-min-microvolt = <500 64 regulator-min-microvolt = <5000000>;
85 regulator-max-microvolt = <500 65 regulator-max-microvolt = <5000000>;
86 }; 66 };
87 67
88 reg_usdhc2_vmmc: regulator-usdhc2-vmmc 68 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
89 compatible = "regulator-fixed" 69 compatible = "regulator-fixed";
90 pinctrl-names = "default"; 70 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_usdhc2_v 71 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
92 regulator-name = "VDD_3V3_SD"; 72 regulator-name = "VDD_3V3_SD";
93 enable-active-high; 73 enable-active-high;
94 gpio = <&gpio2 19 0>; /* SD2_R 74 gpio = <&gpio2 19 0>; /* SD2_RESET */
95 off-on-delay-us = <12000>; 75 off-on-delay-us = <12000>;
96 regulator-max-microvolt = <330 76 regulator-max-microvolt = <3300000>;
97 regulator-min-microvolt = <330 77 regulator-min-microvolt = <3300000>;
98 startup-delay-us = <100>; 78 startup-delay-us = <100>;
99 }; 79 };
100 }; 80 };
101 81
102 /* off-board header */ 82 /* off-board header */
103 &ecspi2 { 83 &ecspi2 {
104 pinctrl-names = "default"; 84 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_spi2>; 85 pinctrl-0 = <&pinctrl_spi2>;
106 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> !! 86 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
107 <&gpio1 10 GPIO_ACTIVE_LOW> <<
108 status = "okay"; 87 status = "okay";
109 <<
110 tpm@1 { <<
111 compatible = "atmel,attpm20p", <<
112 reg = <0x1>; <<
113 spi-max-frequency = <36000000> <<
114 }; <<
115 }; 88 };
116 89
117 &gpio4 { 90 &gpio4 {
118 gpio-line-names = 91 gpio-line-names =
119 "", "", "", "", 92 "", "", "", "",
120 "", "", "", "", 93 "", "", "", "",
121 "dio1", "", "", "dio0", 94 "dio1", "", "", "dio0",
122 "", "", "pci_usb_sel", "", 95 "", "", "pci_usb_sel", "",
123 "", "", "", "", 96 "", "", "", "",
124 "", "", "rs485_en", "rs485_ter 97 "", "", "rs485_en", "rs485_term",
125 "", "", "", "rs485_half", 98 "", "", "", "rs485_half",
126 "pci_wdis#", "", "", ""; 99 "pci_wdis#", "", "", "";
127 }; 100 };
128 101
129 &i2c2 { 102 &i2c2 {
130 clock-frequency = <400000>; 103 clock-frequency = <400000>;
131 pinctrl-names = "default"; 104 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_i2c2>; 105 pinctrl-0 = <&pinctrl_i2c2>;
133 status = "okay"; 106 status = "okay";
134 107
135 accelerometer@19 { 108 accelerometer@19 {
136 compatible = "st,lis2de12"; 109 compatible = "st,lis2de12";
137 reg = <0x19>; 110 reg = <0x19>;
138 pinctrl-names = "default"; 111 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_accel>; 112 pinctrl-0 = <&pinctrl_accel>;
140 st,drdy-int-pin = <1>; 113 st,drdy-int-pin = <1>;
141 interrupt-parent = <&gpio4>; 114 interrupt-parent = <&gpio4>;
142 interrupts = <21 IRQ_TYPE_LEVE 115 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
>> 116 interrupt-names = "INT1";
143 }; 117 };
144 }; 118 };
145 119
146 &pcie_phy { 120 &pcie_phy {
147 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 121 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
148 fsl,clkreq-unsupported; 122 fsl,clkreq-unsupported;
149 clocks = <&pcie0_refclk>; 123 clocks = <&pcie0_refclk>;
150 clock-names = "ref"; 124 clock-names = "ref";
151 status = "okay"; 125 status = "okay";
152 }; 126 };
153 127
154 &pcie { 128 &pcie {
155 pinctrl-names = "default"; 129 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_pcie0>; 130 pinctrl-0 = <&pinctrl_pcie0>;
157 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LO 131 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
158 status = "okay"; 132 status = "okay";
159 <<
160 pcie@0,0 { <<
161 reg = <0x0000 0 0 0 0>; <<
162 device_type = "pci"; <<
163 #address-cells = <3>; <<
164 #size-cells = <2>; <<
165 ranges; <<
166 <<
167 pcie@0,0 { <<
168 reg = <0x0000 0 0 0 0> <<
169 device_type = "pci"; <<
170 #address-cells = <3>; <<
171 #size-cells = <2>; <<
172 ranges; <<
173 <<
174 pcie@3,0 { <<
175 reg = <0x1800 <<
176 device_type = <<
177 #address-cells <<
178 #size-cells = <<
179 ranges; <<
180 <<
181 eth1: ethernet <<
182 reg = <<
183 #addre <<
184 #size- <<
185 ranges <<
186 local- <<
187 }; <<
188 }; <<
189 }; <<
190 }; <<
191 }; 133 };
192 134
193 /* GPS */ 135 /* GPS */
194 &uart1 { 136 &uart1 {
195 pinctrl-names = "default"; 137 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_uart1>; 138 pinctrl-0 = <&pinctrl_uart1>;
197 status = "okay"; 139 status = "okay";
198 }; 140 };
199 141
200 /* off-board header */ 142 /* off-board header */
201 &uart3 { 143 &uart3 {
202 pinctrl-names = "default"; 144 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_uart3>; 145 pinctrl-0 = <&pinctrl_uart3>;
204 status = "okay"; 146 status = "okay";
205 }; 147 };
206 148
207 /* RS232 */ 149 /* RS232 */
208 &uart4 { 150 &uart4 {
209 pinctrl-names = "default"; 151 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_uart4>; 152 pinctrl-0 = <&pinctrl_uart4>;
211 status = "okay"; 153 status = "okay";
212 }; 154 };
213 155
214 /* USB1 - OTG */ 156 /* USB1 - OTG */
215 &usb3_0 { 157 &usb3_0 {
216 pinctrl-names = "default"; 158 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_usb1>; 159 pinctrl-0 = <&pinctrl_usb1>;
218 fsl,over-current-active-low; 160 fsl,over-current-active-low;
219 status = "okay"; 161 status = "okay";
220 }; 162 };
221 163
222 &usb3_phy0 { 164 &usb3_phy0 {
>> 165 vbus-supply = <®_usb1_vbus>;
223 status = "okay"; 166 status = "okay";
224 }; 167 };
225 168
226 &usb_dwc3_0 { 169 &usb_dwc3_0 {
227 /* dual role is implemented but not a 170 /* dual role is implemented but not a full featured OTG */
228 adp-disable; 171 adp-disable;
229 hnp-disable; 172 hnp-disable;
230 srp-disable; 173 srp-disable;
231 dr_mode = "otg"; 174 dr_mode = "otg";
232 usb-role-switch; 175 usb-role-switch;
233 role-switch-default-mode = "peripheral 176 role-switch-default-mode = "peripheral";
234 status = "okay"; 177 status = "okay";
235 178
236 port { !! 179 connector {
237 usb3_dwc: endpoint { !! 180 compatible = "gpio-usb-b-connector", "usb-b-connector";
238 remote-endpoint = <&us !! 181 pinctrl-names = "default";
239 }; !! 182 pinctrl-0 = <&pinctrl_usbcon1>;
>> 183 type = "micro";
>> 184 label = "otg";
>> 185 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
240 }; 186 };
241 }; 187 };
242 188
243 /* USB2 - USB3.0 Hub */ 189 /* USB2 - USB3.0 Hub */
244 &usb3_1 { 190 &usb3_1 {
245 fsl,permanently-attached; 191 fsl,permanently-attached;
246 fsl,disable-port-power-control; 192 fsl,disable-port-power-control;
247 status = "okay"; 193 status = "okay";
248 }; 194 };
249 195
250 &usb3_phy1 { 196 &usb3_phy1 {
251 vbus-supply = <®_usb2_vbus>; 197 vbus-supply = <®_usb2_vbus>;
252 status = "okay"; 198 status = "okay";
253 }; 199 };
254 200
255 &usb_dwc3_1 { 201 &usb_dwc3_1 {
256 dr_mode = "host"; 202 dr_mode = "host";
257 status = "okay"; 203 status = "okay";
258 }; 204 };
259 205
260 /* microSD */ 206 /* microSD */
261 &usdhc2 { 207 &usdhc2 {
262 pinctrl-names = "default", "state_100m 208 pinctrl-names = "default", "state_100mhz", "state_200mhz";
263 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 209 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
264 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 210 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
265 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 211 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
266 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 212 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
267 bus-width = <4>; 213 bus-width = <4>;
268 vmmc-supply = <®_usdhc2_vmmc>; 214 vmmc-supply = <®_usdhc2_vmmc>;
269 status = "okay"; 215 status = "okay";
270 }; 216 };
271 217
272 &iomuxc { 218 &iomuxc {
273 pinctrl-names = "default"; 219 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_hog>; 220 pinctrl-0 = <&pinctrl_hog>;
275 221
276 pinctrl_hog: hoggrp { 222 pinctrl_hog: hoggrp {
277 fsl,pins = < 223 fsl,pins = <
278 MX8MP_IOMUXC_SAI1_RXD6 224 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
279 MX8MP_IOMUXC_SAI1_TXC_ 225 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
280 MX8MP_IOMUXC_SAI1_TXD2 226 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
281 MX8MP_IOMUXC_SAI2_MCLK 227 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
282 MX8MP_IOMUXC_SAI2_RXC_ 228 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
283 MX8MP_IOMUXC_SAI2_RXD0 229 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
284 MX8MP_IOMUXC_SAI3_RXFS 230 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
285 >; 231 >;
286 }; 232 };
287 233
288 pinctrl_accel: accelgrp { 234 pinctrl_accel: accelgrp {
289 fsl,pins = < 235 fsl,pins = <
290 MX8MP_IOMUXC_SAI2_RXFS 236 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
291 >; 237 >;
292 }; 238 };
293 239
294 pinctrl_gpio_leds: gpioledgrp { 240 pinctrl_gpio_leds: gpioledgrp {
295 fsl,pins = < 241 fsl,pins = <
296 MX8MP_IOMUXC_SAI1_RXC_ 242 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
297 MX8MP_IOMUXC_SAI1_RXD3 243 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
298 >; 244 >;
299 }; 245 };
300 246
301 pinctrl_pcie0: pcie0grp { 247 pinctrl_pcie0: pcie0grp {
302 fsl,pins = < 248 fsl,pins = <
303 MX8MP_IOMUXC_SAI3_RXC_ 249 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
304 >; 250 >;
305 }; 251 };
306 252
307 pinctrl_pps: ppsgrp { 253 pinctrl_pps: ppsgrp {
308 fsl,pins = < 254 fsl,pins = <
309 MX8MP_IOMUXC_SAI1_RXD1 255 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
310 >; 256 >;
311 }; 257 };
312 258
313 pinctrl_reg_usb1_en: regusb1grp { 259 pinctrl_reg_usb1_en: regusb1grp {
314 fsl,pins = < 260 fsl,pins = <
315 MX8MP_IOMUXC_GPIO1_IO1 261 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
316 >; 262 >;
317 }; 263 };
318 264
319 pinctrl_usb1: usb1grp { 265 pinctrl_usb1: usb1grp {
320 fsl,pins = < 266 fsl,pins = <
321 MX8MP_IOMUXC_GPIO1_IO1 267 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
322 >; 268 >;
323 }; 269 };
324 270
325 pinctrl_usbcon1: usbcon1grp { 271 pinctrl_usbcon1: usbcon1grp {
326 fsl,pins = < 272 fsl,pins = <
327 MX8MP_IOMUXC_SAI5_RXD0 273 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
328 >; 274 >;
329 }; 275 };
330 276
331 pinctrl_reg_usb2_en: regusb2grp { 277 pinctrl_reg_usb2_en: regusb2grp {
332 fsl,pins = < 278 fsl,pins = <
333 MX8MP_IOMUXC_SAI1_TXD0 279 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
334 >; 280 >;
335 }; 281 };
336 282
337 pinctrl_spi2: spi2grp { 283 pinctrl_spi2: spi2grp {
338 fsl,pins = < 284 fsl,pins = <
339 MX8MP_IOMUXC_ECSPI2_SC 285 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
340 MX8MP_IOMUXC_ECSPI2_MO 286 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
341 MX8MP_IOMUXC_ECSPI2_MI 287 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
342 MX8MP_IOMUXC_ECSPI2_SS 288 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
343 MX8MP_IOMUXC_GPIO1_IO1 <<
344 >; 289 >;
345 }; 290 };
346 291
347 pinctrl_uart1: uart1grp { 292 pinctrl_uart1: uart1grp {
348 fsl,pins = < 293 fsl,pins = <
349 MX8MP_IOMUXC_UART1_RXD 294 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
350 MX8MP_IOMUXC_UART1_TXD 295 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
351 >; 296 >;
352 }; 297 };
353 298
354 pinctrl_uart3: uart3grp { 299 pinctrl_uart3: uart3grp {
355 fsl,pins = < 300 fsl,pins = <
356 MX8MP_IOMUXC_UART3_RXD 301 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
357 MX8MP_IOMUXC_UART3_TXD 302 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
358 >; 303 >;
359 }; 304 };
360 305
361 pinctrl_uart4: uart4grp { 306 pinctrl_uart4: uart4grp {
362 fsl,pins = < 307 fsl,pins = <
363 MX8MP_IOMUXC_UART4_RXD 308 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
364 MX8MP_IOMUXC_UART4_TXD 309 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
365 >; 310 >;
366 }; 311 };
367 312
368 pinctrl_usdhc1: usdhc1grp { 313 pinctrl_usdhc1: usdhc1grp {
369 fsl,pins = < 314 fsl,pins = <
370 MX8MP_IOMUXC_SD1_CLK__ 315 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
371 MX8MP_IOMUXC_SD1_CMD__ 316 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
372 MX8MP_IOMUXC_SD1_DATA0 317 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
373 MX8MP_IOMUXC_SD1_DATA1 318 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
374 MX8MP_IOMUXC_SD1_DATA2 319 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
375 MX8MP_IOMUXC_SD1_DATA3 320 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
376 >; 321 >;
377 }; 322 };
378 323
379 pinctrl_usdhc2: usdhc2grp { 324 pinctrl_usdhc2: usdhc2grp {
380 fsl,pins = < 325 fsl,pins = <
381 MX8MP_IOMUXC_SD2_CLK__ 326 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
382 MX8MP_IOMUXC_SD2_CMD__ 327 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
383 MX8MP_IOMUXC_SD2_DATA0 328 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
384 MX8MP_IOMUXC_SD2_DATA1 329 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
385 MX8MP_IOMUXC_SD2_DATA2 330 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
386 MX8MP_IOMUXC_SD2_DATA3 331 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
387 MX8MP_IOMUXC_GPIO1_IO0 332 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
388 >; 333 >;
389 }; 334 };
390 335
391 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 336 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
392 fsl,pins = < 337 fsl,pins = <
393 MX8MP_IOMUXC_SD2_CLK__ 338 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
394 MX8MP_IOMUXC_SD2_CMD__ 339 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
395 MX8MP_IOMUXC_SD2_DATA0 340 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
396 MX8MP_IOMUXC_SD2_DATA1 341 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
397 MX8MP_IOMUXC_SD2_DATA2 342 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
398 MX8MP_IOMUXC_SD2_DATA3 343 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
399 MX8MP_IOMUXC_GPIO1_IO0 344 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
400 >; 345 >;
401 }; 346 };
402 347
403 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 348 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
404 fsl,pins = < 349 fsl,pins = <
405 MX8MP_IOMUXC_SD2_CLK__ 350 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
406 MX8MP_IOMUXC_SD2_CMD__ 351 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
407 MX8MP_IOMUXC_SD2_DATA0 352 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
408 MX8MP_IOMUXC_SD2_DATA1 353 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
409 MX8MP_IOMUXC_SD2_DATA2 354 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
410 MX8MP_IOMUXC_SD2_DATA3 355 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
411 MX8MP_IOMUXC_GPIO1_IO0 356 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
412 >; 357 >;
413 }; 358 };
414 359
415 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 360 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
416 fsl,pins = < 361 fsl,pins = <
417 MX8MP_IOMUXC_SD2_RESET 362 MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
418 >; 363 >;
419 }; 364 };
420 365
421 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 366 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
422 fsl,pins = < 367 fsl,pins = <
423 MX8MP_IOMUXC_SD2_CD_B_ 368 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
424 >; 369 >;
425 }; 370 };
426 }; 371 };
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