1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2023 Gateworks Corporation 3 * Copyright 2023 Gateworks Corporation
4 */ 4 */
5 5
6 #include <dt-bindings/gpio/gpio.h> 6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/leds/common.h> 7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/phy/phy-imx8-pcie.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h>
9 9
10 / { 10 / {
11 aliases { <<
12 ethernet1 = ð1; <<
13 }; <<
14 <<
15 connector { 11 connector {
16 compatible = "gpio-usb-b-conne 12 compatible = "gpio-usb-b-connector", "usb-b-connector";
17 pinctrl-names = "default"; 13 pinctrl-names = "default";
18 pinctrl-0 = <&pinctrl_usbcon1> 14 pinctrl-0 = <&pinctrl_usbcon1>;
19 type = "micro"; 15 type = "micro";
20 label = "otg"; 16 label = "otg";
21 vbus-supply = <®_usb1_vbus> 17 vbus-supply = <®_usb1_vbus>;
22 id-gpios = <&gpio3 21 GPIO_ACT 18 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
23 19
24 port { 20 port {
25 usb_dr_connector: endp 21 usb_dr_connector: endpoint {
26 remote-endpoin 22 remote-endpoint = <&usb3_dwc>;
27 }; 23 };
28 }; 24 };
29 }; 25 };
30 26
31 led-controller { 27 led-controller {
32 compatible = "gpio-leds"; 28 compatible = "gpio-leds";
33 pinctrl-names = "default"; 29 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_led 30 pinctrl-0 = <&pinctrl_gpio_leds>;
35 31
36 led-0 { 32 led-0 {
37 function = LED_FUNCTIO 33 function = LED_FUNCTION_STATUS;
38 color = <LED_COLOR_ID_ 34 color = <LED_COLOR_ID_GREEN>;
39 gpios = <&gpio4 1 GPIO 35 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
40 default-state = "on"; 36 default-state = "on";
41 linux,default-trigger 37 linux,default-trigger = "heartbeat";
42 }; 38 };
43 39
44 led-1 { 40 led-1 {
45 function = LED_FUNCTIO 41 function = LED_FUNCTION_STATUS;
46 color = <LED_COLOR_ID_ 42 color = <LED_COLOR_ID_RED>;
47 gpios = <&gpio4 5 GPIO 43 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
48 default-state = "off"; 44 default-state = "off";
49 }; 45 };
50 }; 46 };
51 47
52 pcie0_refclk: clock-pcie0 { 48 pcie0_refclk: clock-pcie0 {
53 compatible = "fixed-clock"; 49 compatible = "fixed-clock";
54 #clock-cells = <0>; 50 #clock-cells = <0>;
55 clock-frequency = <100000000>; 51 clock-frequency = <100000000>;
56 }; 52 };
57 53
58 pps { 54 pps {
59 compatible = "pps-gpio"; 55 compatible = "pps-gpio";
60 pinctrl-names = "default"; 56 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_pps>; 57 pinctrl-0 = <&pinctrl_pps>;
62 gpios = <&gpio4 3 GPIO_ACTIVE_ 58 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
63 status = "okay"; 59 status = "okay";
64 }; 60 };
65 61
66 reg_usb1_vbus: regulator-usb1 { 62 reg_usb1_vbus: regulator-usb1 {
67 compatible = "regulator-fixed" 63 compatible = "regulator-fixed";
68 pinctrl-names = "default"; 64 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_reg_usb1 65 pinctrl-0 = <&pinctrl_reg_usb1_en>;
70 regulator-name = "usb1_vbus"; 66 regulator-name = "usb1_vbus";
71 gpio = <&gpio1 12 GPIO_ACTIVE_ 67 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
72 enable-active-high; 68 enable-active-high;
73 regulator-min-microvolt = <500 69 regulator-min-microvolt = <5000000>;
74 regulator-max-microvolt = <500 70 regulator-max-microvolt = <5000000>;
75 }; 71 };
76 72
77 reg_usb2_vbus: regulator-usb2 { 73 reg_usb2_vbus: regulator-usb2 {
78 compatible = "regulator-fixed" 74 compatible = "regulator-fixed";
79 pinctrl-names = "default"; 75 pinctrl-names = "default";
80 pinctrl-0 = <&pinctrl_reg_usb2 76 pinctrl-0 = <&pinctrl_reg_usb2_en>;
81 regulator-name = "usb2_vbus"; 77 regulator-name = "usb2_vbus";
82 gpio = <&gpio4 12 GPIO_ACTIVE_ 78 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>;
83 enable-active-high; 79 enable-active-high;
84 regulator-min-microvolt = <500 80 regulator-min-microvolt = <5000000>;
85 regulator-max-microvolt = <500 81 regulator-max-microvolt = <5000000>;
86 }; 82 };
87 83
88 reg_usdhc2_vmmc: regulator-usdhc2-vmmc 84 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
89 compatible = "regulator-fixed" 85 compatible = "regulator-fixed";
90 pinctrl-names = "default"; 86 pinctrl-names = "default";
91 pinctrl-0 = <&pinctrl_usdhc2_v 87 pinctrl-0 = <&pinctrl_usdhc2_vmmc>;
92 regulator-name = "VDD_3V3_SD"; 88 regulator-name = "VDD_3V3_SD";
93 enable-active-high; 89 enable-active-high;
94 gpio = <&gpio2 19 0>; /* SD2_R 90 gpio = <&gpio2 19 0>; /* SD2_RESET */
95 off-on-delay-us = <12000>; 91 off-on-delay-us = <12000>;
96 regulator-max-microvolt = <330 92 regulator-max-microvolt = <3300000>;
97 regulator-min-microvolt = <330 93 regulator-min-microvolt = <3300000>;
98 startup-delay-us = <100>; 94 startup-delay-us = <100>;
99 }; 95 };
100 }; 96 };
101 97
102 /* off-board header */ 98 /* off-board header */
103 &ecspi2 { 99 &ecspi2 {
104 pinctrl-names = "default"; 100 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_spi2>; 101 pinctrl-0 = <&pinctrl_spi2>;
106 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 102 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>,
107 <&gpio1 10 GPIO_ACTIVE_LOW> 103 <&gpio1 10 GPIO_ACTIVE_LOW>;
108 status = "okay"; 104 status = "okay";
109 105
110 tpm@1 { 106 tpm@1 {
111 compatible = "atmel,attpm20p", 107 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
112 reg = <0x1>; 108 reg = <0x1>;
113 spi-max-frequency = <36000000> 109 spi-max-frequency = <36000000>;
114 }; 110 };
115 }; 111 };
116 112
117 &gpio4 { 113 &gpio4 {
118 gpio-line-names = 114 gpio-line-names =
119 "", "", "", "", 115 "", "", "", "",
120 "", "", "", "", 116 "", "", "", "",
121 "dio1", "", "", "dio0", 117 "dio1", "", "", "dio0",
122 "", "", "pci_usb_sel", "", 118 "", "", "pci_usb_sel", "",
123 "", "", "", "", 119 "", "", "", "",
124 "", "", "rs485_en", "rs485_ter 120 "", "", "rs485_en", "rs485_term",
125 "", "", "", "rs485_half", 121 "", "", "", "rs485_half",
126 "pci_wdis#", "", "", ""; 122 "pci_wdis#", "", "", "";
127 }; 123 };
128 124
129 &i2c2 { 125 &i2c2 {
130 clock-frequency = <400000>; 126 clock-frequency = <400000>;
131 pinctrl-names = "default"; 127 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_i2c2>; 128 pinctrl-0 = <&pinctrl_i2c2>;
133 status = "okay"; 129 status = "okay";
134 130
135 accelerometer@19 { 131 accelerometer@19 {
136 compatible = "st,lis2de12"; 132 compatible = "st,lis2de12";
137 reg = <0x19>; 133 reg = <0x19>;
138 pinctrl-names = "default"; 134 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_accel>; 135 pinctrl-0 = <&pinctrl_accel>;
140 st,drdy-int-pin = <1>; 136 st,drdy-int-pin = <1>;
141 interrupt-parent = <&gpio4>; 137 interrupt-parent = <&gpio4>;
142 interrupts = <21 IRQ_TYPE_LEVE 138 interrupts = <21 IRQ_TYPE_LEVEL_LOW>;
143 }; 139 };
144 }; 140 };
145 141
146 &pcie_phy { 142 &pcie_phy {
147 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 143 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
148 fsl,clkreq-unsupported; 144 fsl,clkreq-unsupported;
149 clocks = <&pcie0_refclk>; 145 clocks = <&pcie0_refclk>;
150 clock-names = "ref"; 146 clock-names = "ref";
151 status = "okay"; 147 status = "okay";
152 }; 148 };
153 149
154 &pcie { 150 &pcie {
155 pinctrl-names = "default"; 151 pinctrl-names = "default";
156 pinctrl-0 = <&pinctrl_pcie0>; 152 pinctrl-0 = <&pinctrl_pcie0>;
157 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LO 153 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
158 status = "okay"; 154 status = "okay";
159 <<
160 pcie@0,0 { <<
161 reg = <0x0000 0 0 0 0>; <<
162 device_type = "pci"; <<
163 #address-cells = <3>; <<
164 #size-cells = <2>; <<
165 ranges; <<
166 <<
167 pcie@0,0 { <<
168 reg = <0x0000 0 0 0 0> <<
169 device_type = "pci"; <<
170 #address-cells = <3>; <<
171 #size-cells = <2>; <<
172 ranges; <<
173 <<
174 pcie@3,0 { <<
175 reg = <0x1800 <<
176 device_type = <<
177 #address-cells <<
178 #size-cells = <<
179 ranges; <<
180 <<
181 eth1: ethernet <<
182 reg = <<
183 #addre <<
184 #size- <<
185 ranges <<
186 local- <<
187 }; <<
188 }; <<
189 }; <<
190 }; <<
191 }; 155 };
192 156
193 /* GPS */ 157 /* GPS */
194 &uart1 { 158 &uart1 {
195 pinctrl-names = "default"; 159 pinctrl-names = "default";
196 pinctrl-0 = <&pinctrl_uart1>; 160 pinctrl-0 = <&pinctrl_uart1>;
197 status = "okay"; 161 status = "okay";
198 }; 162 };
199 163
200 /* off-board header */ 164 /* off-board header */
201 &uart3 { 165 &uart3 {
202 pinctrl-names = "default"; 166 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_uart3>; 167 pinctrl-0 = <&pinctrl_uart3>;
204 status = "okay"; 168 status = "okay";
205 }; 169 };
206 170
207 /* RS232 */ 171 /* RS232 */
208 &uart4 { 172 &uart4 {
209 pinctrl-names = "default"; 173 pinctrl-names = "default";
210 pinctrl-0 = <&pinctrl_uart4>; 174 pinctrl-0 = <&pinctrl_uart4>;
211 status = "okay"; 175 status = "okay";
212 }; 176 };
213 177
214 /* USB1 - OTG */ 178 /* USB1 - OTG */
215 &usb3_0 { 179 &usb3_0 {
216 pinctrl-names = "default"; 180 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_usb1>; 181 pinctrl-0 = <&pinctrl_usb1>;
218 fsl,over-current-active-low; 182 fsl,over-current-active-low;
219 status = "okay"; 183 status = "okay";
220 }; 184 };
221 185
222 &usb3_phy0 { 186 &usb3_phy0 {
223 status = "okay"; 187 status = "okay";
224 }; 188 };
225 189
226 &usb_dwc3_0 { 190 &usb_dwc3_0 {
227 /* dual role is implemented but not a 191 /* dual role is implemented but not a full featured OTG */
228 adp-disable; 192 adp-disable;
229 hnp-disable; 193 hnp-disable;
230 srp-disable; 194 srp-disable;
231 dr_mode = "otg"; 195 dr_mode = "otg";
232 usb-role-switch; 196 usb-role-switch;
233 role-switch-default-mode = "peripheral 197 role-switch-default-mode = "peripheral";
234 status = "okay"; 198 status = "okay";
235 199
236 port { 200 port {
237 usb3_dwc: endpoint { 201 usb3_dwc: endpoint {
238 remote-endpoint = <&us 202 remote-endpoint = <&usb_dr_connector>;
239 }; 203 };
240 }; 204 };
241 }; 205 };
242 206
243 /* USB2 - USB3.0 Hub */ 207 /* USB2 - USB3.0 Hub */
244 &usb3_1 { 208 &usb3_1 {
245 fsl,permanently-attached; 209 fsl,permanently-attached;
246 fsl,disable-port-power-control; 210 fsl,disable-port-power-control;
247 status = "okay"; 211 status = "okay";
248 }; 212 };
249 213
250 &usb3_phy1 { 214 &usb3_phy1 {
251 vbus-supply = <®_usb2_vbus>; 215 vbus-supply = <®_usb2_vbus>;
252 status = "okay"; 216 status = "okay";
253 }; 217 };
254 218
255 &usb_dwc3_1 { 219 &usb_dwc3_1 {
256 dr_mode = "host"; 220 dr_mode = "host";
257 status = "okay"; 221 status = "okay";
258 }; 222 };
259 223
260 /* microSD */ 224 /* microSD */
261 &usdhc2 { 225 &usdhc2 {
262 pinctrl-names = "default", "state_100m 226 pinctrl-names = "default", "state_100mhz", "state_200mhz";
263 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 227 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
264 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 228 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
265 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 229 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
266 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 230 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
267 bus-width = <4>; 231 bus-width = <4>;
268 vmmc-supply = <®_usdhc2_vmmc>; 232 vmmc-supply = <®_usdhc2_vmmc>;
269 status = "okay"; 233 status = "okay";
270 }; 234 };
271 235
272 &iomuxc { 236 &iomuxc {
273 pinctrl-names = "default"; 237 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_hog>; 238 pinctrl-0 = <&pinctrl_hog>;
275 239
276 pinctrl_hog: hoggrp { 240 pinctrl_hog: hoggrp {
277 fsl,pins = < 241 fsl,pins = <
278 MX8MP_IOMUXC_SAI1_RXD6 242 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */
279 MX8MP_IOMUXC_SAI1_TXC_ 243 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */
280 MX8MP_IOMUXC_SAI1_TXD2 244 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */
281 MX8MP_IOMUXC_SAI2_MCLK 245 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */
282 MX8MP_IOMUXC_SAI2_RXC_ 246 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */
283 MX8MP_IOMUXC_SAI2_RXD0 247 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */
284 MX8MP_IOMUXC_SAI3_RXFS 248 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */
285 >; 249 >;
286 }; 250 };
287 251
288 pinctrl_accel: accelgrp { 252 pinctrl_accel: accelgrp {
289 fsl,pins = < 253 fsl,pins = <
290 MX8MP_IOMUXC_SAI2_RXFS 254 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */
291 >; 255 >;
292 }; 256 };
293 257
294 pinctrl_gpio_leds: gpioledgrp { 258 pinctrl_gpio_leds: gpioledgrp {
295 fsl,pins = < 259 fsl,pins = <
296 MX8MP_IOMUXC_SAI1_RXC_ 260 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */
297 MX8MP_IOMUXC_SAI1_RXD3 261 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */
298 >; 262 >;
299 }; 263 };
300 264
301 pinctrl_pcie0: pcie0grp { 265 pinctrl_pcie0: pcie0grp {
302 fsl,pins = < 266 fsl,pins = <
303 MX8MP_IOMUXC_SAI3_RXC_ 267 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106
304 >; 268 >;
305 }; 269 };
306 270
307 pinctrl_pps: ppsgrp { 271 pinctrl_pps: ppsgrp {
308 fsl,pins = < 272 fsl,pins = <
309 MX8MP_IOMUXC_SAI1_RXD1 273 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146
310 >; 274 >;
311 }; 275 };
312 276
313 pinctrl_reg_usb1_en: regusb1grp { 277 pinctrl_reg_usb1_en: regusb1grp {
314 fsl,pins = < 278 fsl,pins = <
315 MX8MP_IOMUXC_GPIO1_IO1 279 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */
316 >; 280 >;
317 }; 281 };
318 282
319 pinctrl_usb1: usb1grp { 283 pinctrl_usb1: usb1grp {
320 fsl,pins = < 284 fsl,pins = <
321 MX8MP_IOMUXC_GPIO1_IO1 285 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */
322 >; 286 >;
323 }; 287 };
324 288
325 pinctrl_usbcon1: usbcon1grp { 289 pinctrl_usbcon1: usbcon1grp {
326 fsl,pins = < 290 fsl,pins = <
327 MX8MP_IOMUXC_SAI5_RXD0 291 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */
328 >; 292 >;
329 }; 293 };
330 294
331 pinctrl_reg_usb2_en: regusb2grp { 295 pinctrl_reg_usb2_en: regusb2grp {
332 fsl,pins = < 296 fsl,pins = <
333 MX8MP_IOMUXC_SAI1_TXD0 297 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */
334 >; 298 >;
335 }; 299 };
336 300
337 pinctrl_spi2: spi2grp { 301 pinctrl_spi2: spi2grp {
338 fsl,pins = < 302 fsl,pins = <
339 MX8MP_IOMUXC_ECSPI2_SC 303 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140
340 MX8MP_IOMUXC_ECSPI2_MO 304 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140
341 MX8MP_IOMUXC_ECSPI2_MI 305 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140
342 MX8MP_IOMUXC_ECSPI2_SS 306 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
343 MX8MP_IOMUXC_GPIO1_IO1 307 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
344 >; 308 >;
345 }; 309 };
346 310
347 pinctrl_uart1: uart1grp { 311 pinctrl_uart1: uart1grp {
348 fsl,pins = < 312 fsl,pins = <
349 MX8MP_IOMUXC_UART1_RXD 313 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
350 MX8MP_IOMUXC_UART1_TXD 314 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
351 >; 315 >;
352 }; 316 };
353 317
354 pinctrl_uart3: uart3grp { 318 pinctrl_uart3: uart3grp {
355 fsl,pins = < 319 fsl,pins = <
356 MX8MP_IOMUXC_UART3_RXD 320 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
357 MX8MP_IOMUXC_UART3_TXD 321 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
358 >; 322 >;
359 }; 323 };
360 324
361 pinctrl_uart4: uart4grp { 325 pinctrl_uart4: uart4grp {
362 fsl,pins = < 326 fsl,pins = <
363 MX8MP_IOMUXC_UART4_RXD 327 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
364 MX8MP_IOMUXC_UART4_TXD 328 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
365 >; 329 >;
366 }; 330 };
367 331
368 pinctrl_usdhc1: usdhc1grp { 332 pinctrl_usdhc1: usdhc1grp {
369 fsl,pins = < 333 fsl,pins = <
370 MX8MP_IOMUXC_SD1_CLK__ 334 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
371 MX8MP_IOMUXC_SD1_CMD__ 335 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
372 MX8MP_IOMUXC_SD1_DATA0 336 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
373 MX8MP_IOMUXC_SD1_DATA1 337 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
374 MX8MP_IOMUXC_SD1_DATA2 338 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
375 MX8MP_IOMUXC_SD1_DATA3 339 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
376 >; 340 >;
377 }; 341 };
378 342
379 pinctrl_usdhc2: usdhc2grp { 343 pinctrl_usdhc2: usdhc2grp {
380 fsl,pins = < 344 fsl,pins = <
381 MX8MP_IOMUXC_SD2_CLK__ 345 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
382 MX8MP_IOMUXC_SD2_CMD__ 346 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0
383 MX8MP_IOMUXC_SD2_DATA0 347 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0
384 MX8MP_IOMUXC_SD2_DATA1 348 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
385 MX8MP_IOMUXC_SD2_DATA2 349 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
386 MX8MP_IOMUXC_SD2_DATA3 350 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
387 MX8MP_IOMUXC_GPIO1_IO0 351 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
388 >; 352 >;
389 }; 353 };
390 354
391 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 355 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
392 fsl,pins = < 356 fsl,pins = <
393 MX8MP_IOMUXC_SD2_CLK__ 357 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194
394 MX8MP_IOMUXC_SD2_CMD__ 358 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4
395 MX8MP_IOMUXC_SD2_DATA0 359 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4
396 MX8MP_IOMUXC_SD2_DATA1 360 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
397 MX8MP_IOMUXC_SD2_DATA2 361 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
398 MX8MP_IOMUXC_SD2_DATA3 362 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
399 MX8MP_IOMUXC_GPIO1_IO0 363 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
400 >; 364 >;
401 }; 365 };
402 366
403 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 367 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
404 fsl,pins = < 368 fsl,pins = <
405 MX8MP_IOMUXC_SD2_CLK__ 369 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196
406 MX8MP_IOMUXC_SD2_CMD__ 370 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6
407 MX8MP_IOMUXC_SD2_DATA0 371 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6
408 MX8MP_IOMUXC_SD2_DATA1 372 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
409 MX8MP_IOMUXC_SD2_DATA2 373 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
410 MX8MP_IOMUXC_SD2_DATA3 374 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
411 MX8MP_IOMUXC_GPIO1_IO0 375 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1
412 >; 376 >;
413 }; 377 };
414 378
415 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 379 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp {
416 fsl,pins = < 380 fsl,pins = <
417 MX8MP_IOMUXC_SD2_RESET 381 MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0
418 >; 382 >;
419 }; 383 };
420 384
421 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 385 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
422 fsl,pins = < 386 fsl,pins = <
423 MX8MP_IOMUXC_SD2_CD_B_ 387 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4
424 >; 388 >;
425 }; 389 };
426 }; 390 };
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