1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h> <<
12 #include <dt-bindings/net/ti-dp83867.h> <<
13 11
14 #include "imx8mp.dtsi" 12 #include "imx8mp.dtsi"
15 13
16 / { 14 / {
17 model = "Gateworks Venice GW74xx i.MX8 15 model = "Gateworks Venice GW74xx i.MX8MP board";
18 compatible = "gateworks,imx8mp-gw74xx" 16 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
19 17
20 aliases { 18 aliases {
21 ethernet0 = &eqos; 19 ethernet0 = &eqos;
22 ethernet1 = &fec; 20 ethernet1 = &fec;
23 ethernet2 = &lan1; 21 ethernet2 = &lan1;
24 ethernet3 = &lan2; 22 ethernet3 = &lan2;
25 ethernet4 = &lan3; 23 ethernet4 = &lan3;
26 ethernet5 = &lan4; 24 ethernet5 = &lan4;
27 ethernet6 = &lan5; 25 ethernet6 = &lan5;
28 }; 26 };
29 27
30 chosen { 28 chosen {
31 stdout-path = &uart2; 29 stdout-path = &uart2;
32 }; 30 };
33 31
34 memory@40000000 { 32 memory@40000000 {
35 device_type = "memory"; 33 device_type = "memory";
36 reg = <0x0 0x40000000 0 0x8000 34 reg = <0x0 0x40000000 0 0x80000000>;
37 }; 35 };
38 36
39 connector { <<
40 pinctrl-names = "default"; <<
41 pinctrl-0 = <&pinctrl_usbcon1> <<
42 compatible = "gpio-usb-b-conne <<
43 type = "micro"; <<
44 label = "Type-C"; <<
45 id-gpios = <&gpio1 10 GPIO_ACT <<
46 <<
47 port { <<
48 usb_dr_connector: endp <<
49 remote-endpoin <<
50 }; <<
51 }; <<
52 }; <<
53 <<
54 gpio-keys { 37 gpio-keys {
55 compatible = "gpio-keys"; 38 compatible = "gpio-keys";
56 39
57 key-0 { 40 key-0 {
58 label = "user_pb"; 41 label = "user_pb";
59 gpios = <&gpio 2 GPIO_ 42 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
60 linux,code = <BTN_0>; 43 linux,code = <BTN_0>;
61 }; 44 };
62 45
63 key-1 { 46 key-1 {
64 label = "user_pb1x"; 47 label = "user_pb1x";
65 linux,code = <BTN_1>; 48 linux,code = <BTN_1>;
66 interrupt-parent = <&g 49 interrupt-parent = <&gsc>;
67 interrupts = <0>; 50 interrupts = <0>;
68 }; 51 };
69 52
70 key-2 { 53 key-2 {
71 label = "key_erased"; 54 label = "key_erased";
72 linux,code = <BTN_2>; 55 linux,code = <BTN_2>;
73 interrupt-parent = <&g 56 interrupt-parent = <&gsc>;
74 interrupts = <1>; 57 interrupts = <1>;
75 }; 58 };
76 59
77 key-3 { 60 key-3 {
78 label = "eeprom_wp"; 61 label = "eeprom_wp";
79 linux,code = <BTN_3>; 62 linux,code = <BTN_3>;
80 interrupt-parent = <&g 63 interrupt-parent = <&gsc>;
81 interrupts = <2>; 64 interrupts = <2>;
82 }; 65 };
83 66
84 key-4 { 67 key-4 {
85 label = "tamper"; 68 label = "tamper";
86 linux,code = <BTN_4>; 69 linux,code = <BTN_4>;
87 interrupt-parent = <&g 70 interrupt-parent = <&gsc>;
88 interrupts = <5>; 71 interrupts = <5>;
89 }; 72 };
90 73
91 key-5 { 74 key-5 {
92 label = "switch_hold"; 75 label = "switch_hold";
93 linux,code = <BTN_5>; 76 linux,code = <BTN_5>;
94 interrupt-parent = <&g 77 interrupt-parent = <&gsc>;
95 interrupts = <7>; 78 interrupts = <7>;
96 }; 79 };
97 }; 80 };
98 81
99 led-controller { 82 led-controller {
100 compatible = "gpio-leds"; 83 compatible = "gpio-leds";
101 pinctrl-names = "default"; 84 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_gpio_led 85 pinctrl-0 = <&pinctrl_gpio_leds>;
103 86
104 led-0 { 87 led-0 {
105 function = LED_FUNCTIO 88 function = LED_FUNCTION_HEARTBEAT;
106 color = <LED_COLOR_ID_ 89 color = <LED_COLOR_ID_GREEN>;
107 gpios = <&gpio2 15 GPI 90 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
108 default-state = "on"; 91 default-state = "on";
109 linux,default-trigger 92 linux,default-trigger = "heartbeat";
110 }; 93 };
111 94
112 led-1 { 95 led-1 {
113 function = LED_FUNCTIO 96 function = LED_FUNCTION_STATUS;
114 color = <LED_COLOR_ID_ 97 color = <LED_COLOR_ID_RED>;
115 gpios = <&gpio2 16 GPI 98 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
116 default-state = "off"; 99 default-state = "off";
117 }; 100 };
118 }; 101 };
119 102
120 pcie0_refclk: pcie0-refclk { <<
121 compatible = "fixed-clock"; <<
122 #clock-cells = <0>; <<
123 clock-frequency = <100000000>; <<
124 }; <<
125 <<
126 pps { 103 pps {
127 compatible = "pps-gpio"; 104 compatible = "pps-gpio";
128 pinctrl-names = "default"; 105 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_pps>; 106 pinctrl-0 = <&pinctrl_pps>;
130 gpios = <&gpio1 12 GPIO_ACTIVE 107 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
131 }; 108 };
132 109
133 reg_usb2_vbus: regulator-usb2 { 110 reg_usb2_vbus: regulator-usb2 {
134 pinctrl-names = "default"; 111 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_reg_usb2 112 pinctrl-0 = <&pinctrl_reg_usb2>;
136 compatible = "regulator-fixed" 113 compatible = "regulator-fixed";
137 regulator-name = "usb_usb2_vbu 114 regulator-name = "usb_usb2_vbus";
138 gpio = <&gpio1 6 GPIO_ACTIVE_H 115 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
139 enable-active-high; 116 enable-active-high;
140 regulator-min-microvolt = <500 117 regulator-min-microvolt = <5000000>;
141 regulator-max-microvolt = <500 118 regulator-max-microvolt = <5000000>;
142 }; 119 };
143 120
144 reg_can1_stby: regulator-can1-stby { <<
145 compatible = "regulator-fixed" <<
146 pinctrl-names = "default"; <<
147 pinctrl-0 = <&pinctrl_reg_can1 <<
148 regulator-name = "can1_stby"; <<
149 gpio = <&gpio3 19 GPIO_ACTIVE_ <<
150 regulator-min-microvolt = <330 <<
151 regulator-max-microvolt = <330 <<
152 }; <<
153 <<
154 reg_can2_stby: regulator-can2-stby { 121 reg_can2_stby: regulator-can2-stby {
155 compatible = "regulator-fixed" 122 compatible = "regulator-fixed";
156 pinctrl-names = "default"; 123 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_reg_can2 !! 124 pinctrl-0 = <&pinctrl_reg_can>;
158 regulator-name = "can2_stby"; 125 regulator-name = "can2_stby";
159 gpio = <&gpio5 5 GPIO_ACTIVE_L !! 126 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
160 regulator-min-microvolt = <330 127 regulator-min-microvolt = <3300000>;
161 regulator-max-microvolt = <330 128 regulator-max-microvolt = <3300000>;
162 }; 129 };
163 130
164 reg_wifi_en: regulator-wifi-en { 131 reg_wifi_en: regulator-wifi-en {
165 pinctrl-names = "default"; 132 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_reg_wifi 133 pinctrl-0 = <&pinctrl_reg_wifi>;
167 compatible = "regulator-fixed" 134 compatible = "regulator-fixed";
168 regulator-name = "wl"; 135 regulator-name = "wl";
169 gpio = <&gpio3 9 GPIO_ACTIVE_H 136 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
170 startup-delay-us = <70000>; !! 137 startup-delay-us = <100>;
171 enable-active-high; 138 enable-active-high;
172 regulator-min-microvolt = <330 !! 139 regulator-min-microvolt = <1800000>;
173 regulator-max-microvolt = <330 !! 140 regulator-max-microvolt = <1800000>;
174 }; <<
175 }; <<
176 <<
177 &A53_0 { <<
178 cpu-supply = <®_arm>; <<
179 }; <<
180 <<
181 &A53_1 { <<
182 cpu-supply = <®_arm>; <<
183 }; <<
184 <<
185 &A53_2 { <<
186 cpu-supply = <®_arm>; <<
187 }; <<
188 <<
189 &A53_3 { <<
190 cpu-supply = <®_arm>; <<
191 }; <<
192 <<
193 &ecspi1 { <<
194 pinctrl-names = "default"; <<
195 pinctrl-0 = <&pinctrl_spi1>; <<
196 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; <<
197 status = "okay"; <<
198 <<
199 tpm@0 { <<
200 compatible = "atmel,attpm20p", <<
201 reg = <0x0>; <<
202 spi-max-frequency = <36000000> <<
203 }; 141 };
204 }; 142 };
205 143
206 /* off-board header */ 144 /* off-board header */
207 &ecspi2 { 145 &ecspi2 {
208 pinctrl-names = "default"; 146 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_spi2>; 147 pinctrl-0 = <&pinctrl_spi2>;
210 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 148 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
211 status = "okay"; 149 status = "okay";
212 }; 150 };
213 151
214 &eqos { 152 &eqos {
215 pinctrl-names = "default"; 153 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_eqos>; 154 pinctrl-0 = <&pinctrl_eqos>;
217 phy-mode = "rgmii-id"; 155 phy-mode = "rgmii-id";
218 phy-handle = <ðphy0>; 156 phy-handle = <ðphy0>;
219 status = "okay"; 157 status = "okay";
220 158
221 mdio { 159 mdio {
222 compatible = "snps,dwmac-mdio" 160 compatible = "snps,dwmac-mdio";
223 #address-cells = <1>; 161 #address-cells = <1>;
224 #size-cells = <0>; 162 #size-cells = <0>;
225 163
226 ethphy0: ethernet-phy@0 { 164 ethphy0: ethernet-phy@0 {
227 compatible = "ethernet 165 compatible = "ethernet-phy-ieee802.3-c22";
228 reg = <0x0>; 166 reg = <0x0>;
229 ti,rx-internal-delay = <<
230 ti,tx-internal-delay = <<
231 tx-fifo-depth = <DP838 <<
232 rx-fifo-depth = <DP838 <<
233 <<
234 leds { <<
235 #address-cells <<
236 #size-cells = <<
237 <<
238 led@1 { <<
239 reg = <<
240 color <<
241 functi <<
242 defaul <<
243 }; <<
244 <<
245 led@2 { <<
246 reg = <<
247 color <<
248 functi <<
249 defaul <<
250 }; <<
251 }; <<
252 }; 167 };
253 }; 168 };
254 }; 169 };
255 170
256 &fec { 171 &fec {
257 pinctrl-names = "default"; 172 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_fec>; 173 pinctrl-0 = <&pinctrl_fec>;
259 phy-mode = "rgmii-id"; 174 phy-mode = "rgmii-id";
260 local-mac-address = [00 00 00 00 00 00 175 local-mac-address = [00 00 00 00 00 00];
261 status = "okay"; 176 status = "okay";
262 177
263 fixed-link { 178 fixed-link {
264 speed = <1000>; 179 speed = <1000>;
265 full-duplex; 180 full-duplex;
266 }; 181 };
267 }; 182 };
268 183
269 &flexcan1 { <<
270 pinctrl-names = "default"; <<
271 pinctrl-0 = <&pinctrl_flexcan1>; <<
272 xceiver-supply = <®_can1_stby>; <<
273 status = "okay"; <<
274 }; <<
275 <<
276 &flexcan2 { 184 &flexcan2 {
277 pinctrl-names = "default"; 185 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_flexcan2>; 186 pinctrl-0 = <&pinctrl_flexcan2>;
279 xceiver-supply = <®_can2_stby>; 187 xceiver-supply = <®_can2_stby>;
280 status = "okay"; 188 status = "okay";
281 }; 189 };
282 190
283 &gpio1 { 191 &gpio1 {
284 gpio-line-names = 192 gpio-line-names =
285 "", "", "", "", "", "", "", "" 193 "", "", "", "", "", "", "", "",
286 "", "dio0", "", "dio1", "", "" !! 194 "", "", "dio0", "", "dio1", "", "", "",
287 "", "", "", "", "", "", "", "" 195 "", "", "", "", "", "", "", "",
288 "", "", "", "", "", "", "", "" 196 "", "", "", "", "", "", "", "";
289 }; 197 };
290 198
291 &gpio2 { 199 &gpio2 {
292 gpio-line-names = 200 gpio-line-names =
293 "", "", "", "", "", "", "m2_pi !! 201 "", "", "", "", "", "", "", "",
294 "", "", "", "", "", "pcie1_wdi !! 202 "", "", "", "", "", "", "", "",
295 "", "", "pcie2_wdis#", "", "", !! 203 "pcie3_wdis#", "", "", "pcie1_wdis@", "pcie2_wdis#", "", "", "",
296 "", "", "", "", "", "", "", "" 204 "", "", "", "", "", "", "", "";
297 }; 205 };
298 206
299 &gpio3 { 207 &gpio3 {
300 gpio-line-names = 208 gpio-line-names =
301 "", "", "", "", "", "", "m2_rs !! 209 "m2_gdis#", "", "", "", "", "", "", "m2_rst#",
302 "", "", "", "", "", "", "", "" <<
303 "", "", "", "", "", "", "", "" 210 "", "", "", "", "", "", "", "",
>> 211 "m2_off#", "", "", "", "", "", "", "",
304 "", "", "", "", "", "", "", "" 212 "", "", "", "", "", "", "", "";
305 }; 213 };
306 214
307 &gpio4 { 215 &gpio4 {
308 gpio-line-names = 216 gpio-line-names =
309 "", "", "m2_off#", "", "", "", <<
310 "", "", "", "", "", "", "", "" 217 "", "", "", "", "", "", "", "",
311 "", "", "m2_wdis#", "", "", "" !! 218 "", "", "", "", "", "", "", "",
312 "", "", "", "", "", "", "", "r !! 219 "", "", "", "", "m2_wdis#", "", "", "",
>> 220 "", "", "", "", "", "", "", "uart_rs485";
313 }; 221 };
314 222
315 &gpio5 { 223 &gpio5 {
316 gpio-line-names = 224 gpio-line-names =
317 "rs485_hd", "rs485_term", "", !! 225 "uart_half", "uart_term", "", "", "", "", "", "",
318 "", "", "", "", "", "", "", "" 226 "", "", "", "", "", "", "", "",
319 "", "", "", "", "", "", "", "" 227 "", "", "", "", "", "", "", "",
320 "", "", "", "", "", "", "", "" 228 "", "", "", "", "", "", "", "";
321 }; 229 };
322 230
323 &i2c1 { 231 &i2c1 {
324 clock-frequency = <100000>; 232 clock-frequency = <100000>;
325 pinctrl-names = "default", "gpio"; !! 233 pinctrl-names = "default";
326 pinctrl-0 = <&pinctrl_i2c1>; 234 pinctrl-0 = <&pinctrl_i2c1>;
327 pinctrl-1 = <&pinctrl_i2c1_gpio>; <<
328 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI <<
329 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI <<
330 status = "okay"; 235 status = "okay";
331 236
332 gsc: gsc@20 { 237 gsc: gsc@20 {
333 compatible = "gw,gsc"; 238 compatible = "gw,gsc";
334 reg = <0x20>; 239 reg = <0x20>;
335 pinctrl-0 = <&pinctrl_gsc>; 240 pinctrl-0 = <&pinctrl_gsc>;
336 interrupt-parent = <&gpio4>; 241 interrupt-parent = <&gpio4>;
337 interrupts = <20 IRQ_TYPE_EDGE 242 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
338 interrupt-controller; 243 interrupt-controller;
339 #interrupt-cells = <1>; 244 #interrupt-cells = <1>;
340 #address-cells = <1>; <<
341 #size-cells = <0>; <<
342 245
343 adc { 246 adc {
344 compatible = "gw,gsc-a 247 compatible = "gw,gsc-adc";
345 #address-cells = <1>; 248 #address-cells = <1>;
346 #size-cells = <0>; 249 #size-cells = <0>;
347 250
348 channel@6 { 251 channel@6 {
349 gw,mode = <0>; 252 gw,mode = <0>;
350 reg = <0x06>; 253 reg = <0x06>;
351 label = "temp" 254 label = "temp";
352 }; 255 };
353 256
354 channel@8 { 257 channel@8 {
355 gw,mode = <3>; !! 258 gw,mode = <1>;
356 reg = <0x08>; 259 reg = <0x08>;
357 label = "vdd_b 260 label = "vdd_bat";
358 }; 261 };
359 262
360 channel@16 { <<
361 gw,mode = <4>; <<
362 reg = <0x16>; <<
363 label = "fan_t <<
364 }; <<
365 <<
366 channel@82 { 263 channel@82 {
367 gw,mode = <2>; 264 gw,mode = <2>;
368 reg = <0x82>; 265 reg = <0x82>;
369 label = "vdd_a 266 label = "vdd_adc1";
370 gw,voltage-div 267 gw,voltage-divider-ohms = <10000 10000>;
371 }; 268 };
372 269
373 channel@84 { 270 channel@84 {
374 gw,mode = <2>; 271 gw,mode = <2>;
375 reg = <0x84>; 272 reg = <0x84>;
376 label = "vdd_a 273 label = "vdd_adc2";
377 gw,voltage-div 274 gw,voltage-divider-ohms = <10000 10000>;
378 }; 275 };
379 276
380 channel@86 { 277 channel@86 {
381 gw,mode = <2>; 278 gw,mode = <2>;
382 reg = <0x86>; 279 reg = <0x86>;
383 label = "vdd_v 280 label = "vdd_vin";
384 gw,voltage-div 281 gw,voltage-divider-ohms = <22100 1000>;
385 }; 282 };
386 283
387 channel@88 { 284 channel@88 {
388 gw,mode = <2>; 285 gw,mode = <2>;
389 reg = <0x88>; 286 reg = <0x88>;
390 label = "vdd_3 287 label = "vdd_3p3";
391 gw,voltage-div 288 gw,voltage-divider-ohms = <10000 10000>;
392 }; 289 };
393 290
394 channel@8c { 291 channel@8c {
395 gw,mode = <2>; 292 gw,mode = <2>;
396 reg = <0x8c>; 293 reg = <0x8c>;
397 label = "vdd_2 294 label = "vdd_2p5";
398 gw,voltage-div 295 gw,voltage-divider-ohms = <10000 10000>;
399 }; 296 };
400 297
401 channel@90 { 298 channel@90 {
402 gw,mode = <2>; 299 gw,mode = <2>;
403 reg = <0x90>; 300 reg = <0x90>;
404 label = "vdd_s 301 label = "vdd_soc";
405 }; 302 };
406 303
407 channel@92 { 304 channel@92 {
408 gw,mode = <2>; 305 gw,mode = <2>;
409 reg = <0x92>; 306 reg = <0x92>;
410 label = "vdd_a 307 label = "vdd_arm";
411 }; 308 };
412 309
413 channel@98 { 310 channel@98 {
414 gw,mode = <2>; 311 gw,mode = <2>;
415 reg = <0x98>; 312 reg = <0x98>;
416 label = "vdd_1 313 label = "vdd_1p8";
417 }; 314 };
418 315
419 channel@9a { 316 channel@9a {
420 gw,mode = <2>; 317 gw,mode = <2>;
421 reg = <0x9a>; 318 reg = <0x9a>;
422 label = "vdd_1 319 label = "vdd_1p2";
423 }; 320 };
424 321
425 channel@9c { 322 channel@9c {
426 gw,mode = <2>; 323 gw,mode = <2>;
427 reg = <0x9c>; 324 reg = <0x9c>;
428 label = "vdd_d 325 label = "vdd_dram";
429 }; 326 };
430 327
431 channel@9e { <<
432 gw,mode = <2>; <<
433 reg = <0x9e>; <<
434 label = "vdd_1 <<
435 }; <<
436 <<
437 channel@a2 { 328 channel@a2 {
438 gw,mode = <2>; 329 gw,mode = <2>;
439 reg = <0xa2>; 330 reg = <0xa2>;
440 label = "vdd_g 331 label = "vdd_gsc";
441 gw,voltage-div 332 gw,voltage-divider-ohms = <10000 10000>;
442 }; 333 };
443 }; 334 };
444 <<
445 fan-controller@a { <<
446 compatible = "gw,gsc-f <<
447 reg = <0x0a>; <<
448 }; <<
449 }; 335 };
450 336
451 gpio: gpio@23 { 337 gpio: gpio@23 {
452 compatible = "nxp,pca9555"; 338 compatible = "nxp,pca9555";
453 reg = <0x23>; 339 reg = <0x23>;
454 gpio-controller; 340 gpio-controller;
455 #gpio-cells = <2>; 341 #gpio-cells = <2>;
456 interrupt-parent = <&gsc>; 342 interrupt-parent = <&gsc>;
457 interrupts = <4>; 343 interrupts = <4>;
458 }; 344 };
459 345
>> 346 pmic@25 {
>> 347 compatible = "nxp,pca9450c";
>> 348 reg = <0x25>;
>> 349 pinctrl-names = "default";
>> 350 pinctrl-0 = <&pinctrl_pmic>;
>> 351 interrupt-parent = <&gpio3>;
>> 352 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
>> 353
>> 354 regulators {
>> 355 BUCK1 {
>> 356 regulator-name = "BUCK1";
>> 357 regulator-min-microvolt = <720000>;
>> 358 regulator-max-microvolt = <1000000>;
>> 359 regulator-boot-on;
>> 360 regulator-always-on;
>> 361 regulator-ramp-delay = <3125>;
>> 362 };
>> 363
>> 364 BUCK2 {
>> 365 regulator-name = "BUCK2";
>> 366 regulator-min-microvolt = <720000>;
>> 367 regulator-max-microvolt = <1025000>;
>> 368 regulator-boot-on;
>> 369 regulator-always-on;
>> 370 regulator-ramp-delay = <3125>;
>> 371 nxp,dvs-run-voltage = <950000>;
>> 372 nxp,dvs-standby-voltage = <850000>;
>> 373 };
>> 374
>> 375 BUCK4 {
>> 376 regulator-name = "BUCK4";
>> 377 regulator-min-microvolt = <3000000>;
>> 378 regulator-max-microvolt = <3600000>;
>> 379 regulator-boot-on;
>> 380 regulator-always-on;
>> 381 };
>> 382
>> 383 BUCK5 {
>> 384 regulator-name = "BUCK5";
>> 385 regulator-min-microvolt = <1650000>;
>> 386 regulator-max-microvolt = <1950000>;
>> 387 regulator-boot-on;
>> 388 regulator-always-on;
>> 389 };
>> 390
>> 391 BUCK6 {
>> 392 regulator-name = "BUCK6";
>> 393 regulator-min-microvolt = <1045000>;
>> 394 regulator-max-microvolt = <1155000>;
>> 395 regulator-boot-on;
>> 396 regulator-always-on;
>> 397 };
>> 398
>> 399 LDO1 {
>> 400 regulator-name = "LDO1";
>> 401 regulator-min-microvolt = <1650000>;
>> 402 regulator-max-microvolt = <1950000>;
>> 403 regulator-boot-on;
>> 404 regulator-always-on;
>> 405 };
>> 406
>> 407 LDO3 {
>> 408 regulator-name = "LDO3";
>> 409 regulator-min-microvolt = <1710000>;
>> 410 regulator-max-microvolt = <1890000>;
>> 411 regulator-boot-on;
>> 412 regulator-always-on;
>> 413 };
>> 414
>> 415 LDO5 {
>> 416 regulator-name = "LDO5";
>> 417 regulator-min-microvolt = <1800000>;
>> 418 regulator-max-microvolt = <3300000>;
>> 419 regulator-boot-on;
>> 420 regulator-always-on;
>> 421 };
>> 422 };
>> 423 };
>> 424
460 eeprom@50 { 425 eeprom@50 {
461 compatible = "atmel,24c02"; 426 compatible = "atmel,24c02";
462 reg = <0x50>; 427 reg = <0x50>;
463 pagesize = <16>; 428 pagesize = <16>;
464 }; 429 };
465 430
466 eeprom@51 { 431 eeprom@51 {
467 compatible = "atmel,24c02"; 432 compatible = "atmel,24c02";
468 reg = <0x51>; 433 reg = <0x51>;
469 pagesize = <16>; 434 pagesize = <16>;
470 }; 435 };
471 436
472 eeprom@52 { 437 eeprom@52 {
473 compatible = "atmel,24c02"; 438 compatible = "atmel,24c02";
474 reg = <0x52>; 439 reg = <0x52>;
475 pagesize = <16>; 440 pagesize = <16>;
476 }; 441 };
477 442
478 eeprom@53 { 443 eeprom@53 {
479 compatible = "atmel,24c02"; 444 compatible = "atmel,24c02";
480 reg = <0x53>; 445 reg = <0x53>;
481 pagesize = <16>; 446 pagesize = <16>;
482 }; 447 };
483 448
484 rtc@68 { 449 rtc@68 {
485 compatible = "dallas,ds1672"; 450 compatible = "dallas,ds1672";
486 reg = <0x68>; 451 reg = <0x68>;
487 }; 452 };
488 }; 453 };
489 454
490 &i2c2 { 455 &i2c2 {
491 clock-frequency = <400000>; 456 clock-frequency = <400000>;
492 pinctrl-names = "default", "gpio"; !! 457 pinctrl-names = "default";
493 pinctrl-0 = <&pinctrl_i2c2>; 458 pinctrl-0 = <&pinctrl_i2c2>;
494 pinctrl-1 = <&pinctrl_i2c2_gpio>; <<
495 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI <<
496 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI <<
497 status = "okay"; 459 status = "okay";
498 460
499 accelerometer@19 { 461 accelerometer@19 {
500 compatible = "st,lis2de12"; 462 compatible = "st,lis2de12";
501 pinctrl-names = "default"; 463 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_accel>; 464 pinctrl-0 = <&pinctrl_accel>;
503 reg = <0x19>; 465 reg = <0x19>;
504 st,drdy-int-pin = <1>; 466 st,drdy-int-pin = <1>;
505 interrupt-parent = <&gpio1>; 467 interrupt-parent = <&gpio1>;
506 interrupts = <7 IRQ_TYPE_LEVEL 468 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
>> 469 interrupt-names = "INT1";
507 }; 470 };
508 471
509 switch: switch@5f { 472 switch: switch@5f {
510 compatible = "microchip,ksz989 473 compatible = "microchip,ksz9897";
511 reg = <0x5f>; 474 reg = <0x5f>;
512 pinctrl-0 = <&pinctrl_ksz>; 475 pinctrl-0 = <&pinctrl_ksz>;
513 interrupt-parent = <&gpio4>; 476 interrupt-parent = <&gpio4>;
514 interrupts = <29 IRQ_TYPE_EDGE 477 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
515 478
516 ports { 479 ports {
517 #address-cells = <1>; 480 #address-cells = <1>;
518 #size-cells = <0>; 481 #size-cells = <0>;
519 482
520 lan1: port@0 { 483 lan1: port@0 {
521 reg = <0>; 484 reg = <0>;
522 label = "lan1" 485 label = "lan1";
523 phy-mode = "in 486 phy-mode = "internal";
524 local-mac-addr 487 local-mac-address = [00 00 00 00 00 00];
525 }; 488 };
526 489
527 lan2: port@1 { 490 lan2: port@1 {
528 reg = <1>; 491 reg = <1>;
529 label = "lan2" 492 label = "lan2";
530 phy-mode = "in 493 phy-mode = "internal";
531 local-mac-addr 494 local-mac-address = [00 00 00 00 00 00];
532 }; 495 };
533 496
534 lan3: port@2 { 497 lan3: port@2 {
535 reg = <2>; 498 reg = <2>;
536 label = "lan3" 499 label = "lan3";
537 phy-mode = "in 500 phy-mode = "internal";
538 local-mac-addr 501 local-mac-address = [00 00 00 00 00 00];
539 }; 502 };
540 503
541 lan4: port@3 { 504 lan4: port@3 {
542 reg = <3>; 505 reg = <3>;
543 label = "lan4" 506 label = "lan4";
544 phy-mode = "in 507 phy-mode = "internal";
545 local-mac-addr 508 local-mac-address = [00 00 00 00 00 00];
546 }; 509 };
547 510
548 lan5: port@4 { 511 lan5: port@4 {
549 reg = <4>; 512 reg = <4>;
550 label = "lan5" 513 label = "lan5";
551 phy-mode = "in 514 phy-mode = "internal";
552 local-mac-addr 515 local-mac-address = [00 00 00 00 00 00];
553 }; 516 };
554 517
555 port@5 { 518 port@5 {
556 reg = <5>; 519 reg = <5>;
>> 520 label = "cpu";
557 ethernet = <&f 521 ethernet = <&fec>;
558 phy-mode = "rg 522 phy-mode = "rgmii-id";
559 523
560 fixed-link { 524 fixed-link {
561 speed 525 speed = <1000>;
562 full-d 526 full-duplex;
563 }; 527 };
564 }; 528 };
565 }; 529 };
566 }; 530 };
567 }; 531 };
568 532
>> 533 /* off-board header */
569 &i2c3 { 534 &i2c3 {
570 clock-frequency = <400000>; 535 clock-frequency = <400000>;
571 pinctrl-names = "default", "gpio"; !! 536 pinctrl-names = "default";
572 pinctrl-0 = <&pinctrl_i2c3>; 537 pinctrl-0 = <&pinctrl_i2c3>;
573 pinctrl-1 = <&pinctrl_i2c3_gpio>; <<
574 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI <<
575 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI <<
576 status = "okay"; 538 status = "okay";
577 <<
578 pmic@25 { <<
579 compatible = "nxp,pca9450c"; <<
580 reg = <0x25>; <<
581 pinctrl-names = "default"; <<
582 pinctrl-0 = <&pinctrl_pmic>; <<
583 interrupt-parent = <&gpio3>; <<
584 interrupts = <7 IRQ_TYPE_LEVEL <<
585 <<
586 regulators { <<
587 BUCK1 { <<
588 regulator-name <<
589 regulator-min- <<
590 regulator-max- <<
591 regulator-boot <<
592 regulator-alwa <<
593 regulator-ramp <<
594 }; <<
595 <<
596 reg_arm: BUCK2 { <<
597 regulator-name <<
598 regulator-min- <<
599 regulator-max- <<
600 regulator-boot <<
601 regulator-alwa <<
602 regulator-ramp <<
603 nxp,dvs-run-vo <<
604 nxp,dvs-standb <<
605 }; <<
606 <<
607 BUCK4 { <<
608 regulator-name <<
609 regulator-min- <<
610 regulator-max- <<
611 regulator-boot <<
612 regulator-alwa <<
613 }; <<
614 <<
615 BUCK5 { <<
616 regulator-name <<
617 regulator-min- <<
618 regulator-max- <<
619 regulator-boot <<
620 regulator-alwa <<
621 }; <<
622 <<
623 BUCK6 { <<
624 regulator-name <<
625 regulator-min- <<
626 regulator-max- <<
627 regulator-boot <<
628 regulator-alwa <<
629 }; <<
630 <<
631 LDO1 { <<
632 regulator-name <<
633 regulator-min- <<
634 regulator-max- <<
635 regulator-boot <<
636 regulator-alwa <<
637 }; <<
638 <<
639 LDO3 { <<
640 regulator-name <<
641 regulator-min- <<
642 regulator-max- <<
643 regulator-boot <<
644 regulator-alwa <<
645 }; <<
646 <<
647 LDO5 { <<
648 regulator-name <<
649 regulator-min- <<
650 regulator-max- <<
651 regulator-boot <<
652 regulator-alwa <<
653 }; <<
654 }; <<
655 }; <<
656 }; 539 };
657 540
658 /* off-board header */ 541 /* off-board header */
659 &i2c4 { 542 &i2c4 {
660 clock-frequency = <400000>; 543 clock-frequency = <400000>;
661 pinctrl-names = "default", "gpio"; <<
662 pinctrl-0 = <&pinctrl_i2c4>; <<
663 pinctrl-1 = <&pinctrl_i2c4_gpio>; <<
664 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI <<
665 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI <<
666 status = "okay"; <<
667 }; <<
668 <<
669 &pcie_phy { <<
670 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
671 fsl,clkreq-unsupported; <<
672 clocks = <&pcie0_refclk>; <<
673 clock-names = "ref"; <<
674 status = "okay"; <<
675 }; <<
676 <<
677 &pcie { <<
678 pinctrl-names = "default"; 544 pinctrl-names = "default";
679 pinctrl-0 = <&pinctrl_pcie0>; !! 545 pinctrl-0 = <&pinctrl_i2c4>;
680 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LO <<
681 status = "okay"; 546 status = "okay";
682 }; 547 };
683 548
684 /* GPS / off-board header */ 549 /* GPS / off-board header */
685 &uart1 { 550 &uart1 {
686 pinctrl-names = "default"; 551 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_uart1>; 552 pinctrl-0 = <&pinctrl_uart1>;
688 status = "okay"; 553 status = "okay";
689 }; 554 };
690 555
691 /* RS232 console */ 556 /* RS232 console */
692 &uart2 { 557 &uart2 {
693 pinctrl-names = "default"; 558 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_uart2>; 559 pinctrl-0 = <&pinctrl_uart2>;
695 status = "okay"; 560 status = "okay";
696 }; 561 };
697 562
698 /* bluetooth HCI */ <<
699 &uart3 { <<
700 pinctrl-names = "default"; <<
701 pinctrl-0 = <&pinctrl_uart3>, <&pinctr <<
702 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW <<
703 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW <<
704 status = "okay"; <<
705 <<
706 bluetooth { <<
707 compatible = "brcm,bcm4330-bt" <<
708 shutdown-gpios = <&gpio3 8 GPI <<
709 }; <<
710 }; <<
711 <<
712 &uart4 { 563 &uart4 {
713 pinctrl-names = "default"; 564 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_uart4>; 565 pinctrl-0 = <&pinctrl_uart4>;
715 status = "okay"; 566 status = "okay";
716 }; 567 };
717 568
718 /* USB1 - Type C front panel */ 569 /* USB1 - Type C front panel */
719 &usb3_0 { !! 570 &usb3_phy0 {
720 pinctrl-names = "default"; 571 pinctrl-names = "default";
721 pinctrl-0 = <&pinctrl_usb1>; 572 pinctrl-0 = <&pinctrl_usb1>;
722 fsl,over-current-active-low; <<
723 status = "okay"; 573 status = "okay";
724 }; 574 };
725 575
726 &usb3_phy0 { !! 576 &usb3_0 {
>> 577 fsl,over-current-active-low;
727 status = "okay"; 578 status = "okay";
728 }; 579 };
729 580
730 &usb_dwc3_0 { 581 &usb_dwc3_0 {
731 /* dual role is implemented but not a !! 582 dr_mode = "host";
732 adp-disable; <<
733 hnp-disable; <<
734 srp-disable; <<
735 dr_mode = "otg"; <<
736 usb-role-switch; <<
737 role-switch-default-mode = "peripheral <<
738 status = "okay"; 583 status = "okay";
739 <<
740 port { <<
741 usb3_dwc: endpoint { <<
742 remote-endpoint = <&us <<
743 }; <<
744 }; <<
745 }; 584 };
746 585
747 /* USB2 - USB3.0 Hub */ 586 /* USB2 - USB3.0 Hub */
748 &usb3_phy1 { 587 &usb3_phy1 {
749 vbus-supply = <®_usb2_vbus>; 588 vbus-supply = <®_usb2_vbus>;
750 status = "okay"; 589 status = "okay";
751 }; 590 };
752 591
753 &usb3_1 { 592 &usb3_1 {
754 fsl,permanently-attached; 593 fsl,permanently-attached;
755 fsl,disable-port-power-control; 594 fsl,disable-port-power-control;
756 status = "okay"; 595 status = "okay";
757 }; 596 };
758 597
759 &usb_dwc3_1 { 598 &usb_dwc3_1 {
760 dr_mode = "host"; 599 dr_mode = "host";
761 status = "okay"; 600 status = "okay";
762 }; 601 };
763 602
764 /* SDIO WiFi */ <<
765 &usdhc1 { <<
766 pinctrl-names = "default", "state_100m <<
767 pinctrl-0 = <&pinctrl_usdhc1>; <<
768 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; <<
769 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; <<
770 bus-width = <4>; <<
771 non-removable; <<
772 vmmc-supply = <®_wifi_en>; <<
773 #address-cells = <1>; <<
774 #size-cells = <0>; <<
775 status = "okay"; <<
776 <<
777 wifi@0 { <<
778 compatible = "cypress,cyw4373- <<
779 reg = <0>; <<
780 }; <<
781 }; <<
782 <<
783 /* eMMC */ 603 /* eMMC */
784 &usdhc3 { 604 &usdhc3 {
785 assigned-clocks = <&clk IMX8MP_CLK_USD 605 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
786 assigned-clock-rates = <400000000>; 606 assigned-clock-rates = <400000000>;
787 pinctrl-names = "default", "state_100m 607 pinctrl-names = "default", "state_100mhz", "state_200mhz";
788 pinctrl-0 = <&pinctrl_usdhc3>; 608 pinctrl-0 = <&pinctrl_usdhc3>;
789 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 609 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
790 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 610 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
791 bus-width = <8>; 611 bus-width = <8>;
792 non-removable; 612 non-removable;
793 status = "okay"; 613 status = "okay";
794 }; 614 };
795 615
796 &wdog1 { 616 &wdog1 {
797 pinctrl-names = "default"; 617 pinctrl-names = "default";
798 pinctrl-0 = <&pinctrl_wdog>; 618 pinctrl-0 = <&pinctrl_wdog>;
799 fsl,ext-reset-output; 619 fsl,ext-reset-output;
800 status = "okay"; 620 status = "okay";
801 }; 621 };
802 622
803 &iomuxc { 623 &iomuxc {
804 pinctrl-names = "default"; 624 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_hog>; 625 pinctrl-0 = <&pinctrl_hog>;
806 626
807 pinctrl_hog: hoggrp { 627 pinctrl_hog: hoggrp {
808 fsl,pins = < 628 fsl,pins = <
809 MX8MP_IOMUXC_GPIO1_IO0 629 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
810 MX8MP_IOMUXC_GPIO1_IO1 630 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
811 MX8MP_IOMUXC_SAI1_RXD0 !! 631 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
812 MX8MP_IOMUXC_SAI1_TXD6 !! 632 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */
813 MX8MP_IOMUXC_SD1_DATA4 <<
814 MX8MP_IOMUXC_SD1_STROB <<
815 MX8MP_IOMUXC_SD2_CLK__ <<
816 MX8MP_IOMUXC_SD2_CMD__ <<
817 MX8MP_IOMUXC_SD2_DATA3 633 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
>> 634 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
818 MX8MP_IOMUXC_NAND_DATA 635 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
>> 636 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
>> 637 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
819 MX8MP_IOMUXC_SAI3_TXD_ 638 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
820 MX8MP_IOMUXC_SAI3_TXFS 639 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
821 MX8MP_IOMUXC_SAI3_TXC_ 640 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
822 >; 641 >;
823 }; 642 };
824 643
825 pinctrl_accel: accelgrp { 644 pinctrl_accel: accelgrp {
826 fsl,pins = < 645 fsl,pins = <
827 MX8MP_IOMUXC_GPIO1_IO0 646 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
828 >; 647 >;
829 }; 648 };
830 649
831 pinctrl_eqos: eqosgrp { 650 pinctrl_eqos: eqosgrp {
832 fsl,pins = < 651 fsl,pins = <
833 MX8MP_IOMUXC_ENET_MDC_ 652 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
834 MX8MP_IOMUXC_ENET_MDIO 653 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
835 MX8MP_IOMUXC_ENET_RD0_ 654 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
836 MX8MP_IOMUXC_ENET_RD1_ 655 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
837 MX8MP_IOMUXC_ENET_RD2_ 656 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
838 MX8MP_IOMUXC_ENET_RD3_ 657 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
839 MX8MP_IOMUXC_ENET_RXC_ 658 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
840 MX8MP_IOMUXC_ENET_RX_C 659 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
841 MX8MP_IOMUXC_ENET_TD0_ 660 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
842 MX8MP_IOMUXC_ENET_TD1_ 661 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
843 MX8MP_IOMUXC_ENET_TD2_ 662 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
844 MX8MP_IOMUXC_ENET_TD3_ 663 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
845 MX8MP_IOMUXC_ENET_TX_C 664 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
846 MX8MP_IOMUXC_ENET_TXC_ 665 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
847 MX8MP_IOMUXC_SAI3_RXD_ 666 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
848 MX8MP_IOMUXC_SAI3_RXFS 667 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
849 >; 668 >;
850 }; 669 };
851 670
852 pinctrl_fec: fecgrp { 671 pinctrl_fec: fecgrp {
853 fsl,pins = < 672 fsl,pins = <
854 MX8MP_IOMUXC_SAI1_RXD4 673 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
855 MX8MP_IOMUXC_SAI1_RXD5 674 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
856 MX8MP_IOMUXC_SAI1_RXD6 675 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
857 MX8MP_IOMUXC_SAI1_RXD7 676 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
858 MX8MP_IOMUXC_SAI1_TXC_ 677 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
859 MX8MP_IOMUXC_SAI1_TXFS 678 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
860 MX8MP_IOMUXC_SAI1_TXD0 679 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
861 MX8MP_IOMUXC_SAI1_TXD1 680 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
862 MX8MP_IOMUXC_SAI1_TXD2 681 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
863 MX8MP_IOMUXC_SAI1_TXD3 682 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
864 MX8MP_IOMUXC_SAI1_TXD4 683 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
865 MX8MP_IOMUXC_SAI1_TXD5 684 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
866 MX8MP_IOMUXC_SAI1_RXFS 685 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
867 MX8MP_IOMUXC_SAI1_RXC_ 686 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
868 >; 687 >;
869 }; 688 };
870 689
871 pinctrl_flexcan1: flexcan1grp { <<
872 fsl,pins = < <<
873 MX8MP_IOMUXC_SPDIF_RX_ <<
874 MX8MP_IOMUXC_SPDIF_TX_ <<
875 >; <<
876 }; <<
877 <<
878 pinctrl_flexcan2: flexcan2grp { 690 pinctrl_flexcan2: flexcan2grp {
879 fsl,pins = < 691 fsl,pins = <
880 MX8MP_IOMUXC_SAI5_RXD3 692 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
881 MX8MP_IOMUXC_SAI5_MCLK 693 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
882 >; 694 >;
883 }; 695 };
884 696
885 pinctrl_gsc: gscgrp { 697 pinctrl_gsc: gscgrp {
886 fsl,pins = < 698 fsl,pins = <
887 MX8MP_IOMUXC_SAI1_MCLK 699 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
888 >; 700 >;
889 }; 701 };
890 702
891 pinctrl_i2c1: i2c1grp { 703 pinctrl_i2c1: i2c1grp {
892 fsl,pins = < 704 fsl,pins = <
893 MX8MP_IOMUXC_I2C1_SCL_ 705 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
894 MX8MP_IOMUXC_I2C1_SDA_ 706 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
895 >; 707 >;
896 }; 708 };
897 709
898 pinctrl_i2c1_gpio: i2c1gpiogrp { <<
899 fsl,pins = < <<
900 MX8MP_IOMUXC_I2C1_SCL_ <<
901 MX8MP_IOMUXC_I2C1_SDA_ <<
902 >; <<
903 }; <<
904 <<
905 pinctrl_i2c2: i2c2grp { 710 pinctrl_i2c2: i2c2grp {
906 fsl,pins = < 711 fsl,pins = <
907 MX8MP_IOMUXC_I2C2_SCL_ 712 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
908 MX8MP_IOMUXC_I2C2_SDA_ 713 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
909 >; 714 >;
910 }; 715 };
911 716
912 pinctrl_i2c2_gpio: i2c2gpiogrp { <<
913 fsl,pins = < <<
914 MX8MP_IOMUXC_I2C2_SCL_ <<
915 MX8MP_IOMUXC_I2C2_SDA_ <<
916 >; <<
917 }; <<
918 <<
919 pinctrl_i2c3: i2c3grp { 717 pinctrl_i2c3: i2c3grp {
920 fsl,pins = < 718 fsl,pins = <
921 MX8MP_IOMUXC_I2C3_SCL_ 719 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
922 MX8MP_IOMUXC_I2C3_SDA_ 720 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
923 >; 721 >;
924 }; 722 };
925 723
926 pinctrl_i2c3_gpio: i2c3gpiogrp { <<
927 fsl,pins = < <<
928 MX8MP_IOMUXC_I2C3_SCL_ <<
929 MX8MP_IOMUXC_I2C3_SDA_ <<
930 >; <<
931 }; <<
932 <<
933 pinctrl_i2c4: i2c4grp { 724 pinctrl_i2c4: i2c4grp {
934 fsl,pins = < 725 fsl,pins = <
935 MX8MP_IOMUXC_I2C4_SCL_ 726 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
936 MX8MP_IOMUXC_I2C4_SDA_ 727 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
937 >; 728 >;
938 }; 729 };
939 730
940 pinctrl_i2c4_gpio: i2c4gpiogrp { <<
941 fsl,pins = < <<
942 MX8MP_IOMUXC_I2C4_SCL_ <<
943 MX8MP_IOMUXC_I2C4_SDA_ <<
944 >; <<
945 }; <<
946 <<
947 pinctrl_ksz: kszgrp { 731 pinctrl_ksz: kszgrp {
948 fsl,pins = < 732 fsl,pins = <
949 MX8MP_IOMUXC_SAI3_RXC_ 733 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
950 MX8MP_IOMUXC_SAI3_MCLK 734 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
951 >; 735 >;
952 }; 736 };
953 737
954 pinctrl_gpio_leds: ledgrp { 738 pinctrl_gpio_leds: ledgrp {
955 fsl,pins = < 739 fsl,pins = <
956 MX8MP_IOMUXC_SD2_DATA0 740 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
957 MX8MP_IOMUXC_SD2_DATA1 741 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
958 >; 742 >;
959 }; 743 };
960 744
961 pinctrl_pcie0: pciegrp { <<
962 fsl,pins = < <<
963 MX8MP_IOMUXC_SD2_DATA2 <<
964 >; <<
965 }; <<
966 <<
967 pinctrl_pmic: pmicgrp { 745 pinctrl_pmic: pmicgrp {
968 fsl,pins = < 746 fsl,pins = <
969 MX8MP_IOMUXC_NAND_DATA 747 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
970 >; 748 >;
971 }; 749 };
972 750
973 pinctrl_pps: ppsgrp { 751 pinctrl_pps: ppsgrp {
974 fsl,pins = < 752 fsl,pins = <
975 MX8MP_IOMUXC_GPIO1_IO1 753 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
976 >; 754 >;
977 }; 755 };
978 756
979 pinctrl_reg_can1: regcan1grp { !! 757 pinctrl_reg_can: regcangrp {
980 fsl,pins = < 758 fsl,pins = <
981 MX8MP_IOMUXC_SAI5_RXFS 759 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
982 >; 760 >;
983 }; 761 };
984 762
985 pinctrl_reg_can2: regcan2grp { <<
986 fsl,pins = < <<
987 MX8MP_IOMUXC_SPDIF_EXT <<
988 >; <<
989 }; <<
990 <<
991 pinctrl_reg_usb2: regusb2grp { 763 pinctrl_reg_usb2: regusb2grp {
992 fsl,pins = < 764 fsl,pins = <
993 MX8MP_IOMUXC_GPIO1_IO0 765 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
994 >; 766 >;
995 }; 767 };
996 768
997 pinctrl_reg_wifi: regwifigrp { 769 pinctrl_reg_wifi: regwifigrp {
998 fsl,pins = < 770 fsl,pins = <
999 MX8MP_IOMUXC_NAND_DATA 771 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
1000 >; 772 >;
1001 }; 773 };
1002 774
1003 pinctrl_spi1: spi1grp { !! 775 pinctrl_sai2: sai2grp {
1004 fsl,pins = < 776 fsl,pins = <
1005 MX8MP_IOMUXC_ECSPI1_S !! 777 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
1006 MX8MP_IOMUXC_ECSPI1_M !! 778 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
1007 MX8MP_IOMUXC_ECSPI1_M !! 779 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
1008 MX8MP_IOMUXC_ECSPI1_S !! 780 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
1009 >; 781 >;
1010 }; 782 };
1011 783
1012 pinctrl_spi2: spi2grp { 784 pinctrl_spi2: spi2grp {
1013 fsl,pins = < 785 fsl,pins = <
1014 MX8MP_IOMUXC_ECSPI2_S 786 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
1015 MX8MP_IOMUXC_ECSPI2_M 787 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
1016 MX8MP_IOMUXC_ECSPI2_M 788 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
1017 MX8MP_IOMUXC_ECSPI2_S 789 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
1018 >; 790 >;
1019 }; 791 };
1020 792
1021 pinctrl_uart1: uart1grp { 793 pinctrl_uart1: uart1grp {
1022 fsl,pins = < 794 fsl,pins = <
1023 MX8MP_IOMUXC_UART1_RX 795 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
1024 MX8MP_IOMUXC_UART1_TX 796 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
1025 >; 797 >;
1026 }; 798 };
1027 799
1028 pinctrl_uart2: uart2grp { 800 pinctrl_uart2: uart2grp {
1029 fsl,pins = < 801 fsl,pins = <
1030 MX8MP_IOMUXC_UART2_RX 802 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
1031 MX8MP_IOMUXC_UART2_TX 803 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
1032 >; 804 >;
1033 }; 805 };
1034 806
1035 pinctrl_uart3: uart3grp { 807 pinctrl_uart3: uart3grp {
1036 fsl,pins = < 808 fsl,pins = <
1037 MX8MP_IOMUXC_UART3_RX 809 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
1038 MX8MP_IOMUXC_UART3_TX 810 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
1039 MX8MP_IOMUXC_SAI5_RXD 811 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
1040 MX8MP_IOMUXC_SAI5_RXD 812 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
1041 >; 813 >;
1042 }; 814 };
1043 815
1044 pinctrl_uart3_gpio: uart3gpiogrp { 816 pinctrl_uart3_gpio: uart3gpiogrp {
1045 fsl,pins = < 817 fsl,pins = <
1046 MX8MP_IOMUXC_NAND_DAT 818 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
1047 >; 819 >;
1048 }; 820 };
1049 821
1050 pinctrl_uart4: uart4grp { 822 pinctrl_uart4: uart4grp {
1051 fsl,pins = < 823 fsl,pins = <
1052 MX8MP_IOMUXC_UART4_RX 824 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
1053 MX8MP_IOMUXC_UART4_TX 825 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
1054 >; 826 >;
1055 }; 827 };
1056 828
1057 pinctrl_usb1: usb1grp { 829 pinctrl_usb1: usb1grp {
1058 fsl,pins = < 830 fsl,pins = <
1059 MX8MP_IOMUXC_GPIO1_IO 831 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
1060 >; !! 832 MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x140
1061 }; <<
1062 <<
1063 pinctrl_usbcon1: usb1congrp { <<
1064 fsl,pins = < <<
1065 MX8MP_IOMUXC_GPIO1_IO <<
1066 >; 833 >;
1067 }; 834 };
1068 835
1069 pinctrl_usdhc1: usdhc1grp { 836 pinctrl_usdhc1: usdhc1grp {
1070 fsl,pins = < 837 fsl,pins = <
1071 MX8MP_IOMUXC_SD1_CLK_ 838 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1072 MX8MP_IOMUXC_SD1_CMD_ 839 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1073 MX8MP_IOMUXC_SD1_DATA 840 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1074 MX8MP_IOMUXC_SD1_DATA 841 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1075 MX8MP_IOMUXC_SD1_DATA 842 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1076 MX8MP_IOMUXC_SD1_DATA 843 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1077 >; <<
1078 }; <<
1079 <<
1080 pinctrl_usdhc1_100mhz: usdhc1-100mhzg <<
1081 fsl,pins = < <<
1082 MX8MP_IOMUXC_SD1_CLK_ <<
1083 MX8MP_IOMUXC_SD1_CMD_ <<
1084 MX8MP_IOMUXC_SD1_DATA <<
1085 MX8MP_IOMUXC_SD1_DATA <<
1086 MX8MP_IOMUXC_SD1_DATA <<
1087 MX8MP_IOMUXC_SD1_DATA <<
1088 >; <<
1089 }; <<
1090 <<
1091 pinctrl_usdhc1_200mhz: usdhc1-200mhzg <<
1092 fsl,pins = < <<
1093 MX8MP_IOMUXC_SD1_CLK_ <<
1094 MX8MP_IOMUXC_SD1_CMD_ <<
1095 MX8MP_IOMUXC_SD1_DATA <<
1096 MX8MP_IOMUXC_SD1_DATA <<
1097 MX8MP_IOMUXC_SD1_DATA <<
1098 MX8MP_IOMUXC_SD1_DATA <<
1099 >; 844 >;
1100 }; 845 };
1101 846
1102 pinctrl_usdhc3: usdhc3grp { 847 pinctrl_usdhc3: usdhc3grp {
1103 fsl,pins = < 848 fsl,pins = <
1104 MX8MP_IOMUXC_NAND_WE_ 849 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1105 MX8MP_IOMUXC_NAND_WP_ 850 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1106 MX8MP_IOMUXC_NAND_DAT 851 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1107 MX8MP_IOMUXC_NAND_DAT 852 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1108 MX8MP_IOMUXC_NAND_DAT 853 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1109 MX8MP_IOMUXC_NAND_DAT 854 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1110 MX8MP_IOMUXC_NAND_RE_ 855 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1111 MX8MP_IOMUXC_NAND_CE2 856 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1112 MX8MP_IOMUXC_NAND_CE3 857 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1113 MX8MP_IOMUXC_NAND_CLE 858 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1114 MX8MP_IOMUXC_NAND_CE1 859 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1115 >; 860 >;
1116 }; 861 };
1117 862
1118 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 863 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1119 fsl,pins = < 864 fsl,pins = <
1120 MX8MP_IOMUXC_NAND_WE_ 865 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1121 MX8MP_IOMUXC_NAND_WP_ 866 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1122 MX8MP_IOMUXC_NAND_DAT 867 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1123 MX8MP_IOMUXC_NAND_DAT 868 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1124 MX8MP_IOMUXC_NAND_DAT 869 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1125 MX8MP_IOMUXC_NAND_DAT 870 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1126 MX8MP_IOMUXC_NAND_RE_ 871 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1127 MX8MP_IOMUXC_NAND_CE2 872 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1128 MX8MP_IOMUXC_NAND_CE3 873 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1129 MX8MP_IOMUXC_NAND_CLE 874 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1130 MX8MP_IOMUXC_NAND_CE1 875 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1131 >; 876 >;
1132 }; 877 };
1133 878
1134 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 879 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1135 fsl,pins = < 880 fsl,pins = <
1136 MX8MP_IOMUXC_NAND_WE_ 881 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1137 MX8MP_IOMUXC_NAND_WP_ 882 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1138 MX8MP_IOMUXC_NAND_DAT 883 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1139 MX8MP_IOMUXC_NAND_DAT 884 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1140 MX8MP_IOMUXC_NAND_DAT 885 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1141 MX8MP_IOMUXC_NAND_DAT 886 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1142 MX8MP_IOMUXC_NAND_RE_ 887 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1143 MX8MP_IOMUXC_NAND_CE2 888 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1144 MX8MP_IOMUXC_NAND_CE3 889 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1145 MX8MP_IOMUXC_NAND_CLE 890 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1146 MX8MP_IOMUXC_NAND_CE1 891 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1147 >; 892 >;
1148 }; 893 };
1149 894
1150 pinctrl_wdog: wdoggrp { 895 pinctrl_wdog: wdoggrp {
1151 fsl,pins = < 896 fsl,pins = <
1152 MX8MP_IOMUXC_GPIO1_IO 897 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
1153 >; 898 >;
1154 }; 899 };
1155 }; 900 };
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