1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2021 Gateworks Corporation 3 * Copyright 2021 Gateworks Corporation
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/linux-event-codes. 9 #include <dt-bindings/input/linux-event-codes.h>
10 #include <dt-bindings/leds/common.h> 10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 #include <dt-bindings/phy/phy-imx8-pcie.h>
12 #include <dt-bindings/net/ti-dp83867.h> <<
13 12
14 #include "imx8mp.dtsi" 13 #include "imx8mp.dtsi"
15 14
16 / { 15 / {
17 model = "Gateworks Venice GW74xx i.MX8 16 model = "Gateworks Venice GW74xx i.MX8MP board";
18 compatible = "gateworks,imx8mp-gw74xx" 17 compatible = "gateworks,imx8mp-gw74xx", "fsl,imx8mp";
19 18
20 aliases { 19 aliases {
21 ethernet0 = &eqos; 20 ethernet0 = &eqos;
22 ethernet1 = &fec; 21 ethernet1 = &fec;
23 ethernet2 = &lan1; 22 ethernet2 = &lan1;
24 ethernet3 = &lan2; 23 ethernet3 = &lan2;
25 ethernet4 = &lan3; 24 ethernet4 = &lan3;
26 ethernet5 = &lan4; 25 ethernet5 = &lan4;
27 ethernet6 = &lan5; 26 ethernet6 = &lan5;
28 }; 27 };
29 28
30 chosen { 29 chosen {
31 stdout-path = &uart2; 30 stdout-path = &uart2;
32 }; 31 };
33 32
34 memory@40000000 { 33 memory@40000000 {
35 device_type = "memory"; 34 device_type = "memory";
36 reg = <0x0 0x40000000 0 0x8000 35 reg = <0x0 0x40000000 0 0x80000000>;
37 }; 36 };
38 37
39 connector { <<
40 pinctrl-names = "default"; <<
41 pinctrl-0 = <&pinctrl_usbcon1> <<
42 compatible = "gpio-usb-b-conne <<
43 type = "micro"; <<
44 label = "Type-C"; <<
45 id-gpios = <&gpio1 10 GPIO_ACT <<
46 <<
47 port { <<
48 usb_dr_connector: endp <<
49 remote-endpoin <<
50 }; <<
51 }; <<
52 }; <<
53 <<
54 gpio-keys { 38 gpio-keys {
55 compatible = "gpio-keys"; 39 compatible = "gpio-keys";
56 40
57 key-0 { 41 key-0 {
58 label = "user_pb"; 42 label = "user_pb";
59 gpios = <&gpio 2 GPIO_ 43 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
60 linux,code = <BTN_0>; 44 linux,code = <BTN_0>;
61 }; 45 };
62 46
63 key-1 { 47 key-1 {
64 label = "user_pb1x"; 48 label = "user_pb1x";
65 linux,code = <BTN_1>; 49 linux,code = <BTN_1>;
66 interrupt-parent = <&g 50 interrupt-parent = <&gsc>;
67 interrupts = <0>; 51 interrupts = <0>;
68 }; 52 };
69 53
70 key-2 { 54 key-2 {
71 label = "key_erased"; 55 label = "key_erased";
72 linux,code = <BTN_2>; 56 linux,code = <BTN_2>;
73 interrupt-parent = <&g 57 interrupt-parent = <&gsc>;
74 interrupts = <1>; 58 interrupts = <1>;
75 }; 59 };
76 60
77 key-3 { 61 key-3 {
78 label = "eeprom_wp"; 62 label = "eeprom_wp";
79 linux,code = <BTN_3>; 63 linux,code = <BTN_3>;
80 interrupt-parent = <&g 64 interrupt-parent = <&gsc>;
81 interrupts = <2>; 65 interrupts = <2>;
82 }; 66 };
83 67
84 key-4 { 68 key-4 {
85 label = "tamper"; 69 label = "tamper";
86 linux,code = <BTN_4>; 70 linux,code = <BTN_4>;
87 interrupt-parent = <&g 71 interrupt-parent = <&gsc>;
88 interrupts = <5>; 72 interrupts = <5>;
89 }; 73 };
90 74
91 key-5 { 75 key-5 {
92 label = "switch_hold"; 76 label = "switch_hold";
93 linux,code = <BTN_5>; 77 linux,code = <BTN_5>;
94 interrupt-parent = <&g 78 interrupt-parent = <&gsc>;
95 interrupts = <7>; 79 interrupts = <7>;
96 }; 80 };
97 }; 81 };
98 82
99 led-controller { 83 led-controller {
100 compatible = "gpio-leds"; 84 compatible = "gpio-leds";
101 pinctrl-names = "default"; 85 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_gpio_led 86 pinctrl-0 = <&pinctrl_gpio_leds>;
103 87
104 led-0 { 88 led-0 {
105 function = LED_FUNCTIO 89 function = LED_FUNCTION_HEARTBEAT;
106 color = <LED_COLOR_ID_ 90 color = <LED_COLOR_ID_GREEN>;
107 gpios = <&gpio2 15 GPI 91 gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
108 default-state = "on"; 92 default-state = "on";
109 linux,default-trigger 93 linux,default-trigger = "heartbeat";
110 }; 94 };
111 95
112 led-1 { 96 led-1 {
113 function = LED_FUNCTIO 97 function = LED_FUNCTION_STATUS;
114 color = <LED_COLOR_ID_ 98 color = <LED_COLOR_ID_RED>;
115 gpios = <&gpio2 16 GPI 99 gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
116 default-state = "off"; 100 default-state = "off";
117 }; 101 };
118 }; 102 };
119 103
120 pcie0_refclk: pcie0-refclk { 104 pcie0_refclk: pcie0-refclk {
121 compatible = "fixed-clock"; 105 compatible = "fixed-clock";
122 #clock-cells = <0>; 106 #clock-cells = <0>;
123 clock-frequency = <100000000>; 107 clock-frequency = <100000000>;
124 }; 108 };
125 109
126 pps { 110 pps {
127 compatible = "pps-gpio"; 111 compatible = "pps-gpio";
128 pinctrl-names = "default"; 112 pinctrl-names = "default";
129 pinctrl-0 = <&pinctrl_pps>; 113 pinctrl-0 = <&pinctrl_pps>;
130 gpios = <&gpio1 12 GPIO_ACTIVE 114 gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
131 }; 115 };
132 116
133 reg_usb2_vbus: regulator-usb2 { 117 reg_usb2_vbus: regulator-usb2 {
134 pinctrl-names = "default"; 118 pinctrl-names = "default";
135 pinctrl-0 = <&pinctrl_reg_usb2 119 pinctrl-0 = <&pinctrl_reg_usb2>;
136 compatible = "regulator-fixed" 120 compatible = "regulator-fixed";
137 regulator-name = "usb_usb2_vbu 121 regulator-name = "usb_usb2_vbus";
138 gpio = <&gpio1 6 GPIO_ACTIVE_H 122 gpio = <&gpio1 6 GPIO_ACTIVE_HIGH>;
139 enable-active-high; 123 enable-active-high;
140 regulator-min-microvolt = <500 124 regulator-min-microvolt = <5000000>;
141 regulator-max-microvolt = <500 125 regulator-max-microvolt = <5000000>;
142 }; 126 };
143 127
144 reg_can1_stby: regulator-can1-stby { <<
145 compatible = "regulator-fixed" <<
146 pinctrl-names = "default"; <<
147 pinctrl-0 = <&pinctrl_reg_can1 <<
148 regulator-name = "can1_stby"; <<
149 gpio = <&gpio3 19 GPIO_ACTIVE_ <<
150 regulator-min-microvolt = <330 <<
151 regulator-max-microvolt = <330 <<
152 }; <<
153 <<
154 reg_can2_stby: regulator-can2-stby { 128 reg_can2_stby: regulator-can2-stby {
155 compatible = "regulator-fixed" 129 compatible = "regulator-fixed";
156 pinctrl-names = "default"; 130 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_reg_can2 !! 131 pinctrl-0 = <&pinctrl_reg_can>;
158 regulator-name = "can2_stby"; 132 regulator-name = "can2_stby";
159 gpio = <&gpio5 5 GPIO_ACTIVE_L !! 133 gpio = <&gpio3 19 GPIO_ACTIVE_LOW>;
160 regulator-min-microvolt = <330 134 regulator-min-microvolt = <3300000>;
161 regulator-max-microvolt = <330 135 regulator-max-microvolt = <3300000>;
162 }; 136 };
163 137
164 reg_wifi_en: regulator-wifi-en { 138 reg_wifi_en: regulator-wifi-en {
165 pinctrl-names = "default"; 139 pinctrl-names = "default";
166 pinctrl-0 = <&pinctrl_reg_wifi 140 pinctrl-0 = <&pinctrl_reg_wifi>;
167 compatible = "regulator-fixed" 141 compatible = "regulator-fixed";
168 regulator-name = "wl"; 142 regulator-name = "wl";
169 gpio = <&gpio3 9 GPIO_ACTIVE_H 143 gpio = <&gpio3 9 GPIO_ACTIVE_HIGH>;
170 startup-delay-us = <70000>; 144 startup-delay-us = <70000>;
171 enable-active-high; 145 enable-active-high;
172 regulator-min-microvolt = <330 146 regulator-min-microvolt = <3300000>;
173 regulator-max-microvolt = <330 147 regulator-max-microvolt = <3300000>;
174 }; 148 };
175 }; 149 };
176 150
177 &A53_0 { 151 &A53_0 {
178 cpu-supply = <®_arm>; 152 cpu-supply = <®_arm>;
179 }; 153 };
180 154
181 &A53_1 { 155 &A53_1 {
182 cpu-supply = <®_arm>; 156 cpu-supply = <®_arm>;
183 }; 157 };
184 158
185 &A53_2 { 159 &A53_2 {
186 cpu-supply = <®_arm>; 160 cpu-supply = <®_arm>;
187 }; 161 };
188 162
189 &A53_3 { 163 &A53_3 {
190 cpu-supply = <®_arm>; 164 cpu-supply = <®_arm>;
191 }; 165 };
192 166
193 &ecspi1 { <<
194 pinctrl-names = "default"; <<
195 pinctrl-0 = <&pinctrl_spi1>; <<
196 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; <<
197 status = "okay"; <<
198 <<
199 tpm@0 { <<
200 compatible = "atmel,attpm20p", <<
201 reg = <0x0>; <<
202 spi-max-frequency = <36000000> <<
203 }; <<
204 }; <<
205 <<
206 /* off-board header */ 167 /* off-board header */
207 &ecspi2 { 168 &ecspi2 {
208 pinctrl-names = "default"; 169 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_spi2>; 170 pinctrl-0 = <&pinctrl_spi2>;
210 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW> 171 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
211 status = "okay"; 172 status = "okay";
212 }; 173 };
213 174
214 &eqos { 175 &eqos {
215 pinctrl-names = "default"; 176 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_eqos>; 177 pinctrl-0 = <&pinctrl_eqos>;
217 phy-mode = "rgmii-id"; 178 phy-mode = "rgmii-id";
218 phy-handle = <ðphy0>; 179 phy-handle = <ðphy0>;
219 status = "okay"; 180 status = "okay";
220 181
221 mdio { 182 mdio {
222 compatible = "snps,dwmac-mdio" 183 compatible = "snps,dwmac-mdio";
223 #address-cells = <1>; 184 #address-cells = <1>;
224 #size-cells = <0>; 185 #size-cells = <0>;
225 186
226 ethphy0: ethernet-phy@0 { 187 ethphy0: ethernet-phy@0 {
227 compatible = "ethernet 188 compatible = "ethernet-phy-ieee802.3-c22";
228 reg = <0x0>; 189 reg = <0x0>;
229 ti,rx-internal-delay = <<
230 ti,tx-internal-delay = <<
231 tx-fifo-depth = <DP838 <<
232 rx-fifo-depth = <DP838 <<
233 <<
234 leds { <<
235 #address-cells <<
236 #size-cells = <<
237 <<
238 led@1 { <<
239 reg = <<
240 color <<
241 functi <<
242 defaul <<
243 }; <<
244 <<
245 led@2 { <<
246 reg = <<
247 color <<
248 functi <<
249 defaul <<
250 }; <<
251 }; <<
252 }; 190 };
253 }; 191 };
254 }; 192 };
255 193
256 &fec { 194 &fec {
257 pinctrl-names = "default"; 195 pinctrl-names = "default";
258 pinctrl-0 = <&pinctrl_fec>; 196 pinctrl-0 = <&pinctrl_fec>;
259 phy-mode = "rgmii-id"; 197 phy-mode = "rgmii-id";
260 local-mac-address = [00 00 00 00 00 00 198 local-mac-address = [00 00 00 00 00 00];
261 status = "okay"; 199 status = "okay";
262 200
263 fixed-link { 201 fixed-link {
264 speed = <1000>; 202 speed = <1000>;
265 full-duplex; 203 full-duplex;
266 }; 204 };
267 }; 205 };
268 206
269 &flexcan1 { <<
270 pinctrl-names = "default"; <<
271 pinctrl-0 = <&pinctrl_flexcan1>; <<
272 xceiver-supply = <®_can1_stby>; <<
273 status = "okay"; <<
274 }; <<
275 <<
276 &flexcan2 { 207 &flexcan2 {
277 pinctrl-names = "default"; 208 pinctrl-names = "default";
278 pinctrl-0 = <&pinctrl_flexcan2>; 209 pinctrl-0 = <&pinctrl_flexcan2>;
279 xceiver-supply = <®_can2_stby>; 210 xceiver-supply = <®_can2_stby>;
280 status = "okay"; 211 status = "okay";
281 }; 212 };
282 213
283 &gpio1 { 214 &gpio1 {
284 gpio-line-names = 215 gpio-line-names =
285 "", "", "", "", "", "", "", "" 216 "", "", "", "", "", "", "", "",
286 "", "dio0", "", "dio1", "", "" !! 217 "", "", "dio0", "", "dio1", "", "", "",
287 "", "", "", "", "", "", "", "" 218 "", "", "", "", "", "", "", "",
288 "", "", "", "", "", "", "", "" 219 "", "", "", "", "", "", "", "";
289 }; 220 };
290 221
291 &gpio2 { 222 &gpio2 {
292 gpio-line-names = 223 gpio-line-names =
293 "", "", "", "", "", "", "m2_pi !! 224 "", "", "", "", "", "", "", "",
294 "", "", "", "", "", "pcie1_wdi !! 225 "", "", "", "", "", "", "pcie3_wdis#", "",
295 "", "", "pcie2_wdis#", "", "", 226 "", "", "pcie2_wdis#", "", "", "", "", "",
296 "", "", "", "", "", "", "", "" 227 "", "", "", "", "", "", "", "";
297 }; 228 };
298 229
299 &gpio3 { 230 &gpio3 {
300 gpio-line-names = 231 gpio-line-names =
301 "", "", "", "", "", "", "m2_rs !! 232 "m2_gdis#", "", "", "", "", "", "", "m2_rst#",
302 "", "", "", "", "", "", "", "" <<
303 "", "", "", "", "", "", "", "" 233 "", "", "", "", "", "", "", "",
>> 234 "m2_off#", "", "", "", "", "", "", "",
304 "", "", "", "", "", "", "", "" 235 "", "", "", "", "", "", "", "";
305 }; 236 };
306 237
307 &gpio4 { 238 &gpio4 {
308 gpio-line-names = 239 gpio-line-names =
309 "", "", "m2_off#", "", "", "", <<
310 "", "", "", "", "", "", "", "" 240 "", "", "", "", "", "", "", "",
311 "", "", "m2_wdis#", "", "", "" !! 241 "", "", "", "", "", "", "", "",
312 "", "", "", "", "", "", "", "r !! 242 "", "", "", "", "m2_wdis#", "", "", "",
>> 243 "", "", "", "", "", "", "", "uart_rs485";
313 }; 244 };
314 245
315 &gpio5 { 246 &gpio5 {
316 gpio-line-names = 247 gpio-line-names =
317 "rs485_hd", "rs485_term", "", !! 248 "uart_half", "uart_term", "", "", "", "", "", "",
318 "", "", "", "", "", "", "", "" 249 "", "", "", "", "", "", "", "",
319 "", "", "", "", "", "", "", "" 250 "", "", "", "", "", "", "", "",
320 "", "", "", "", "", "", "", "" 251 "", "", "", "", "", "", "", "";
321 }; 252 };
322 253
323 &i2c1 { 254 &i2c1 {
324 clock-frequency = <100000>; 255 clock-frequency = <100000>;
325 pinctrl-names = "default", "gpio"; 256 pinctrl-names = "default", "gpio";
326 pinctrl-0 = <&pinctrl_i2c1>; 257 pinctrl-0 = <&pinctrl_i2c1>;
327 pinctrl-1 = <&pinctrl_i2c1_gpio>; 258 pinctrl-1 = <&pinctrl_i2c1_gpio>;
328 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 259 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
329 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 260 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
330 status = "okay"; 261 status = "okay";
331 262
332 gsc: gsc@20 { 263 gsc: gsc@20 {
333 compatible = "gw,gsc"; 264 compatible = "gw,gsc";
334 reg = <0x20>; 265 reg = <0x20>;
335 pinctrl-0 = <&pinctrl_gsc>; 266 pinctrl-0 = <&pinctrl_gsc>;
336 interrupt-parent = <&gpio4>; 267 interrupt-parent = <&gpio4>;
337 interrupts = <20 IRQ_TYPE_EDGE 268 interrupts = <20 IRQ_TYPE_EDGE_FALLING>;
338 interrupt-controller; 269 interrupt-controller;
339 #interrupt-cells = <1>; 270 #interrupt-cells = <1>;
340 #address-cells = <1>; <<
341 #size-cells = <0>; <<
342 271
343 adc { 272 adc {
344 compatible = "gw,gsc-a 273 compatible = "gw,gsc-adc";
345 #address-cells = <1>; 274 #address-cells = <1>;
346 #size-cells = <0>; 275 #size-cells = <0>;
347 276
348 channel@6 { 277 channel@6 {
349 gw,mode = <0>; 278 gw,mode = <0>;
350 reg = <0x06>; 279 reg = <0x06>;
351 label = "temp" 280 label = "temp";
352 }; 281 };
353 282
354 channel@8 { 283 channel@8 {
355 gw,mode = <3>; 284 gw,mode = <3>;
356 reg = <0x08>; 285 reg = <0x08>;
357 label = "vdd_b 286 label = "vdd_bat";
358 }; 287 };
359 288
360 channel@16 { <<
361 gw,mode = <4>; <<
362 reg = <0x16>; <<
363 label = "fan_t <<
364 }; <<
365 <<
366 channel@82 { 289 channel@82 {
367 gw,mode = <2>; 290 gw,mode = <2>;
368 reg = <0x82>; 291 reg = <0x82>;
369 label = "vdd_a 292 label = "vdd_adc1";
370 gw,voltage-div 293 gw,voltage-divider-ohms = <10000 10000>;
371 }; 294 };
372 295
373 channel@84 { 296 channel@84 {
374 gw,mode = <2>; 297 gw,mode = <2>;
375 reg = <0x84>; 298 reg = <0x84>;
376 label = "vdd_a 299 label = "vdd_adc2";
377 gw,voltage-div 300 gw,voltage-divider-ohms = <10000 10000>;
378 }; 301 };
379 302
380 channel@86 { 303 channel@86 {
381 gw,mode = <2>; 304 gw,mode = <2>;
382 reg = <0x86>; 305 reg = <0x86>;
383 label = "vdd_v 306 label = "vdd_vin";
384 gw,voltage-div 307 gw,voltage-divider-ohms = <22100 1000>;
385 }; 308 };
386 309
387 channel@88 { 310 channel@88 {
388 gw,mode = <2>; 311 gw,mode = <2>;
389 reg = <0x88>; 312 reg = <0x88>;
390 label = "vdd_3 313 label = "vdd_3p3";
391 gw,voltage-div 314 gw,voltage-divider-ohms = <10000 10000>;
392 }; 315 };
393 316
394 channel@8c { 317 channel@8c {
395 gw,mode = <2>; 318 gw,mode = <2>;
396 reg = <0x8c>; 319 reg = <0x8c>;
397 label = "vdd_2 320 label = "vdd_2p5";
398 gw,voltage-div 321 gw,voltage-divider-ohms = <10000 10000>;
399 }; 322 };
400 323
401 channel@90 { 324 channel@90 {
402 gw,mode = <2>; 325 gw,mode = <2>;
403 reg = <0x90>; 326 reg = <0x90>;
404 label = "vdd_s 327 label = "vdd_soc";
405 }; 328 };
406 329
407 channel@92 { 330 channel@92 {
408 gw,mode = <2>; 331 gw,mode = <2>;
409 reg = <0x92>; 332 reg = <0x92>;
410 label = "vdd_a 333 label = "vdd_arm";
411 }; 334 };
412 335
413 channel@98 { 336 channel@98 {
414 gw,mode = <2>; 337 gw,mode = <2>;
415 reg = <0x98>; 338 reg = <0x98>;
416 label = "vdd_1 339 label = "vdd_1p8";
417 }; 340 };
418 341
419 channel@9a { 342 channel@9a {
420 gw,mode = <2>; 343 gw,mode = <2>;
421 reg = <0x9a>; 344 reg = <0x9a>;
422 label = "vdd_1 345 label = "vdd_1p2";
423 }; 346 };
424 347
425 channel@9c { 348 channel@9c {
426 gw,mode = <2>; 349 gw,mode = <2>;
427 reg = <0x9c>; 350 reg = <0x9c>;
428 label = "vdd_d 351 label = "vdd_dram";
429 }; 352 };
430 353
431 channel@9e { <<
432 gw,mode = <2>; <<
433 reg = <0x9e>; <<
434 label = "vdd_1 <<
435 }; <<
436 <<
437 channel@a2 { 354 channel@a2 {
438 gw,mode = <2>; 355 gw,mode = <2>;
439 reg = <0xa2>; 356 reg = <0xa2>;
440 label = "vdd_g 357 label = "vdd_gsc";
441 gw,voltage-div 358 gw,voltage-divider-ohms = <10000 10000>;
442 }; 359 };
443 }; 360 };
444 <<
445 fan-controller@a { <<
446 compatible = "gw,gsc-f <<
447 reg = <0x0a>; <<
448 }; <<
449 }; 361 };
450 362
451 gpio: gpio@23 { 363 gpio: gpio@23 {
452 compatible = "nxp,pca9555"; 364 compatible = "nxp,pca9555";
453 reg = <0x23>; 365 reg = <0x23>;
454 gpio-controller; 366 gpio-controller;
455 #gpio-cells = <2>; 367 #gpio-cells = <2>;
456 interrupt-parent = <&gsc>; 368 interrupt-parent = <&gsc>;
457 interrupts = <4>; 369 interrupts = <4>;
458 }; 370 };
459 371
>> 372 pmic@25 {
>> 373 compatible = "nxp,pca9450c";
>> 374 reg = <0x25>;
>> 375 pinctrl-names = "default";
>> 376 pinctrl-0 = <&pinctrl_pmic>;
>> 377 interrupt-parent = <&gpio3>;
>> 378 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
>> 379
>> 380 regulators {
>> 381 BUCK1 {
>> 382 regulator-name = "BUCK1";
>> 383 regulator-min-microvolt = <720000>;
>> 384 regulator-max-microvolt = <1000000>;
>> 385 regulator-boot-on;
>> 386 regulator-always-on;
>> 387 regulator-ramp-delay = <3125>;
>> 388 };
>> 389
>> 390 reg_arm: BUCK2 {
>> 391 regulator-name = "BUCK2";
>> 392 regulator-min-microvolt = <720000>;
>> 393 regulator-max-microvolt = <1025000>;
>> 394 regulator-boot-on;
>> 395 regulator-always-on;
>> 396 regulator-ramp-delay = <3125>;
>> 397 nxp,dvs-run-voltage = <950000>;
>> 398 nxp,dvs-standby-voltage = <850000>;
>> 399 };
>> 400
>> 401 BUCK4 {
>> 402 regulator-name = "BUCK4";
>> 403 regulator-min-microvolt = <3000000>;
>> 404 regulator-max-microvolt = <3600000>;
>> 405 regulator-boot-on;
>> 406 regulator-always-on;
>> 407 };
>> 408
>> 409 BUCK5 {
>> 410 regulator-name = "BUCK5";
>> 411 regulator-min-microvolt = <1650000>;
>> 412 regulator-max-microvolt = <1950000>;
>> 413 regulator-boot-on;
>> 414 regulator-always-on;
>> 415 };
>> 416
>> 417 BUCK6 {
>> 418 regulator-name = "BUCK6";
>> 419 regulator-min-microvolt = <1045000>;
>> 420 regulator-max-microvolt = <1155000>;
>> 421 regulator-boot-on;
>> 422 regulator-always-on;
>> 423 };
>> 424
>> 425 LDO1 {
>> 426 regulator-name = "LDO1";
>> 427 regulator-min-microvolt = <1650000>;
>> 428 regulator-max-microvolt = <1950000>;
>> 429 regulator-boot-on;
>> 430 regulator-always-on;
>> 431 };
>> 432
>> 433 LDO3 {
>> 434 regulator-name = "LDO3";
>> 435 regulator-min-microvolt = <1710000>;
>> 436 regulator-max-microvolt = <1890000>;
>> 437 regulator-boot-on;
>> 438 regulator-always-on;
>> 439 };
>> 440
>> 441 LDO5 {
>> 442 regulator-name = "LDO5";
>> 443 regulator-min-microvolt = <1800000>;
>> 444 regulator-max-microvolt = <3300000>;
>> 445 regulator-boot-on;
>> 446 regulator-always-on;
>> 447 };
>> 448 };
>> 449 };
>> 450
460 eeprom@50 { 451 eeprom@50 {
461 compatible = "atmel,24c02"; 452 compatible = "atmel,24c02";
462 reg = <0x50>; 453 reg = <0x50>;
463 pagesize = <16>; 454 pagesize = <16>;
464 }; 455 };
465 456
466 eeprom@51 { 457 eeprom@51 {
467 compatible = "atmel,24c02"; 458 compatible = "atmel,24c02";
468 reg = <0x51>; 459 reg = <0x51>;
469 pagesize = <16>; 460 pagesize = <16>;
470 }; 461 };
471 462
472 eeprom@52 { 463 eeprom@52 {
473 compatible = "atmel,24c02"; 464 compatible = "atmel,24c02";
474 reg = <0x52>; 465 reg = <0x52>;
475 pagesize = <16>; 466 pagesize = <16>;
476 }; 467 };
477 468
478 eeprom@53 { 469 eeprom@53 {
479 compatible = "atmel,24c02"; 470 compatible = "atmel,24c02";
480 reg = <0x53>; 471 reg = <0x53>;
481 pagesize = <16>; 472 pagesize = <16>;
482 }; 473 };
483 474
484 rtc@68 { 475 rtc@68 {
485 compatible = "dallas,ds1672"; 476 compatible = "dallas,ds1672";
486 reg = <0x68>; 477 reg = <0x68>;
487 }; 478 };
488 }; 479 };
489 480
490 &i2c2 { 481 &i2c2 {
491 clock-frequency = <400000>; 482 clock-frequency = <400000>;
492 pinctrl-names = "default", "gpio"; 483 pinctrl-names = "default", "gpio";
493 pinctrl-0 = <&pinctrl_i2c2>; 484 pinctrl-0 = <&pinctrl_i2c2>;
494 pinctrl-1 = <&pinctrl_i2c2_gpio>; 485 pinctrl-1 = <&pinctrl_i2c2_gpio>;
495 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 486 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
496 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 487 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
497 status = "okay"; 488 status = "okay";
498 489
499 accelerometer@19 { 490 accelerometer@19 {
500 compatible = "st,lis2de12"; 491 compatible = "st,lis2de12";
501 pinctrl-names = "default"; 492 pinctrl-names = "default";
502 pinctrl-0 = <&pinctrl_accel>; 493 pinctrl-0 = <&pinctrl_accel>;
503 reg = <0x19>; 494 reg = <0x19>;
504 st,drdy-int-pin = <1>; 495 st,drdy-int-pin = <1>;
505 interrupt-parent = <&gpio1>; 496 interrupt-parent = <&gpio1>;
506 interrupts = <7 IRQ_TYPE_LEVEL 497 interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
>> 498 interrupt-names = "INT1";
507 }; 499 };
508 500
509 switch: switch@5f { 501 switch: switch@5f {
510 compatible = "microchip,ksz989 502 compatible = "microchip,ksz9897";
511 reg = <0x5f>; 503 reg = <0x5f>;
512 pinctrl-0 = <&pinctrl_ksz>; 504 pinctrl-0 = <&pinctrl_ksz>;
513 interrupt-parent = <&gpio4>; 505 interrupt-parent = <&gpio4>;
514 interrupts = <29 IRQ_TYPE_EDGE 506 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
515 507
516 ports { 508 ports {
517 #address-cells = <1>; 509 #address-cells = <1>;
518 #size-cells = <0>; 510 #size-cells = <0>;
519 511
520 lan1: port@0 { 512 lan1: port@0 {
521 reg = <0>; 513 reg = <0>;
522 label = "lan1" 514 label = "lan1";
523 phy-mode = "in 515 phy-mode = "internal";
524 local-mac-addr 516 local-mac-address = [00 00 00 00 00 00];
525 }; 517 };
526 518
527 lan2: port@1 { 519 lan2: port@1 {
528 reg = <1>; 520 reg = <1>;
529 label = "lan2" 521 label = "lan2";
530 phy-mode = "in 522 phy-mode = "internal";
531 local-mac-addr 523 local-mac-address = [00 00 00 00 00 00];
532 }; 524 };
533 525
534 lan3: port@2 { 526 lan3: port@2 {
535 reg = <2>; 527 reg = <2>;
536 label = "lan3" 528 label = "lan3";
537 phy-mode = "in 529 phy-mode = "internal";
538 local-mac-addr 530 local-mac-address = [00 00 00 00 00 00];
539 }; 531 };
540 532
541 lan4: port@3 { 533 lan4: port@3 {
542 reg = <3>; 534 reg = <3>;
543 label = "lan4" 535 label = "lan4";
544 phy-mode = "in 536 phy-mode = "internal";
545 local-mac-addr 537 local-mac-address = [00 00 00 00 00 00];
546 }; 538 };
547 539
548 lan5: port@4 { 540 lan5: port@4 {
549 reg = <4>; 541 reg = <4>;
550 label = "lan5" 542 label = "lan5";
551 phy-mode = "in 543 phy-mode = "internal";
552 local-mac-addr 544 local-mac-address = [00 00 00 00 00 00];
553 }; 545 };
554 546
555 port@5 { 547 port@5 {
556 reg = <5>; 548 reg = <5>;
>> 549 label = "cpu";
557 ethernet = <&f 550 ethernet = <&fec>;
558 phy-mode = "rg 551 phy-mode = "rgmii-id";
559 552
560 fixed-link { 553 fixed-link {
561 speed 554 speed = <1000>;
562 full-d 555 full-duplex;
563 }; 556 };
564 }; 557 };
565 }; 558 };
566 }; 559 };
567 }; 560 };
568 561
>> 562 /* off-board header */
569 &i2c3 { 563 &i2c3 {
570 clock-frequency = <400000>; 564 clock-frequency = <400000>;
571 pinctrl-names = "default", "gpio"; 565 pinctrl-names = "default", "gpio";
572 pinctrl-0 = <&pinctrl_i2c3>; 566 pinctrl-0 = <&pinctrl_i2c3>;
573 pinctrl-1 = <&pinctrl_i2c3_gpio>; 567 pinctrl-1 = <&pinctrl_i2c3_gpio>;
574 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 568 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
575 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 569 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
576 status = "okay"; 570 status = "okay";
577 <<
578 pmic@25 { <<
579 compatible = "nxp,pca9450c"; <<
580 reg = <0x25>; <<
581 pinctrl-names = "default"; <<
582 pinctrl-0 = <&pinctrl_pmic>; <<
583 interrupt-parent = <&gpio3>; <<
584 interrupts = <7 IRQ_TYPE_LEVEL <<
585 <<
586 regulators { <<
587 BUCK1 { <<
588 regulator-name <<
589 regulator-min- <<
590 regulator-max- <<
591 regulator-boot <<
592 regulator-alwa <<
593 regulator-ramp <<
594 }; <<
595 <<
596 reg_arm: BUCK2 { <<
597 regulator-name <<
598 regulator-min- <<
599 regulator-max- <<
600 regulator-boot <<
601 regulator-alwa <<
602 regulator-ramp <<
603 nxp,dvs-run-vo <<
604 nxp,dvs-standb <<
605 }; <<
606 <<
607 BUCK4 { <<
608 regulator-name <<
609 regulator-min- <<
610 regulator-max- <<
611 regulator-boot <<
612 regulator-alwa <<
613 }; <<
614 <<
615 BUCK5 { <<
616 regulator-name <<
617 regulator-min- <<
618 regulator-max- <<
619 regulator-boot <<
620 regulator-alwa <<
621 }; <<
622 <<
623 BUCK6 { <<
624 regulator-name <<
625 regulator-min- <<
626 regulator-max- <<
627 regulator-boot <<
628 regulator-alwa <<
629 }; <<
630 <<
631 LDO1 { <<
632 regulator-name <<
633 regulator-min- <<
634 regulator-max- <<
635 regulator-boot <<
636 regulator-alwa <<
637 }; <<
638 <<
639 LDO3 { <<
640 regulator-name <<
641 regulator-min- <<
642 regulator-max- <<
643 regulator-boot <<
644 regulator-alwa <<
645 }; <<
646 <<
647 LDO5 { <<
648 regulator-name <<
649 regulator-min- <<
650 regulator-max- <<
651 regulator-boot <<
652 regulator-alwa <<
653 }; <<
654 }; <<
655 }; <<
656 }; 571 };
657 572
658 /* off-board header */ 573 /* off-board header */
659 &i2c4 { 574 &i2c4 {
660 clock-frequency = <400000>; 575 clock-frequency = <400000>;
661 pinctrl-names = "default", "gpio"; 576 pinctrl-names = "default", "gpio";
662 pinctrl-0 = <&pinctrl_i2c4>; 577 pinctrl-0 = <&pinctrl_i2c4>;
663 pinctrl-1 = <&pinctrl_i2c4_gpio>; 578 pinctrl-1 = <&pinctrl_i2c4_gpio>;
664 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 579 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
665 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 580 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
666 status = "okay"; 581 status = "okay";
667 }; 582 };
668 583
669 &pcie_phy { 584 &pcie_phy {
670 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL 585 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>;
671 fsl,clkreq-unsupported; 586 fsl,clkreq-unsupported;
672 clocks = <&pcie0_refclk>; 587 clocks = <&pcie0_refclk>;
673 clock-names = "ref"; 588 clock-names = "ref";
674 status = "okay"; 589 status = "okay";
675 }; 590 };
676 591
677 &pcie { 592 &pcie {
678 pinctrl-names = "default"; 593 pinctrl-names = "default";
679 pinctrl-0 = <&pinctrl_pcie0>; 594 pinctrl-0 = <&pinctrl_pcie0>;
680 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LO 595 reset-gpio = <&gpio2 17 GPIO_ACTIVE_LOW>;
681 status = "okay"; 596 status = "okay";
682 }; 597 };
683 598
684 /* GPS / off-board header */ 599 /* GPS / off-board header */
685 &uart1 { 600 &uart1 {
686 pinctrl-names = "default"; 601 pinctrl-names = "default";
687 pinctrl-0 = <&pinctrl_uart1>; 602 pinctrl-0 = <&pinctrl_uart1>;
688 status = "okay"; 603 status = "okay";
689 }; 604 };
690 605
691 /* RS232 console */ 606 /* RS232 console */
692 &uart2 { 607 &uart2 {
693 pinctrl-names = "default"; 608 pinctrl-names = "default";
694 pinctrl-0 = <&pinctrl_uart2>; 609 pinctrl-0 = <&pinctrl_uart2>;
695 status = "okay"; 610 status = "okay";
696 }; 611 };
697 612
698 /* bluetooth HCI */ 613 /* bluetooth HCI */
699 &uart3 { 614 &uart3 {
700 pinctrl-names = "default"; 615 pinctrl-names = "default";
701 pinctrl-0 = <&pinctrl_uart3>, <&pinctr 616 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_uart3_gpio>;
702 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW 617 cts-gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
703 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW 618 rts-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
704 status = "okay"; 619 status = "okay";
705 620
706 bluetooth { 621 bluetooth {
707 compatible = "brcm,bcm4330-bt" 622 compatible = "brcm,bcm4330-bt";
708 shutdown-gpios = <&gpio3 8 GPI 623 shutdown-gpios = <&gpio3 8 GPIO_ACTIVE_HIGH>;
709 }; 624 };
710 }; 625 };
711 626
712 &uart4 { 627 &uart4 {
713 pinctrl-names = "default"; 628 pinctrl-names = "default";
714 pinctrl-0 = <&pinctrl_uart4>; 629 pinctrl-0 = <&pinctrl_uart4>;
715 status = "okay"; 630 status = "okay";
716 }; 631 };
717 632
718 /* USB1 - Type C front panel */ 633 /* USB1 - Type C front panel */
719 &usb3_0 { 634 &usb3_0 {
720 pinctrl-names = "default"; 635 pinctrl-names = "default";
721 pinctrl-0 = <&pinctrl_usb1>; 636 pinctrl-0 = <&pinctrl_usb1>;
722 fsl,over-current-active-low; 637 fsl,over-current-active-low;
723 status = "okay"; 638 status = "okay";
724 }; 639 };
725 640
726 &usb3_phy0 { 641 &usb3_phy0 {
727 status = "okay"; 642 status = "okay";
728 }; 643 };
729 644
730 &usb_dwc3_0 { 645 &usb_dwc3_0 {
731 /* dual role is implemented but not a 646 /* dual role is implemented but not a full featured OTG */
732 adp-disable; 647 adp-disable;
733 hnp-disable; 648 hnp-disable;
734 srp-disable; 649 srp-disable;
735 dr_mode = "otg"; 650 dr_mode = "otg";
736 usb-role-switch; 651 usb-role-switch;
737 role-switch-default-mode = "peripheral 652 role-switch-default-mode = "peripheral";
738 status = "okay"; 653 status = "okay";
739 654
740 port { !! 655 connector {
741 usb3_dwc: endpoint { !! 656 pinctrl-names = "default";
742 remote-endpoint = <&us !! 657 pinctrl-0 = <&pinctrl_usbcon1>;
743 }; !! 658 compatible = "gpio-usb-b-connector", "usb-b-connector";
>> 659 type = "micro";
>> 660 label = "Type-C";
>> 661 id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
744 }; 662 };
745 }; 663 };
746 664
747 /* USB2 - USB3.0 Hub */ 665 /* USB2 - USB3.0 Hub */
748 &usb3_phy1 { 666 &usb3_phy1 {
749 vbus-supply = <®_usb2_vbus>; 667 vbus-supply = <®_usb2_vbus>;
750 status = "okay"; 668 status = "okay";
751 }; 669 };
752 670
753 &usb3_1 { 671 &usb3_1 {
754 fsl,permanently-attached; 672 fsl,permanently-attached;
755 fsl,disable-port-power-control; 673 fsl,disable-port-power-control;
756 status = "okay"; 674 status = "okay";
757 }; 675 };
758 676
759 &usb_dwc3_1 { 677 &usb_dwc3_1 {
760 dr_mode = "host"; 678 dr_mode = "host";
761 status = "okay"; 679 status = "okay";
762 }; 680 };
763 681
764 /* SDIO WiFi */ 682 /* SDIO WiFi */
765 &usdhc1 { 683 &usdhc1 {
766 pinctrl-names = "default", "state_100m 684 pinctrl-names = "default", "state_100mhz", "state_200mhz";
767 pinctrl-0 = <&pinctrl_usdhc1>; 685 pinctrl-0 = <&pinctrl_usdhc1>;
768 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 686 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
769 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 687 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
770 bus-width = <4>; 688 bus-width = <4>;
771 non-removable; 689 non-removable;
772 vmmc-supply = <®_wifi_en>; 690 vmmc-supply = <®_wifi_en>;
773 #address-cells = <1>; 691 #address-cells = <1>;
774 #size-cells = <0>; 692 #size-cells = <0>;
775 status = "okay"; 693 status = "okay";
776 694
777 wifi@0 { 695 wifi@0 {
778 compatible = "cypress,cyw4373- !! 696 compatible = "cypress,cyw4373-fmac";
779 reg = <0>; 697 reg = <0>;
780 }; 698 };
781 }; 699 };
782 700
783 /* eMMC */ 701 /* eMMC */
784 &usdhc3 { 702 &usdhc3 {
785 assigned-clocks = <&clk IMX8MP_CLK_USD 703 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>;
786 assigned-clock-rates = <400000000>; 704 assigned-clock-rates = <400000000>;
787 pinctrl-names = "default", "state_100m 705 pinctrl-names = "default", "state_100mhz", "state_200mhz";
788 pinctrl-0 = <&pinctrl_usdhc3>; 706 pinctrl-0 = <&pinctrl_usdhc3>;
789 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 707 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
790 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 708 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
791 bus-width = <8>; 709 bus-width = <8>;
792 non-removable; 710 non-removable;
793 status = "okay"; 711 status = "okay";
794 }; 712 };
795 713
796 &wdog1 { 714 &wdog1 {
797 pinctrl-names = "default"; 715 pinctrl-names = "default";
798 pinctrl-0 = <&pinctrl_wdog>; 716 pinctrl-0 = <&pinctrl_wdog>;
799 fsl,ext-reset-output; 717 fsl,ext-reset-output;
800 status = "okay"; 718 status = "okay";
801 }; 719 };
802 720
803 &iomuxc { 721 &iomuxc {
804 pinctrl-names = "default"; 722 pinctrl-names = "default";
805 pinctrl-0 = <&pinctrl_hog>; 723 pinctrl-0 = <&pinctrl_hog>;
806 724
807 pinctrl_hog: hoggrp { 725 pinctrl_hog: hoggrp {
808 fsl,pins = < 726 fsl,pins = <
809 MX8MP_IOMUXC_GPIO1_IO0 727 MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
810 MX8MP_IOMUXC_GPIO1_IO1 728 MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
811 MX8MP_IOMUXC_SAI1_RXD0 !! 729 MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
812 MX8MP_IOMUXC_SAI1_TXD6 <<
813 MX8MP_IOMUXC_SD1_DATA4 <<
814 MX8MP_IOMUXC_SD1_STROB <<
815 MX8MP_IOMUXC_SD2_CLK__ <<
816 MX8MP_IOMUXC_SD2_CMD__ <<
817 MX8MP_IOMUXC_SD2_DATA3 730 MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
>> 731 MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
818 MX8MP_IOMUXC_NAND_DATA 732 MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
>> 733 MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
>> 734 MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
819 MX8MP_IOMUXC_SAI3_TXD_ 735 MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
820 MX8MP_IOMUXC_SAI3_TXFS 736 MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
821 MX8MP_IOMUXC_SAI3_TXC_ 737 MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
822 >; 738 >;
823 }; 739 };
824 740
825 pinctrl_accel: accelgrp { 741 pinctrl_accel: accelgrp {
826 fsl,pins = < 742 fsl,pins = <
827 MX8MP_IOMUXC_GPIO1_IO0 743 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
828 >; 744 >;
829 }; 745 };
830 746
831 pinctrl_eqos: eqosgrp { 747 pinctrl_eqos: eqosgrp {
832 fsl,pins = < 748 fsl,pins = <
833 MX8MP_IOMUXC_ENET_MDC_ 749 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
834 MX8MP_IOMUXC_ENET_MDIO 750 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
835 MX8MP_IOMUXC_ENET_RD0_ 751 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
836 MX8MP_IOMUXC_ENET_RD1_ 752 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
837 MX8MP_IOMUXC_ENET_RD2_ 753 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
838 MX8MP_IOMUXC_ENET_RD3_ 754 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
839 MX8MP_IOMUXC_ENET_RXC_ 755 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
840 MX8MP_IOMUXC_ENET_RX_C 756 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
841 MX8MP_IOMUXC_ENET_TD0_ 757 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
842 MX8MP_IOMUXC_ENET_TD1_ 758 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
843 MX8MP_IOMUXC_ENET_TD2_ 759 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
844 MX8MP_IOMUXC_ENET_TD3_ 760 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
845 MX8MP_IOMUXC_ENET_TX_C 761 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
846 MX8MP_IOMUXC_ENET_TXC_ 762 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
847 MX8MP_IOMUXC_SAI3_RXD_ 763 MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
848 MX8MP_IOMUXC_SAI3_RXFS 764 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
849 >; 765 >;
850 }; 766 };
851 767
852 pinctrl_fec: fecgrp { 768 pinctrl_fec: fecgrp {
853 fsl,pins = < 769 fsl,pins = <
854 MX8MP_IOMUXC_SAI1_RXD4 770 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
855 MX8MP_IOMUXC_SAI1_RXD5 771 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
856 MX8MP_IOMUXC_SAI1_RXD6 772 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
857 MX8MP_IOMUXC_SAI1_RXD7 773 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
858 MX8MP_IOMUXC_SAI1_TXC_ 774 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
859 MX8MP_IOMUXC_SAI1_TXFS 775 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
860 MX8MP_IOMUXC_SAI1_TXD0 776 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
861 MX8MP_IOMUXC_SAI1_TXD1 777 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
862 MX8MP_IOMUXC_SAI1_TXD2 778 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
863 MX8MP_IOMUXC_SAI1_TXD3 779 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
864 MX8MP_IOMUXC_SAI1_TXD4 780 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
865 MX8MP_IOMUXC_SAI1_TXD5 781 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
866 MX8MP_IOMUXC_SAI1_RXFS 782 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
867 MX8MP_IOMUXC_SAI1_RXC_ 783 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
868 >; 784 >;
869 }; 785 };
870 786
871 pinctrl_flexcan1: flexcan1grp { <<
872 fsl,pins = < <<
873 MX8MP_IOMUXC_SPDIF_RX_ <<
874 MX8MP_IOMUXC_SPDIF_TX_ <<
875 >; <<
876 }; <<
877 <<
878 pinctrl_flexcan2: flexcan2grp { 787 pinctrl_flexcan2: flexcan2grp {
879 fsl,pins = < 788 fsl,pins = <
880 MX8MP_IOMUXC_SAI5_RXD3 789 MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154
881 MX8MP_IOMUXC_SAI5_MCLK 790 MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154
882 >; 791 >;
883 }; 792 };
884 793
885 pinctrl_gsc: gscgrp { 794 pinctrl_gsc: gscgrp {
886 fsl,pins = < 795 fsl,pins = <
887 MX8MP_IOMUXC_SAI1_MCLK 796 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
888 >; 797 >;
889 }; 798 };
890 799
891 pinctrl_i2c1: i2c1grp { 800 pinctrl_i2c1: i2c1grp {
892 fsl,pins = < 801 fsl,pins = <
893 MX8MP_IOMUXC_I2C1_SCL_ 802 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
894 MX8MP_IOMUXC_I2C1_SDA_ 803 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
895 >; 804 >;
896 }; 805 };
897 806
898 pinctrl_i2c1_gpio: i2c1gpiogrp { 807 pinctrl_i2c1_gpio: i2c1gpiogrp {
899 fsl,pins = < 808 fsl,pins = <
900 MX8MP_IOMUXC_I2C1_SCL_ 809 MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c2
901 MX8MP_IOMUXC_I2C1_SDA_ 810 MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c2
902 >; 811 >;
903 }; 812 };
904 813
905 pinctrl_i2c2: i2c2grp { 814 pinctrl_i2c2: i2c2grp {
906 fsl,pins = < 815 fsl,pins = <
907 MX8MP_IOMUXC_I2C2_SCL_ 816 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
908 MX8MP_IOMUXC_I2C2_SDA_ 817 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
909 >; 818 >;
910 }; 819 };
911 820
912 pinctrl_i2c2_gpio: i2c2gpiogrp { 821 pinctrl_i2c2_gpio: i2c2gpiogrp {
913 fsl,pins = < 822 fsl,pins = <
914 MX8MP_IOMUXC_I2C2_SCL_ 823 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c3
915 MX8MP_IOMUXC_I2C2_SDA_ 824 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c3
916 >; 825 >;
917 }; 826 };
918 827
919 pinctrl_i2c3: i2c3grp { 828 pinctrl_i2c3: i2c3grp {
920 fsl,pins = < 829 fsl,pins = <
921 MX8MP_IOMUXC_I2C3_SCL_ 830 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
922 MX8MP_IOMUXC_I2C3_SDA_ 831 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
923 >; 832 >;
924 }; 833 };
925 834
926 pinctrl_i2c3_gpio: i2c3gpiogrp { 835 pinctrl_i2c3_gpio: i2c3gpiogrp {
927 fsl,pins = < 836 fsl,pins = <
928 MX8MP_IOMUXC_I2C3_SCL_ 837 MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c3
929 MX8MP_IOMUXC_I2C3_SDA_ 838 MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c3
930 >; 839 >;
931 }; 840 };
932 841
933 pinctrl_i2c4: i2c4grp { 842 pinctrl_i2c4: i2c4grp {
934 fsl,pins = < 843 fsl,pins = <
935 MX8MP_IOMUXC_I2C4_SCL_ 844 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
936 MX8MP_IOMUXC_I2C4_SDA_ 845 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
937 >; 846 >;
938 }; 847 };
939 848
940 pinctrl_i2c4_gpio: i2c4gpiogrp { 849 pinctrl_i2c4_gpio: i2c4gpiogrp {
941 fsl,pins = < 850 fsl,pins = <
942 MX8MP_IOMUXC_I2C4_SCL_ 851 MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c3
943 MX8MP_IOMUXC_I2C4_SDA_ 852 MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c3
944 >; 853 >;
945 }; 854 };
946 855
947 pinctrl_ksz: kszgrp { 856 pinctrl_ksz: kszgrp {
948 fsl,pins = < 857 fsl,pins = <
949 MX8MP_IOMUXC_SAI3_RXC_ 858 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
950 MX8MP_IOMUXC_SAI3_MCLK 859 MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
951 >; 860 >;
952 }; 861 };
953 862
954 pinctrl_gpio_leds: ledgrp { 863 pinctrl_gpio_leds: ledgrp {
955 fsl,pins = < 864 fsl,pins = <
956 MX8MP_IOMUXC_SD2_DATA0 865 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
957 MX8MP_IOMUXC_SD2_DATA1 866 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
958 >; 867 >;
959 }; 868 };
960 869
961 pinctrl_pcie0: pciegrp { 870 pinctrl_pcie0: pciegrp {
962 fsl,pins = < 871 fsl,pins = <
963 MX8MP_IOMUXC_SD2_DATA2 !! 872 MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x110
964 >; 873 >;
965 }; 874 };
966 875
967 pinctrl_pmic: pmicgrp { 876 pinctrl_pmic: pmicgrp {
968 fsl,pins = < 877 fsl,pins = <
969 MX8MP_IOMUXC_NAND_DATA 878 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
970 >; 879 >;
971 }; 880 };
972 881
973 pinctrl_pps: ppsgrp { 882 pinctrl_pps: ppsgrp {
974 fsl,pins = < 883 fsl,pins = <
975 MX8MP_IOMUXC_GPIO1_IO1 884 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
976 >; 885 >;
977 }; 886 };
978 887
979 pinctrl_reg_can1: regcan1grp { !! 888 pinctrl_reg_can: regcangrp {
980 fsl,pins = < 889 fsl,pins = <
981 MX8MP_IOMUXC_SAI5_RXFS 890 MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x154
982 >; 891 >;
983 }; 892 };
984 893
985 pinctrl_reg_can2: regcan2grp { <<
986 fsl,pins = < <<
987 MX8MP_IOMUXC_SPDIF_EXT <<
988 >; <<
989 }; <<
990 <<
991 pinctrl_reg_usb2: regusb2grp { 894 pinctrl_reg_usb2: regusb2grp {
992 fsl,pins = < 895 fsl,pins = <
993 MX8MP_IOMUXC_GPIO1_IO0 896 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
994 >; 897 >;
995 }; 898 };
996 899
997 pinctrl_reg_wifi: regwifigrp { 900 pinctrl_reg_wifi: regwifigrp {
998 fsl,pins = < 901 fsl,pins = <
999 MX8MP_IOMUXC_NAND_DATA 902 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
1000 >; 903 >;
1001 }; 904 };
1002 905
1003 pinctrl_spi1: spi1grp { !! 906 pinctrl_sai2: sai2grp {
1004 fsl,pins = < 907 fsl,pins = <
1005 MX8MP_IOMUXC_ECSPI1_S !! 908 MX8MP_IOMUXC_SAI2_TXFS__AUDIOMIX_SAI2_TX_SYNC 0xd6
1006 MX8MP_IOMUXC_ECSPI1_M !! 909 MX8MP_IOMUXC_SAI2_TXD0__AUDIOMIX_SAI2_TX_DATA00 0xd6
1007 MX8MP_IOMUXC_ECSPI1_M !! 910 MX8MP_IOMUXC_SAI2_TXC__AUDIOMIX_SAI2_TX_BCLK 0xd6
1008 MX8MP_IOMUXC_ECSPI1_S !! 911 MX8MP_IOMUXC_SAI2_MCLK__AUDIOMIX_SAI2_MCLK 0xd6
1009 >; 912 >;
1010 }; 913 };
1011 914
1012 pinctrl_spi2: spi2grp { 915 pinctrl_spi2: spi2grp {
1013 fsl,pins = < 916 fsl,pins = <
1014 MX8MP_IOMUXC_ECSPI2_S 917 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x82
1015 MX8MP_IOMUXC_ECSPI2_M 918 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x82
1016 MX8MP_IOMUXC_ECSPI2_M 919 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x82
1017 MX8MP_IOMUXC_ECSPI2_S 920 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140
1018 >; 921 >;
1019 }; 922 };
1020 923
1021 pinctrl_uart1: uart1grp { 924 pinctrl_uart1: uart1grp {
1022 fsl,pins = < 925 fsl,pins = <
1023 MX8MP_IOMUXC_UART1_RX 926 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
1024 MX8MP_IOMUXC_UART1_TX 927 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
1025 >; 928 >;
1026 }; 929 };
1027 930
1028 pinctrl_uart2: uart2grp { 931 pinctrl_uart2: uart2grp {
1029 fsl,pins = < 932 fsl,pins = <
1030 MX8MP_IOMUXC_UART2_RX 933 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
1031 MX8MP_IOMUXC_UART2_TX 934 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
1032 >; 935 >;
1033 }; 936 };
1034 937
1035 pinctrl_uart3: uart3grp { 938 pinctrl_uart3: uart3grp {
1036 fsl,pins = < 939 fsl,pins = <
1037 MX8MP_IOMUXC_UART3_RX 940 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140
1038 MX8MP_IOMUXC_UART3_TX 941 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140
1039 MX8MP_IOMUXC_SAI5_RXD 942 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140
1040 MX8MP_IOMUXC_SAI5_RXD 943 MX8MP_IOMUXC_SAI5_RXD1__GPIO3_IO22 0x140
1041 >; 944 >;
1042 }; 945 };
1043 946
1044 pinctrl_uart3_gpio: uart3gpiogrp { 947 pinctrl_uart3_gpio: uart3gpiogrp {
1045 fsl,pins = < 948 fsl,pins = <
1046 MX8MP_IOMUXC_NAND_DAT 949 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
1047 >; 950 >;
1048 }; 951 };
1049 952
1050 pinctrl_uart4: uart4grp { 953 pinctrl_uart4: uart4grp {
1051 fsl,pins = < 954 fsl,pins = <
1052 MX8MP_IOMUXC_UART4_RX 955 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140
1053 MX8MP_IOMUXC_UART4_TX 956 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140
1054 >; 957 >;
1055 }; 958 };
1056 959
1057 pinctrl_usb1: usb1grp { 960 pinctrl_usb1: usb1grp {
1058 fsl,pins = < 961 fsl,pins = <
1059 MX8MP_IOMUXC_GPIO1_IO 962 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140
1060 >; 963 >;
1061 }; 964 };
1062 965
1063 pinctrl_usbcon1: usb1congrp { 966 pinctrl_usbcon1: usb1congrp {
1064 fsl,pins = < 967 fsl,pins = <
1065 MX8MP_IOMUXC_GPIO1_IO 968 MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140
1066 >; 969 >;
1067 }; 970 };
1068 971
1069 pinctrl_usdhc1: usdhc1grp { 972 pinctrl_usdhc1: usdhc1grp {
1070 fsl,pins = < 973 fsl,pins = <
1071 MX8MP_IOMUXC_SD1_CLK_ 974 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190
1072 MX8MP_IOMUXC_SD1_CMD_ 975 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0
1073 MX8MP_IOMUXC_SD1_DATA 976 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
1074 MX8MP_IOMUXC_SD1_DATA 977 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
1075 MX8MP_IOMUXC_SD1_DATA 978 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
1076 MX8MP_IOMUXC_SD1_DATA 979 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
1077 >; 980 >;
1078 }; 981 };
1079 982
1080 pinctrl_usdhc1_100mhz: usdhc1-100mhzg 983 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1081 fsl,pins = < 984 fsl,pins = <
1082 MX8MP_IOMUXC_SD1_CLK_ 985 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194
1083 MX8MP_IOMUXC_SD1_CMD_ 986 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4
1084 MX8MP_IOMUXC_SD1_DATA 987 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
1085 MX8MP_IOMUXC_SD1_DATA 988 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
1086 MX8MP_IOMUXC_SD1_DATA 989 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
1087 MX8MP_IOMUXC_SD1_DATA 990 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
1088 >; 991 >;
1089 }; 992 };
1090 993
1091 pinctrl_usdhc1_200mhz: usdhc1-200mhzg 994 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1092 fsl,pins = < 995 fsl,pins = <
1093 MX8MP_IOMUXC_SD1_CLK_ 996 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196
1094 MX8MP_IOMUXC_SD1_CMD_ 997 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6
1095 MX8MP_IOMUXC_SD1_DATA 998 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
1096 MX8MP_IOMUXC_SD1_DATA 999 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
1097 MX8MP_IOMUXC_SD1_DATA 1000 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
1098 MX8MP_IOMUXC_SD1_DATA 1001 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
1099 >; 1002 >;
1100 }; 1003 };
1101 1004
1102 pinctrl_usdhc3: usdhc3grp { 1005 pinctrl_usdhc3: usdhc3grp {
1103 fsl,pins = < 1006 fsl,pins = <
1104 MX8MP_IOMUXC_NAND_WE_ 1007 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
1105 MX8MP_IOMUXC_NAND_WP_ 1008 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
1106 MX8MP_IOMUXC_NAND_DAT 1009 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
1107 MX8MP_IOMUXC_NAND_DAT 1010 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
1108 MX8MP_IOMUXC_NAND_DAT 1011 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
1109 MX8MP_IOMUXC_NAND_DAT 1012 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
1110 MX8MP_IOMUXC_NAND_RE_ 1013 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
1111 MX8MP_IOMUXC_NAND_CE2 1014 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
1112 MX8MP_IOMUXC_NAND_CE3 1015 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
1113 MX8MP_IOMUXC_NAND_CLE 1016 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
1114 MX8MP_IOMUXC_NAND_CE1 1017 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
1115 >; 1018 >;
1116 }; 1019 };
1117 1020
1118 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1021 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1119 fsl,pins = < 1022 fsl,pins = <
1120 MX8MP_IOMUXC_NAND_WE_ 1023 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
1121 MX8MP_IOMUXC_NAND_WP_ 1024 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
1122 MX8MP_IOMUXC_NAND_DAT 1025 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
1123 MX8MP_IOMUXC_NAND_DAT 1026 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
1124 MX8MP_IOMUXC_NAND_DAT 1027 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
1125 MX8MP_IOMUXC_NAND_DAT 1028 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
1126 MX8MP_IOMUXC_NAND_RE_ 1029 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
1127 MX8MP_IOMUXC_NAND_CE2 1030 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
1128 MX8MP_IOMUXC_NAND_CE3 1031 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
1129 MX8MP_IOMUXC_NAND_CLE 1032 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
1130 MX8MP_IOMUXC_NAND_CE1 1033 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
1131 >; 1034 >;
1132 }; 1035 };
1133 1036
1134 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1037 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1135 fsl,pins = < 1038 fsl,pins = <
1136 MX8MP_IOMUXC_NAND_WE_ 1039 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
1137 MX8MP_IOMUXC_NAND_WP_ 1040 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
1138 MX8MP_IOMUXC_NAND_DAT 1041 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6
1139 MX8MP_IOMUXC_NAND_DAT 1042 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6
1140 MX8MP_IOMUXC_NAND_DAT 1043 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6
1141 MX8MP_IOMUXC_NAND_DAT 1044 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6
1142 MX8MP_IOMUXC_NAND_RE_ 1045 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6
1143 MX8MP_IOMUXC_NAND_CE2 1046 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6
1144 MX8MP_IOMUXC_NAND_CE3 1047 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6
1145 MX8MP_IOMUXC_NAND_CLE 1048 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6
1146 MX8MP_IOMUXC_NAND_CE1 1049 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
1147 >; 1050 >;
1148 }; 1051 };
1149 1052
1150 pinctrl_wdog: wdoggrp { 1053 pinctrl_wdog: wdoggrp {
1151 fsl,pins = < 1054 fsl,pins = <
1152 MX8MP_IOMUXC_GPIO1_IO 1055 MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0x166
1153 >; 1056 >;
1154 }; 1057 };
1155 }; 1058 };
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