1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2022 Toradex 3 * Copyright 2022 Toradex
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy-imx8-pcie.h> !! 6 #include "dt-bindings/pwm/pwm.h"
7 #include <dt-bindings/pwm/pwm.h> <<
8 #include "imx8mp.dtsi" 7 #include "imx8mp.dtsi"
9 8
10 / { 9 / {
11 chosen { 10 chosen {
12 stdout-path = &uart3; 11 stdout-path = &uart3;
13 }; 12 };
14 13
15 aliases { 14 aliases {
16 /* Ethernet aliases to ensure 15 /* Ethernet aliases to ensure correct MAC addresses */
17 ethernet0 = &eqos; 16 ethernet0 = &eqos;
18 ethernet1 = &fec; 17 ethernet1 = &fec;
19 rtc0 = &rtc_i2c; 18 rtc0 = &rtc_i2c;
20 rtc1 = &snvs_rtc; 19 rtc1 = &snvs_rtc;
21 }; 20 };
22 21
23 backlight: backlight { 22 backlight: backlight {
24 compatible = "pwm-backlight"; 23 compatible = "pwm-backlight";
25 brightness-levels = <0 45 63 8 24 brightness-levels = <0 45 63 88 119 158 203 255>;
26 default-brightness-level = <4> 25 default-brightness-level = <4>;
27 /* Verdin I2S_2_D_OUT (DSI_1_B 26 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
28 enable-gpios = <&gpio5 1 GPIO_ 27 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
29 pinctrl-names = "default"; 28 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2s_2_d_ 29 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
31 power-supply = <®_3p3v>; 30 power-supply = <®_3p3v>;
32 /* Verdin PWM_3_DSI/PWM_3_DSI_ 31 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
33 pwms = <&pwm3 0 6666667 PWM_PO 32 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
34 status = "disabled"; 33 status = "disabled";
35 }; 34 };
36 35
37 backlight_mezzanine: backlight-mezzani 36 backlight_mezzanine: backlight-mezzanine {
38 compatible = "pwm-backlight"; 37 compatible = "pwm-backlight";
39 brightness-levels = <0 45 63 8 38 brightness-levels = <0 45 63 88 119 158 203 255>;
40 default-brightness-level = <4> 39 default-brightness-level = <4>;
41 /* Verdin GPIO 4 (SODIMM 212) 40 /* Verdin GPIO 4 (SODIMM 212) */
42 enable-gpios = <&gpio1 6 GPIO_ 41 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
43 /* Verdin PWM_2 (SODIMM 16) */ 42 /* Verdin PWM_2 (SODIMM 16) */
44 pwms = <&pwm2 0 6666667 PWM_PO 43 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
45 status = "disabled"; 44 status = "disabled";
46 }; 45 };
47 46
48 connector { <<
49 compatible = "gpio-usb-b-conne <<
50 id-gpios = <&gpio2 10 GPIO_ACT <<
51 label = "Type-C"; <<
52 pinctrl-names = "default"; <<
53 pinctrl-0 = <&pinctrl_usb_1_id <<
54 self-powered; <<
55 type = "micro"; <<
56 vbus-supply = <®_usb1_vbus> <<
57 <<
58 port { <<
59 usb_dr_connector: endp <<
60 remote-endpoin <<
61 }; <<
62 }; <<
63 }; <<
64 <<
65 gpio-keys { 47 gpio-keys {
66 compatible = "gpio-keys"; 48 compatible = "gpio-keys";
67 pinctrl-names = "default"; 49 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_gpio_key 50 pinctrl-0 = <&pinctrl_gpio_keys>;
69 51
70 key-wakeup { !! 52 wakeup {
71 debounce-interval = <1 53 debounce-interval = <10>;
72 /* Verdin CTRL_WAKE1_M 54 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
73 gpios = <&gpio4 0 GPIO 55 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
74 label = "Wake-Up"; 56 label = "Wake-Up";
75 linux,code = <KEY_WAKE 57 linux,code = <KEY_WAKEUP>;
76 wakeup-source; 58 wakeup-source;
77 }; 59 };
78 }; 60 };
79 61
80 sound_hdmi: sound-hdmi { <<
81 compatible = "fsl,imx-audio-hd <<
82 model = "audio-hdmi"; <<
83 audio-cpu = <&aud2htx>; <<
84 hdmi-out; <<
85 status = "disabled"; <<
86 }; <<
87 <<
88 /* Carrier Board Supplies */ 62 /* Carrier Board Supplies */
89 reg_1p8v: regulator-1p8v { 63 reg_1p8v: regulator-1p8v {
90 compatible = "regulator-fixed" 64 compatible = "regulator-fixed";
91 regulator-max-microvolt = <180 65 regulator-max-microvolt = <1800000>;
92 regulator-min-microvolt = <180 66 regulator-min-microvolt = <1800000>;
93 regulator-name = "+V1.8_SW"; 67 regulator-name = "+V1.8_SW";
94 }; 68 };
95 69
96 reg_3p3v: regulator-3p3v { 70 reg_3p3v: regulator-3p3v {
97 compatible = "regulator-fixed" 71 compatible = "regulator-fixed";
98 regulator-max-microvolt = <330 72 regulator-max-microvolt = <3300000>;
99 regulator-min-microvolt = <330 73 regulator-min-microvolt = <3300000>;
100 regulator-name = "+V3.3_SW"; 74 regulator-name = "+V3.3_SW";
101 }; 75 };
102 76
103 reg_5p0v: regulator-5p0v { 77 reg_5p0v: regulator-5p0v {
104 compatible = "regulator-fixed" 78 compatible = "regulator-fixed";
105 regulator-max-microvolt = <500 79 regulator-max-microvolt = <5000000>;
106 regulator-min-microvolt = <500 80 regulator-min-microvolt = <5000000>;
107 regulator-name = "+V5_SW"; 81 regulator-name = "+V5_SW";
108 }; 82 };
109 83
110 /* Non PMIC On-module Supplies */ 84 /* Non PMIC On-module Supplies */
111 reg_module_eth1phy: regulator-module-e 85 reg_module_eth1phy: regulator-module-eth1phy {
112 compatible = "regulator-fixed" 86 compatible = "regulator-fixed";
113 enable-active-high; 87 enable-active-high;
114 gpio = <&gpio2 20 GPIO_ACTIVE_ 88 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
115 off-on-delay-us = <500000>; !! 89 off-on-delay = <500000>;
116 pinctrl-names = "default"; 90 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_reg_eth> 91 pinctrl-0 = <&pinctrl_reg_eth>;
118 regulator-always-on; 92 regulator-always-on;
119 regulator-boot-on; 93 regulator-boot-on;
120 regulator-max-microvolt = <330 94 regulator-max-microvolt = <3300000>;
121 regulator-min-microvolt = <330 95 regulator-min-microvolt = <3300000>;
122 regulator-name = "On-module +V 96 regulator-name = "On-module +V3.3_ETH";
123 startup-delay-us = <200000>; 97 startup-delay-us = <200000>;
124 vin-supply = <®_vdd_3v3>; 98 vin-supply = <®_vdd_3v3>;
125 }; 99 };
126 100
127 /* <<
128 * By default we enable CTRL_SLEEP_MOC <<
129 * peripherals on the carrier board po <<
130 * If more granularity or power saving <<
131 * in the carrier board device tree fi <<
132 */ <<
133 reg_force_sleep_moci: regulator-force- <<
134 compatible = "regulator-fixed" <<
135 enable-active-high; <<
136 /* Verdin CTRL_SLEEP_MOCI# (SO <<
137 gpio = <&gpio4 29 GPIO_ACTIVE_ <<
138 regulator-always-on; <<
139 regulator-boot-on; <<
140 regulator-name = "CTRL_SLEEP_M <<
141 }; <<
142 <<
143 reg_usb1_vbus: regulator-usb1-vbus { 101 reg_usb1_vbus: regulator-usb1-vbus {
144 compatible = "regulator-fixed" 102 compatible = "regulator-fixed";
145 enable-active-high; 103 enable-active-high;
146 /* Verdin USB_1_EN (SODIMM 155 104 /* Verdin USB_1_EN (SODIMM 155) */
147 gpio = <&gpio1 12 GPIO_ACTIVE_ 105 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
148 pinctrl-names = "default"; 106 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_usb1_vbu 107 pinctrl-0 = <&pinctrl_usb1_vbus>;
150 regulator-max-microvolt = <500 108 regulator-max-microvolt = <5000000>;
151 regulator-min-microvolt = <500 109 regulator-min-microvolt = <5000000>;
152 regulator-name = "USB_1_EN"; 110 regulator-name = "USB_1_EN";
153 }; 111 };
154 112
155 reg_usb2_vbus: regulator-usb2-vbus { 113 reg_usb2_vbus: regulator-usb2-vbus {
156 compatible = "regulator-fixed" 114 compatible = "regulator-fixed";
157 enable-active-high; 115 enable-active-high;
158 /* Verdin USB_2_EN (SODIMM 185 116 /* Verdin USB_2_EN (SODIMM 185) */
159 gpio = <&gpio1 14 GPIO_ACTIVE_ 117 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
160 pinctrl-names = "default"; 118 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usb2_vbu 119 pinctrl-0 = <&pinctrl_usb2_vbus>;
162 regulator-max-microvolt = <500 120 regulator-max-microvolt = <5000000>;
163 regulator-min-microvolt = <500 121 regulator-min-microvolt = <5000000>;
164 regulator-name = "USB_2_EN"; 122 regulator-name = "USB_2_EN";
165 }; 123 };
166 124
167 reg_usdhc2_vmmc: regulator-usdhc2 { 125 reg_usdhc2_vmmc: regulator-usdhc2 {
168 compatible = "regulator-fixed" 126 compatible = "regulator-fixed";
169 enable-active-high; 127 enable-active-high;
170 /* Verdin SD_1_PWR_EN (SODIMM 128 /* Verdin SD_1_PWR_EN (SODIMM 76) */
171 gpio = <&gpio4 22 GPIO_ACTIVE_ 129 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
172 off-on-delay-us = <100000>; !! 130 off-on-delay = <100000>;
173 pinctrl-names = "default"; 131 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_usdhc2_p 132 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
175 regulator-max-microvolt = <330 133 regulator-max-microvolt = <3300000>;
176 regulator-min-microvolt = <330 134 regulator-min-microvolt = <3300000>;
177 regulator-name = "+V3.3_SD"; 135 regulator-name = "+V3.3_SD";
178 startup-delay-us = <2000>; 136 startup-delay-us = <2000>;
179 }; 137 };
180 138
181 reserved-memory { 139 reserved-memory {
182 #address-cells = <2>; 140 #address-cells = <2>;
183 #size-cells = <2>; 141 #size-cells = <2>;
184 ranges; 142 ranges;
185 143
186 /* Use the kernel configuratio 144 /* Use the kernel configuration settings instead */
187 /delete-node/ linux,cma; 145 /delete-node/ linux,cma;
188 }; 146 };
189 }; 147 };
190 148
191 &A53_0 { <<
192 cpu-supply = <®_vdd_arm>; <<
193 }; <<
194 <<
195 &A53_1 { <<
196 cpu-supply = <®_vdd_arm>; <<
197 }; <<
198 <<
199 &A53_2 { <<
200 cpu-supply = <®_vdd_arm>; <<
201 }; <<
202 <<
203 &A53_3 { <<
204 cpu-supply = <®_vdd_arm>; <<
205 }; <<
206 <<
207 &cpu_alert0 { <<
208 temperature = <95000>; <<
209 }; <<
210 <<
211 &cpu_crit0 { <<
212 temperature = <105000>; <<
213 }; <<
214 <<
215 /* Verdin SPI_1 */ 149 /* Verdin SPI_1 */
216 &ecspi1 { 150 &ecspi1 {
217 #address-cells = <1>; 151 #address-cells = <1>;
218 #size-cells = <0>; 152 #size-cells = <0>;
219 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 153 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
220 pinctrl-names = "default"; 154 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_ecspi1>; 155 pinctrl-0 = <&pinctrl_ecspi1>;
222 }; 156 };
223 157
224 /* Verdin ETH_1 (On-module PHY) */ 158 /* Verdin ETH_1 (On-module PHY) */
225 &eqos { 159 &eqos {
226 phy-handle = <ðphy0>; 160 phy-handle = <ðphy0>;
227 phy-mode = "rgmii-id"; 161 phy-mode = "rgmii-id";
>> 162 phy-supply = <®_module_eth1phy>;
228 pinctrl-names = "default"; 163 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_eqos>; 164 pinctrl-0 = <&pinctrl_eqos>;
230 snps,force_thresh_dma_mode; 165 snps,force_thresh_dma_mode;
231 snps,mtl-rx-config = <&mtl_rx_setup>; 166 snps,mtl-rx-config = <&mtl_rx_setup>;
232 snps,mtl-tx-config = <&mtl_tx_setup>; 167 snps,mtl-tx-config = <&mtl_tx_setup>;
233 168
234 mdio { 169 mdio {
235 compatible = "snps,dwmac-mdio" 170 compatible = "snps,dwmac-mdio";
236 #address-cells = <1>; 171 #address-cells = <1>;
237 #size-cells = <0>; 172 #size-cells = <0>;
238 173
239 ethphy0: ethernet-phy@7 { 174 ethphy0: ethernet-phy@7 {
240 compatible = "ethernet 175 compatible = "ethernet-phy-ieee802.3-c22";
241 eee-broken-100tx; 176 eee-broken-100tx;
242 eee-broken-1000t; 177 eee-broken-1000t;
243 interrupt-parent = <&g 178 interrupt-parent = <&gpio1>;
244 interrupts = <10 IRQ_T 179 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
245 micrel,led-mode = <0>; 180 micrel,led-mode = <0>;
246 reg = <7>; 181 reg = <7>;
247 }; 182 };
248 }; 183 };
249 184
250 mtl_rx_setup: rx-queues-config { 185 mtl_rx_setup: rx-queues-config {
251 snps,rx-queues-to-use = <5>; 186 snps,rx-queues-to-use = <5>;
>> 187 snps,rx-sched-sp;
252 188
253 queue0 { 189 queue0 {
254 snps,dcb-algorithm; 190 snps,dcb-algorithm;
255 snps,priority = <0x1>; 191 snps,priority = <0x1>;
256 snps,map-to-dma-channe 192 snps,map-to-dma-channel = <0>;
257 }; 193 };
258 194
259 queue1 { 195 queue1 {
260 snps,dcb-algorithm; 196 snps,dcb-algorithm;
261 snps,priority = <0x2>; 197 snps,priority = <0x2>;
262 snps,map-to-dma-channe 198 snps,map-to-dma-channel = <1>;
263 }; 199 };
264 200
265 queue2 { 201 queue2 {
266 snps,dcb-algorithm; 202 snps,dcb-algorithm;
267 snps,priority = <0x4>; 203 snps,priority = <0x4>;
268 snps,map-to-dma-channe 204 snps,map-to-dma-channel = <2>;
269 }; 205 };
270 206
271 queue3 { 207 queue3 {
272 snps,dcb-algorithm; 208 snps,dcb-algorithm;
273 snps,priority = <0x8>; 209 snps,priority = <0x8>;
274 snps,map-to-dma-channe 210 snps,map-to-dma-channel = <3>;
275 }; 211 };
276 212
277 queue4 { 213 queue4 {
278 snps,dcb-algorithm; 214 snps,dcb-algorithm;
279 snps,priority = <0xf0> 215 snps,priority = <0xf0>;
280 snps,map-to-dma-channe 216 snps,map-to-dma-channel = <4>;
281 }; 217 };
282 }; 218 };
283 219
284 mtl_tx_setup: tx-queues-config { 220 mtl_tx_setup: tx-queues-config {
285 snps,tx-queues-to-use = <5>; 221 snps,tx-queues-to-use = <5>;
>> 222 snps,tx-sched-sp;
286 223
287 queue0 { 224 queue0 {
288 snps,dcb-algorithm; 225 snps,dcb-algorithm;
289 snps,priority = <0x1>; 226 snps,priority = <0x1>;
290 }; 227 };
291 228
292 queue1 { 229 queue1 {
293 snps,dcb-algorithm; 230 snps,dcb-algorithm;
294 snps,priority = <0x2>; 231 snps,priority = <0x2>;
295 }; 232 };
296 233
297 queue2 { 234 queue2 {
298 snps,dcb-algorithm; 235 snps,dcb-algorithm;
299 snps,priority = <0x4>; 236 snps,priority = <0x4>;
300 }; 237 };
301 238
302 queue3 { 239 queue3 {
303 snps,dcb-algorithm; 240 snps,dcb-algorithm;
304 snps,priority = <0x8>; 241 snps,priority = <0x8>;
305 }; 242 };
306 243
307 queue4 { 244 queue4 {
308 snps,dcb-algorithm; 245 snps,dcb-algorithm;
309 snps,priority = <0xf0> 246 snps,priority = <0xf0>;
310 }; 247 };
311 }; 248 };
312 }; 249 };
313 250
314 /* Verdin ETH_2_RGMII */ 251 /* Verdin ETH_2_RGMII */
315 &fec { 252 &fec {
316 fsl,magic-packet; 253 fsl,magic-packet;
317 phy-handle = <ðphy1>; 254 phy-handle = <ðphy1>;
318 phy-mode = "rgmii-id"; 255 phy-mode = "rgmii-id";
319 pinctrl-names = "default", "sleep"; 256 pinctrl-names = "default", "sleep";
320 pinctrl-0 = <&pinctrl_fec>; 257 pinctrl-0 = <&pinctrl_fec>;
321 pinctrl-1 = <&pinctrl_fec_sleep>; 258 pinctrl-1 = <&pinctrl_fec_sleep>;
322 259
323 mdio { 260 mdio {
324 #address-cells = <1>; 261 #address-cells = <1>;
325 #size-cells = <0>; 262 #size-cells = <0>;
326 263
327 ethphy1: ethernet-phy@7 { 264 ethphy1: ethernet-phy@7 {
328 compatible = "ethernet 265 compatible = "ethernet-phy-ieee802.3-c22";
329 interrupt-parent = <&g 266 interrupt-parent = <&gpio4>;
330 interrupts = <18 IRQ_T 267 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
331 micrel,led-mode = <0>; 268 micrel,led-mode = <0>;
332 reg = <7>; 269 reg = <7>;
333 }; 270 };
334 }; 271 };
335 }; 272 };
336 273
337 /* Verdin CAN_1 */ 274 /* Verdin CAN_1 */
338 &flexcan1 { 275 &flexcan1 {
339 pinctrl-names = "default"; 276 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_flexcan1>; 277 pinctrl-0 = <&pinctrl_flexcan1>;
341 status = "disabled"; 278 status = "disabled";
342 }; 279 };
343 280
>> 281
344 /* Verdin CAN_2 */ 282 /* Verdin CAN_2 */
345 &flexcan2 { 283 &flexcan2 {
346 pinctrl-names = "default"; 284 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_flexcan2>; 285 pinctrl-0 = <&pinctrl_flexcan2>;
348 status = "disabled"; 286 status = "disabled";
349 }; 287 };
350 288
351 /* Verdin QSPI_1 */ 289 /* Verdin QSPI_1 */
352 &flexspi { 290 &flexspi {
353 pinctrl-names = "default"; 291 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_flexspi0>; 292 pinctrl-0 = <&pinctrl_flexspi0>;
355 }; 293 };
356 294
357 &gpio1 { 295 &gpio1 {
358 gpio-line-names = "SODIMM_206", 296 gpio-line-names = "SODIMM_206",
359 "SODIMM_208", 297 "SODIMM_208",
360 "", 298 "",
361 "", 299 "",
362 "", 300 "",
363 "SODIMM_210", 301 "SODIMM_210",
364 "SODIMM_212", 302 "SODIMM_212",
365 "SODIMM_216", 303 "SODIMM_216",
366 "SODIMM_218", 304 "SODIMM_218",
367 "", 305 "",
368 "", 306 "",
369 "SODIMM_16", 307 "SODIMM_16",
370 "SODIMM_155", 308 "SODIMM_155",
371 "SODIMM_157", 309 "SODIMM_157",
372 "SODIMM_185", 310 "SODIMM_185",
373 "SODIMM_91"; 311 "SODIMM_91";
374 }; 312 };
375 313
376 &gpio2 { 314 &gpio2 {
377 gpio-line-names = "", 315 gpio-line-names = "",
378 "", 316 "",
379 "", 317 "",
380 "", 318 "",
381 "", 319 "",
382 "", 320 "",
383 "SODIMM_143", 321 "SODIMM_143",
384 "SODIMM_141", 322 "SODIMM_141",
385 "", 323 "",
386 "", 324 "",
387 "SODIMM_161", 325 "SODIMM_161",
388 "", 326 "",
389 "SODIMM_84", 327 "SODIMM_84",
390 "SODIMM_78", 328 "SODIMM_78",
391 "SODIMM_74", 329 "SODIMM_74",
392 "SODIMM_80", 330 "SODIMM_80",
393 "SODIMM_82", 331 "SODIMM_82",
394 "SODIMM_70", 332 "SODIMM_70",
395 "SODIMM_72"; 333 "SODIMM_72";
>> 334
>> 335 ctrl-sleep-moci-hog {
>> 336 gpio-hog;
>> 337 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
>> 338 gpios = <29 GPIO_ACTIVE_HIGH>;
>> 339 line-name = "CTRL_SLEEP_MOCI#";
>> 340 output-high;
>> 341 pinctrl-names = "default";
>> 342 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
>> 343 };
396 }; 344 };
397 345
398 &gpio3 { 346 &gpio3 {
399 gpio-line-names = "SODIMM_52", 347 gpio-line-names = "SODIMM_52",
400 "SODIMM_54", 348 "SODIMM_54",
401 "", 349 "",
402 "", 350 "",
403 "", 351 "",
404 "", 352 "",
405 "SODIMM_56", 353 "SODIMM_56",
406 "SODIMM_58", 354 "SODIMM_58",
407 "SODIMM_60", 355 "SODIMM_60",
408 "SODIMM_62", 356 "SODIMM_62",
409 "", 357 "",
410 "", 358 "",
411 "", 359 "",
412 "", 360 "",
413 "SODIMM_66", 361 "SODIMM_66",
414 "", 362 "",
415 "SODIMM_64", 363 "SODIMM_64",
416 "", 364 "",
417 "", 365 "",
418 "SODIMM_34", 366 "SODIMM_34",
419 "SODIMM_19", 367 "SODIMM_19",
420 "", 368 "",
421 "SODIMM_32", 369 "SODIMM_32",
422 "", 370 "",
423 "", 371 "",
424 "SODIMM_30", 372 "SODIMM_30",
425 "SODIMM_59", 373 "SODIMM_59",
426 "SODIMM_57", 374 "SODIMM_57",
427 "SODIMM_63", 375 "SODIMM_63",
428 "SODIMM_61"; 376 "SODIMM_61";
429 }; 377 };
430 378
431 &gpio4 { 379 &gpio4 {
432 gpio-line-names = "SODIMM_252", 380 gpio-line-names = "SODIMM_252",
433 "SODIMM_222", 381 "SODIMM_222",
434 "SODIMM_36", 382 "SODIMM_36",
435 "SODIMM_220", 383 "SODIMM_220",
436 "SODIMM_193", 384 "SODIMM_193",
437 "SODIMM_191", 385 "SODIMM_191",
438 "SODIMM_201", 386 "SODIMM_201",
439 "SODIMM_203", 387 "SODIMM_203",
440 "SODIMM_205", 388 "SODIMM_205",
441 "SODIMM_207", 389 "SODIMM_207",
442 "SODIMM_199", 390 "SODIMM_199",
443 "SODIMM_197", 391 "SODIMM_197",
444 "SODIMM_221", 392 "SODIMM_221",
445 "SODIMM_219", 393 "SODIMM_219",
446 "SODIMM_217", 394 "SODIMM_217",
447 "SODIMM_215", 395 "SODIMM_215",
448 "SODIMM_211", 396 "SODIMM_211",
449 "SODIMM_213", 397 "SODIMM_213",
450 "SODIMM_189", 398 "SODIMM_189",
451 "SODIMM_244", 399 "SODIMM_244",
452 "SODIMM_38", 400 "SODIMM_38",
453 "", 401 "",
454 "SODIMM_76", 402 "SODIMM_76",
455 "SODIMM_135", 403 "SODIMM_135",
456 "SODIMM_133", 404 "SODIMM_133",
457 "SODIMM_17", 405 "SODIMM_17",
458 "SODIMM_24", 406 "SODIMM_24",
459 "SODIMM_26", 407 "SODIMM_26",
460 "SODIMM_21", 408 "SODIMM_21",
461 "SODIMM_256", 409 "SODIMM_256",
462 "SODIMM_48", 410 "SODIMM_48",
463 "SODIMM_44"; 411 "SODIMM_44";
464 }; 412 };
465 413
466 /* Verdin HDMI_1 */ <<
467 &hdmi_tx { <<
468 ddc-i2c-bus = <&i2c5>; <<
469 pinctrl-names = "default"; <<
470 pinctrl-0 = <&pinctrl_hdmi>; <<
471 }; <<
472 <<
473 /* On-module I2C */ 414 /* On-module I2C */
474 &i2c1 { 415 &i2c1 {
475 clock-frequency = <400000>; 416 clock-frequency = <400000>;
476 pinctrl-names = "default", "gpio"; 417 pinctrl-names = "default", "gpio";
477 pinctrl-0 = <&pinctrl_i2c1>; 418 pinctrl-0 = <&pinctrl_i2c1>;
478 pinctrl-1 = <&pinctrl_i2c1_gpio>; 419 pinctrl-1 = <&pinctrl_i2c1_gpio>;
479 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 420 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
480 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 421 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
481 status = "okay"; 422 status = "okay";
482 423
483 pca9450: pmic@25 { 424 pca9450: pmic@25 {
484 compatible = "nxp,pca9450c"; 425 compatible = "nxp,pca9450c";
485 interrupt-parent = <&gpio1>; 426 interrupt-parent = <&gpio1>;
486 /* PMIC PCA9450 PMIC_nINT GPIO 427 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
487 interrupts = <3 IRQ_TYPE_LEVEL 428 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
488 pinctrl-names = "default"; 429 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_pmic>; 430 pinctrl-0 = <&pinctrl_pmic>;
490 reg = <0x25>; 431 reg = <0x25>;
>> 432 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
491 433
492 /* 434 /*
493 * The bootloader is expected 435 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
494 * I2C level shifter for the T 436 * I2C level shifter for the TLA2024 ADC behind this PMIC.
495 */ 437 */
496 438
497 regulators { 439 regulators {
498 BUCK1 { 440 BUCK1 {
499 regulator-alwa 441 regulator-always-on;
500 regulator-boot 442 regulator-boot-on;
501 regulator-max- 443 regulator-max-microvolt = <1000000>;
502 regulator-min- 444 regulator-min-microvolt = <720000>;
503 regulator-name 445 regulator-name = "On-module +VDD_SOC (BUCK1)";
504 regulator-ramp 446 regulator-ramp-delay = <3125>;
505 }; 447 };
506 448
507 reg_vdd_arm: BUCK2 { !! 449 BUCK2 {
508 nxp,dvs-run-vo 450 nxp,dvs-run-voltage = <950000>;
509 nxp,dvs-standb 451 nxp,dvs-standby-voltage = <850000>;
510 regulator-alwa 452 regulator-always-on;
511 regulator-boot 453 regulator-boot-on;
512 regulator-max- 454 regulator-max-microvolt = <1025000>;
513 regulator-min- 455 regulator-min-microvolt = <720000>;
514 regulator-name 456 regulator-name = "On-module +VDD_ARM (BUCK2)";
515 regulator-ramp 457 regulator-ramp-delay = <3125>;
516 }; 458 };
517 459
518 reg_vdd_3v3: BUCK4 { 460 reg_vdd_3v3: BUCK4 {
519 regulator-alwa 461 regulator-always-on;
520 regulator-boot 462 regulator-boot-on;
521 regulator-max- 463 regulator-max-microvolt = <3300000>;
522 regulator-min- 464 regulator-min-microvolt = <3300000>;
523 regulator-name 465 regulator-name = "On-module +V3.3 (BUCK4)";
524 }; 466 };
525 467
526 reg_vdd_1v8: BUCK5 { 468 reg_vdd_1v8: BUCK5 {
527 regulator-alwa 469 regulator-always-on;
528 regulator-boot 470 regulator-boot-on;
529 regulator-max- 471 regulator-max-microvolt = <1800000>;
530 regulator-min- 472 regulator-min-microvolt = <1800000>;
531 regulator-name 473 regulator-name = "PWR_1V8_MOCI (BUCK5)";
532 }; 474 };
533 475
534 BUCK6 { 476 BUCK6 {
535 regulator-alwa 477 regulator-always-on;
536 regulator-boot 478 regulator-boot-on;
537 regulator-max- 479 regulator-max-microvolt = <1155000>;
538 regulator-min- 480 regulator-min-microvolt = <1045000>;
539 regulator-name 481 regulator-name = "On-module +VDD_DDR (BUCK6)";
540 }; 482 };
541 483
542 LDO1 { 484 LDO1 {
543 regulator-alwa 485 regulator-always-on;
544 regulator-boot 486 regulator-boot-on;
545 regulator-max- 487 regulator-max-microvolt = <1950000>;
546 regulator-min- 488 regulator-min-microvolt = <1650000>;
547 regulator-name 489 regulator-name = "On-module +V1.8_SNVS (LDO1)";
548 }; 490 };
549 491
550 LDO2 { 492 LDO2 {
551 regulator-alwa 493 regulator-always-on;
552 regulator-boot 494 regulator-boot-on;
553 regulator-max- 495 regulator-max-microvolt = <1150000>;
554 regulator-min- 496 regulator-min-microvolt = <800000>;
555 regulator-name 497 regulator-name = "On-module +V0.8_SNVS (LDO2)";
556 }; 498 };
557 499
558 LDO3 { 500 LDO3 {
559 regulator-alwa 501 regulator-always-on;
560 regulator-boot 502 regulator-boot-on;
561 regulator-max- 503 regulator-max-microvolt = <1800000>;
562 regulator-min- 504 regulator-min-microvolt = <1800000>;
563 regulator-name 505 regulator-name = "On-module +V1.8A (LDO3)";
564 }; 506 };
565 507
566 LDO4 { 508 LDO4 {
567 regulator-alwa 509 regulator-always-on;
568 regulator-boot 510 regulator-boot-on;
569 regulator-max- 511 regulator-max-microvolt = <3300000>;
570 regulator-min- 512 regulator-min-microvolt = <3300000>;
571 regulator-name 513 regulator-name = "On-module +V3.3_ADC (LDO4)";
572 }; 514 };
573 515
574 reg_vdd_sdio: LDO5 { !! 516 LDO5 {
575 regulator-max- 517 regulator-max-microvolt = <3300000>;
576 regulator-min- 518 regulator-min-microvolt = <1800000>;
577 regulator-name 519 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
578 }; 520 };
579 }; 521 };
580 }; 522 };
581 523
582 rtc_i2c: rtc@32 { 524 rtc_i2c: rtc@32 {
583 compatible = "epson,rx8130"; 525 compatible = "epson,rx8130";
584 reg = <0x32>; 526 reg = <0x32>;
585 }; 527 };
586 528
587 /* On-module temperature sensor */ 529 /* On-module temperature sensor */
588 hwmon_temp_module: sensor@48 { 530 hwmon_temp_module: sensor@48 {
589 compatible = "ti,tmp1075"; 531 compatible = "ti,tmp1075";
590 reg = <0x48>; 532 reg = <0x48>;
591 vs-supply = <®_vdd_1v8>; 533 vs-supply = <®_vdd_1v8>;
592 }; 534 };
593 535
594 adc@49 { 536 adc@49 {
595 compatible = "ti,ads1015"; 537 compatible = "ti,ads1015";
596 reg = <0x49>; 538 reg = <0x49>;
597 #address-cells = <1>; 539 #address-cells = <1>;
598 #size-cells = <0>; 540 #size-cells = <0>;
599 541
600 /* Verdin I2C_1 (ADC_4 - ADC_3 542 /* Verdin I2C_1 (ADC_4 - ADC_3) */
601 channel@0 { 543 channel@0 {
602 reg = <0>; 544 reg = <0>;
603 ti,datarate = <4>; 545 ti,datarate = <4>;
604 ti,gain = <2>; 546 ti,gain = <2>;
605 }; 547 };
606 548
607 /* Verdin I2C_1 (ADC_4 - ADC_1 549 /* Verdin I2C_1 (ADC_4 - ADC_1) */
608 channel@1 { 550 channel@1 {
609 reg = <1>; 551 reg = <1>;
610 ti,datarate = <4>; 552 ti,datarate = <4>;
611 ti,gain = <2>; 553 ti,gain = <2>;
612 }; 554 };
613 555
614 /* Verdin I2C_1 (ADC_3 - ADC_1 556 /* Verdin I2C_1 (ADC_3 - ADC_1) */
615 channel@2 { 557 channel@2 {
616 reg = <2>; 558 reg = <2>;
617 ti,datarate = <4>; 559 ti,datarate = <4>;
618 ti,gain = <2>; 560 ti,gain = <2>;
619 }; 561 };
620 562
621 /* Verdin I2C_1 (ADC_2 - ADC_1 563 /* Verdin I2C_1 (ADC_2 - ADC_1) */
622 channel@3 { 564 channel@3 {
623 reg = <3>; 565 reg = <3>;
624 ti,datarate = <4>; 566 ti,datarate = <4>;
625 ti,gain = <2>; 567 ti,gain = <2>;
626 }; 568 };
627 569
628 /* Verdin I2C_1 ADC_4 */ 570 /* Verdin I2C_1 ADC_4 */
629 channel@4 { 571 channel@4 {
630 reg = <4>; 572 reg = <4>;
631 ti,datarate = <4>; 573 ti,datarate = <4>;
632 ti,gain = <2>; 574 ti,gain = <2>;
633 }; 575 };
634 576
635 /* Verdin I2C_1 ADC_3 */ 577 /* Verdin I2C_1 ADC_3 */
636 channel@5 { 578 channel@5 {
637 reg = <5>; 579 reg = <5>;
638 ti,datarate = <4>; 580 ti,datarate = <4>;
639 ti,gain = <2>; 581 ti,gain = <2>;
640 }; 582 };
641 583
642 /* Verdin I2C_1 ADC_2 */ 584 /* Verdin I2C_1 ADC_2 */
643 channel@6 { 585 channel@6 {
644 reg = <6>; 586 reg = <6>;
645 ti,datarate = <4>; 587 ti,datarate = <4>;
646 ti,gain = <2>; 588 ti,gain = <2>;
647 }; 589 };
648 590
649 /* Verdin I2C_1 ADC_1 */ 591 /* Verdin I2C_1 ADC_1 */
650 channel@7 { 592 channel@7 {
651 reg = <7>; 593 reg = <7>;
652 ti,datarate = <4>; 594 ti,datarate = <4>;
653 ti,gain = <2>; 595 ti,gain = <2>;
654 }; 596 };
655 }; 597 };
656 598
657 eeprom@50 { 599 eeprom@50 {
658 compatible = "st,24c02"; 600 compatible = "st,24c02";
659 pagesize = <16>; 601 pagesize = <16>;
660 reg = <0x50>; 602 reg = <0x50>;
661 }; 603 };
662 }; 604 };
663 605
664 /* Verdin I2C_2_DSI */ 606 /* Verdin I2C_2_DSI */
665 &i2c2 { 607 &i2c2 {
666 clock-frequency = <400000>; !! 608 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
>> 609 clock-frequency = <10000>;
667 pinctrl-names = "default", "gpio"; 610 pinctrl-names = "default", "gpio";
668 pinctrl-0 = <&pinctrl_i2c2>; 611 pinctrl-0 = <&pinctrl_i2c2>;
669 pinctrl-1 = <&pinctrl_i2c2_gpio>; 612 pinctrl-1 = <&pinctrl_i2c2_gpio>;
670 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 613 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
671 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 614 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
672 615
673 atmel_mxt_ts_mezzanine: touch-mezzanin 616 atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
674 compatible = "atmel,maxtouch"; 617 compatible = "atmel,maxtouch";
675 /* Verdin GPIO_3 (SODIMM 210) 618 /* Verdin GPIO_3 (SODIMM 210) */
676 interrupt-parent = <&gpio1>; 619 interrupt-parent = <&gpio1>;
677 interrupts = <5 IRQ_TYPE_EDGE_ 620 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
678 reg = <0x4a>; 621 reg = <0x4a>;
679 /* Verdin GPIO_2 (SODIMM 208) 622 /* Verdin GPIO_2 (SODIMM 208) */
680 reset-gpios = <&gpio1 1 GPIO_A 623 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
681 status = "disabled"; 624 status = "disabled";
682 }; 625 };
683 }; 626 };
684 627
>> 628 /* TODO: Verdin I2C_3_HDMI */
>> 629
685 /* Verdin I2C_4_CSI */ 630 /* Verdin I2C_4_CSI */
686 &i2c3 { 631 &i2c3 {
687 clock-frequency = <400000>; 632 clock-frequency = <400000>;
688 pinctrl-names = "default", "gpio"; 633 pinctrl-names = "default", "gpio";
689 pinctrl-0 = <&pinctrl_i2c3>; 634 pinctrl-0 = <&pinctrl_i2c3>;
690 pinctrl-1 = <&pinctrl_i2c3_gpio>; 635 pinctrl-1 = <&pinctrl_i2c3_gpio>;
691 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 636 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
692 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 637 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
693 }; 638 };
694 639
695 /* Verdin I2C_1 */ 640 /* Verdin I2C_1 */
696 &i2c4 { 641 &i2c4 {
697 clock-frequency = <400000>; 642 clock-frequency = <400000>;
698 pinctrl-names = "default", "gpio"; 643 pinctrl-names = "default", "gpio";
699 pinctrl-0 = <&pinctrl_i2c4>; 644 pinctrl-0 = <&pinctrl_i2c4>;
700 pinctrl-1 = <&pinctrl_i2c4_gpio>; 645 pinctrl-1 = <&pinctrl_i2c4_gpio>;
701 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 646 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
702 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 647 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
703 648
704 gpio_expander_21: gpio-expander@21 { 649 gpio_expander_21: gpio-expander@21 {
705 compatible = "nxp,pcal6416"; 650 compatible = "nxp,pcal6416";
706 #gpio-cells = <2>; 651 #gpio-cells = <2>;
707 gpio-controller; 652 gpio-controller;
708 reg = <0x21>; 653 reg = <0x21>;
709 vcc-supply = <®_3p3v>; 654 vcc-supply = <®_3p3v>;
710 status = "disabled"; 655 status = "disabled";
711 }; 656 };
712 657
713 lvds_ti_sn65dsi84: bridge@2c { !! 658 lvds_ti_sn65dsi83: bridge@2c {
714 compatible = "ti,sn65dsi84"; !! 659 compatible = "ti,sn65dsi83";
715 /* Verdin GPIO_9_DSI (SN65DSI8 660 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
716 /* Verdin GPIO_10_DSI (SODIMM 661 /* Verdin GPIO_10_DSI (SODIMM 21) */
717 enable-gpios = <&gpio4 28 GPIO 662 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
718 pinctrl-names = "default"; 663 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_gpio_10_ 664 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
720 reg = <0x2c>; 665 reg = <0x2c>;
721 status = "disabled"; 666 status = "disabled";
722 }; 667 };
723 668
724 /* Current measurement into module VCC 669 /* Current measurement into module VCC */
725 hwmon: hwmon@40 { 670 hwmon: hwmon@40 {
726 compatible = "ti,ina219"; 671 compatible = "ti,ina219";
727 reg = <0x40>; 672 reg = <0x40>;
728 shunt-resistor = <10000>; 673 shunt-resistor = <10000>;
729 status = "disabled"; 674 status = "disabled";
730 }; 675 };
731 676
732 hdmi_lontium_lt8912: hdmi@48 { 677 hdmi_lontium_lt8912: hdmi@48 {
733 compatible = "lontium,lt8912b" 678 compatible = "lontium,lt8912b";
734 pinctrl-names = "default"; 679 pinctrl-names = "default";
735 pinctrl-0 = <&pinctrl_gpio_10_ 680 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
736 reg = <0x48>; 681 reg = <0x48>;
737 /* Verdin GPIO_9_DSI (LT8912 I 682 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
738 /* Verdin GPIO_10_DSI (SODIMM 683 /* Verdin GPIO_10_DSI (SODIMM 21) */
739 reset-gpios = <&gpio4 28 GPIO_ 684 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
740 status = "disabled"; 685 status = "disabled";
741 }; 686 };
742 687
743 atmel_mxt_ts: touch@4a { 688 atmel_mxt_ts: touch@4a {
744 compatible = "atmel,maxtouch"; 689 compatible = "atmel,maxtouch";
745 /* 690 /*
746 * Verdin GPIO_9_DSI 691 * Verdin GPIO_9_DSI
747 * (TOUCH_INT#, SODIMM 17, als !! 692 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
748 */ 693 */
749 interrupt-parent = <&gpio4>; 694 interrupt-parent = <&gpio4>;
750 interrupts = <25 IRQ_TYPE_EDGE 695 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
751 pinctrl-names = "default"; 696 pinctrl-names = "default";
752 pinctrl-0 = <&pinctrl_gpio_9_d 697 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
753 reg = <0x4a>; 698 reg = <0x4a>;
754 /* Verdin I2S_2_BCLK (TOUCH_RE 699 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
755 reset-gpios = <&gpio5 0 GPIO_A 700 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
756 status = "disabled"; 701 status = "disabled";
757 }; 702 };
758 703
759 /* Temperature sensor on carrier board 704 /* Temperature sensor on carrier board */
760 hwmon_temp: sensor@4f { 705 hwmon_temp: sensor@4f {
761 compatible = "ti,tmp75c"; 706 compatible = "ti,tmp75c";
762 reg = <0x4f>; 707 reg = <0x4f>;
763 status = "disabled"; 708 status = "disabled";
764 }; 709 };
765 710
766 /* EEPROM on display adapter (MIPI DSI 711 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
767 eeprom_display_adapter: eeprom@50 { 712 eeprom_display_adapter: eeprom@50 {
768 compatible = "st,24c02"; 713 compatible = "st,24c02";
769 pagesize = <16>; 714 pagesize = <16>;
770 reg = <0x50>; 715 reg = <0x50>;
771 status = "disabled"; 716 status = "disabled";
772 }; 717 };
773 718
774 /* EEPROM on carrier board */ 719 /* EEPROM on carrier board */
775 eeprom_carrier_board: eeprom@57 { 720 eeprom_carrier_board: eeprom@57 {
776 compatible = "st,24c02"; 721 compatible = "st,24c02";
777 pagesize = <16>; 722 pagesize = <16>;
778 reg = <0x57>; 723 reg = <0x57>;
779 status = "disabled"; 724 status = "disabled";
780 }; 725 };
781 }; 726 };
782 727
783 /* Verdin I2C_3_HDMI */ !! 728 /* TODO: Verdin PCIE_1 */
784 &i2c5 { <<
785 clock-frequency = <100000>; <<
786 pinctrl-names = "default", "gpio"; <<
787 pinctrl-0 = <&pinctrl_i2c5>; <<
788 pinctrl-1 = <&pinctrl_i2c5_gpio>; <<
789 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HI <<
790 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HI <<
791 }; <<
792 <<
793 /* Verdin PCIE_1 */ <<
794 &pcie { <<
795 pinctrl-names = "default"; <<
796 pinctrl-0 = <&pinctrl_pcie>; <<
797 /* PCIE_1_RESET# (SODIMM 244) */ <<
798 reset-gpio = <&gpio4 19 GPIO_ACTIVE_LO <<
799 }; <<
800 <<
801 &pcie_phy { <<
802 clocks = <&hsio_blk_ctrl>; <<
803 clock-names = "ref"; <<
804 fsl,clkreq-unsupported; <<
805 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
806 }; <<
807 729
808 /* Verdin PWM_1 */ 730 /* Verdin PWM_1 */
809 &pwm1 { 731 &pwm1 {
810 pinctrl-names = "default"; 732 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_pwm_1>; 733 pinctrl-0 = <&pinctrl_pwm_1>;
812 #pwm-cells = <3>; 734 #pwm-cells = <3>;
813 }; 735 };
814 736
815 /* Verdin PWM_2 */ 737 /* Verdin PWM_2 */
816 &pwm2 { 738 &pwm2 {
817 pinctrl-names = "default"; 739 pinctrl-names = "default";
818 pinctrl-0 = <&pinctrl_pwm_2>; 740 pinctrl-0 = <&pinctrl_pwm_2>;
819 #pwm-cells = <3>; 741 #pwm-cells = <3>;
820 }; 742 };
821 743
822 /* Verdin PWM_3_DSI */ 744 /* Verdin PWM_3_DSI */
823 &pwm3 { 745 &pwm3 {
824 pinctrl-names = "default"; 746 pinctrl-names = "default";
825 pinctrl-0 = <&pinctrl_pwm_3>; 747 pinctrl-0 = <&pinctrl_pwm_3>;
826 #pwm-cells = <3>; 748 #pwm-cells = <3>;
827 }; 749 };
828 750
829 /* TODO: Verdin I2S_1 */ 751 /* TODO: Verdin I2S_1 */
830 752
831 /* TODO: Verdin I2S_2 */ 753 /* TODO: Verdin I2S_2 */
832 754
833 &snvs_pwrkey { 755 &snvs_pwrkey {
834 status = "okay"; 756 status = "okay";
835 }; 757 };
836 758
837 /* Verdin UART_1 */ 759 /* Verdin UART_1 */
838 &uart1 { 760 &uart1 {
839 pinctrl-names = "default"; 761 pinctrl-names = "default";
840 pinctrl-0 = <&pinctrl_uart1>; 762 pinctrl-0 = <&pinctrl_uart1>;
841 uart-has-rtscts; 763 uart-has-rtscts;
842 }; 764 };
843 765
844 /* Verdin UART_2 */ 766 /* Verdin UART_2 */
845 &uart2 { 767 &uart2 {
846 pinctrl-names = "default"; 768 pinctrl-names = "default";
847 pinctrl-0 = <&pinctrl_uart2>; 769 pinctrl-0 = <&pinctrl_uart2>;
848 uart-has-rtscts; 770 uart-has-rtscts;
849 }; 771 };
850 772
851 /* Verdin UART_3, used as the Linux Console */ 773 /* Verdin UART_3, used as the Linux Console */
852 &uart3 { 774 &uart3 {
853 pinctrl-names = "default"; 775 pinctrl-names = "default";
854 pinctrl-0 = <&pinctrl_uart3>; 776 pinctrl-0 = <&pinctrl_uart3>;
855 }; 777 };
856 778
857 /* Verdin UART_4, used for Bluetooth on Wi-Fi/ 779 /* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
858 &uart4 { 780 &uart4 {
859 pinctrl-names = "default"; 781 pinctrl-names = "default";
860 pinctrl-0 = <&pinctrl_uart4>; 782 pinctrl-0 = <&pinctrl_uart4>;
861 }; 783 };
862 784
863 /* Verdin USB_1 */ 785 /* Verdin USB_1 */
864 &usb3_0 { !! 786 &usb3_phy0 {
865 fsl,disable-port-power-control; !! 787 vbus-supply = <®_usb1_vbus>;
866 fsl,over-current-active-low; <<
867 pinctrl-names = "default"; <<
868 pinctrl-0 = <&pinctrl_usb_1_oc_n>; <<
869 }; 788 };
870 789
871 &usb_dwc3_0 { 790 &usb_dwc3_0 {
872 /* dual role only, not full featured O <<
873 adp-disable; 791 adp-disable;
874 dr_mode = "otg"; 792 dr_mode = "otg";
875 hnp-disable; 793 hnp-disable;
876 maximum-speed = "high-speed"; 794 maximum-speed = "high-speed";
877 role-switch-default-mode = "peripheral !! 795 over-current-active-low;
>> 796 pinctrl-names = "default";
>> 797 pinctrl-0 = <&pinctrl_usb_1_id>;
878 srp-disable; 798 srp-disable;
879 usb-role-switch; <<
880 <<
881 port { <<
882 usb3_dwc: endpoint { <<
883 remote-endpoint = <&us <<
884 }; <<
885 }; <<
886 }; 799 };
887 800
888 /* Verdin USB_2 */ 801 /* Verdin USB_2 */
889 &usb3_1 { <<
890 fsl,disable-port-power-control; <<
891 }; <<
892 <<
893 &usb3_phy1 { 802 &usb3_phy1 {
894 vbus-supply = <®_usb2_vbus>; 803 vbus-supply = <®_usb2_vbus>;
895 }; 804 };
896 805
897 &usb_dwc3_1 { 806 &usb_dwc3_1 {
>> 807 disable-over-current;
898 dr_mode = "host"; 808 dr_mode = "host";
899 }; 809 };
900 810
901 /* Verdin SD_1 */ 811 /* Verdin SD_1 */
902 &usdhc2 { 812 &usdhc2 {
903 assigned-clocks = <&clk IMX8MP_CLK_USD 813 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
904 assigned-clock-rates = <400000000>; 814 assigned-clock-rates = <400000000>;
905 bus-width = <4>; 815 bus-width = <4>;
906 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 816 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
907 disable-wp; 817 disable-wp;
908 pinctrl-names = "default", "state_100m 818 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
909 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 819 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
910 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 820 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
911 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 821 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
912 pinctrl-3 = <&pinctrl_usdhc2_sleep>, < 822 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
913 vmmc-supply = <®_usdhc2_vmmc>; 823 vmmc-supply = <®_usdhc2_vmmc>;
914 vqmmc-supply = <®_vdd_sdio>; <<
915 }; 824 };
916 825
917 /* On-module eMMC */ 826 /* On-module eMMC */
918 &usdhc3 { 827 &usdhc3 {
919 assigned-clocks = <&clk IMX8MP_CLK_USD 828 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
920 assigned-clock-rates = <400000000>; 829 assigned-clock-rates = <400000000>;
921 bus-width = <8>; 830 bus-width = <8>;
922 non-removable; 831 non-removable;
923 pinctrl-names = "default", "state_100m 832 pinctrl-names = "default", "state_100mhz", "state_200mhz";
924 pinctrl-0 = <&pinctrl_usdhc3>; 833 pinctrl-0 = <&pinctrl_usdhc3>;
925 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 834 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
926 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 835 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
927 status = "okay"; 836 status = "okay";
928 }; 837 };
929 838
930 &wdog1 { 839 &wdog1 {
931 fsl,ext-reset-output; 840 fsl,ext-reset-output;
932 pinctrl-names = "default"; 841 pinctrl-names = "default";
933 pinctrl-0 = <&pinctrl_wdog>; 842 pinctrl-0 = <&pinctrl_wdog>;
934 status = "okay"; 843 status = "okay";
935 }; 844 };
936 845
937 &iomuxc { 846 &iomuxc {
938 pinctrl_bt_uart: btuartgrp { 847 pinctrl_bt_uart: btuartgrp {
939 fsl,pins = 848 fsl,pins =
940 <MX8MP_IOMUXC_ECSPI2_M 849 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
941 <MX8MP_IOMUXC_ECSPI2_M 850 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
942 <MX8MP_IOMUXC_ECSPI2_S 851 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
943 <MX8MP_IOMUXC_ECSPI2_S 852 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
944 }; 853 };
945 854
946 pinctrl_ctrl_sleep_moci: ctrlsleepmoci 855 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
947 fsl,pins = 856 fsl,pins =
948 <MX8MP_IOMUXC_SAI3_RXC 857 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
949 }; 858 };
950 859
951 pinctrl_ecspi1: ecspi1grp { 860 pinctrl_ecspi1: ecspi1grp {
952 fsl,pins = 861 fsl,pins =
953 <MX8MP_IOMUXC_ECSPI1_M 862 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
954 <MX8MP_IOMUXC_ECSPI1_M 863 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
955 <MX8MP_IOMUXC_ECSPI1_S 864 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
956 <MX8MP_IOMUXC_ECSPI1_S 865 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
957 }; 866 };
958 867
959 /* Connection On Board PHY */ 868 /* Connection On Board PHY */
960 pinctrl_eqos: eqosgrp { 869 pinctrl_eqos: eqosgrp {
961 fsl,pins = 870 fsl,pins =
962 <MX8MP_IOMUXC_ENET_MDC 871 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
963 <MX8MP_IOMUXC_ENET_MDI 872 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
964 <MX8MP_IOMUXC_ENET_RD0 873 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
965 <MX8MP_IOMUXC_ENET_RD1 874 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
966 <MX8MP_IOMUXC_ENET_RD2 875 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
967 <MX8MP_IOMUXC_ENET_RD3 876 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
968 <MX8MP_IOMUXC_ENET_RXC 877 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
969 <MX8MP_IOMUXC_ENET_RX_ 878 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
970 <MX8MP_IOMUXC_ENET_TD0 879 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
971 <MX8MP_IOMUXC_ENET_TD1 880 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
972 <MX8MP_IOMUXC_ENET_TD2 881 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
973 <MX8MP_IOMUXC_ENET_TD3 882 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
974 <MX8MP_IOMUXC_ENET_TX_ 883 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
975 <MX8MP_IOMUXC_ENET_TXC 884 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
976 }; 885 };
977 886
978 /* ETH_INT# shared with TPM_INT# (usua 887 /* ETH_INT# shared with TPM_INT# (usually N/A) */
979 pinctrl_eth_tpm_int: ethtpmintgrp { 888 pinctrl_eth_tpm_int: ethtpmintgrp {
980 fsl,pins = 889 fsl,pins =
981 <MX8MP_IOMUXC_GPIO1_IO 890 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
982 }; 891 };
983 892
984 /* Connection Carrier Board PHY ETH_2 893 /* Connection Carrier Board PHY ETH_2 */
985 pinctrl_fec: fecgrp { 894 pinctrl_fec: fecgrp {
986 fsl,pins = 895 fsl,pins =
987 <MX8MP_IOMUXC_SAI1_RXD 896 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
988 <MX8MP_IOMUXC_SAI1_RXD 897 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
989 <MX8MP_IOMUXC_SAI1_RXD 898 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
990 <MX8MP_IOMUXC_SAI1_RXD 899 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
991 <MX8MP_IOMUXC_SAI1_RXD 900 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
992 <MX8MP_IOMUXC_SAI1_RXD 901 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
993 <MX8MP_IOMUXC_SAI1_TXC 902 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
994 <MX8MP_IOMUXC_SAI1_TXF 903 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
995 <MX8MP_IOMUXC_SAI1_TXD 904 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
996 <MX8MP_IOMUXC_SAI1_TXD 905 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
997 <MX8MP_IOMUXC_SAI1_TXD 906 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
998 <MX8MP_IOMUXC_SAI1_TXD 907 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
999 <MX8MP_IOMUXC_SAI1_TXD 908 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
1000 <MX8MP_IOMUXC_SAI1_TX 909 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
1001 <MX8MP_IOMUXC_SAI1_TX 910 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
1002 }; 911 };
1003 912
1004 pinctrl_fec_sleep: fecsleepgrp { 913 pinctrl_fec_sleep: fecsleepgrp {
1005 fsl,pins = 914 fsl,pins =
1006 <MX8MP_IOMUXC_SAI1_RX 915 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
1007 <MX8MP_IOMUXC_SAI1_RX 916 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
1008 <MX8MP_IOMUXC_SAI1_RX 917 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
1009 <MX8MP_IOMUXC_SAI1_RX 918 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
1010 <MX8MP_IOMUXC_SAI1_RX 919 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
1011 <MX8MP_IOMUXC_SAI1_RX 920 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
1012 <MX8MP_IOMUXC_SAI1_TX 921 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
1013 <MX8MP_IOMUXC_SAI1_TX 922 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
1014 <MX8MP_IOMUXC_SAI1_TX 923 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
1015 <MX8MP_IOMUXC_SAI1_TX 924 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
1016 <MX8MP_IOMUXC_SAI1_TX 925 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
1017 <MX8MP_IOMUXC_SAI1_TX 926 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
1018 <MX8MP_IOMUXC_SAI1_TX 927 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
1019 <MX8MP_IOMUXC_SAI1_TX 928 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
1020 <MX8MP_IOMUXC_SAI1_TX 929 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
1021 }; 930 };
1022 931
1023 pinctrl_flexcan1: flexcan1grp { 932 pinctrl_flexcan1: flexcan1grp {
1024 fsl,pins = 933 fsl,pins =
1025 <MX8MP_IOMUXC_SPDIF_R 934 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
1026 <MX8MP_IOMUXC_SPDIF_T 935 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
1027 }; 936 };
1028 937
1029 pinctrl_flexcan2: flexcan2grp { 938 pinctrl_flexcan2: flexcan2grp {
1030 fsl,pins = 939 fsl,pins =
1031 <MX8MP_IOMUXC_SAI2_MC 940 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
1032 <MX8MP_IOMUXC_SAI2_TX 941 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
1033 }; 942 };
1034 943
1035 pinctrl_flexspi0: flexspi0grp { 944 pinctrl_flexspi0: flexspi0grp {
1036 fsl,pins = 945 fsl,pins =
1037 <MX8MP_IOMUXC_NAND_AL 946 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
1038 <MX8MP_IOMUXC_NAND_CE 947 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
1039 <MX8MP_IOMUXC_NAND_DQ 948 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
1040 <MX8MP_IOMUXC_NAND_DA 949 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
1041 <MX8MP_IOMUXC_NAND_DA 950 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
1042 <MX8MP_IOMUXC_NAND_DA 951 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
1043 <MX8MP_IOMUXC_NAND_DA 952 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
1044 <MX8MP_IOMUXC_NAND_RE 953 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
1045 }; 954 };
1046 955
1047 pinctrl_gpio1: gpio1grp { 956 pinctrl_gpio1: gpio1grp {
1048 fsl,pins = 957 fsl,pins =
1049 <MX8MP_IOMUXC_GPIO1_I 958 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
1050 }; 959 };
1051 960
1052 pinctrl_gpio2: gpio2grp { 961 pinctrl_gpio2: gpio2grp {
1053 fsl,pins = 962 fsl,pins =
1054 <MX8MP_IOMUXC_GPIO1_I 963 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
1055 }; 964 };
1056 965
1057 pinctrl_gpio3: gpio3grp { 966 pinctrl_gpio3: gpio3grp {
1058 fsl,pins = 967 fsl,pins =
1059 <MX8MP_IOMUXC_GPIO1_I 968 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
1060 }; 969 };
1061 970
1062 pinctrl_gpio4: gpio4grp { 971 pinctrl_gpio4: gpio4grp {
1063 fsl,pins = 972 fsl,pins =
1064 <MX8MP_IOMUXC_GPIO1_I 973 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
1065 }; 974 };
1066 975
1067 pinctrl_gpio5: gpio5grp { 976 pinctrl_gpio5: gpio5grp {
1068 fsl,pins = 977 fsl,pins =
1069 <MX8MP_IOMUXC_GPIO1_I 978 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
1070 }; 979 };
1071 980
1072 pinctrl_gpio6: gpio6grp { 981 pinctrl_gpio6: gpio6grp {
1073 fsl,pins = 982 fsl,pins =
1074 <MX8MP_IOMUXC_GPIO1_I 983 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
1075 }; 984 };
1076 985
1077 pinctrl_gpio7: gpio7grp { 986 pinctrl_gpio7: gpio7grp {
1078 fsl,pins = 987 fsl,pins =
1079 <MX8MP_IOMUXC_SAI1_RX 988 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
1080 }; 989 };
1081 990
1082 pinctrl_gpio8: gpio8grp { 991 pinctrl_gpio8: gpio8grp {
1083 fsl,pins = 992 fsl,pins =
1084 <MX8MP_IOMUXC_SAI1_RX 993 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
1085 }; 994 };
1086 995
1087 /* Verdin GPIO_9_DSI (pulled-up as ac 996 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1088 pinctrl_gpio_9_dsi: gpio9dsigrp { 997 pinctrl_gpio_9_dsi: gpio9dsigrp {
1089 fsl,pins = 998 fsl,pins =
1090 <MX8MP_IOMUXC_SAI2_TX 999 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
1091 }; 1000 };
1092 1001
1093 /* Verdin GPIO_10_DSI */ 1002 /* Verdin GPIO_10_DSI */
1094 pinctrl_gpio_10_dsi: gpio10dsigrp { 1003 pinctrl_gpio_10_dsi: gpio10dsigrp {
1095 fsl,pins = 1004 fsl,pins =
1096 <MX8MP_IOMUXC_SAI3_RX 1005 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
1097 }; 1006 };
1098 1007
1099 /* Non-wifi MSP usage only */ 1008 /* Non-wifi MSP usage only */
1100 pinctrl_gpio_hog1: gpiohog1grp { 1009 pinctrl_gpio_hog1: gpiohog1grp {
1101 fsl,pins = 1010 fsl,pins =
1102 <MX8MP_IOMUXC_ECSPI2_ 1011 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
1103 <MX8MP_IOMUXC_ECSPI2_ 1012 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
1104 <MX8MP_IOMUXC_ECSPI2_ 1013 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
1105 <MX8MP_IOMUXC_ECSPI2_ 1014 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
1106 }; 1015 };
1107 1016
1108 /* USB_2_OC# */ 1017 /* USB_2_OC# */
1109 pinctrl_gpio_hog2: gpiohog2grp { 1018 pinctrl_gpio_hog2: gpiohog2grp {
1110 fsl,pins = 1019 fsl,pins =
1111 <MX8MP_IOMUXC_SAI3_MC 1020 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
1112 }; 1021 };
1113 1022
1114 pinctrl_gpio_hog3: gpiohog3grp { 1023 pinctrl_gpio_hog3: gpiohog3grp {
1115 fsl,pins = 1024 fsl,pins =
>> 1025 <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
1116 /* CSI_1_MCLK */ 1026 /* CSI_1_MCLK */
1117 <MX8MP_IOMUXC_GPIO1_I 1027 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
1118 }; 1028 };
1119 1029
1120 /* Wifi usage only */ 1030 /* Wifi usage only */
1121 pinctrl_gpio_hog4: gpiohog4grp { 1031 pinctrl_gpio_hog4: gpiohog4grp {
1122 fsl,pins = 1032 fsl,pins =
1123 <MX8MP_IOMUXC_UART4_R 1033 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
1124 <MX8MP_IOMUXC_UART4_T 1034 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
1125 }; 1035 };
1126 1036
1127 pinctrl_gpio_keys: gpiokeysgrp { 1037 pinctrl_gpio_keys: gpiokeysgrp {
1128 fsl,pins = 1038 fsl,pins =
1129 <MX8MP_IOMUXC_SAI1_RX 1039 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
1130 }; 1040 };
1131 1041
1132 pinctrl_hdmi: hdmigrp { !! 1042 pinctrl_hdmi_hog: hdmihoggrp {
1133 fsl,pins = 1043 fsl,pins =
1134 <MX8MP_IOMUXC_HDMI_CE !! 1044 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
1135 <MX8MP_IOMUXC_HDMI_HP !! 1045 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
>> 1046 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
>> 1047 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
1136 }; 1048 };
1137 1049
1138 /* On-module I2C */ 1050 /* On-module I2C */
1139 pinctrl_i2c1: i2c1grp { 1051 pinctrl_i2c1: i2c1grp {
1140 fsl,pins = 1052 fsl,pins =
1141 <MX8MP_IOMUXC_I2C1_SC 1053 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
1142 <MX8MP_IOMUXC_I2C1_SD 1054 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
1143 }; 1055 };
1144 1056
1145 pinctrl_i2c1_gpio: i2c1gpiogrp { 1057 pinctrl_i2c1_gpio: i2c1gpiogrp {
1146 fsl,pins = 1058 fsl,pins =
1147 <MX8MP_IOMUXC_I2C1_SC 1059 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
1148 <MX8MP_IOMUXC_I2C1_SD 1060 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
1149 }; 1061 };
1150 1062
1151 /* Verdin I2C_2_DSI */ 1063 /* Verdin I2C_2_DSI */
1152 pinctrl_i2c2: i2c2grp { 1064 pinctrl_i2c2: i2c2grp {
1153 fsl,pins = 1065 fsl,pins =
1154 <MX8MP_IOMUXC_I2C2_SC 1066 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
1155 <MX8MP_IOMUXC_I2C2_SD 1067 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
1156 }; 1068 };
1157 1069
1158 pinctrl_i2c2_gpio: i2c2gpiogrp { 1070 pinctrl_i2c2_gpio: i2c2gpiogrp {
1159 fsl,pins = 1071 fsl,pins =
1160 <MX8MP_IOMUXC_I2C2_SC 1072 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
1161 <MX8MP_IOMUXC_I2C2_SD 1073 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
1162 }; 1074 };
1163 1075
1164 /* Verdin I2C_4_CSI */ 1076 /* Verdin I2C_4_CSI */
1165 pinctrl_i2c3: i2c3grp { 1077 pinctrl_i2c3: i2c3grp {
1166 fsl,pins = 1078 fsl,pins =
1167 <MX8MP_IOMUXC_I2C3_SC 1079 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
1168 <MX8MP_IOMUXC_I2C3_SD 1080 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
1169 }; 1081 };
1170 1082
1171 pinctrl_i2c3_gpio: i2c3gpiogrp { 1083 pinctrl_i2c3_gpio: i2c3gpiogrp {
1172 fsl,pins = 1084 fsl,pins =
1173 <MX8MP_IOMUXC_I2C3_SC 1085 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
1174 <MX8MP_IOMUXC_I2C3_SD 1086 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
1175 }; 1087 };
1176 1088
1177 /* Verdin I2C_1 */ 1089 /* Verdin I2C_1 */
1178 pinctrl_i2c4: i2c4grp { 1090 pinctrl_i2c4: i2c4grp {
1179 fsl,pins = 1091 fsl,pins =
1180 <MX8MP_IOMUXC_I2C4_SC 1092 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
1181 <MX8MP_IOMUXC_I2C4_SD 1093 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
1182 }; 1094 };
1183 1095
1184 pinctrl_i2c4_gpio: i2c4gpiogrp { 1096 pinctrl_i2c4_gpio: i2c4gpiogrp {
1185 fsl,pins = 1097 fsl,pins =
1186 <MX8MP_IOMUXC_I2C4_SC 1098 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
1187 <MX8MP_IOMUXC_I2C4_SD 1099 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
1188 }; 1100 };
1189 1101
1190 /* Verdin I2C_3_HDMI */ <<
1191 pinctrl_i2c5: i2c5grp { <<
1192 fsl,pins = <<
1193 <MX8MP_IOMUXC_HDMI_DD <<
1194 <MX8MP_IOMUXC_HDMI_DD <<
1195 }; <<
1196 <<
1197 pinctrl_i2c5_gpio: i2c5gpiogrp { <<
1198 fsl,pins = <<
1199 <MX8MP_IOMUXC_HDMI_DD <<
1200 <MX8MP_IOMUXC_HDMI_DD <<
1201 }; <<
1202 <<
1203 /* Verdin I2S_2_BCLK (TOUCH_RESET#) * 1102 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1204 pinctrl_i2s_2_bclk_touch_reset: i2s2b 1103 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1205 fsl,pins = 1104 fsl,pins =
1206 <MX8MP_IOMUXC_SAI3_TX 1105 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
1207 }; 1106 };
1208 1107
1209 /* Verdin I2S_2_D_OUT shared with SAI 1108 /* Verdin I2S_2_D_OUT shared with SAI3 */
1210 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s 1109 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1211 fsl,pins = 1110 fsl,pins =
1212 <MX8MP_IOMUXC_SAI3_TX 1111 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
1213 }; 1112 };
1214 1113
1215 pinctrl_pcie: pciegrp { 1114 pinctrl_pcie: pciegrp {
1216 fsl,pins = 1115 fsl,pins =
1217 <MX8MP_IOMUXC_SAI1_TX 1116 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
1218 <MX8MP_IOMUXC_SD2_RES 1117 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1219 }; 1118 };
1220 1119
1221 pinctrl_pmic: pmicirqgrp { 1120 pinctrl_pmic: pmicirqgrp {
1222 fsl,pins = 1121 fsl,pins =
1223 <MX8MP_IOMUXC_GPIO1_I 1122 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1224 }; 1123 };
1225 1124
1226 pinctrl_pwm_1: pwm1grp { 1125 pinctrl_pwm_1: pwm1grp {
1227 fsl,pins = 1126 fsl,pins =
1228 <MX8MP_IOMUXC_SPDIF_E 1127 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
1229 }; 1128 };
1230 1129
1231 pinctrl_pwm_2: pwm2grp { 1130 pinctrl_pwm_2: pwm2grp {
1232 fsl,pins = 1131 fsl,pins =
1233 <MX8MP_IOMUXC_GPIO1_I 1132 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
1234 }; 1133 };
1235 1134
1236 /* Verdin PWM_3_DSI shared with GPIO3 1135 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1237 pinctrl_pwm_3: pwm3grp { 1136 pinctrl_pwm_3: pwm3grp {
1238 fsl,pins = 1137 fsl,pins =
1239 <MX8MP_IOMUXC_SAI5_RX 1138 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
1240 }; 1139 };
1241 1140
1242 /* Verdin PWM_3_DSI (pulled-down as a 1141 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1243 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1h 1142 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1244 fsl,pins = 1143 fsl,pins =
1245 <MX8MP_IOMUXC_SAI5_RX 1144 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
1246 }; 1145 };
1247 1146
1248 pinctrl_reg_eth: regethgrp { 1147 pinctrl_reg_eth: regethgrp {
1249 fsl,pins = 1148 fsl,pins =
1250 <MX8MP_IOMUXC_SD2_WP_ 1149 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
1251 }; 1150 };
1252 1151
1253 pinctrl_sai1: sai1grp { 1152 pinctrl_sai1: sai1grp {
1254 fsl,pins = 1153 fsl,pins =
1255 <MX8MP_IOMUXC_SAI1_MC 1154 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
1256 <MX8MP_IOMUXC_SAI1_RX 1155 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
1257 <MX8MP_IOMUXC_SAI5_MC 1156 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
1258 <MX8MP_IOMUXC_SAI5_RX 1157 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
1259 <MX8MP_IOMUXC_SAI5_RX 1158 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
1260 }; 1159 };
1261 1160
1262 pinctrl_sai3: sai3grp { 1161 pinctrl_sai3: sai3grp {
1263 fsl,pins = 1162 fsl,pins =
1264 <MX8MP_IOMUXC_SAI3_RX 1163 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1265 <MX8MP_IOMUXC_SAI3_TX 1164 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
1266 <MX8MP_IOMUXC_SAI3_TX 1165 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
1267 <MX8MP_IOMUXC_SAI3_TX 1166 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
1268 }; 1167 };
1269 1168
1270 pinctrl_uart1: uart1grp { 1169 pinctrl_uart1: uart1grp {
1271 fsl,pins = 1170 fsl,pins =
1272 <MX8MP_IOMUXC_SAI2_RX 1171 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
1273 <MX8MP_IOMUXC_SAI2_TX 1172 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
1274 <MX8MP_IOMUXC_UART1_R 1173 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
1275 <MX8MP_IOMUXC_UART1_T 1174 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
1276 }; 1175 };
1277 1176
1278 pinctrl_uart2: uart2grp { 1177 pinctrl_uart2: uart2grp {
1279 fsl,pins = 1178 fsl,pins =
1280 <MX8MP_IOMUXC_SD1_DAT 1179 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
1281 <MX8MP_IOMUXC_SD1_DAT 1180 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
1282 <MX8MP_IOMUXC_UART2_R 1181 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
1283 <MX8MP_IOMUXC_UART2_T 1182 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
1284 }; 1183 };
1285 1184
1286 pinctrl_uart3: uart3grp { 1185 pinctrl_uart3: uart3grp {
1287 fsl,pins = 1186 fsl,pins =
1288 <MX8MP_IOMUXC_UART3_R 1187 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
1289 <MX8MP_IOMUXC_UART3_T 1188 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
1290 }; 1189 };
1291 1190
1292 /* Non-wifi usage only */ 1191 /* Non-wifi usage only */
1293 pinctrl_uart4: uart4grp { 1192 pinctrl_uart4: uart4grp {
1294 fsl,pins = 1193 fsl,pins =
1295 <MX8MP_IOMUXC_UART4_R 1194 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
1296 <MX8MP_IOMUXC_UART4_T 1195 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
1297 }; 1196 };
1298 1197
1299 pinctrl_usb1_vbus: usb1vbusgrp { 1198 pinctrl_usb1_vbus: usb1vbusgrp {
1300 fsl,pins = 1199 fsl,pins =
1301 <MX8MP_IOMUXC_GPIO1_I !! 1200 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
1302 }; 1201 };
1303 1202
1304 /* USB_1_ID */ 1203 /* USB_1_ID */
1305 pinctrl_usb_1_id: usb1idgrp { 1204 pinctrl_usb_1_id: usb1idgrp {
1306 fsl,pins = 1205 fsl,pins =
1307 <MX8MP_IOMUXC_SD1_RES 1206 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
1308 }; 1207 };
1309 1208
1310 /* USB_1_OC# */ <<
1311 pinctrl_usb_1_oc_n: usb1ocngrp { <<
1312 fsl,pins = <<
1313 <MX8MP_IOMUXC_GPIO1_I <<
1314 }; <<
1315 <<
1316 pinctrl_usb2_vbus: usb2vbusgrp { 1209 pinctrl_usb2_vbus: usb2vbusgrp {
1317 fsl,pins = 1210 fsl,pins =
1318 <MX8MP_IOMUXC_GPIO1_I !! 1211 <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
1319 }; 1212 };
1320 1213
1321 /* On-module Wi-Fi */ 1214 /* On-module Wi-Fi */
1322 pinctrl_usdhc1: usdhc1grp { 1215 pinctrl_usdhc1: usdhc1grp {
1323 fsl,pins = 1216 fsl,pins =
1324 <MX8MP_IOMUXC_SD1_CLK 1217 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
1325 <MX8MP_IOMUXC_SD1_CMD 1218 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
1326 <MX8MP_IOMUXC_SD1_DAT 1219 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
1327 <MX8MP_IOMUXC_SD1_DAT 1220 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
1328 <MX8MP_IOMUXC_SD1_DAT 1221 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
1329 <MX8MP_IOMUXC_SD1_DAT 1222 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
1330 }; 1223 };
1331 1224
1332 pinctrl_usdhc1_100mhz: usdhc1-100mhzg 1225 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1333 fsl,pins = 1226 fsl,pins =
1334 <MX8MP_IOMUXC_SD1_CLK 1227 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
1335 <MX8MP_IOMUXC_SD1_CMD 1228 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
1336 <MX8MP_IOMUXC_SD1_DAT 1229 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
1337 <MX8MP_IOMUXC_SD1_DAT 1230 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
1338 <MX8MP_IOMUXC_SD1_DAT 1231 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
1339 <MX8MP_IOMUXC_SD1_DAT 1232 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
1340 }; 1233 };
1341 1234
1342 pinctrl_usdhc1_200mhz: usdhc1-200mhzg 1235 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1343 fsl,pins = 1236 fsl,pins =
1344 <MX8MP_IOMUXC_SD1_CLK 1237 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
1345 <MX8MP_IOMUXC_SD1_CMD 1238 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
1346 <MX8MP_IOMUXC_SD1_DAT 1239 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
1347 <MX8MP_IOMUXC_SD1_DAT 1240 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
1348 <MX8MP_IOMUXC_SD1_DAT 1241 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
1349 <MX8MP_IOMUXC_SD1_DAT 1242 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
1350 }; 1243 };
1351 1244
1352 pinctrl_usdhc2_cd: usdhc2cdgrp { 1245 pinctrl_usdhc2_cd: usdhc2cdgrp {
1353 fsl,pins = 1246 fsl,pins =
1354 <MX8MP_IOMUXC_SD2_CD_ 1247 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
1355 }; 1248 };
1356 1249
1357 pinctrl_usdhc2_cd_sleep: usdhc2cdslpg 1250 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1358 fsl,pins = 1251 fsl,pins =
1359 <MX8MP_IOMUXC_SD2_CD_ 1252 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
1360 }; 1253 };
1361 1254
1362 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp 1255 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1363 fsl,pins = 1256 fsl,pins =
1364 <MX8MP_IOMUXC_SAI2_RX 1257 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
1365 }; 1258 };
1366 1259
1367 pinctrl_usdhc2: usdhc2grp { 1260 pinctrl_usdhc2: usdhc2grp {
1368 fsl,pins = 1261 fsl,pins =
1369 <MX8MP_IOMUXC_GPIO1_I 1262 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
1370 <MX8MP_IOMUXC_SD2_CLK 1263 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
1371 <MX8MP_IOMUXC_SD2_CMD 1264 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
1372 <MX8MP_IOMUXC_SD2_DAT 1265 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
1373 <MX8MP_IOMUXC_SD2_DAT 1266 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
1374 <MX8MP_IOMUXC_SD2_DAT 1267 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
1375 <MX8MP_IOMUXC_SD2_DAT 1268 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
1376 }; 1269 };
1377 1270
1378 pinctrl_usdhc2_100mhz: usdhc2-100mhzg 1271 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1379 fsl,pins = 1272 fsl,pins =
1380 <MX8MP_IOMUXC_GPIO1_I 1273 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1381 <MX8MP_IOMUXC_SD2_CLK 1274 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
1382 <MX8MP_IOMUXC_SD2_CMD 1275 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
1383 <MX8MP_IOMUXC_SD2_DAT 1276 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
1384 <MX8MP_IOMUXC_SD2_DAT 1277 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
1385 <MX8MP_IOMUXC_SD2_DAT 1278 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1386 <MX8MP_IOMUXC_SD2_DAT 1279 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
1387 }; 1280 };
1388 1281
1389 pinctrl_usdhc2_200mhz: usdhc2-200mhzg 1282 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1390 fsl,pins = 1283 fsl,pins =
1391 <MX8MP_IOMUXC_GPIO1_I 1284 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1392 <MX8MP_IOMUXC_SD2_CLK 1285 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
1393 <MX8MP_IOMUXC_SD2_CMD 1286 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
1394 <MX8MP_IOMUXC_SD2_DAT 1287 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
1395 <MX8MP_IOMUXC_SD2_DAT 1288 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
1396 <MX8MP_IOMUXC_SD2_DAT 1289 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
1397 <MX8MP_IOMUXC_SD2_DAT 1290 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
1398 }; 1291 };
1399 1292
1400 /* Avoid backfeeding with removed car 1293 /* Avoid backfeeding with removed card power */
1401 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1294 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1402 fsl,pins = 1295 fsl,pins =
1403 <MX8MP_IOMUXC_GPIO1_I 1296 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
1404 <MX8MP_IOMUXC_SD2_CLK 1297 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
1405 <MX8MP_IOMUXC_SD2_CMD 1298 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
1406 <MX8MP_IOMUXC_SD2_DAT 1299 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
1407 <MX8MP_IOMUXC_SD2_DAT 1300 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
1408 <MX8MP_IOMUXC_SD2_DAT 1301 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
1409 <MX8MP_IOMUXC_SD2_DAT 1302 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
1410 }; 1303 };
1411 1304
1412 pinctrl_usdhc3: usdhc3grp { 1305 pinctrl_usdhc3: usdhc3grp {
1413 fsl,pins = 1306 fsl,pins =
1414 <MX8MP_IOMUXC_GPIO1_I 1307 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1415 <MX8MP_IOMUXC_NAND_CE 1308 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
1416 <MX8MP_IOMUXC_NAND_CE 1309 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
1417 <MX8MP_IOMUXC_NAND_CE 1310 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
1418 <MX8MP_IOMUXC_NAND_CL 1311 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
1419 <MX8MP_IOMUXC_NAND_DA 1312 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
1420 <MX8MP_IOMUXC_NAND_DA 1313 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
1421 <MX8MP_IOMUXC_NAND_DA 1314 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
1422 <MX8MP_IOMUXC_NAND_DA 1315 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
1423 <MX8MP_IOMUXC_NAND_RE 1316 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
1424 <MX8MP_IOMUXC_NAND_WE 1317 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
1425 <MX8MP_IOMUXC_NAND_WP 1318 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
1426 }; 1319 };
1427 1320
1428 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1321 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1429 fsl,pins = 1322 fsl,pins =
1430 <MX8MP_IOMUXC_GPIO1_I 1323 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1431 <MX8MP_IOMUXC_NAND_CE 1324 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
1432 <MX8MP_IOMUXC_NAND_CE 1325 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
1433 <MX8MP_IOMUXC_NAND_CE 1326 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
1434 <MX8MP_IOMUXC_NAND_CL 1327 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
1435 <MX8MP_IOMUXC_NAND_DA 1328 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
1436 <MX8MP_IOMUXC_NAND_DA 1329 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
1437 <MX8MP_IOMUXC_NAND_DA 1330 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
1438 <MX8MP_IOMUXC_NAND_DA 1331 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
1439 <MX8MP_IOMUXC_NAND_RE 1332 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
1440 <MX8MP_IOMUXC_NAND_WE 1333 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
1441 <MX8MP_IOMUXC_NAND_WP 1334 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
1442 }; 1335 };
1443 1336
1444 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1337 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1445 fsl,pins = 1338 fsl,pins =
1446 <MX8MP_IOMUXC_GPIO1_I 1339 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1447 <MX8MP_IOMUXC_NAND_CE 1340 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
1448 <MX8MP_IOMUXC_NAND_CE 1341 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
1449 <MX8MP_IOMUXC_NAND_CE 1342 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
1450 <MX8MP_IOMUXC_NAND_CL 1343 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
1451 <MX8MP_IOMUXC_NAND_DA 1344 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
1452 <MX8MP_IOMUXC_NAND_DA 1345 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
1453 <MX8MP_IOMUXC_NAND_DA 1346 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
1454 <MX8MP_IOMUXC_NAND_DA 1347 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
1455 <MX8MP_IOMUXC_NAND_RE 1348 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
1456 <MX8MP_IOMUXC_NAND_WE 1349 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
1457 <MX8MP_IOMUXC_NAND_WP 1350 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
1458 }; 1351 };
1459 1352
1460 pinctrl_wdog: wdoggrp { 1353 pinctrl_wdog: wdoggrp {
1461 fsl,pins = 1354 fsl,pins =
1462 <MX8MP_IOMUXC_GPIO1_I 1355 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
1463 }; 1356 };
1464 1357
1465 pinctrl_bluetooth_ctrl: bluetoothctrl 1358 pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1466 fsl,pins = 1359 fsl,pins =
1467 <MX8MP_IOMUXC_SD1_DAT 1360 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
1468 }; 1361 };
1469 1362
1470 pinctrl_wifi_ctrl: wifictrlgrp { 1363 pinctrl_wifi_ctrl: wifictrlgrp {
1471 fsl,pins = 1364 fsl,pins =
1472 <MX8MP_IOMUXC_SD1_DAT 1365 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
1473 }; 1366 };
1474 1367
1475 pinctrl_wifi_i2s: wifii2sgrp { 1368 pinctrl_wifi_i2s: wifii2sgrp {
1476 fsl,pins = 1369 fsl,pins =
1477 <MX8MP_IOMUXC_SAI2_RX 1370 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
1478 <MX8MP_IOMUXC_SAI5_RX 1371 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
1479 <MX8MP_IOMUXC_SAI5_RX 1372 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
1480 <MX8MP_IOMUXC_SAI5_RX 1373 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
1481 }; 1374 };
1482 1375
1483 pinctrl_wifi_pwr_en: wifipwrengrp { 1376 pinctrl_wifi_pwr_en: wifipwrengrp {
1484 fsl,pins = 1377 fsl,pins =
1485 <MX8MP_IOMUXC_SD1_STR 1378 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
1486 }; 1379 };
1487 }; 1380 };
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