1 // SPDX-License-Identifier: GPL-2.0-or-later O 1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /* 2 /*
3 * Copyright 2022 Toradex 3 * Copyright 2022 Toradex
4 */ 4 */
5 5
6 #include <dt-bindings/phy/phy-imx8-pcie.h> !! 6 #include "dt-bindings/pwm/pwm.h"
7 #include <dt-bindings/pwm/pwm.h> <<
8 #include "imx8mp.dtsi" 7 #include "imx8mp.dtsi"
9 8
10 / { 9 / {
11 chosen { 10 chosen {
12 stdout-path = &uart3; 11 stdout-path = &uart3;
13 }; 12 };
14 13
15 aliases { 14 aliases {
16 /* Ethernet aliases to ensure 15 /* Ethernet aliases to ensure correct MAC addresses */
17 ethernet0 = &eqos; 16 ethernet0 = &eqos;
18 ethernet1 = &fec; 17 ethernet1 = &fec;
19 rtc0 = &rtc_i2c; 18 rtc0 = &rtc_i2c;
20 rtc1 = &snvs_rtc; 19 rtc1 = &snvs_rtc;
21 }; 20 };
22 21
23 backlight: backlight { 22 backlight: backlight {
24 compatible = "pwm-backlight"; 23 compatible = "pwm-backlight";
25 brightness-levels = <0 45 63 8 24 brightness-levels = <0 45 63 88 119 158 203 255>;
26 default-brightness-level = <4> 25 default-brightness-level = <4>;
27 /* Verdin I2S_2_D_OUT (DSI_1_B 26 /* Verdin I2S_2_D_OUT (DSI_1_BKL_EN/DSI_1_BKL_EN_LVDS, SODIMM 46) */
28 enable-gpios = <&gpio5 1 GPIO_ 27 enable-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
29 pinctrl-names = "default"; 28 pinctrl-names = "default";
30 pinctrl-0 = <&pinctrl_i2s_2_d_ 29 pinctrl-0 = <&pinctrl_i2s_2_d_out_dsi_1_bkl_en>;
31 power-supply = <®_3p3v>; 30 power-supply = <®_3p3v>;
32 /* Verdin PWM_3_DSI/PWM_3_DSI_ 31 /* Verdin PWM_3_DSI/PWM_3_DSI_LVDS (SODIMM 19) */
33 pwms = <&pwm3 0 6666667 PWM_PO 32 pwms = <&pwm3 0 6666667 PWM_POLARITY_INVERTED>;
34 status = "disabled"; 33 status = "disabled";
35 }; 34 };
36 35
37 backlight_mezzanine: backlight-mezzani 36 backlight_mezzanine: backlight-mezzanine {
38 compatible = "pwm-backlight"; 37 compatible = "pwm-backlight";
39 brightness-levels = <0 45 63 8 38 brightness-levels = <0 45 63 88 119 158 203 255>;
40 default-brightness-level = <4> 39 default-brightness-level = <4>;
41 /* Verdin GPIO 4 (SODIMM 212) 40 /* Verdin GPIO 4 (SODIMM 212) */
42 enable-gpios = <&gpio1 6 GPIO_ 41 enable-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
43 /* Verdin PWM_2 (SODIMM 16) */ 42 /* Verdin PWM_2 (SODIMM 16) */
44 pwms = <&pwm2 0 6666667 PWM_PO 43 pwms = <&pwm2 0 6666667 PWM_POLARITY_INVERTED>;
45 status = "disabled"; 44 status = "disabled";
46 }; 45 };
47 46
48 connector { <<
49 compatible = "gpio-usb-b-conne <<
50 id-gpios = <&gpio2 10 GPIO_ACT <<
51 label = "Type-C"; <<
52 pinctrl-names = "default"; <<
53 pinctrl-0 = <&pinctrl_usb_1_id <<
54 self-powered; <<
55 type = "micro"; <<
56 vbus-supply = <®_usb1_vbus> <<
57 <<
58 port { <<
59 usb_dr_connector: endp <<
60 remote-endpoin <<
61 }; <<
62 }; <<
63 }; <<
64 <<
65 gpio-keys { 47 gpio-keys {
66 compatible = "gpio-keys"; 48 compatible = "gpio-keys";
67 pinctrl-names = "default"; 49 pinctrl-names = "default";
68 pinctrl-0 = <&pinctrl_gpio_key 50 pinctrl-0 = <&pinctrl_gpio_keys>;
69 51
70 key-wakeup { !! 52 button-wakeup {
71 debounce-interval = <1 53 debounce-interval = <10>;
72 /* Verdin CTRL_WAKE1_M 54 /* Verdin CTRL_WAKE1_MICO# (SODIMM 252) */
73 gpios = <&gpio4 0 GPIO 55 gpios = <&gpio4 0 GPIO_ACTIVE_LOW>;
74 label = "Wake-Up"; 56 label = "Wake-Up";
75 linux,code = <KEY_WAKE 57 linux,code = <KEY_WAKEUP>;
76 wakeup-source; 58 wakeup-source;
77 }; 59 };
78 }; 60 };
79 61
80 sound_hdmi: sound-hdmi { <<
81 compatible = "fsl,imx-audio-hd <<
82 model = "audio-hdmi"; <<
83 audio-cpu = <&aud2htx>; <<
84 hdmi-out; <<
85 status = "disabled"; <<
86 }; <<
87 <<
88 /* Carrier Board Supplies */ 62 /* Carrier Board Supplies */
89 reg_1p8v: regulator-1p8v { 63 reg_1p8v: regulator-1p8v {
90 compatible = "regulator-fixed" 64 compatible = "regulator-fixed";
91 regulator-max-microvolt = <180 65 regulator-max-microvolt = <1800000>;
92 regulator-min-microvolt = <180 66 regulator-min-microvolt = <1800000>;
93 regulator-name = "+V1.8_SW"; 67 regulator-name = "+V1.8_SW";
94 }; 68 };
95 69
96 reg_3p3v: regulator-3p3v { 70 reg_3p3v: regulator-3p3v {
97 compatible = "regulator-fixed" 71 compatible = "regulator-fixed";
98 regulator-max-microvolt = <330 72 regulator-max-microvolt = <3300000>;
99 regulator-min-microvolt = <330 73 regulator-min-microvolt = <3300000>;
100 regulator-name = "+V3.3_SW"; 74 regulator-name = "+V3.3_SW";
101 }; 75 };
102 76
103 reg_5p0v: regulator-5p0v { 77 reg_5p0v: regulator-5p0v {
104 compatible = "regulator-fixed" 78 compatible = "regulator-fixed";
105 regulator-max-microvolt = <500 79 regulator-max-microvolt = <5000000>;
106 regulator-min-microvolt = <500 80 regulator-min-microvolt = <5000000>;
107 regulator-name = "+V5_SW"; 81 regulator-name = "+V5_SW";
108 }; 82 };
109 83
110 /* Non PMIC On-module Supplies */ 84 /* Non PMIC On-module Supplies */
111 reg_module_eth1phy: regulator-module-e 85 reg_module_eth1phy: regulator-module-eth1phy {
112 compatible = "regulator-fixed" 86 compatible = "regulator-fixed";
113 enable-active-high; 87 enable-active-high;
114 gpio = <&gpio2 20 GPIO_ACTIVE_ 88 gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>; /* PMIC_EN_ETH */
115 off-on-delay-us = <500000>; 89 off-on-delay-us = <500000>;
116 pinctrl-names = "default"; 90 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_reg_eth> 91 pinctrl-0 = <&pinctrl_reg_eth>;
118 regulator-always-on; 92 regulator-always-on;
119 regulator-boot-on; 93 regulator-boot-on;
120 regulator-max-microvolt = <330 94 regulator-max-microvolt = <3300000>;
121 regulator-min-microvolt = <330 95 regulator-min-microvolt = <3300000>;
122 regulator-name = "On-module +V 96 regulator-name = "On-module +V3.3_ETH";
123 startup-delay-us = <200000>; 97 startup-delay-us = <200000>;
124 vin-supply = <®_vdd_3v3>; 98 vin-supply = <®_vdd_3v3>;
125 }; 99 };
126 100
127 /* <<
128 * By default we enable CTRL_SLEEP_MOC <<
129 * peripherals on the carrier board po <<
130 * If more granularity or power saving <<
131 * in the carrier board device tree fi <<
132 */ <<
133 reg_force_sleep_moci: regulator-force- <<
134 compatible = "regulator-fixed" <<
135 enable-active-high; <<
136 /* Verdin CTRL_SLEEP_MOCI# (SO <<
137 gpio = <&gpio4 29 GPIO_ACTIVE_ <<
138 regulator-always-on; <<
139 regulator-boot-on; <<
140 regulator-name = "CTRL_SLEEP_M <<
141 }; <<
142 <<
143 reg_usb1_vbus: regulator-usb1-vbus { 101 reg_usb1_vbus: regulator-usb1-vbus {
144 compatible = "regulator-fixed" 102 compatible = "regulator-fixed";
145 enable-active-high; 103 enable-active-high;
146 /* Verdin USB_1_EN (SODIMM 155 104 /* Verdin USB_1_EN (SODIMM 155) */
147 gpio = <&gpio1 12 GPIO_ACTIVE_ 105 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
148 pinctrl-names = "default"; 106 pinctrl-names = "default";
149 pinctrl-0 = <&pinctrl_usb1_vbu 107 pinctrl-0 = <&pinctrl_usb1_vbus>;
150 regulator-max-microvolt = <500 108 regulator-max-microvolt = <5000000>;
151 regulator-min-microvolt = <500 109 regulator-min-microvolt = <5000000>;
152 regulator-name = "USB_1_EN"; 110 regulator-name = "USB_1_EN";
153 }; 111 };
154 112
155 reg_usb2_vbus: regulator-usb2-vbus { 113 reg_usb2_vbus: regulator-usb2-vbus {
156 compatible = "regulator-fixed" 114 compatible = "regulator-fixed";
157 enable-active-high; 115 enable-active-high;
158 /* Verdin USB_2_EN (SODIMM 185 116 /* Verdin USB_2_EN (SODIMM 185) */
159 gpio = <&gpio1 14 GPIO_ACTIVE_ 117 gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
160 pinctrl-names = "default"; 118 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_usb2_vbu 119 pinctrl-0 = <&pinctrl_usb2_vbus>;
162 regulator-max-microvolt = <500 120 regulator-max-microvolt = <5000000>;
163 regulator-min-microvolt = <500 121 regulator-min-microvolt = <5000000>;
164 regulator-name = "USB_2_EN"; 122 regulator-name = "USB_2_EN";
165 }; 123 };
166 124
167 reg_usdhc2_vmmc: regulator-usdhc2 { 125 reg_usdhc2_vmmc: regulator-usdhc2 {
168 compatible = "regulator-fixed" 126 compatible = "regulator-fixed";
169 enable-active-high; 127 enable-active-high;
170 /* Verdin SD_1_PWR_EN (SODIMM 128 /* Verdin SD_1_PWR_EN (SODIMM 76) */
171 gpio = <&gpio4 22 GPIO_ACTIVE_ 129 gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
172 off-on-delay-us = <100000>; 130 off-on-delay-us = <100000>;
173 pinctrl-names = "default"; 131 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_usdhc2_p 132 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
175 regulator-max-microvolt = <330 133 regulator-max-microvolt = <3300000>;
176 regulator-min-microvolt = <330 134 regulator-min-microvolt = <3300000>;
177 regulator-name = "+V3.3_SD"; 135 regulator-name = "+V3.3_SD";
178 startup-delay-us = <2000>; 136 startup-delay-us = <2000>;
179 }; 137 };
180 138
181 reserved-memory { 139 reserved-memory {
182 #address-cells = <2>; 140 #address-cells = <2>;
183 #size-cells = <2>; 141 #size-cells = <2>;
184 ranges; 142 ranges;
185 143
186 /* Use the kernel configuratio 144 /* Use the kernel configuration settings instead */
187 /delete-node/ linux,cma; 145 /delete-node/ linux,cma;
188 }; 146 };
189 }; 147 };
190 148
191 &A53_0 { 149 &A53_0 {
192 cpu-supply = <®_vdd_arm>; 150 cpu-supply = <®_vdd_arm>;
193 }; 151 };
194 152
195 &A53_1 { 153 &A53_1 {
196 cpu-supply = <®_vdd_arm>; 154 cpu-supply = <®_vdd_arm>;
197 }; 155 };
198 156
199 &A53_2 { 157 &A53_2 {
200 cpu-supply = <®_vdd_arm>; 158 cpu-supply = <®_vdd_arm>;
201 }; 159 };
202 160
203 &A53_3 { 161 &A53_3 {
204 cpu-supply = <®_vdd_arm>; 162 cpu-supply = <®_vdd_arm>;
205 }; 163 };
206 164
207 &cpu_alert0 { 165 &cpu_alert0 {
208 temperature = <95000>; 166 temperature = <95000>;
209 }; 167 };
210 168
211 &cpu_crit0 { 169 &cpu_crit0 {
212 temperature = <105000>; 170 temperature = <105000>;
213 }; 171 };
214 172
215 /* Verdin SPI_1 */ 173 /* Verdin SPI_1 */
216 &ecspi1 { 174 &ecspi1 {
217 #address-cells = <1>; 175 #address-cells = <1>;
218 #size-cells = <0>; 176 #size-cells = <0>;
219 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 177 cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
220 pinctrl-names = "default"; 178 pinctrl-names = "default";
221 pinctrl-0 = <&pinctrl_ecspi1>; 179 pinctrl-0 = <&pinctrl_ecspi1>;
222 }; 180 };
223 181
224 /* Verdin ETH_1 (On-module PHY) */ 182 /* Verdin ETH_1 (On-module PHY) */
225 &eqos { 183 &eqos {
226 phy-handle = <ðphy0>; 184 phy-handle = <ðphy0>;
227 phy-mode = "rgmii-id"; 185 phy-mode = "rgmii-id";
>> 186 phy-supply = <®_module_eth1phy>;
228 pinctrl-names = "default"; 187 pinctrl-names = "default";
229 pinctrl-0 = <&pinctrl_eqos>; 188 pinctrl-0 = <&pinctrl_eqos>;
230 snps,force_thresh_dma_mode; 189 snps,force_thresh_dma_mode;
231 snps,mtl-rx-config = <&mtl_rx_setup>; 190 snps,mtl-rx-config = <&mtl_rx_setup>;
232 snps,mtl-tx-config = <&mtl_tx_setup>; 191 snps,mtl-tx-config = <&mtl_tx_setup>;
233 192
234 mdio { 193 mdio {
235 compatible = "snps,dwmac-mdio" 194 compatible = "snps,dwmac-mdio";
236 #address-cells = <1>; 195 #address-cells = <1>;
237 #size-cells = <0>; 196 #size-cells = <0>;
238 197
239 ethphy0: ethernet-phy@7 { 198 ethphy0: ethernet-phy@7 {
240 compatible = "ethernet 199 compatible = "ethernet-phy-ieee802.3-c22";
241 eee-broken-100tx; 200 eee-broken-100tx;
242 eee-broken-1000t; 201 eee-broken-1000t;
243 interrupt-parent = <&g 202 interrupt-parent = <&gpio1>;
244 interrupts = <10 IRQ_T 203 interrupts = <10 IRQ_TYPE_LEVEL_LOW>;
245 micrel,led-mode = <0>; 204 micrel,led-mode = <0>;
246 reg = <7>; 205 reg = <7>;
247 }; 206 };
248 }; 207 };
249 208
250 mtl_rx_setup: rx-queues-config { 209 mtl_rx_setup: rx-queues-config {
251 snps,rx-queues-to-use = <5>; 210 snps,rx-queues-to-use = <5>;
>> 211 snps,rx-sched-sp;
252 212
253 queue0 { 213 queue0 {
254 snps,dcb-algorithm; 214 snps,dcb-algorithm;
255 snps,priority = <0x1>; 215 snps,priority = <0x1>;
256 snps,map-to-dma-channe 216 snps,map-to-dma-channel = <0>;
257 }; 217 };
258 218
259 queue1 { 219 queue1 {
260 snps,dcb-algorithm; 220 snps,dcb-algorithm;
261 snps,priority = <0x2>; 221 snps,priority = <0x2>;
262 snps,map-to-dma-channe 222 snps,map-to-dma-channel = <1>;
263 }; 223 };
264 224
265 queue2 { 225 queue2 {
266 snps,dcb-algorithm; 226 snps,dcb-algorithm;
267 snps,priority = <0x4>; 227 snps,priority = <0x4>;
268 snps,map-to-dma-channe 228 snps,map-to-dma-channel = <2>;
269 }; 229 };
270 230
271 queue3 { 231 queue3 {
272 snps,dcb-algorithm; 232 snps,dcb-algorithm;
273 snps,priority = <0x8>; 233 snps,priority = <0x8>;
274 snps,map-to-dma-channe 234 snps,map-to-dma-channel = <3>;
275 }; 235 };
276 236
277 queue4 { 237 queue4 {
278 snps,dcb-algorithm; 238 snps,dcb-algorithm;
279 snps,priority = <0xf0> 239 snps,priority = <0xf0>;
280 snps,map-to-dma-channe 240 snps,map-to-dma-channel = <4>;
281 }; 241 };
282 }; 242 };
283 243
284 mtl_tx_setup: tx-queues-config { 244 mtl_tx_setup: tx-queues-config {
285 snps,tx-queues-to-use = <5>; 245 snps,tx-queues-to-use = <5>;
>> 246 snps,tx-sched-sp;
286 247
287 queue0 { 248 queue0 {
288 snps,dcb-algorithm; 249 snps,dcb-algorithm;
289 snps,priority = <0x1>; 250 snps,priority = <0x1>;
290 }; 251 };
291 252
292 queue1 { 253 queue1 {
293 snps,dcb-algorithm; 254 snps,dcb-algorithm;
294 snps,priority = <0x2>; 255 snps,priority = <0x2>;
295 }; 256 };
296 257
297 queue2 { 258 queue2 {
298 snps,dcb-algorithm; 259 snps,dcb-algorithm;
299 snps,priority = <0x4>; 260 snps,priority = <0x4>;
300 }; 261 };
301 262
302 queue3 { 263 queue3 {
303 snps,dcb-algorithm; 264 snps,dcb-algorithm;
304 snps,priority = <0x8>; 265 snps,priority = <0x8>;
305 }; 266 };
306 267
307 queue4 { 268 queue4 {
308 snps,dcb-algorithm; 269 snps,dcb-algorithm;
309 snps,priority = <0xf0> 270 snps,priority = <0xf0>;
310 }; 271 };
311 }; 272 };
312 }; 273 };
313 274
314 /* Verdin ETH_2_RGMII */ 275 /* Verdin ETH_2_RGMII */
315 &fec { 276 &fec {
316 fsl,magic-packet; 277 fsl,magic-packet;
317 phy-handle = <ðphy1>; 278 phy-handle = <ðphy1>;
318 phy-mode = "rgmii-id"; 279 phy-mode = "rgmii-id";
319 pinctrl-names = "default", "sleep"; 280 pinctrl-names = "default", "sleep";
320 pinctrl-0 = <&pinctrl_fec>; 281 pinctrl-0 = <&pinctrl_fec>;
321 pinctrl-1 = <&pinctrl_fec_sleep>; 282 pinctrl-1 = <&pinctrl_fec_sleep>;
322 283
323 mdio { 284 mdio {
324 #address-cells = <1>; 285 #address-cells = <1>;
325 #size-cells = <0>; 286 #size-cells = <0>;
326 287
327 ethphy1: ethernet-phy@7 { 288 ethphy1: ethernet-phy@7 {
328 compatible = "ethernet 289 compatible = "ethernet-phy-ieee802.3-c22";
329 interrupt-parent = <&g 290 interrupt-parent = <&gpio4>;
330 interrupts = <18 IRQ_T 291 interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
331 micrel,led-mode = <0>; 292 micrel,led-mode = <0>;
332 reg = <7>; 293 reg = <7>;
333 }; 294 };
334 }; 295 };
335 }; 296 };
336 297
337 /* Verdin CAN_1 */ 298 /* Verdin CAN_1 */
338 &flexcan1 { 299 &flexcan1 {
339 pinctrl-names = "default"; 300 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_flexcan1>; 301 pinctrl-0 = <&pinctrl_flexcan1>;
341 status = "disabled"; 302 status = "disabled";
342 }; 303 };
343 304
344 /* Verdin CAN_2 */ 305 /* Verdin CAN_2 */
345 &flexcan2 { 306 &flexcan2 {
346 pinctrl-names = "default"; 307 pinctrl-names = "default";
347 pinctrl-0 = <&pinctrl_flexcan2>; 308 pinctrl-0 = <&pinctrl_flexcan2>;
348 status = "disabled"; 309 status = "disabled";
349 }; 310 };
350 311
351 /* Verdin QSPI_1 */ 312 /* Verdin QSPI_1 */
352 &flexspi { 313 &flexspi {
353 pinctrl-names = "default"; 314 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_flexspi0>; 315 pinctrl-0 = <&pinctrl_flexspi0>;
355 }; 316 };
356 317
357 &gpio1 { 318 &gpio1 {
358 gpio-line-names = "SODIMM_206", 319 gpio-line-names = "SODIMM_206",
359 "SODIMM_208", 320 "SODIMM_208",
360 "", 321 "",
361 "", 322 "",
362 "", 323 "",
363 "SODIMM_210", 324 "SODIMM_210",
364 "SODIMM_212", 325 "SODIMM_212",
365 "SODIMM_216", 326 "SODIMM_216",
366 "SODIMM_218", 327 "SODIMM_218",
367 "", 328 "",
368 "", 329 "",
369 "SODIMM_16", 330 "SODIMM_16",
370 "SODIMM_155", 331 "SODIMM_155",
371 "SODIMM_157", 332 "SODIMM_157",
372 "SODIMM_185", 333 "SODIMM_185",
373 "SODIMM_91"; 334 "SODIMM_91";
374 }; 335 };
375 336
376 &gpio2 { 337 &gpio2 {
377 gpio-line-names = "", 338 gpio-line-names = "",
378 "", 339 "",
379 "", 340 "",
380 "", 341 "",
381 "", 342 "",
382 "", 343 "",
383 "SODIMM_143", 344 "SODIMM_143",
384 "SODIMM_141", 345 "SODIMM_141",
385 "", 346 "",
386 "", 347 "",
387 "SODIMM_161", 348 "SODIMM_161",
388 "", 349 "",
389 "SODIMM_84", 350 "SODIMM_84",
390 "SODIMM_78", 351 "SODIMM_78",
391 "SODIMM_74", 352 "SODIMM_74",
392 "SODIMM_80", 353 "SODIMM_80",
393 "SODIMM_82", 354 "SODIMM_82",
394 "SODIMM_70", 355 "SODIMM_70",
395 "SODIMM_72"; 356 "SODIMM_72";
396 }; 357 };
397 358
398 &gpio3 { 359 &gpio3 {
399 gpio-line-names = "SODIMM_52", 360 gpio-line-names = "SODIMM_52",
400 "SODIMM_54", 361 "SODIMM_54",
401 "", 362 "",
402 "", 363 "",
403 "", 364 "",
404 "", 365 "",
405 "SODIMM_56", 366 "SODIMM_56",
406 "SODIMM_58", 367 "SODIMM_58",
407 "SODIMM_60", 368 "SODIMM_60",
408 "SODIMM_62", 369 "SODIMM_62",
409 "", 370 "",
410 "", 371 "",
411 "", 372 "",
412 "", 373 "",
413 "SODIMM_66", 374 "SODIMM_66",
414 "", 375 "",
415 "SODIMM_64", 376 "SODIMM_64",
416 "", 377 "",
417 "", 378 "",
418 "SODIMM_34", 379 "SODIMM_34",
419 "SODIMM_19", 380 "SODIMM_19",
420 "", 381 "",
421 "SODIMM_32", 382 "SODIMM_32",
422 "", 383 "",
423 "", 384 "",
424 "SODIMM_30", 385 "SODIMM_30",
425 "SODIMM_59", 386 "SODIMM_59",
426 "SODIMM_57", 387 "SODIMM_57",
427 "SODIMM_63", 388 "SODIMM_63",
428 "SODIMM_61"; 389 "SODIMM_61";
429 }; 390 };
430 391
431 &gpio4 { 392 &gpio4 {
432 gpio-line-names = "SODIMM_252", 393 gpio-line-names = "SODIMM_252",
433 "SODIMM_222", 394 "SODIMM_222",
434 "SODIMM_36", 395 "SODIMM_36",
435 "SODIMM_220", 396 "SODIMM_220",
436 "SODIMM_193", 397 "SODIMM_193",
437 "SODIMM_191", 398 "SODIMM_191",
438 "SODIMM_201", 399 "SODIMM_201",
439 "SODIMM_203", 400 "SODIMM_203",
440 "SODIMM_205", 401 "SODIMM_205",
441 "SODIMM_207", 402 "SODIMM_207",
442 "SODIMM_199", 403 "SODIMM_199",
443 "SODIMM_197", 404 "SODIMM_197",
444 "SODIMM_221", 405 "SODIMM_221",
445 "SODIMM_219", 406 "SODIMM_219",
446 "SODIMM_217", 407 "SODIMM_217",
447 "SODIMM_215", 408 "SODIMM_215",
448 "SODIMM_211", 409 "SODIMM_211",
449 "SODIMM_213", 410 "SODIMM_213",
450 "SODIMM_189", 411 "SODIMM_189",
451 "SODIMM_244", 412 "SODIMM_244",
452 "SODIMM_38", 413 "SODIMM_38",
453 "", 414 "",
454 "SODIMM_76", 415 "SODIMM_76",
455 "SODIMM_135", 416 "SODIMM_135",
456 "SODIMM_133", 417 "SODIMM_133",
457 "SODIMM_17", 418 "SODIMM_17",
458 "SODIMM_24", 419 "SODIMM_24",
459 "SODIMM_26", 420 "SODIMM_26",
460 "SODIMM_21", 421 "SODIMM_21",
461 "SODIMM_256", 422 "SODIMM_256",
462 "SODIMM_48", 423 "SODIMM_48",
463 "SODIMM_44"; 424 "SODIMM_44";
464 }; <<
465 425
466 /* Verdin HDMI_1 */ !! 426 ctrl-sleep-moci-hog {
467 &hdmi_tx { !! 427 gpio-hog;
468 ddc-i2c-bus = <&i2c5>; !! 428 /* Verdin CTRL_SLEEP_MOCI# (SODIMM 256) */
469 pinctrl-names = "default"; !! 429 gpios = <29 GPIO_ACTIVE_HIGH>;
470 pinctrl-0 = <&pinctrl_hdmi>; !! 430 line-name = "CTRL_SLEEP_MOCI#";
>> 431 output-high;
>> 432 pinctrl-names = "default";
>> 433 pinctrl-0 = <&pinctrl_ctrl_sleep_moci>;
>> 434 };
471 }; 435 };
472 436
473 /* On-module I2C */ 437 /* On-module I2C */
474 &i2c1 { 438 &i2c1 {
475 clock-frequency = <400000>; 439 clock-frequency = <400000>;
476 pinctrl-names = "default", "gpio"; 440 pinctrl-names = "default", "gpio";
477 pinctrl-0 = <&pinctrl_i2c1>; 441 pinctrl-0 = <&pinctrl_i2c1>;
478 pinctrl-1 = <&pinctrl_i2c1_gpio>; 442 pinctrl-1 = <&pinctrl_i2c1_gpio>;
479 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HI 443 scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
480 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HI 444 sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
481 status = "okay"; 445 status = "okay";
482 446
483 pca9450: pmic@25 { 447 pca9450: pmic@25 {
484 compatible = "nxp,pca9450c"; 448 compatible = "nxp,pca9450c";
485 interrupt-parent = <&gpio1>; 449 interrupt-parent = <&gpio1>;
486 /* PMIC PCA9450 PMIC_nINT GPIO 450 /* PMIC PCA9450 PMIC_nINT GPIO1_IO3 */
487 interrupts = <3 IRQ_TYPE_LEVEL 451 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
488 pinctrl-names = "default"; 452 pinctrl-names = "default";
489 pinctrl-0 = <&pinctrl_pmic>; 453 pinctrl-0 = <&pinctrl_pmic>;
490 reg = <0x25>; 454 reg = <0x25>;
>> 455 sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
491 456
492 /* 457 /*
493 * The bootloader is expected 458 * The bootloader is expected to switch on LDO4 for the on-module +V3.3_ADC and the
494 * I2C level shifter for the T 459 * I2C level shifter for the TLA2024 ADC behind this PMIC.
495 */ 460 */
496 461
497 regulators { 462 regulators {
498 BUCK1 { 463 BUCK1 {
499 regulator-alwa 464 regulator-always-on;
500 regulator-boot 465 regulator-boot-on;
501 regulator-max- 466 regulator-max-microvolt = <1000000>;
502 regulator-min- 467 regulator-min-microvolt = <720000>;
503 regulator-name 468 regulator-name = "On-module +VDD_SOC (BUCK1)";
504 regulator-ramp 469 regulator-ramp-delay = <3125>;
505 }; 470 };
506 471
507 reg_vdd_arm: BUCK2 { 472 reg_vdd_arm: BUCK2 {
508 nxp,dvs-run-vo 473 nxp,dvs-run-voltage = <950000>;
509 nxp,dvs-standb 474 nxp,dvs-standby-voltage = <850000>;
510 regulator-alwa 475 regulator-always-on;
511 regulator-boot 476 regulator-boot-on;
512 regulator-max- 477 regulator-max-microvolt = <1025000>;
513 regulator-min- 478 regulator-min-microvolt = <720000>;
514 regulator-name 479 regulator-name = "On-module +VDD_ARM (BUCK2)";
515 regulator-ramp 480 regulator-ramp-delay = <3125>;
516 }; 481 };
517 482
518 reg_vdd_3v3: BUCK4 { 483 reg_vdd_3v3: BUCK4 {
519 regulator-alwa 484 regulator-always-on;
520 regulator-boot 485 regulator-boot-on;
521 regulator-max- 486 regulator-max-microvolt = <3300000>;
522 regulator-min- 487 regulator-min-microvolt = <3300000>;
523 regulator-name 488 regulator-name = "On-module +V3.3 (BUCK4)";
524 }; 489 };
525 490
526 reg_vdd_1v8: BUCK5 { 491 reg_vdd_1v8: BUCK5 {
527 regulator-alwa 492 regulator-always-on;
528 regulator-boot 493 regulator-boot-on;
529 regulator-max- 494 regulator-max-microvolt = <1800000>;
530 regulator-min- 495 regulator-min-microvolt = <1800000>;
531 regulator-name 496 regulator-name = "PWR_1V8_MOCI (BUCK5)";
532 }; 497 };
533 498
534 BUCK6 { 499 BUCK6 {
535 regulator-alwa 500 regulator-always-on;
536 regulator-boot 501 regulator-boot-on;
537 regulator-max- 502 regulator-max-microvolt = <1155000>;
538 regulator-min- 503 regulator-min-microvolt = <1045000>;
539 regulator-name 504 regulator-name = "On-module +VDD_DDR (BUCK6)";
540 }; 505 };
541 506
542 LDO1 { 507 LDO1 {
543 regulator-alwa 508 regulator-always-on;
544 regulator-boot 509 regulator-boot-on;
545 regulator-max- 510 regulator-max-microvolt = <1950000>;
546 regulator-min- 511 regulator-min-microvolt = <1650000>;
547 regulator-name 512 regulator-name = "On-module +V1.8_SNVS (LDO1)";
548 }; 513 };
549 514
550 LDO2 { 515 LDO2 {
551 regulator-alwa 516 regulator-always-on;
552 regulator-boot 517 regulator-boot-on;
553 regulator-max- 518 regulator-max-microvolt = <1150000>;
554 regulator-min- 519 regulator-min-microvolt = <800000>;
555 regulator-name 520 regulator-name = "On-module +V0.8_SNVS (LDO2)";
556 }; 521 };
557 522
558 LDO3 { 523 LDO3 {
559 regulator-alwa 524 regulator-always-on;
560 regulator-boot 525 regulator-boot-on;
561 regulator-max- 526 regulator-max-microvolt = <1800000>;
562 regulator-min- 527 regulator-min-microvolt = <1800000>;
563 regulator-name 528 regulator-name = "On-module +V1.8A (LDO3)";
564 }; 529 };
565 530
566 LDO4 { 531 LDO4 {
567 regulator-alwa 532 regulator-always-on;
568 regulator-boot 533 regulator-boot-on;
569 regulator-max- 534 regulator-max-microvolt = <3300000>;
570 regulator-min- 535 regulator-min-microvolt = <3300000>;
571 regulator-name 536 regulator-name = "On-module +V3.3_ADC (LDO4)";
572 }; 537 };
573 538
574 reg_vdd_sdio: LDO5 { !! 539 LDO5 {
575 regulator-max- 540 regulator-max-microvolt = <3300000>;
576 regulator-min- 541 regulator-min-microvolt = <1800000>;
577 regulator-name 542 regulator-name = "On-module +V3.3_1.8_SD (LDO5)";
578 }; 543 };
579 }; 544 };
580 }; 545 };
581 546
582 rtc_i2c: rtc@32 { 547 rtc_i2c: rtc@32 {
583 compatible = "epson,rx8130"; 548 compatible = "epson,rx8130";
584 reg = <0x32>; 549 reg = <0x32>;
585 }; 550 };
586 551
587 /* On-module temperature sensor */ 552 /* On-module temperature sensor */
588 hwmon_temp_module: sensor@48 { 553 hwmon_temp_module: sensor@48 {
589 compatible = "ti,tmp1075"; 554 compatible = "ti,tmp1075";
590 reg = <0x48>; 555 reg = <0x48>;
591 vs-supply = <®_vdd_1v8>; 556 vs-supply = <®_vdd_1v8>;
592 }; 557 };
593 558
594 adc@49 { 559 adc@49 {
595 compatible = "ti,ads1015"; 560 compatible = "ti,ads1015";
596 reg = <0x49>; 561 reg = <0x49>;
597 #address-cells = <1>; 562 #address-cells = <1>;
598 #size-cells = <0>; 563 #size-cells = <0>;
599 564
600 /* Verdin I2C_1 (ADC_4 - ADC_3 565 /* Verdin I2C_1 (ADC_4 - ADC_3) */
601 channel@0 { 566 channel@0 {
602 reg = <0>; 567 reg = <0>;
603 ti,datarate = <4>; 568 ti,datarate = <4>;
604 ti,gain = <2>; 569 ti,gain = <2>;
605 }; 570 };
606 571
607 /* Verdin I2C_1 (ADC_4 - ADC_1 572 /* Verdin I2C_1 (ADC_4 - ADC_1) */
608 channel@1 { 573 channel@1 {
609 reg = <1>; 574 reg = <1>;
610 ti,datarate = <4>; 575 ti,datarate = <4>;
611 ti,gain = <2>; 576 ti,gain = <2>;
612 }; 577 };
613 578
614 /* Verdin I2C_1 (ADC_3 - ADC_1 579 /* Verdin I2C_1 (ADC_3 - ADC_1) */
615 channel@2 { 580 channel@2 {
616 reg = <2>; 581 reg = <2>;
617 ti,datarate = <4>; 582 ti,datarate = <4>;
618 ti,gain = <2>; 583 ti,gain = <2>;
619 }; 584 };
620 585
621 /* Verdin I2C_1 (ADC_2 - ADC_1 586 /* Verdin I2C_1 (ADC_2 - ADC_1) */
622 channel@3 { 587 channel@3 {
623 reg = <3>; 588 reg = <3>;
624 ti,datarate = <4>; 589 ti,datarate = <4>;
625 ti,gain = <2>; 590 ti,gain = <2>;
626 }; 591 };
627 592
628 /* Verdin I2C_1 ADC_4 */ 593 /* Verdin I2C_1 ADC_4 */
629 channel@4 { 594 channel@4 {
630 reg = <4>; 595 reg = <4>;
631 ti,datarate = <4>; 596 ti,datarate = <4>;
632 ti,gain = <2>; 597 ti,gain = <2>;
633 }; 598 };
634 599
635 /* Verdin I2C_1 ADC_3 */ 600 /* Verdin I2C_1 ADC_3 */
636 channel@5 { 601 channel@5 {
637 reg = <5>; 602 reg = <5>;
638 ti,datarate = <4>; 603 ti,datarate = <4>;
639 ti,gain = <2>; 604 ti,gain = <2>;
640 }; 605 };
641 606
642 /* Verdin I2C_1 ADC_2 */ 607 /* Verdin I2C_1 ADC_2 */
643 channel@6 { 608 channel@6 {
644 reg = <6>; 609 reg = <6>;
645 ti,datarate = <4>; 610 ti,datarate = <4>;
646 ti,gain = <2>; 611 ti,gain = <2>;
647 }; 612 };
648 613
649 /* Verdin I2C_1 ADC_1 */ 614 /* Verdin I2C_1 ADC_1 */
650 channel@7 { 615 channel@7 {
651 reg = <7>; 616 reg = <7>;
652 ti,datarate = <4>; 617 ti,datarate = <4>;
653 ti,gain = <2>; 618 ti,gain = <2>;
654 }; 619 };
655 }; 620 };
656 621
657 eeprom@50 { 622 eeprom@50 {
658 compatible = "st,24c02"; 623 compatible = "st,24c02";
659 pagesize = <16>; 624 pagesize = <16>;
660 reg = <0x50>; 625 reg = <0x50>;
661 }; 626 };
662 }; 627 };
663 628
664 /* Verdin I2C_2_DSI */ 629 /* Verdin I2C_2_DSI */
665 &i2c2 { 630 &i2c2 {
666 clock-frequency = <400000>; !! 631 /* Lower frequency to avoid DDC/EDID issues with certain displays/screens. */
>> 632 clock-frequency = <10000>;
667 pinctrl-names = "default", "gpio"; 633 pinctrl-names = "default", "gpio";
668 pinctrl-0 = <&pinctrl_i2c2>; 634 pinctrl-0 = <&pinctrl_i2c2>;
669 pinctrl-1 = <&pinctrl_i2c2_gpio>; 635 pinctrl-1 = <&pinctrl_i2c2_gpio>;
670 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HI 636 scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
671 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HI 637 sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
672 638
673 atmel_mxt_ts_mezzanine: touch-mezzanin 639 atmel_mxt_ts_mezzanine: touch-mezzanine@4a {
674 compatible = "atmel,maxtouch"; 640 compatible = "atmel,maxtouch";
675 /* Verdin GPIO_3 (SODIMM 210) 641 /* Verdin GPIO_3 (SODIMM 210) */
676 interrupt-parent = <&gpio1>; 642 interrupt-parent = <&gpio1>;
677 interrupts = <5 IRQ_TYPE_EDGE_ 643 interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
678 reg = <0x4a>; 644 reg = <0x4a>;
679 /* Verdin GPIO_2 (SODIMM 208) 645 /* Verdin GPIO_2 (SODIMM 208) */
680 reset-gpios = <&gpio1 1 GPIO_A 646 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
681 status = "disabled"; 647 status = "disabled";
682 }; 648 };
683 }; 649 };
684 650
>> 651 /* TODO: Verdin I2C_3_HDMI */
>> 652
685 /* Verdin I2C_4_CSI */ 653 /* Verdin I2C_4_CSI */
686 &i2c3 { 654 &i2c3 {
687 clock-frequency = <400000>; 655 clock-frequency = <400000>;
688 pinctrl-names = "default", "gpio"; 656 pinctrl-names = "default", "gpio";
689 pinctrl-0 = <&pinctrl_i2c3>; 657 pinctrl-0 = <&pinctrl_i2c3>;
690 pinctrl-1 = <&pinctrl_i2c3_gpio>; 658 pinctrl-1 = <&pinctrl_i2c3_gpio>;
691 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HI 659 scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
692 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HI 660 sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
693 }; 661 };
694 662
695 /* Verdin I2C_1 */ 663 /* Verdin I2C_1 */
696 &i2c4 { 664 &i2c4 {
697 clock-frequency = <400000>; 665 clock-frequency = <400000>;
698 pinctrl-names = "default", "gpio"; 666 pinctrl-names = "default", "gpio";
699 pinctrl-0 = <&pinctrl_i2c4>; 667 pinctrl-0 = <&pinctrl_i2c4>;
700 pinctrl-1 = <&pinctrl_i2c4_gpio>; 668 pinctrl-1 = <&pinctrl_i2c4_gpio>;
701 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HI 669 scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
702 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HI 670 sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
703 671
704 gpio_expander_21: gpio-expander@21 { 672 gpio_expander_21: gpio-expander@21 {
705 compatible = "nxp,pcal6416"; 673 compatible = "nxp,pcal6416";
706 #gpio-cells = <2>; 674 #gpio-cells = <2>;
707 gpio-controller; 675 gpio-controller;
708 reg = <0x21>; 676 reg = <0x21>;
709 vcc-supply = <®_3p3v>; 677 vcc-supply = <®_3p3v>;
710 status = "disabled"; 678 status = "disabled";
711 }; 679 };
712 680
713 lvds_ti_sn65dsi84: bridge@2c { !! 681 lvds_ti_sn65dsi83: bridge@2c {
714 compatible = "ti,sn65dsi84"; !! 682 compatible = "ti,sn65dsi83";
715 /* Verdin GPIO_9_DSI (SN65DSI8 683 /* Verdin GPIO_9_DSI (SN65DSI84 IRQ, SODIMM 17, unused) */
716 /* Verdin GPIO_10_DSI (SODIMM 684 /* Verdin GPIO_10_DSI (SODIMM 21) */
717 enable-gpios = <&gpio4 28 GPIO 685 enable-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
718 pinctrl-names = "default"; 686 pinctrl-names = "default";
719 pinctrl-0 = <&pinctrl_gpio_10_ 687 pinctrl-0 = <&pinctrl_gpio_10_dsi>;
720 reg = <0x2c>; 688 reg = <0x2c>;
721 status = "disabled"; 689 status = "disabled";
722 }; 690 };
723 691
724 /* Current measurement into module VCC 692 /* Current measurement into module VCC */
725 hwmon: hwmon@40 { 693 hwmon: hwmon@40 {
726 compatible = "ti,ina219"; 694 compatible = "ti,ina219";
727 reg = <0x40>; 695 reg = <0x40>;
728 shunt-resistor = <10000>; 696 shunt-resistor = <10000>;
729 status = "disabled"; 697 status = "disabled";
730 }; 698 };
731 699
732 hdmi_lontium_lt8912: hdmi@48 { 700 hdmi_lontium_lt8912: hdmi@48 {
733 compatible = "lontium,lt8912b" 701 compatible = "lontium,lt8912b";
734 pinctrl-names = "default"; 702 pinctrl-names = "default";
735 pinctrl-0 = <&pinctrl_gpio_10_ 703 pinctrl-0 = <&pinctrl_gpio_10_dsi>, <&pinctrl_pwm_3_dsi_hpd_gpio>;
736 reg = <0x48>; 704 reg = <0x48>;
737 /* Verdin GPIO_9_DSI (LT8912 I 705 /* Verdin GPIO_9_DSI (LT8912 INT, SODIMM 17, unused) */
738 /* Verdin GPIO_10_DSI (SODIMM 706 /* Verdin GPIO_10_DSI (SODIMM 21) */
739 reset-gpios = <&gpio4 28 GPIO_ 707 reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
740 status = "disabled"; 708 status = "disabled";
741 }; 709 };
742 710
743 atmel_mxt_ts: touch@4a { 711 atmel_mxt_ts: touch@4a {
744 compatible = "atmel,maxtouch"; 712 compatible = "atmel,maxtouch";
745 /* 713 /*
746 * Verdin GPIO_9_DSI 714 * Verdin GPIO_9_DSI
747 * (TOUCH_INT#, SODIMM 17, als !! 715 * (TOUCH_INT#, SODIMM 17, also routed to SN65DSI83 IRQ albeit currently unused)
748 */ 716 */
749 interrupt-parent = <&gpio4>; 717 interrupt-parent = <&gpio4>;
750 interrupts = <25 IRQ_TYPE_EDGE 718 interrupts = <25 IRQ_TYPE_EDGE_FALLING>;
751 pinctrl-names = "default"; 719 pinctrl-names = "default";
752 pinctrl-0 = <&pinctrl_gpio_9_d 720 pinctrl-0 = <&pinctrl_gpio_9_dsi>, <&pinctrl_i2s_2_bclk_touch_reset>;
753 reg = <0x4a>; 721 reg = <0x4a>;
754 /* Verdin I2S_2_BCLK (TOUCH_RE 722 /* Verdin I2S_2_BCLK (TOUCH_RESET#, SODIMM 42) */
755 reset-gpios = <&gpio5 0 GPIO_A 723 reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>;
756 status = "disabled"; 724 status = "disabled";
757 }; 725 };
758 726
759 /* Temperature sensor on carrier board 727 /* Temperature sensor on carrier board */
760 hwmon_temp: sensor@4f { 728 hwmon_temp: sensor@4f {
761 compatible = "ti,tmp75c"; 729 compatible = "ti,tmp75c";
762 reg = <0x4f>; 730 reg = <0x4f>;
763 status = "disabled"; 731 status = "disabled";
764 }; 732 };
765 733
766 /* EEPROM on display adapter (MIPI DSI 734 /* EEPROM on display adapter (MIPI DSI Display Adapter) */
767 eeprom_display_adapter: eeprom@50 { 735 eeprom_display_adapter: eeprom@50 {
768 compatible = "st,24c02"; 736 compatible = "st,24c02";
769 pagesize = <16>; 737 pagesize = <16>;
770 reg = <0x50>; 738 reg = <0x50>;
771 status = "disabled"; 739 status = "disabled";
772 }; 740 };
773 741
774 /* EEPROM on carrier board */ 742 /* EEPROM on carrier board */
775 eeprom_carrier_board: eeprom@57 { 743 eeprom_carrier_board: eeprom@57 {
776 compatible = "st,24c02"; 744 compatible = "st,24c02";
777 pagesize = <16>; 745 pagesize = <16>;
778 reg = <0x57>; 746 reg = <0x57>;
779 status = "disabled"; 747 status = "disabled";
780 }; 748 };
781 }; 749 };
782 750
783 /* Verdin I2C_3_HDMI */ !! 751 /* TODO: Verdin PCIE_1 */
784 &i2c5 { <<
785 clock-frequency = <100000>; <<
786 pinctrl-names = "default", "gpio"; <<
787 pinctrl-0 = <&pinctrl_i2c5>; <<
788 pinctrl-1 = <&pinctrl_i2c5_gpio>; <<
789 scl-gpios = <&gpio3 26 (GPIO_ACTIVE_HI <<
790 sda-gpios = <&gpio3 27 (GPIO_ACTIVE_HI <<
791 }; <<
792 <<
793 /* Verdin PCIE_1 */ <<
794 &pcie { <<
795 pinctrl-names = "default"; <<
796 pinctrl-0 = <&pinctrl_pcie>; <<
797 /* PCIE_1_RESET# (SODIMM 244) */ <<
798 reset-gpio = <&gpio4 19 GPIO_ACTIVE_LO <<
799 }; <<
800 <<
801 &pcie_phy { <<
802 clocks = <&hsio_blk_ctrl>; <<
803 clock-names = "ref"; <<
804 fsl,clkreq-unsupported; <<
805 fsl,refclk-pad-mode = <IMX8_PCIE_REFCL <<
806 }; <<
807 752
808 /* Verdin PWM_1 */ 753 /* Verdin PWM_1 */
809 &pwm1 { 754 &pwm1 {
810 pinctrl-names = "default"; 755 pinctrl-names = "default";
811 pinctrl-0 = <&pinctrl_pwm_1>; 756 pinctrl-0 = <&pinctrl_pwm_1>;
812 #pwm-cells = <3>; 757 #pwm-cells = <3>;
813 }; 758 };
814 759
815 /* Verdin PWM_2 */ 760 /* Verdin PWM_2 */
816 &pwm2 { 761 &pwm2 {
817 pinctrl-names = "default"; 762 pinctrl-names = "default";
818 pinctrl-0 = <&pinctrl_pwm_2>; 763 pinctrl-0 = <&pinctrl_pwm_2>;
819 #pwm-cells = <3>; 764 #pwm-cells = <3>;
820 }; 765 };
821 766
822 /* Verdin PWM_3_DSI */ 767 /* Verdin PWM_3_DSI */
823 &pwm3 { 768 &pwm3 {
824 pinctrl-names = "default"; 769 pinctrl-names = "default";
825 pinctrl-0 = <&pinctrl_pwm_3>; 770 pinctrl-0 = <&pinctrl_pwm_3>;
826 #pwm-cells = <3>; 771 #pwm-cells = <3>;
827 }; 772 };
828 773
829 /* TODO: Verdin I2S_1 */ 774 /* TODO: Verdin I2S_1 */
830 775
831 /* TODO: Verdin I2S_2 */ 776 /* TODO: Verdin I2S_2 */
832 777
833 &snvs_pwrkey { 778 &snvs_pwrkey {
834 status = "okay"; 779 status = "okay";
835 }; 780 };
836 781
837 /* Verdin UART_1 */ 782 /* Verdin UART_1 */
838 &uart1 { 783 &uart1 {
839 pinctrl-names = "default"; 784 pinctrl-names = "default";
840 pinctrl-0 = <&pinctrl_uart1>; 785 pinctrl-0 = <&pinctrl_uart1>;
841 uart-has-rtscts; 786 uart-has-rtscts;
842 }; 787 };
843 788
844 /* Verdin UART_2 */ 789 /* Verdin UART_2 */
845 &uart2 { 790 &uart2 {
846 pinctrl-names = "default"; 791 pinctrl-names = "default";
847 pinctrl-0 = <&pinctrl_uart2>; 792 pinctrl-0 = <&pinctrl_uart2>;
848 uart-has-rtscts; 793 uart-has-rtscts;
849 }; 794 };
850 795
851 /* Verdin UART_3, used as the Linux Console */ 796 /* Verdin UART_3, used as the Linux Console */
852 &uart3 { 797 &uart3 {
853 pinctrl-names = "default"; 798 pinctrl-names = "default";
854 pinctrl-0 = <&pinctrl_uart3>; 799 pinctrl-0 = <&pinctrl_uart3>;
855 }; 800 };
856 801
857 /* Verdin UART_4, used for Bluetooth on Wi-Fi/ 802 /* Verdin UART_4, used for Bluetooth on Wi-Fi/Bluetooth SKUs */
858 &uart4 { 803 &uart4 {
859 pinctrl-names = "default"; 804 pinctrl-names = "default";
860 pinctrl-0 = <&pinctrl_uart4>; 805 pinctrl-0 = <&pinctrl_uart4>;
861 }; 806 };
862 807
863 /* Verdin USB_1 */ 808 /* Verdin USB_1 */
864 &usb3_0 { !! 809 &usb3_phy0 {
865 fsl,disable-port-power-control; !! 810 vbus-supply = <®_usb1_vbus>;
866 fsl,over-current-active-low; <<
867 pinctrl-names = "default"; <<
868 pinctrl-0 = <&pinctrl_usb_1_oc_n>; <<
869 }; 811 };
870 812
871 &usb_dwc3_0 { 813 &usb_dwc3_0 {
872 /* dual role only, not full featured O <<
873 adp-disable; 814 adp-disable;
874 dr_mode = "otg"; 815 dr_mode = "otg";
875 hnp-disable; 816 hnp-disable;
876 maximum-speed = "high-speed"; 817 maximum-speed = "high-speed";
877 role-switch-default-mode = "peripheral !! 818 over-current-active-low;
>> 819 pinctrl-names = "default";
>> 820 pinctrl-0 = <&pinctrl_usb_1_id>;
878 srp-disable; 821 srp-disable;
879 usb-role-switch; <<
880 <<
881 port { <<
882 usb3_dwc: endpoint { <<
883 remote-endpoint = <&us <<
884 }; <<
885 }; <<
886 }; 822 };
887 823
888 /* Verdin USB_2 */ 824 /* Verdin USB_2 */
889 &usb3_1 { <<
890 fsl,disable-port-power-control; <<
891 }; <<
892 <<
893 &usb3_phy1 { 825 &usb3_phy1 {
894 vbus-supply = <®_usb2_vbus>; 826 vbus-supply = <®_usb2_vbus>;
895 }; 827 };
896 828
897 &usb_dwc3_1 { 829 &usb_dwc3_1 {
>> 830 disable-over-current;
898 dr_mode = "host"; 831 dr_mode = "host";
899 }; 832 };
900 833
901 /* Verdin SD_1 */ 834 /* Verdin SD_1 */
902 &usdhc2 { 835 &usdhc2 {
903 assigned-clocks = <&clk IMX8MP_CLK_USD 836 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
904 assigned-clock-rates = <400000000>; 837 assigned-clock-rates = <400000000>;
905 bus-width = <4>; 838 bus-width = <4>;
906 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 839 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
907 disable-wp; 840 disable-wp;
908 pinctrl-names = "default", "state_100m 841 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
909 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 842 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
910 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 843 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_cd>;
911 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 844 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_cd>;
912 pinctrl-3 = <&pinctrl_usdhc2_sleep>, < 845 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd_sleep>;
913 vmmc-supply = <®_usdhc2_vmmc>; 846 vmmc-supply = <®_usdhc2_vmmc>;
914 vqmmc-supply = <®_vdd_sdio>; <<
915 }; 847 };
916 848
917 /* On-module eMMC */ 849 /* On-module eMMC */
918 &usdhc3 { 850 &usdhc3 {
919 assigned-clocks = <&clk IMX8MP_CLK_USD 851 assigned-clocks = <&clk IMX8MP_CLK_USDHC3_ROOT>;
920 assigned-clock-rates = <400000000>; 852 assigned-clock-rates = <400000000>;
921 bus-width = <8>; 853 bus-width = <8>;
922 non-removable; 854 non-removable;
923 pinctrl-names = "default", "state_100m 855 pinctrl-names = "default", "state_100mhz", "state_200mhz";
924 pinctrl-0 = <&pinctrl_usdhc3>; 856 pinctrl-0 = <&pinctrl_usdhc3>;
925 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 857 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
926 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 858 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
927 status = "okay"; 859 status = "okay";
928 }; 860 };
929 861
930 &wdog1 { 862 &wdog1 {
931 fsl,ext-reset-output; 863 fsl,ext-reset-output;
932 pinctrl-names = "default"; 864 pinctrl-names = "default";
933 pinctrl-0 = <&pinctrl_wdog>; 865 pinctrl-0 = <&pinctrl_wdog>;
934 status = "okay"; 866 status = "okay";
935 }; 867 };
936 868
937 &iomuxc { 869 &iomuxc {
938 pinctrl_bt_uart: btuartgrp { 870 pinctrl_bt_uart: btuartgrp {
939 fsl,pins = 871 fsl,pins =
940 <MX8MP_IOMUXC_ECSPI2_M 872 <MX8MP_IOMUXC_ECSPI2_MISO__UART4_DCE_CTS 0x1c4>,
941 <MX8MP_IOMUXC_ECSPI2_M 873 <MX8MP_IOMUXC_ECSPI2_MOSI__UART4_DCE_TX 0x1c4>,
942 <MX8MP_IOMUXC_ECSPI2_S 874 <MX8MP_IOMUXC_ECSPI2_SCLK__UART4_DCE_RX 0x1c4>,
943 <MX8MP_IOMUXC_ECSPI2_S 875 <MX8MP_IOMUXC_ECSPI2_SS0__UART4_DCE_RTS 0x1c4>;
944 }; 876 };
945 877
946 pinctrl_ctrl_sleep_moci: ctrlsleepmoci 878 pinctrl_ctrl_sleep_moci: ctrlsleepmocigrp {
947 fsl,pins = 879 fsl,pins =
948 <MX8MP_IOMUXC_SAI3_RXC 880 <MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x1c4>; /* SODIMM 256 */
949 }; 881 };
950 882
951 pinctrl_ecspi1: ecspi1grp { 883 pinctrl_ecspi1: ecspi1grp {
952 fsl,pins = 884 fsl,pins =
953 <MX8MP_IOMUXC_ECSPI1_M 885 <MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x1c4>, /* SODIMM 198 */
954 <MX8MP_IOMUXC_ECSPI1_M 886 <MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x4>, /* SODIMM 200 */
955 <MX8MP_IOMUXC_ECSPI1_S 887 <MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x4>, /* SODIMM 196 */
956 <MX8MP_IOMUXC_ECSPI1_S 888 <MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x1c4>; /* SODIMM 202 */
957 }; 889 };
958 890
959 /* Connection On Board PHY */ 891 /* Connection On Board PHY */
960 pinctrl_eqos: eqosgrp { 892 pinctrl_eqos: eqosgrp {
961 fsl,pins = 893 fsl,pins =
962 <MX8MP_IOMUXC_ENET_MDC 894 <MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3>,
963 <MX8MP_IOMUXC_ENET_MDI 895 <MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3>,
964 <MX8MP_IOMUXC_ENET_RD0 896 <MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91>,
965 <MX8MP_IOMUXC_ENET_RD1 897 <MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91>,
966 <MX8MP_IOMUXC_ENET_RD2 898 <MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91>,
967 <MX8MP_IOMUXC_ENET_RD3 899 <MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91>,
968 <MX8MP_IOMUXC_ENET_RXC 900 <MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91>,
969 <MX8MP_IOMUXC_ENET_RX_ 901 <MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91>,
970 <MX8MP_IOMUXC_ENET_TD0 902 <MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f>,
971 <MX8MP_IOMUXC_ENET_TD1 903 <MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f>,
972 <MX8MP_IOMUXC_ENET_TD2 904 <MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f>,
973 <MX8MP_IOMUXC_ENET_TD3 905 <MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f>,
974 <MX8MP_IOMUXC_ENET_TX_ 906 <MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f>,
975 <MX8MP_IOMUXC_ENET_TXC 907 <MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f>;
976 }; 908 };
977 909
978 /* ETH_INT# shared with TPM_INT# (usua 910 /* ETH_INT# shared with TPM_INT# (usually N/A) */
979 pinctrl_eth_tpm_int: ethtpmintgrp { 911 pinctrl_eth_tpm_int: ethtpmintgrp {
980 fsl,pins = 912 fsl,pins =
981 <MX8MP_IOMUXC_GPIO1_IO 913 <MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x1c4>;
982 }; 914 };
983 915
984 /* Connection Carrier Board PHY ETH_2 916 /* Connection Carrier Board PHY ETH_2 */
985 pinctrl_fec: fecgrp { 917 pinctrl_fec: fecgrp {
986 fsl,pins = 918 fsl,pins =
987 <MX8MP_IOMUXC_SAI1_RXD 919 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
988 <MX8MP_IOMUXC_SAI1_RXD 920 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
989 <MX8MP_IOMUXC_SAI1_RXD 921 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
990 <MX8MP_IOMUXC_SAI1_RXD 922 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
991 <MX8MP_IOMUXC_SAI1_RXD 923 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
992 <MX8MP_IOMUXC_SAI1_RXD 924 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
993 <MX8MP_IOMUXC_SAI1_TXC 925 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
994 <MX8MP_IOMUXC_SAI1_TXF 926 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
995 <MX8MP_IOMUXC_SAI1_TXD 927 <MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f>, /* SODIMM 221 */
996 <MX8MP_IOMUXC_SAI1_TXD 928 <MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f>, /* SODIMM 219 */
997 <MX8MP_IOMUXC_SAI1_TXD 929 <MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f>, /* SODIMM 217 */
998 <MX8MP_IOMUXC_SAI1_TXD 930 <MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f>, /* SODIMM 215 */
999 <MX8MP_IOMUXC_SAI1_TXD 931 <MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f>, /* SODIMM 211 */
1000 <MX8MP_IOMUXC_SAI1_TX 932 <MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f>, /* SODIMM 213 */
1001 <MX8MP_IOMUXC_SAI1_TX 933 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x1c4>; /* SODIMM 189 */
1002 }; 934 };
1003 935
1004 pinctrl_fec_sleep: fecsleepgrp { 936 pinctrl_fec_sleep: fecsleepgrp {
1005 fsl,pins = 937 fsl,pins =
1006 <MX8MP_IOMUXC_SAI1_RX 938 <MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3>, /* SODIMM 193 */
1007 <MX8MP_IOMUXC_SAI1_RX 939 <MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3>, /* SODIMM 191 */
1008 <MX8MP_IOMUXC_SAI1_RX 940 <MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91>, /* SODIMM 201 */
1009 <MX8MP_IOMUXC_SAI1_RX 941 <MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91>, /* SODIMM 203 */
1010 <MX8MP_IOMUXC_SAI1_RX 942 <MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91>, /* SODIMM 205 */
1011 <MX8MP_IOMUXC_SAI1_RX 943 <MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91>, /* SODIMM 207 */
1012 <MX8MP_IOMUXC_SAI1_TX 944 <MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91>, /* SODIMM 197 */
1013 <MX8MP_IOMUXC_SAI1_TX 945 <MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91>, /* SODIMM 199 */
1014 <MX8MP_IOMUXC_SAI1_TX 946 <MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x1f>, /* SODIMM 221 */
1015 <MX8MP_IOMUXC_SAI1_TX 947 <MX8MP_IOMUXC_SAI1_TXD1__GPIO4_IO13 0x1f>, /* SODIMM 219 */
1016 <MX8MP_IOMUXC_SAI1_TX 948 <MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x1f>, /* SODIMM 217 */
1017 <MX8MP_IOMUXC_SAI1_TX 949 <MX8MP_IOMUXC_SAI1_TXD3__GPIO4_IO15 0x1f>, /* SODIMM 215 */
1018 <MX8MP_IOMUXC_SAI1_TX 950 <MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x1f>, /* SODIMM 211 */
1019 <MX8MP_IOMUXC_SAI1_TX 951 <MX8MP_IOMUXC_SAI1_TXD5__GPIO4_IO17 0x1f>, /* SODIMM 213 */
1020 <MX8MP_IOMUXC_SAI1_TX 952 <MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x184>; /* SODIMM 189 */
1021 }; 953 };
1022 954
1023 pinctrl_flexcan1: flexcan1grp { 955 pinctrl_flexcan1: flexcan1grp {
1024 fsl,pins = 956 fsl,pins =
1025 <MX8MP_IOMUXC_SPDIF_R 957 <MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154>, /* SODIMM 22 */
1026 <MX8MP_IOMUXC_SPDIF_T 958 <MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154>; /* SODIMM 20 */
1027 }; 959 };
1028 960
1029 pinctrl_flexcan2: flexcan2grp { 961 pinctrl_flexcan2: flexcan2grp {
1030 fsl,pins = 962 fsl,pins =
1031 <MX8MP_IOMUXC_SAI2_MC 963 <MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154>, /* SODIMM 26 */
1032 <MX8MP_IOMUXC_SAI2_TX 964 <MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154>; /* SODIMM 24 */
1033 }; 965 };
1034 966
1035 pinctrl_flexspi0: flexspi0grp { 967 pinctrl_flexspi0: flexspi0grp {
1036 fsl,pins = 968 fsl,pins =
1037 <MX8MP_IOMUXC_NAND_AL 969 <MX8MP_IOMUXC_NAND_ALE__FLEXSPI_A_SCLK 0x1c2>, /* SODIMM 52 */
1038 <MX8MP_IOMUXC_NAND_CE 970 <MX8MP_IOMUXC_NAND_CE0_B__FLEXSPI_A_SS0_B 0x82>, /* SODIMM 54 */
1039 <MX8MP_IOMUXC_NAND_DQ 971 <MX8MP_IOMUXC_NAND_DQS__FLEXSPI_A_DQS 0x82>, /* SODIMM 66 */
1040 <MX8MP_IOMUXC_NAND_DA 972 <MX8MP_IOMUXC_NAND_DATA00__FLEXSPI_A_DATA00 0x82>, /* SODIMM 56 */
1041 <MX8MP_IOMUXC_NAND_DA 973 <MX8MP_IOMUXC_NAND_DATA01__FLEXSPI_A_DATA01 0x82>, /* SODIMM 58 */
1042 <MX8MP_IOMUXC_NAND_DA 974 <MX8MP_IOMUXC_NAND_DATA02__FLEXSPI_A_DATA02 0x82>, /* SODIMM 60 */
1043 <MX8MP_IOMUXC_NAND_DA 975 <MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82>, /* SODIMM 62 */
1044 <MX8MP_IOMUXC_NAND_RE 976 <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */
1045 }; 977 };
1046 978
1047 pinctrl_gpio1: gpio1grp { 979 pinctrl_gpio1: gpio1grp {
1048 fsl,pins = 980 fsl,pins =
1049 <MX8MP_IOMUXC_GPIO1_I 981 <MX8MP_IOMUXC_GPIO1_IO00__GPIO1_IO00 0x184>; /* SODIMM 206 */
1050 }; 982 };
1051 983
1052 pinctrl_gpio2: gpio2grp { 984 pinctrl_gpio2: gpio2grp {
1053 fsl,pins = 985 fsl,pins =
1054 <MX8MP_IOMUXC_GPIO1_I 986 <MX8MP_IOMUXC_GPIO1_IO01__GPIO1_IO01 0x1c4>; /* SODIMM 208 */
1055 }; 987 };
1056 988
1057 pinctrl_gpio3: gpio3grp { 989 pinctrl_gpio3: gpio3grp {
1058 fsl,pins = 990 fsl,pins =
1059 <MX8MP_IOMUXC_GPIO1_I 991 <MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x184>; /* SODIMM 210 */
1060 }; 992 };
1061 993
1062 pinctrl_gpio4: gpio4grp { 994 pinctrl_gpio4: gpio4grp {
1063 fsl,pins = 995 fsl,pins =
1064 <MX8MP_IOMUXC_GPIO1_I 996 <MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x184>; /* SODIMM 212 */
1065 }; 997 };
1066 998
1067 pinctrl_gpio5: gpio5grp { 999 pinctrl_gpio5: gpio5grp {
1068 fsl,pins = 1000 fsl,pins =
1069 <MX8MP_IOMUXC_GPIO1_I 1001 <MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x184>; /* SODIMM 216 */
1070 }; 1002 };
1071 1003
1072 pinctrl_gpio6: gpio6grp { 1004 pinctrl_gpio6: gpio6grp {
1073 fsl,pins = 1005 fsl,pins =
1074 <MX8MP_IOMUXC_GPIO1_I 1006 <MX8MP_IOMUXC_GPIO1_IO08__GPIO1_IO08 0x184>; /* SODIMM 218 */
1075 }; 1007 };
1076 1008
1077 pinctrl_gpio7: gpio7grp { 1009 pinctrl_gpio7: gpio7grp {
1078 fsl,pins = 1010 fsl,pins =
1079 <MX8MP_IOMUXC_SAI1_RX 1011 <MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x184>; /* SODIMM 220 */
1080 }; 1012 };
1081 1013
1082 pinctrl_gpio8: gpio8grp { 1014 pinctrl_gpio8: gpio8grp {
1083 fsl,pins = 1015 fsl,pins =
1084 <MX8MP_IOMUXC_SAI1_RX 1016 <MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x184>; /* SODIMM 222 */
1085 }; 1017 };
1086 1018
1087 /* Verdin GPIO_9_DSI (pulled-up as ac 1019 /* Verdin GPIO_9_DSI (pulled-up as active-low) */
1088 pinctrl_gpio_9_dsi: gpio9dsigrp { 1020 pinctrl_gpio_9_dsi: gpio9dsigrp {
1089 fsl,pins = 1021 fsl,pins =
1090 <MX8MP_IOMUXC_SAI2_TX 1022 <MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x1c4>; /* SODIMM 17 */
1091 }; 1023 };
1092 1024
1093 /* Verdin GPIO_10_DSI */ 1025 /* Verdin GPIO_10_DSI */
1094 pinctrl_gpio_10_dsi: gpio10dsigrp { 1026 pinctrl_gpio_10_dsi: gpio10dsigrp {
1095 fsl,pins = 1027 fsl,pins =
1096 <MX8MP_IOMUXC_SAI3_RX 1028 <MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x1c4>; /* SODIMM 21 */
1097 }; 1029 };
1098 1030
1099 /* Non-wifi MSP usage only */ 1031 /* Non-wifi MSP usage only */
1100 pinctrl_gpio_hog1: gpiohog1grp { 1032 pinctrl_gpio_hog1: gpiohog1grp {
1101 fsl,pins = 1033 fsl,pins =
1102 <MX8MP_IOMUXC_ECSPI2_ 1034 <MX8MP_IOMUXC_ECSPI2_MISO__GPIO5_IO12 0x1c4>, /* SODIMM 116 */
1103 <MX8MP_IOMUXC_ECSPI2_ 1035 <MX8MP_IOMUXC_ECSPI2_MOSI__GPIO5_IO11 0x1c4>, /* SODIMM 152 */
1104 <MX8MP_IOMUXC_ECSPI2_ 1036 <MX8MP_IOMUXC_ECSPI2_SCLK__GPIO5_IO10 0x1c4>, /* SODIMM 164 */
1105 <MX8MP_IOMUXC_ECSPI2_ 1037 <MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x1c4>; /* SODIMM 128 */
1106 }; 1038 };
1107 1039
1108 /* USB_2_OC# */ 1040 /* USB_2_OC# */
1109 pinctrl_gpio_hog2: gpiohog2grp { 1041 pinctrl_gpio_hog2: gpiohog2grp {
1110 fsl,pins = 1042 fsl,pins =
1111 <MX8MP_IOMUXC_SAI3_MC 1043 <MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x1c4>; /* SODIMM 187 */
1112 }; 1044 };
1113 1045
1114 pinctrl_gpio_hog3: gpiohog3grp { 1046 pinctrl_gpio_hog3: gpiohog3grp {
1115 fsl,pins = 1047 fsl,pins =
>> 1048 <MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x1c4>, /* SODIMM 157 */
1116 /* CSI_1_MCLK */ 1049 /* CSI_1_MCLK */
1117 <MX8MP_IOMUXC_GPIO1_I 1050 <MX8MP_IOMUXC_GPIO1_IO15__GPIO1_IO15 0x1c4>; /* SODIMM 91 */
1118 }; 1051 };
1119 1052
1120 /* Wifi usage only */ 1053 /* Wifi usage only */
1121 pinctrl_gpio_hog4: gpiohog4grp { 1054 pinctrl_gpio_hog4: gpiohog4grp {
1122 fsl,pins = 1055 fsl,pins =
1123 <MX8MP_IOMUXC_UART4_R 1056 <MX8MP_IOMUXC_UART4_RXD__GPIO5_IO28 0x1c4>, /* SODIMM 151 */
1124 <MX8MP_IOMUXC_UART4_T 1057 <MX8MP_IOMUXC_UART4_TXD__GPIO5_IO29 0x1c4>; /* SODIMM 153 */
1125 }; 1058 };
1126 1059
1127 pinctrl_gpio_keys: gpiokeysgrp { 1060 pinctrl_gpio_keys: gpiokeysgrp {
1128 fsl,pins = 1061 fsl,pins =
1129 <MX8MP_IOMUXC_SAI1_RX 1062 <MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x1c4>; /* SODIMM 252 */
1130 }; 1063 };
1131 1064
1132 pinctrl_hdmi: hdmigrp { !! 1065 pinctrl_hdmi_hog: hdmihoggrp {
1133 fsl,pins = 1066 fsl,pins =
1134 <MX8MP_IOMUXC_HDMI_CE !! 1067 <MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x40000019>, /* SODIMM 63 */
1135 <MX8MP_IOMUXC_HDMI_HP !! 1068 <MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x400001c3>, /* SODIMM 59 */
>> 1069 <MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x400001c3>, /* SODIMM 57 */
>> 1070 <MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000019>; /* SODIMM 61 */
1136 }; 1071 };
1137 1072
1138 /* On-module I2C */ 1073 /* On-module I2C */
1139 pinctrl_i2c1: i2c1grp { 1074 pinctrl_i2c1: i2c1grp {
1140 fsl,pins = 1075 fsl,pins =
1141 <MX8MP_IOMUXC_I2C1_SC 1076 <MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c6>, /* PMIC_I2C_SCL */
1142 <MX8MP_IOMUXC_I2C1_SD 1077 <MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c6>; /* PMIC_I2C_SDA */
1143 }; 1078 };
1144 1079
1145 pinctrl_i2c1_gpio: i2c1gpiogrp { 1080 pinctrl_i2c1_gpio: i2c1gpiogrp {
1146 fsl,pins = 1081 fsl,pins =
1147 <MX8MP_IOMUXC_I2C1_SC 1082 <MX8MP_IOMUXC_I2C1_SCL__GPIO5_IO14 0x400001c6>, /* PMIC_I2C_SCL */
1148 <MX8MP_IOMUXC_I2C1_SD 1083 <MX8MP_IOMUXC_I2C1_SDA__GPIO5_IO15 0x400001c6>; /* PMIC_I2C_SDA */
1149 }; 1084 };
1150 1085
1151 /* Verdin I2C_2_DSI */ 1086 /* Verdin I2C_2_DSI */
1152 pinctrl_i2c2: i2c2grp { 1087 pinctrl_i2c2: i2c2grp {
1153 fsl,pins = 1088 fsl,pins =
1154 <MX8MP_IOMUXC_I2C2_SC 1089 <MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c6>, /* SODIMM 55 */
1155 <MX8MP_IOMUXC_I2C2_SD 1090 <MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c6>; /* SODIMM 53 */
1156 }; 1091 };
1157 1092
1158 pinctrl_i2c2_gpio: i2c2gpiogrp { 1093 pinctrl_i2c2_gpio: i2c2gpiogrp {
1159 fsl,pins = 1094 fsl,pins =
1160 <MX8MP_IOMUXC_I2C2_SC 1095 <MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x400001c6>, /* SODIMM 55 */
1161 <MX8MP_IOMUXC_I2C2_SD 1096 <MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x400001c6>; /* SODIMM 53 */
1162 }; 1097 };
1163 1098
1164 /* Verdin I2C_4_CSI */ 1099 /* Verdin I2C_4_CSI */
1165 pinctrl_i2c3: i2c3grp { 1100 pinctrl_i2c3: i2c3grp {
1166 fsl,pins = 1101 fsl,pins =
1167 <MX8MP_IOMUXC_I2C3_SC 1102 <MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c6>, /* SODIMM 95 */
1168 <MX8MP_IOMUXC_I2C3_SD 1103 <MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c6>; /* SODIMM 93 */
1169 }; 1104 };
1170 1105
1171 pinctrl_i2c3_gpio: i2c3gpiogrp { 1106 pinctrl_i2c3_gpio: i2c3gpiogrp {
1172 fsl,pins = 1107 fsl,pins =
1173 <MX8MP_IOMUXC_I2C3_SC 1108 <MX8MP_IOMUXC_I2C3_SCL__GPIO5_IO18 0x400001c6>, /* SODIMM 95 */
1174 <MX8MP_IOMUXC_I2C3_SD 1109 <MX8MP_IOMUXC_I2C3_SDA__GPIO5_IO19 0x400001c6>; /* SODIMM 93 */
1175 }; 1110 };
1176 1111
1177 /* Verdin I2C_1 */ 1112 /* Verdin I2C_1 */
1178 pinctrl_i2c4: i2c4grp { 1113 pinctrl_i2c4: i2c4grp {
1179 fsl,pins = 1114 fsl,pins =
1180 <MX8MP_IOMUXC_I2C4_SC 1115 <MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c6>, /* SODIMM 14 */
1181 <MX8MP_IOMUXC_I2C4_SD 1116 <MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c6>; /* SODIMM 12 */
1182 }; 1117 };
1183 1118
1184 pinctrl_i2c4_gpio: i2c4gpiogrp { 1119 pinctrl_i2c4_gpio: i2c4gpiogrp {
1185 fsl,pins = 1120 fsl,pins =
1186 <MX8MP_IOMUXC_I2C4_SC 1121 <MX8MP_IOMUXC_I2C4_SCL__GPIO5_IO20 0x400001c6>, /* SODIMM 14 */
1187 <MX8MP_IOMUXC_I2C4_SD 1122 <MX8MP_IOMUXC_I2C4_SDA__GPIO5_IO21 0x400001c6>; /* SODIMM 12 */
1188 }; 1123 };
1189 1124
1190 /* Verdin I2C_3_HDMI */ <<
1191 pinctrl_i2c5: i2c5grp { <<
1192 fsl,pins = <<
1193 <MX8MP_IOMUXC_HDMI_DD <<
1194 <MX8MP_IOMUXC_HDMI_DD <<
1195 }; <<
1196 <<
1197 pinctrl_i2c5_gpio: i2c5gpiogrp { <<
1198 fsl,pins = <<
1199 <MX8MP_IOMUXC_HDMI_DD <<
1200 <MX8MP_IOMUXC_HDMI_DD <<
1201 }; <<
1202 <<
1203 /* Verdin I2S_2_BCLK (TOUCH_RESET#) * 1125 /* Verdin I2S_2_BCLK (TOUCH_RESET#) */
1204 pinctrl_i2s_2_bclk_touch_reset: i2s2b 1126 pinctrl_i2s_2_bclk_touch_reset: i2s2bclktouchresetgrp {
1205 fsl,pins = 1127 fsl,pins =
1206 <MX8MP_IOMUXC_SAI3_TX 1128 <MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x184>; /* SODIMM 42 */
1207 }; 1129 };
1208 1130
1209 /* Verdin I2S_2_D_OUT shared with SAI 1131 /* Verdin I2S_2_D_OUT shared with SAI3 */
1210 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s 1132 pinctrl_i2s_2_d_out_dsi_1_bkl_en: i2s2doutdsi1bklengrp {
1211 fsl,pins = 1133 fsl,pins =
1212 <MX8MP_IOMUXC_SAI3_TX 1134 <MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x184>; /* SODIMM 46 */
1213 }; 1135 };
1214 1136
1215 pinctrl_pcie: pciegrp { 1137 pinctrl_pcie: pciegrp {
1216 fsl,pins = 1138 fsl,pins =
1217 <MX8MP_IOMUXC_SAI1_TX 1139 <MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x4>, /* SODIMM 244 */
1218 <MX8MP_IOMUXC_SD2_RES 1140 <MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x1c4>; /* PMIC_EN_PCIe_CLK, unused */
1219 }; 1141 };
1220 1142
1221 pinctrl_pmic: pmicirqgrp { 1143 pinctrl_pmic: pmicirqgrp {
1222 fsl,pins = 1144 fsl,pins =
1223 <MX8MP_IOMUXC_GPIO1_I 1145 <MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c4>; /* PMIC_INT# */
1224 }; 1146 };
1225 1147
1226 pinctrl_pwm_1: pwm1grp { 1148 pinctrl_pwm_1: pwm1grp {
1227 fsl,pins = 1149 fsl,pins =
1228 <MX8MP_IOMUXC_SPDIF_E 1150 <MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x6>; /* SODIMM 15 */
1229 }; 1151 };
1230 1152
1231 pinctrl_pwm_2: pwm2grp { 1153 pinctrl_pwm_2: pwm2grp {
1232 fsl,pins = 1154 fsl,pins =
1233 <MX8MP_IOMUXC_GPIO1_I 1155 <MX8MP_IOMUXC_GPIO1_IO11__PWM2_OUT 0x6>; /* SODIMM 16 */
1234 }; 1156 };
1235 1157
1236 /* Verdin PWM_3_DSI shared with GPIO3 1158 /* Verdin PWM_3_DSI shared with GPIO3_IO20 */
1237 pinctrl_pwm_3: pwm3grp { 1159 pinctrl_pwm_3: pwm3grp {
1238 fsl,pins = 1160 fsl,pins =
1239 <MX8MP_IOMUXC_SAI5_RX 1161 <MX8MP_IOMUXC_SAI5_RXC__PWM3_OUT 0x6>; /* SODIMM 19 */
1240 }; 1162 };
1241 1163
1242 /* Verdin PWM_3_DSI (pulled-down as a 1164 /* Verdin PWM_3_DSI (pulled-down as active-high) shared with PWM3_OUT */
1243 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1h 1165 pinctrl_pwm_3_dsi_hpd_gpio: pwm3dsi1hpdgpiogrp {
1244 fsl,pins = 1166 fsl,pins =
1245 <MX8MP_IOMUXC_SAI5_RX 1167 <MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x184>; /* SODIMM 19 */
1246 }; 1168 };
1247 1169
1248 pinctrl_reg_eth: regethgrp { 1170 pinctrl_reg_eth: regethgrp {
1249 fsl,pins = 1171 fsl,pins =
1250 <MX8MP_IOMUXC_SD2_WP_ 1172 <MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x184>; /* PMIC_EN_ETH */
1251 }; 1173 };
1252 1174
1253 pinctrl_sai1: sai1grp { 1175 pinctrl_sai1: sai1grp {
1254 fsl,pins = 1176 fsl,pins =
1255 <MX8MP_IOMUXC_SAI1_MC 1177 <MX8MP_IOMUXC_SAI1_MCLK__AUDIOMIX_SAI1_MCLK 0x96>, /* SODIMM 38 */
1256 <MX8MP_IOMUXC_SAI1_RX 1178 <MX8MP_IOMUXC_SAI1_RXD0__AUDIOMIX_SAI1_RX_DATA00 0x1d6>, /* SODIMM 36 */
1257 <MX8MP_IOMUXC_SAI5_MC 1179 <MX8MP_IOMUXC_SAI5_MCLK__AUDIOMIX_SAI1_TX_BCLK 0x1d6>, /* SODIMM 30 */
1258 <MX8MP_IOMUXC_SAI5_RX 1180 <MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI1_TX_SYNC 0x1d6>, /* SODIMM 32 */
1259 <MX8MP_IOMUXC_SAI5_RX 1181 <MX8MP_IOMUXC_SAI5_RXFS__AUDIOMIX_SAI1_TX_DATA00 0x96>; /* SODIMM 34 */
1260 }; 1182 };
1261 1183
1262 pinctrl_sai3: sai3grp { 1184 pinctrl_sai3: sai3grp {
1263 fsl,pins = 1185 fsl,pins =
1264 <MX8MP_IOMUXC_SAI3_RX 1186 <MX8MP_IOMUXC_SAI3_RXD__AUDIOMIX_SAI3_RX_DATA00 0x1d6>, /* SODIMM 48 */
1265 <MX8MP_IOMUXC_SAI3_TX 1187 <MX8MP_IOMUXC_SAI3_TXC__AUDIOMIX_SAI3_TX_BCLK 0x1d6>, /* SODIMM 42 */
1266 <MX8MP_IOMUXC_SAI3_TX 1188 <MX8MP_IOMUXC_SAI3_TXD__AUDIOMIX_SAI3_TX_DATA00 0x96>, /* SODIMM 46 */
1267 <MX8MP_IOMUXC_SAI3_TX 1189 <MX8MP_IOMUXC_SAI3_TXFS__AUDIOMIX_SAI3_TX_SYNC 0x1d6>; /* SODIMM 44 */
1268 }; 1190 };
1269 1191
1270 pinctrl_uart1: uart1grp { 1192 pinctrl_uart1: uart1grp {
1271 fsl,pins = 1193 fsl,pins =
1272 <MX8MP_IOMUXC_SAI2_RX 1194 <MX8MP_IOMUXC_SAI2_RXD0__UART1_DCE_RTS 0x1c4>, /* SODIMM 135 */
1273 <MX8MP_IOMUXC_SAI2_TX 1195 <MX8MP_IOMUXC_SAI2_TXFS__UART1_DCE_CTS 0x1c4>, /* SODIMM 133 */
1274 <MX8MP_IOMUXC_UART1_R 1196 <MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x1c4>, /* SODIMM 129 */
1275 <MX8MP_IOMUXC_UART1_T 1197 <MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x1c4>; /* SODIMM 131 */
1276 }; 1198 };
1277 1199
1278 pinctrl_uart2: uart2grp { 1200 pinctrl_uart2: uart2grp {
1279 fsl,pins = 1201 fsl,pins =
1280 <MX8MP_IOMUXC_SD1_DAT 1202 <MX8MP_IOMUXC_SD1_DATA4__UART2_DCE_RTS 0x1c4>, /* SODIMM 143 */
1281 <MX8MP_IOMUXC_SD1_DAT 1203 <MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x1c4>, /* SODIMM 141 */
1282 <MX8MP_IOMUXC_UART2_R 1204 <MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x1c4>, /* SODIMM 137 */
1283 <MX8MP_IOMUXC_UART2_T 1205 <MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x1c4>; /* SODIMM 139 */
1284 }; 1206 };
1285 1207
1286 pinctrl_uart3: uart3grp { 1208 pinctrl_uart3: uart3grp {
1287 fsl,pins = 1209 fsl,pins =
1288 <MX8MP_IOMUXC_UART3_R 1210 <MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x1c4>, /* SODIMM 147 */
1289 <MX8MP_IOMUXC_UART3_T 1211 <MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x1c4>; /* SODIMM 149 */
1290 }; 1212 };
1291 1213
1292 /* Non-wifi usage only */ 1214 /* Non-wifi usage only */
1293 pinctrl_uart4: uart4grp { 1215 pinctrl_uart4: uart4grp {
1294 fsl,pins = 1216 fsl,pins =
1295 <MX8MP_IOMUXC_UART4_R 1217 <MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x1c4>, /* SODIMM 151 */
1296 <MX8MP_IOMUXC_UART4_T 1218 <MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x1c4>; /* SODIMM 153 */
1297 }; 1219 };
1298 1220
1299 pinctrl_usb1_vbus: usb1vbusgrp { 1221 pinctrl_usb1_vbus: usb1vbusgrp {
1300 fsl,pins = 1222 fsl,pins =
1301 <MX8MP_IOMUXC_GPIO1_I !! 1223 <MX8MP_IOMUXC_GPIO1_IO12__USB1_OTG_PWR 0x19>; /* SODIMM 155 */
1302 }; 1224 };
1303 1225
1304 /* USB_1_ID */ 1226 /* USB_1_ID */
1305 pinctrl_usb_1_id: usb1idgrp { 1227 pinctrl_usb_1_id: usb1idgrp {
1306 fsl,pins = 1228 fsl,pins =
1307 <MX8MP_IOMUXC_SD1_RES 1229 <MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x1c4>; /* SODIMM 161 */
1308 }; 1230 };
1309 1231
1310 /* USB_1_OC# */ <<
1311 pinctrl_usb_1_oc_n: usb1ocngrp { <<
1312 fsl,pins = <<
1313 <MX8MP_IOMUXC_GPIO1_I <<
1314 }; <<
1315 <<
1316 pinctrl_usb2_vbus: usb2vbusgrp { 1232 pinctrl_usb2_vbus: usb2vbusgrp {
1317 fsl,pins = 1233 fsl,pins =
1318 <MX8MP_IOMUXC_GPIO1_I !! 1234 <MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19>; /* SODIMM 185 */
1319 }; 1235 };
1320 1236
1321 /* On-module Wi-Fi */ 1237 /* On-module Wi-Fi */
1322 pinctrl_usdhc1: usdhc1grp { 1238 pinctrl_usdhc1: usdhc1grp {
1323 fsl,pins = 1239 fsl,pins =
1324 <MX8MP_IOMUXC_SD1_CLK 1240 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190>,
1325 <MX8MP_IOMUXC_SD1_CMD 1241 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0>,
1326 <MX8MP_IOMUXC_SD1_DAT 1242 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0>,
1327 <MX8MP_IOMUXC_SD1_DAT 1243 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0>,
1328 <MX8MP_IOMUXC_SD1_DAT 1244 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0>,
1329 <MX8MP_IOMUXC_SD1_DAT 1245 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0>;
1330 }; 1246 };
1331 1247
1332 pinctrl_usdhc1_100mhz: usdhc1-100mhzg 1248 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
1333 fsl,pins = 1249 fsl,pins =
1334 <MX8MP_IOMUXC_SD1_CLK 1250 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194>,
1335 <MX8MP_IOMUXC_SD1_CMD 1251 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4>,
1336 <MX8MP_IOMUXC_SD1_DAT 1252 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4>,
1337 <MX8MP_IOMUXC_SD1_DAT 1253 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4>,
1338 <MX8MP_IOMUXC_SD1_DAT 1254 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4>,
1339 <MX8MP_IOMUXC_SD1_DAT 1255 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4>;
1340 }; 1256 };
1341 1257
1342 pinctrl_usdhc1_200mhz: usdhc1-200mhzg 1258 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1343 fsl,pins = 1259 fsl,pins =
1344 <MX8MP_IOMUXC_SD1_CLK 1260 <MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196>,
1345 <MX8MP_IOMUXC_SD1_CMD 1261 <MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6>,
1346 <MX8MP_IOMUXC_SD1_DAT 1262 <MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6>,
1347 <MX8MP_IOMUXC_SD1_DAT 1263 <MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6>,
1348 <MX8MP_IOMUXC_SD1_DAT 1264 <MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6>,
1349 <MX8MP_IOMUXC_SD1_DAT 1265 <MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6>;
1350 }; 1266 };
1351 1267
1352 pinctrl_usdhc2_cd: usdhc2cdgrp { 1268 pinctrl_usdhc2_cd: usdhc2cdgrp {
1353 fsl,pins = 1269 fsl,pins =
1354 <MX8MP_IOMUXC_SD2_CD_ 1270 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4>; /* SODIMM 84 */
1355 }; 1271 };
1356 1272
1357 pinctrl_usdhc2_cd_sleep: usdhc2cdslpg 1273 pinctrl_usdhc2_cd_sleep: usdhc2cdslpgrp {
1358 fsl,pins = 1274 fsl,pins =
1359 <MX8MP_IOMUXC_SD2_CD_ 1275 <MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x0>; /* SODIMM 84 */
1360 }; 1276 };
1361 1277
1362 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp 1278 pinctrl_usdhc2_pwr_en: usdhc2pwrengrp {
1363 fsl,pins = 1279 fsl,pins =
1364 <MX8MP_IOMUXC_SAI2_RX 1280 <MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x4>; /* SODIMM 76 */
1365 }; 1281 };
1366 1282
1367 pinctrl_usdhc2: usdhc2grp { 1283 pinctrl_usdhc2: usdhc2grp {
1368 fsl,pins = 1284 fsl,pins =
1369 <MX8MP_IOMUXC_GPIO1_I 1285 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>, /* PMIC_USDHC_VSELECT */
1370 <MX8MP_IOMUXC_SD2_CLK 1286 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190>, /* SODIMM 78 */
1371 <MX8MP_IOMUXC_SD2_CMD 1287 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0>, /* SODIMM 74 */
1372 <MX8MP_IOMUXC_SD2_DAT 1288 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0>, /* SODIMM 80 */
1373 <MX8MP_IOMUXC_SD2_DAT 1289 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0>, /* SODIMM 82 */
1374 <MX8MP_IOMUXC_SD2_DAT 1290 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0>, /* SODIMM 70 */
1375 <MX8MP_IOMUXC_SD2_DAT 1291 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0>; /* SODIMM 72 */
1376 }; 1292 };
1377 1293
1378 pinctrl_usdhc2_100mhz: usdhc2-100mhzg 1294 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
1379 fsl,pins = 1295 fsl,pins =
1380 <MX8MP_IOMUXC_GPIO1_I 1296 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1381 <MX8MP_IOMUXC_SD2_CLK 1297 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194>,
1382 <MX8MP_IOMUXC_SD2_CMD 1298 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4>,
1383 <MX8MP_IOMUXC_SD2_DAT 1299 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4>,
1384 <MX8MP_IOMUXC_SD2_DAT 1300 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4>,
1385 <MX8MP_IOMUXC_SD2_DAT 1301 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4>,
1386 <MX8MP_IOMUXC_SD2_DAT 1302 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4>;
1387 }; 1303 };
1388 1304
1389 pinctrl_usdhc2_200mhz: usdhc2-200mhzg 1305 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1390 fsl,pins = 1306 fsl,pins =
1391 <MX8MP_IOMUXC_GPIO1_I 1307 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x4>,
1392 <MX8MP_IOMUXC_SD2_CLK 1308 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196>,
1393 <MX8MP_IOMUXC_SD2_CMD 1309 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6>,
1394 <MX8MP_IOMUXC_SD2_DAT 1310 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6>,
1395 <MX8MP_IOMUXC_SD2_DAT 1311 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6>,
1396 <MX8MP_IOMUXC_SD2_DAT 1312 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6>,
1397 <MX8MP_IOMUXC_SD2_DAT 1313 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6>;
1398 }; 1314 };
1399 1315
1400 /* Avoid backfeeding with removed car 1316 /* Avoid backfeeding with removed card power */
1401 pinctrl_usdhc2_sleep: usdhc2slpgrp { 1317 pinctrl_usdhc2_sleep: usdhc2slpgrp {
1402 fsl,pins = 1318 fsl,pins =
1403 <MX8MP_IOMUXC_GPIO1_I 1319 <MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0x0>,
1404 <MX8MP_IOMUXC_SD2_CLK 1320 <MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x100>,
1405 <MX8MP_IOMUXC_SD2_CMD 1321 <MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x100>,
1406 <MX8MP_IOMUXC_SD2_DAT 1322 <MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x100>,
1407 <MX8MP_IOMUXC_SD2_DAT 1323 <MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x100>,
1408 <MX8MP_IOMUXC_SD2_DAT 1324 <MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x100>,
1409 <MX8MP_IOMUXC_SD2_DAT 1325 <MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x100>;
1410 }; 1326 };
1411 1327
1412 pinctrl_usdhc3: usdhc3grp { 1328 pinctrl_usdhc3: usdhc3grp {
1413 fsl,pins = 1329 fsl,pins =
1414 <MX8MP_IOMUXC_GPIO1_I 1330 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1415 <MX8MP_IOMUXC_NAND_CE 1331 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190>,
1416 <MX8MP_IOMUXC_NAND_CE 1332 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0>,
1417 <MX8MP_IOMUXC_NAND_CE 1333 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0>,
1418 <MX8MP_IOMUXC_NAND_CL 1334 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0>,
1419 <MX8MP_IOMUXC_NAND_DA 1335 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0>,
1420 <MX8MP_IOMUXC_NAND_DA 1336 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0>,
1421 <MX8MP_IOMUXC_NAND_DA 1337 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0>,
1422 <MX8MP_IOMUXC_NAND_DA 1338 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0>,
1423 <MX8MP_IOMUXC_NAND_RE 1339 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0>,
1424 <MX8MP_IOMUXC_NAND_WE 1340 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190>,
1425 <MX8MP_IOMUXC_NAND_WP 1341 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0>;
1426 }; 1342 };
1427 1343
1428 pinctrl_usdhc3_100mhz: usdhc3-100mhzg 1344 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
1429 fsl,pins = 1345 fsl,pins =
1430 <MX8MP_IOMUXC_GPIO1_I 1346 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1431 <MX8MP_IOMUXC_NAND_CE 1347 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194>,
1432 <MX8MP_IOMUXC_NAND_CE 1348 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4>,
1433 <MX8MP_IOMUXC_NAND_CE 1349 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4>,
1434 <MX8MP_IOMUXC_NAND_CL 1350 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4>,
1435 <MX8MP_IOMUXC_NAND_DA 1351 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4>,
1436 <MX8MP_IOMUXC_NAND_DA 1352 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4>,
1437 <MX8MP_IOMUXC_NAND_DA 1353 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4>,
1438 <MX8MP_IOMUXC_NAND_DA 1354 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4>,
1439 <MX8MP_IOMUXC_NAND_RE 1355 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4>,
1440 <MX8MP_IOMUXC_NAND_WE 1356 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194>,
1441 <MX8MP_IOMUXC_NAND_WP 1357 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4>;
1442 }; 1358 };
1443 1359
1444 pinctrl_usdhc3_200mhz: usdhc3-200mhzg 1360 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1445 fsl,pins = 1361 fsl,pins =
1446 <MX8MP_IOMUXC_GPIO1_I 1362 <MX8MP_IOMUXC_GPIO1_IO09__USDHC3_RESET_B 0x1d1>,
1447 <MX8MP_IOMUXC_NAND_CE 1363 <MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196>,
1448 <MX8MP_IOMUXC_NAND_CE 1364 <MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2>,
1449 <MX8MP_IOMUXC_NAND_CE 1365 <MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2>,
1450 <MX8MP_IOMUXC_NAND_CL 1366 <MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2>,
1451 <MX8MP_IOMUXC_NAND_DA 1367 <MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2>,
1452 <MX8MP_IOMUXC_NAND_DA 1368 <MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2>,
1453 <MX8MP_IOMUXC_NAND_DA 1369 <MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2>,
1454 <MX8MP_IOMUXC_NAND_DA 1370 <MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2>,
1455 <MX8MP_IOMUXC_NAND_RE 1371 <MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2>,
1456 <MX8MP_IOMUXC_NAND_WE 1372 <MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196>,
1457 <MX8MP_IOMUXC_NAND_WP 1373 <MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6>;
1458 }; 1374 };
1459 1375
1460 pinctrl_wdog: wdoggrp { 1376 pinctrl_wdog: wdoggrp {
1461 fsl,pins = 1377 fsl,pins =
1462 <MX8MP_IOMUXC_GPIO1_I 1378 <MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6>; /* PMIC_WDI */
1463 }; 1379 };
1464 1380
1465 pinctrl_bluetooth_ctrl: bluetoothctrl 1381 pinctrl_bluetooth_ctrl: bluetoothctrlgrp {
1466 fsl,pins = 1382 fsl,pins =
1467 <MX8MP_IOMUXC_SD1_DAT 1383 <MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x1c4>; /* WIFI_WKUP_BT */
1468 }; 1384 };
1469 1385
1470 pinctrl_wifi_ctrl: wifictrlgrp { 1386 pinctrl_wifi_ctrl: wifictrlgrp {
1471 fsl,pins = 1387 fsl,pins =
1472 <MX8MP_IOMUXC_SD1_DAT 1388 <MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x1c4>; /* WIFI_WKUP_WLAN */
1473 }; 1389 };
1474 1390
1475 pinctrl_wifi_i2s: wifii2sgrp { 1391 pinctrl_wifi_i2s: wifii2sgrp {
1476 fsl,pins = 1392 fsl,pins =
1477 <MX8MP_IOMUXC_SAI2_RX 1393 <MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x1d6>, /* WIFI_TX_SYNC */
1478 <MX8MP_IOMUXC_SAI5_RX 1394 <MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x96>, /* WIFI_RX_DATA0 */
1479 <MX8MP_IOMUXC_SAI5_RX 1395 <MX8MP_IOMUXC_SAI5_RXD2__GPIO3_IO23 0x1d6>, /* WIFI_TX_BCLK */
1480 <MX8MP_IOMUXC_SAI5_RX 1396 <MX8MP_IOMUXC_SAI5_RXD3__GPIO3_IO24 0x1d6>; /* WIFI_TX_DATA0 */
1481 }; 1397 };
1482 1398
1483 pinctrl_wifi_pwr_en: wifipwrengrp { 1399 pinctrl_wifi_pwr_en: wifipwrengrp {
1484 fsl,pins = 1400 fsl,pins =
1485 <MX8MP_IOMUXC_SD1_STR 1401 <MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 0x184>; /* PMIC_EN_WIFI */
1486 }; 1402 };
1487 }; 1403 };
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