1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mp-clock.h> 6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h> <<
8 #include <dt-bindings/reset/imx8mp-reset.h> <<
9 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp. <<
12 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/thermal/thermal.h>
14 11
15 #include "imx8mp-pinfunc.h" 12 #include "imx8mp-pinfunc.h"
16 13
17 / { 14 / {
18 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
19 #address-cells = <2>; 16 #address-cells = <2>;
20 #size-cells = <2>; 17 #size-cells = <2>;
21 18
22 aliases { 19 aliases {
23 ethernet0 = &fec; 20 ethernet0 = &fec;
24 ethernet1 = &eqos; <<
25 gpio0 = &gpio1; 21 gpio0 = &gpio1;
26 gpio1 = &gpio2; 22 gpio1 = &gpio2;
27 gpio2 = &gpio3; 23 gpio2 = &gpio3;
28 gpio3 = &gpio4; 24 gpio3 = &gpio4;
29 gpio4 = &gpio5; 25 gpio4 = &gpio5;
30 i2c0 = &i2c1; 26 i2c0 = &i2c1;
31 i2c1 = &i2c2; 27 i2c1 = &i2c2;
32 i2c2 = &i2c3; 28 i2c2 = &i2c3;
33 i2c3 = &i2c4; 29 i2c3 = &i2c4;
34 i2c4 = &i2c5; 30 i2c4 = &i2c5;
35 i2c5 = &i2c6; 31 i2c5 = &i2c6;
36 mmc0 = &usdhc1; 32 mmc0 = &usdhc1;
37 mmc1 = &usdhc2; 33 mmc1 = &usdhc2;
38 mmc2 = &usdhc3; 34 mmc2 = &usdhc3;
39 serial0 = &uart1; 35 serial0 = &uart1;
40 serial1 = &uart2; 36 serial1 = &uart2;
41 serial2 = &uart3; 37 serial2 = &uart3;
42 serial3 = &uart4; 38 serial3 = &uart4;
43 spi0 = &flexspi; <<
44 }; 39 };
45 40
46 cpus { 41 cpus {
47 #address-cells = <1>; 42 #address-cells = <1>;
48 #size-cells = <0>; 43 #size-cells = <0>;
49 44
50 A53_0: cpu@0 { 45 A53_0: cpu@0 {
51 device_type = "cpu"; 46 device_type = "cpu";
52 compatible = "arm,cort 47 compatible = "arm,cortex-a53";
53 reg = <0x0>; 48 reg = <0x0>;
54 clock-latency = <61036 49 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_ 50 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci" 51 enable-method = "psci";
57 i-cache-size = <0x8000 <<
58 i-cache-line-size = <6 <<
59 i-cache-sets = <256>; <<
60 d-cache-size = <0x8000 <<
61 d-cache-line-size = <6 <<
62 d-cache-sets = <128>; <<
63 next-level-cache = <&A 52 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_sp <<
65 nvmem-cell-names = "sp <<
66 operating-points-v2 = <<
67 #cooling-cells = <2>; 53 #cooling-cells = <2>;
68 }; 54 };
69 55
70 A53_1: cpu@1 { 56 A53_1: cpu@1 {
71 device_type = "cpu"; 57 device_type = "cpu";
72 compatible = "arm,cort 58 compatible = "arm,cortex-a53";
73 reg = <0x1>; 59 reg = <0x1>;
74 clock-latency = <61036 60 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_ 61 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci" 62 enable-method = "psci";
77 i-cache-size = <0x8000 <<
78 i-cache-line-size = <6 <<
79 i-cache-sets = <256>; <<
80 d-cache-size = <0x8000 <<
81 d-cache-line-size = <6 <<
82 d-cache-sets = <128>; <<
83 next-level-cache = <&A 63 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <<
85 #cooling-cells = <2>; 64 #cooling-cells = <2>;
86 }; 65 };
87 66
88 A53_2: cpu@2 { 67 A53_2: cpu@2 {
89 device_type = "cpu"; 68 device_type = "cpu";
90 compatible = "arm,cort 69 compatible = "arm,cortex-a53";
91 reg = <0x2>; 70 reg = <0x2>;
92 clock-latency = <61036 71 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_ 72 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci" 73 enable-method = "psci";
95 i-cache-size = <0x8000 <<
96 i-cache-line-size = <6 <<
97 i-cache-sets = <256>; <<
98 d-cache-size = <0x8000 <<
99 d-cache-line-size = <6 <<
100 d-cache-sets = <128>; <<
101 next-level-cache = <&A 74 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <<
103 #cooling-cells = <2>; 75 #cooling-cells = <2>;
104 }; 76 };
105 77
106 A53_3: cpu@3 { 78 A53_3: cpu@3 {
107 device_type = "cpu"; 79 device_type = "cpu";
108 compatible = "arm,cort 80 compatible = "arm,cortex-a53";
109 reg = <0x3>; 81 reg = <0x3>;
110 clock-latency = <61036 82 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_ 83 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci" 84 enable-method = "psci";
113 i-cache-size = <0x8000 <<
114 i-cache-line-size = <6 <<
115 i-cache-sets = <256>; <<
116 d-cache-size = <0x8000 <<
117 d-cache-line-size = <6 <<
118 d-cache-sets = <128>; <<
119 next-level-cache = <&A 85 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <<
121 #cooling-cells = <2>; 86 #cooling-cells = <2>;
122 }; 87 };
123 88
124 A53_L2: l2-cache0 { 89 A53_L2: l2-cache0 {
125 compatible = "cache"; 90 compatible = "cache";
126 cache-unified; <<
127 cache-level = <2>; <<
128 cache-size = <0x80000> <<
129 cache-line-size = <64> <<
130 cache-sets = <512>; <<
131 }; <<
132 }; <<
133 <<
134 a53_opp_table: opp-table { <<
135 compatible = "operating-points <<
136 opp-shared; <<
137 <<
138 opp-1200000000 { <<
139 opp-hz = /bits/ 64 <12 <<
140 opp-microvolt = <85000 <<
141 opp-supported-hw = <0x <<
142 clock-latency-ns = <15 <<
143 opp-suspend; <<
144 }; <<
145 <<
146 opp-1600000000 { <<
147 opp-hz = /bits/ 64 <16 <<
148 opp-microvolt = <95000 <<
149 opp-supported-hw = <0x <<
150 clock-latency-ns = <15 <<
151 opp-suspend; <<
152 }; <<
153 <<
154 opp-1800000000 { <<
155 opp-hz = /bits/ 64 <18 <<
156 opp-microvolt = <10000 <<
157 opp-supported-hw = <0x <<
158 clock-latency-ns = <15 <<
159 opp-suspend; <<
160 }; 91 };
161 }; 92 };
162 93
163 osc_32k: clock-osc-32k { 94 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock"; 95 compatible = "fixed-clock";
165 #clock-cells = <0>; 96 #clock-cells = <0>;
166 clock-frequency = <32768>; 97 clock-frequency = <32768>;
167 clock-output-names = "osc_32k" 98 clock-output-names = "osc_32k";
168 }; 99 };
169 100
170 osc_24m: clock-osc-24m { 101 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock"; 102 compatible = "fixed-clock";
172 #clock-cells = <0>; 103 #clock-cells = <0>;
173 clock-frequency = <24000000>; 104 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m" 105 clock-output-names = "osc_24m";
175 }; 106 };
176 107
177 clk_ext1: clock-ext1 { 108 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock"; 109 compatible = "fixed-clock";
179 #clock-cells = <0>; 110 #clock-cells = <0>;
180 clock-frequency = <133000000>; 111 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1 112 clock-output-names = "clk_ext1";
182 }; 113 };
183 114
184 clk_ext2: clock-ext2 { 115 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock"; 116 compatible = "fixed-clock";
186 #clock-cells = <0>; 117 #clock-cells = <0>;
187 clock-frequency = <133000000>; 118 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2 119 clock-output-names = "clk_ext2";
189 }; 120 };
190 121
191 clk_ext3: clock-ext3 { 122 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock"; 123 compatible = "fixed-clock";
193 #clock-cells = <0>; 124 #clock-cells = <0>;
194 clock-frequency = <133000000>; 125 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3 126 clock-output-names = "clk_ext3";
196 }; 127 };
197 128
198 clk_ext4: clock-ext4 { 129 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock"; 130 compatible = "fixed-clock";
200 #clock-cells = <0>; 131 #clock-cells = <0>;
201 clock-frequency = <133000000>; !! 132 clock-frequency= <133000000>;
202 clock-output-names = "clk_ext4 133 clock-output-names = "clk_ext4";
203 }; 134 };
204 135
205 funnel { <<
206 /* <<
207 * non-configurable funnel don <<
208 * bus. As such no need to ad <<
209 */ <<
210 compatible = "arm,coresight-st <<
211 <<
212 in-ports { <<
213 #address-cells = <1>; <<
214 #size-cells = <0>; <<
215 <<
216 port@0 { <<
217 reg = <0>; <<
218 <<
219 ca_funnel_in_p <<
220 remote <<
221 }; <<
222 }; <<
223 <<
224 port@1 { <<
225 reg = <1>; <<
226 <<
227 ca_funnel_in_p <<
228 remote <<
229 }; <<
230 }; <<
231 <<
232 port@2 { <<
233 reg = <2>; <<
234 <<
235 ca_funnel_in_p <<
236 remote <<
237 }; <<
238 }; <<
239 <<
240 port@3 { <<
241 reg = <3>; <<
242 <<
243 ca_fun <<
244 remote <<
245 }; <<
246 }; <<
247 }; <<
248 <<
249 out-ports { <<
250 port { <<
251 <<
252 ca_funnel_out_ <<
253 remote <<
254 }; <<
255 }; <<
256 }; <<
257 }; <<
258 <<
259 reserved-memory { <<
260 #address-cells = <2>; <<
261 #size-cells = <2>; <<
262 ranges; <<
263 <<
264 dsp_reserved: dsp@92400000 { <<
265 reg = <0 0x92400000 0 <<
266 no-map; <<
267 status = "disabled"; <<
268 }; <<
269 }; <<
270 <<
271 pmu { <<
272 compatible = "arm,cortex-a53-p <<
273 interrupts = <GIC_PPI 7 <<
274 (GIC_CPU_MASK_SIM <<
275 }; <<
276 <<
277 psci { 136 psci {
278 compatible = "arm,psci-1.0"; 137 compatible = "arm,psci-1.0";
279 method = "smc"; 138 method = "smc";
280 }; 139 };
281 140
282 thermal-zones { 141 thermal-zones {
283 cpu-thermal { 142 cpu-thermal {
284 polling-delay-passive 143 polling-delay-passive = <250>;
285 polling-delay = <2000> 144 polling-delay = <2000>;
286 thermal-sensors = <&tm 145 thermal-sensors = <&tmu 0>;
287 trips { 146 trips {
288 cpu_alert0: tr 147 cpu_alert0: trip0 {
289 temper 148 temperature = <85000>;
290 hyster 149 hysteresis = <2000>;
291 type = 150 type = "passive";
292 }; 151 };
293 152
294 cpu_crit0: tri 153 cpu_crit0: trip1 {
295 temper 154 temperature = <95000>;
296 hyster 155 hysteresis = <2000>;
297 type = 156 type = "critical";
298 }; 157 };
299 }; 158 };
300 159
301 cooling-maps { 160 cooling-maps {
302 map0 { 161 map0 {
303 trip = 162 trip = <&cpu_alert0>;
304 coolin 163 cooling-device =
305 164 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
306 165 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
307 166 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
308 167 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
309 }; 168 };
310 }; 169 };
311 }; 170 };
312 171
313 soc-thermal { 172 soc-thermal {
314 polling-delay-passive 173 polling-delay-passive = <250>;
315 polling-delay = <2000> 174 polling-delay = <2000>;
316 thermal-sensors = <&tm 175 thermal-sensors = <&tmu 1>;
317 trips { 176 trips {
318 soc_alert0: tr 177 soc_alert0: trip0 {
319 temper 178 temperature = <85000>;
320 hyster 179 hysteresis = <2000>;
321 type = 180 type = "passive";
322 }; 181 };
323 182
324 soc_crit0: tri 183 soc_crit0: trip1 {
325 temper 184 temperature = <95000>;
326 hyster 185 hysteresis = <2000>;
327 type = 186 type = "critical";
328 }; 187 };
329 }; 188 };
330 189
331 cooling-maps { 190 cooling-maps {
332 map0 { 191 map0 {
333 trip = 192 trip = <&soc_alert0>;
334 coolin 193 cooling-device =
335 194 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
336 195 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
337 196 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
338 197 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 }; 198 };
340 }; 199 };
341 }; 200 };
342 }; 201 };
343 202
344 timer { 203 timer {
345 compatible = "arm,armv8-timer" 204 compatible = "arm,armv8-timer";
346 interrupts = <GIC_PPI 13 (GIC_ !! 205 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
347 <GIC_PPI 14 (GIC_ !! 206 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
348 <GIC_PPI 11 (GIC_ !! 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
349 <GIC_PPI 10 (GIC_ !! 208 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
350 clock-frequency = <8000000>; 209 clock-frequency = <8000000>;
351 arm,no-tick-in-suspend; 210 arm,no-tick-in-suspend;
352 }; 211 };
353 212
354 soc: soc@0 { !! 213 soc@0 {
355 compatible = "fsl,imx8mp-soc", !! 214 compatible = "simple-bus";
356 #address-cells = <1>; 215 #address-cells = <1>;
357 #size-cells = <1>; 216 #size-cells = <1>;
358 ranges = <0x0 0x0 0x0 0x3e0000 217 ranges = <0x0 0x0 0x0 0x3e000000>;
359 nvmem-cells = <&imx8mp_uid>; <<
360 nvmem-cell-names = "soc_unique <<
361 <<
362 etm0: etm@28440000 { <<
363 compatible = "arm,core <<
364 reg = <0x28440000 0x10 <<
365 cpu = <&A53_0>; <<
366 clocks = <&clk IMX8MP_ <<
367 clock-names = "apb_pcl <<
368 <<
369 out-ports { <<
370 port { <<
371 etm0_o <<
372 <<
373 }; <<
374 }; <<
375 }; <<
376 }; <<
377 <<
378 etm1: etm@28540000 { <<
379 compatible = "arm,core <<
380 reg = <0x28540000 0x10 <<
381 cpu = <&A53_1>; <<
382 clocks = <&clk IMX8MP_ <<
383 clock-names = "apb_pcl <<
384 <<
385 out-ports { <<
386 port { <<
387 etm1_o <<
388 <<
389 }; <<
390 }; <<
391 }; <<
392 }; <<
393 <<
394 etm2: etm@28640000 { <<
395 compatible = "arm,core <<
396 reg = <0x28640000 0x10 <<
397 cpu = <&A53_2>; <<
398 clocks = <&clk IMX8MP_ <<
399 clock-names = "apb_pcl <<
400 <<
401 out-ports { <<
402 port { <<
403 etm2_o <<
404 <<
405 }; <<
406 }; <<
407 }; <<
408 }; <<
409 <<
410 etm3: etm@28740000 { <<
411 compatible = "arm,core <<
412 reg = <0x28740000 0x10 <<
413 cpu = <&A53_3>; <<
414 clocks = <&clk IMX8MP_ <<
415 clock-names = "apb_pcl <<
416 <<
417 out-ports { <<
418 port { <<
419 etm3_o <<
420 <<
421 }; <<
422 }; <<
423 }; <<
424 }; <<
425 <<
426 funnel@28c03000 { <<
427 compatible = "arm,core <<
428 reg = <0x28c03000 0x10 <<
429 clocks = <&clk IMX8MP_ <<
430 clock-names = "apb_pcl <<
431 <<
432 in-ports { <<
433 #address-cells <<
434 #size-cells = <<
435 <<
436 port@0 { <<
437 reg = <<
438 <<
439 hugo_f <<
440 <<
441 }; <<
442 }; <<
443 <<
444 port@1 { <<
445 reg = <<
446 <<
447 hugo_f <<
448 /* M7 <<
449 }; <<
450 }; <<
451 <<
452 port@2 { <<
453 reg = <<
454 <<
455 hugo_f <<
456 /* DSP <<
457 }; <<
458 }; <<
459 /* the other i <<
460 }; <<
461 <<
462 out-ports { <<
463 port { <<
464 hugo_f <<
465 <<
466 }; <<
467 }; <<
468 }; <<
469 }; <<
470 <<
471 etf@28c04000 { <<
472 compatible = "arm,core <<
473 reg = <0x28c04000 0x10 <<
474 clocks = <&clk IMX8MP_ <<
475 clock-names = "apb_pcl <<
476 <<
477 in-ports { <<
478 port { <<
479 etf_in <<
480 <<
481 }; <<
482 }; <<
483 }; <<
484 <<
485 out-ports { <<
486 port { <<
487 etf_ou <<
488 <<
489 }; <<
490 }; <<
491 }; <<
492 }; <<
493 <<
494 etr@28c06000 { <<
495 compatible = "arm,core <<
496 reg = <0x28c06000 0x10 <<
497 clocks = <&clk IMX8MP_ <<
498 clock-names = "apb_pcl <<
499 <<
500 in-ports { <<
501 port { <<
502 etr_in <<
503 <<
504 }; <<
505 }; <<
506 }; <<
507 }; <<
508 218
509 aips1: bus@30000000 { 219 aips1: bus@30000000 {
510 compatible = "fsl,aips 220 compatible = "fsl,aips-bus", "simple-bus";
511 reg = <0x30000000 0x40 221 reg = <0x30000000 0x400000>;
512 #address-cells = <1>; 222 #address-cells = <1>;
513 #size-cells = <1>; 223 #size-cells = <1>;
514 ranges; 224 ranges;
515 225
516 gpio1: gpio@30200000 { 226 gpio1: gpio@30200000 {
517 compatible = " 227 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
518 reg = <0x30200 228 reg = <0x30200000 0x10000>;
519 interrupts = < 229 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
520 < 230 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clk 231 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
522 gpio-controlle 232 gpio-controller;
523 #gpio-cells = 233 #gpio-cells = <2>;
524 interrupt-cont 234 interrupt-controller;
525 #interrupt-cel 235 #interrupt-cells = <2>;
526 gpio-ranges = 236 gpio-ranges = <&iomuxc 0 5 30>;
527 }; 237 };
528 238
529 gpio2: gpio@30210000 { 239 gpio2: gpio@30210000 {
530 compatible = " 240 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
531 reg = <0x30210 241 reg = <0x30210000 0x10000>;
532 interrupts = < 242 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
533 < 243 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clk 244 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
535 gpio-controlle 245 gpio-controller;
536 #gpio-cells = 246 #gpio-cells = <2>;
537 interrupt-cont 247 interrupt-controller;
538 #interrupt-cel 248 #interrupt-cells = <2>;
539 gpio-ranges = 249 gpio-ranges = <&iomuxc 0 35 21>;
540 }; 250 };
541 251
542 gpio3: gpio@30220000 { 252 gpio3: gpio@30220000 {
543 compatible = " 253 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
544 reg = <0x30220 254 reg = <0x30220000 0x10000>;
545 interrupts = < 255 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
546 < 256 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clk 257 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
548 gpio-controlle 258 gpio-controller;
549 #gpio-cells = 259 #gpio-cells = <2>;
550 interrupt-cont 260 interrupt-controller;
551 #interrupt-cel 261 #interrupt-cells = <2>;
552 gpio-ranges = 262 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
553 }; 263 };
554 264
555 gpio4: gpio@30230000 { 265 gpio4: gpio@30230000 {
556 compatible = " 266 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
557 reg = <0x30230 267 reg = <0x30230000 0x10000>;
558 interrupts = < 268 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
559 < 269 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clk 270 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
561 gpio-controlle 271 gpio-controller;
562 #gpio-cells = 272 #gpio-cells = <2>;
563 interrupt-cont 273 interrupt-controller;
564 #interrupt-cel 274 #interrupt-cells = <2>;
565 gpio-ranges = 275 gpio-ranges = <&iomuxc 0 82 32>;
566 }; 276 };
567 277
568 gpio5: gpio@30240000 { 278 gpio5: gpio@30240000 {
569 compatible = " 279 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
570 reg = <0x30240 280 reg = <0x30240000 0x10000>;
571 interrupts = < 281 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
572 < 282 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk 283 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
574 gpio-controlle 284 gpio-controller;
575 #gpio-cells = 285 #gpio-cells = <2>;
576 interrupt-cont 286 interrupt-controller;
577 #interrupt-cel 287 #interrupt-cells = <2>;
578 gpio-ranges = 288 gpio-ranges = <&iomuxc 0 114 30>;
579 }; 289 };
580 290
581 tmu: tmu@30260000 { 291 tmu: tmu@30260000 {
582 compatible = " 292 compatible = "fsl,imx8mp-tmu";
583 reg = <0x30260 293 reg = <0x30260000 0x10000>;
584 clocks = <&clk 294 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
585 nvmem-cells = <<
586 nvmem-cell-nam <<
587 #thermal-senso 295 #thermal-sensor-cells = <1>;
588 }; 296 };
589 297
590 wdog1: watchdog@302800 298 wdog1: watchdog@30280000 {
591 compatible = " 299 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
592 reg = <0x30280 300 reg = <0x30280000 0x10000>;
593 interrupts = < 301 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clk 302 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
595 status = "disa 303 status = "disabled";
596 }; 304 };
597 305
598 wdog2: watchdog@302900 <<
599 compatible = " <<
600 reg = <0x30290 <<
601 interrupts = < <<
602 clocks = <&clk <<
603 status = "disa <<
604 }; <<
605 <<
606 wdog3: watchdog@302a00 <<
607 compatible = " <<
608 reg = <0x302a0 <<
609 interrupts = < <<
610 clocks = <&clk <<
611 status = "disa <<
612 }; <<
613 <<
614 gpt1: timer@302d0000 { <<
615 compatible = " <<
616 reg = <0x302d0 <<
617 interrupts = < <<
618 clocks = <&clk <<
619 clock-names = <<
620 }; <<
621 <<
622 gpt2: timer@302e0000 { <<
623 compatible = " <<
624 reg = <0x302e0 <<
625 interrupts = < <<
626 clocks = <&clk <<
627 clock-names = <<
628 }; <<
629 <<
630 gpt3: timer@302f0000 { <<
631 compatible = " <<
632 reg = <0x302f0 <<
633 interrupts = < <<
634 clocks = <&clk <<
635 clock-names = <<
636 }; <<
637 <<
638 iomuxc: pinctrl@303300 306 iomuxc: pinctrl@30330000 {
639 compatible = " 307 compatible = "fsl,imx8mp-iomuxc";
640 reg = <0x30330 308 reg = <0x30330000 0x10000>;
641 }; 309 };
642 310
643 gpr: syscon@30340000 { !! 311 gpr: iomuxc-gpr@30340000 {
644 compatible = " 312 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
645 reg = <0x30340 313 reg = <0x30340000 0x10000>;
646 }; 314 };
647 315
648 ocotp: efuse@30350000 316 ocotp: efuse@30350000 {
649 compatible = " 317 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
650 reg = <0x30350 318 reg = <0x30350000 0x10000>;
651 clocks = <&clk 319 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
652 /* For nvmem s 320 /* For nvmem subnodes */
653 #address-cells 321 #address-cells = <1>;
654 #size-cells = 322 #size-cells = <1>;
655 323
656 /* !! 324 cpu_speed_grade: speed-grade@10 {
657 * The registe <<
658 * Fusemap Des <<
659 * Assuming <<
660 * reg = <AD <<
661 * then <<
662 * Fuse Addr <<
663 * Note that i <<
664 * each subseq <<
665 * +0x10 in Fu <<
666 * reg = <0x8 <<
667 * 0x430). <<
668 */ <<
669 imx8mp_uid: un <<
670 reg = <<
671 }; <<
672 <<
673 cpu_speed_grad <<
674 reg = 325 reg = <0x10 4>;
675 }; 326 };
676 <<
677 eth_mac1: mac- <<
678 reg = <<
679 }; <<
680 <<
681 eth_mac2: mac- <<
682 reg = <<
683 }; <<
684 <<
685 tmu_calib: cal <<
686 reg = <<
687 }; <<
688 }; 327 };
689 328
690 anatop: clock-controll !! 329 anatop: anatop@30360000 {
691 compatible = " !! 330 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
>> 331 "syscon";
692 reg = <0x30360 332 reg = <0x30360000 0x10000>;
693 #clock-cells = <<
694 }; 333 };
695 334
696 snvs: snvs@30370000 { 335 snvs: snvs@30370000 {
697 compatible = " 336 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 reg = <0x30370 337 reg = <0x30370000 0x10000>;
699 338
700 snvs_rtc: snvs 339 snvs_rtc: snvs-rtc-lp {
701 compat 340 compatible = "fsl,sec-v4.0-mon-rtc-lp";
702 regmap !! 341 regmap =<&snvs>;
703 offset 342 offset = <0x34>;
704 interr 343 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
705 344 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
706 clocks 345 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
707 clock- 346 clock-names = "snvs-rtc";
708 }; 347 };
709 348
710 snvs_pwrkey: s 349 snvs_pwrkey: snvs-powerkey {
711 compat 350 compatible = "fsl,sec-v4.0-pwrkey";
712 regmap 351 regmap = <&snvs>;
713 interr 352 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
714 clocks 353 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
715 clock- 354 clock-names = "snvs-pwrkey";
716 linux, 355 linux,keycode = <KEY_POWER>;
717 wakeup 356 wakeup-source;
718 status 357 status = "disabled";
719 }; 358 };
720 <<
721 snvs_lpgpr: sn <<
722 compat <<
723 <<
724 }; <<
725 }; 359 };
726 360
727 clk: clock-controller@ 361 clk: clock-controller@30380000 {
728 compatible = " 362 compatible = "fsl,imx8mp-ccm";
729 reg = <0x30380 363 reg = <0x30380000 0x10000>;
730 interrupts = < <<
731 < <<
732 #clock-cells = 364 #clock-cells = <1>;
733 clocks = <&osc 365 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
734 <&clk 366 <&clk_ext3>, <&clk_ext4>;
735 clock-names = 367 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
736 368 "clk_ext3", "clk_ext4";
737 assigned-clock 369 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 370 <&clk IMX8MP_CLK_A53_CORE>,
739 371 <&clk IMX8MP_CLK_NOC>,
740 372 <&clk IMX8MP_CLK_NOC_IO>,
741 !! 373 <&clk IMX8MP_CLK_GIC>,
>> 374 <&clk IMX8MP_CLK_AUDIO_AHB>,
>> 375 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
>> 376 <&clk IMX8MP_CLK_IPG_AUDIO_ROOT>,
>> 377 <&clk IMX8MP_AUDIO_PLL1>,
>> 378 <&clk IMX8MP_AUDIO_PLL2>;
742 assigned-clock 379 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 380 <&clk IMX8MP_ARM_PLL_OUT>,
744 381 <&clk IMX8MP_SYS_PLL2_1000M>,
745 382 <&clk IMX8MP_SYS_PLL1_800M>,
746 !! 383 <&clk IMX8MP_SYS_PLL2_500M>,
>> 384 <&clk IMX8MP_SYS_PLL1_800M>,
>> 385 <&clk IMX8MP_SYS_PLL1_800M>;
747 assigned-clock 386 assigned-clock-rates = <0>, <0>,
748 387 <1000000000>,
749 388 <800000000>,
750 !! 389 <500000000>,
>> 390 <400000000>,
>> 391 <800000000>,
>> 392 <400000000>,
>> 393 <393216000>,
>> 394 <361267200>;
751 }; 395 };
752 396
753 src: reset-controller@ 397 src: reset-controller@30390000 {
754 compatible = " 398 compatible = "fsl,imx8mp-src", "syscon";
755 reg = <0x30390 399 reg = <0x30390000 0x10000>;
756 interrupts = < 400 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
757 #reset-cells = 401 #reset-cells = <1>;
758 }; 402 };
759 <<
760 gpc: gpc@303a0000 { <<
761 compatible = " <<
762 reg = <0x303a0 <<
763 interrupt-pare <<
764 interrupts = < <<
765 interrupt-cont <<
766 #interrupt-cel <<
767 <<
768 pgc { <<
769 #addre <<
770 #size- <<
771 <<
772 pgc_mi <<
773 <<
774 <<
775 }; <<
776 <<
777 pgc_pc <<
778 <<
779 <<
780 }; <<
781 <<
782 pgc_us <<
783 <<
784 <<
785 }; <<
786 <<
787 pgc_us <<
788 <<
789 <<
790 }; <<
791 <<
792 pgc_ml <<
793 <<
794 <<
795 <<
796 <<
797 <<
798 <<
799 <<
800 <<
801 <<
802 <<
803 <<
804 <<
805 <<
806 <<
807 }; <<
808 <<
809 pgc_au <<
810 <<
811 <<
812 <<
813 <<
814 <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 }; <<
821 <<
822 pgc_gp <<
823 <<
824 <<
825 <<
826 <<
827 }; <<
828 <<
829 pgc_gp <<
830 <<
831 <<
832 <<
833 <<
834 <<
835 <<
836 <<
837 <<
838 <<
839 }; <<
840 <<
841 pgc_vp <<
842 <<
843 <<
844 <<
845 }; <<
846 <<
847 pgc_gp <<
848 <<
849 <<
850 <<
851 <<
852 <<
853 }; <<
854 <<
855 pgc_me <<
856 <<
857 <<
858 <<
859 <<
860 }; <<
861 <<
862 pgc_vp <<
863 <<
864 <<
865 <<
866 <<
867 }; <<
868 <<
869 pgc_vp <<
870 <<
871 <<
872 <<
873 <<
874 <<
875 }; <<
876 <<
877 pgc_vp <<
878 <<
879 <<
880 <<
881 <<
882 }; <<
883 <<
884 pgc_hd <<
885 <<
886 <<
887 <<
888 <<
889 <<
890 <<
891 <<
892 <<
893 <<
894 }; <<
895 <<
896 pgc_hd <<
897 <<
898 <<
899 }; <<
900 <<
901 pgc_mi <<
902 <<
903 <<
904 }; <<
905 <<
906 pgc_hs <<
907 <<
908 <<
909 <<
910 <<
911 <<
912 <<
913 <<
914 }; <<
915 <<
916 pgc_is <<
917 <<
918 <<
919 <<
920 }; <<
921 }; <<
922 }; <<
923 }; 403 };
924 404
925 aips2: bus@30400000 { 405 aips2: bus@30400000 {
926 compatible = "fsl,aips 406 compatible = "fsl,aips-bus", "simple-bus";
927 reg = <0x30400000 0x40 407 reg = <0x30400000 0x400000>;
928 #address-cells = <1>; 408 #address-cells = <1>;
929 #size-cells = <1>; 409 #size-cells = <1>;
930 ranges; 410 ranges;
931 411
932 pwm1: pwm@30660000 { 412 pwm1: pwm@30660000 {
933 compatible = " 413 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
934 reg = <0x30660 414 reg = <0x30660000 0x10000>;
935 interrupts = < 415 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clk 416 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
937 <&clk 417 <&clk IMX8MP_CLK_PWM1_ROOT>;
938 clock-names = 418 clock-names = "ipg", "per";
939 #pwm-cells = < !! 419 #pwm-cells = <2>;
940 status = "disa 420 status = "disabled";
941 }; 421 };
942 422
943 pwm2: pwm@30670000 { 423 pwm2: pwm@30670000 {
944 compatible = " 424 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
945 reg = <0x30670 425 reg = <0x30670000 0x10000>;
946 interrupts = < 426 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clk 427 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
948 <&clk 428 <&clk IMX8MP_CLK_PWM2_ROOT>;
949 clock-names = 429 clock-names = "ipg", "per";
950 #pwm-cells = < !! 430 #pwm-cells = <2>;
951 status = "disa 431 status = "disabled";
952 }; 432 };
953 433
954 pwm3: pwm@30680000 { 434 pwm3: pwm@30680000 {
955 compatible = " 435 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
956 reg = <0x30680 436 reg = <0x30680000 0x10000>;
957 interrupts = < 437 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clk 438 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
959 <&clk 439 <&clk IMX8MP_CLK_PWM3_ROOT>;
960 clock-names = 440 clock-names = "ipg", "per";
961 #pwm-cells = < !! 441 #pwm-cells = <2>;
962 status = "disa 442 status = "disabled";
963 }; 443 };
964 444
965 pwm4: pwm@30690000 { 445 pwm4: pwm@30690000 {
966 compatible = " 446 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
967 reg = <0x30690 447 reg = <0x30690000 0x10000>;
968 interrupts = < 448 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clk 449 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
970 <&clk 450 <&clk IMX8MP_CLK_PWM4_ROOT>;
971 clock-names = 451 clock-names = "ipg", "per";
972 #pwm-cells = < !! 452 #pwm-cells = <2>;
973 status = "disa 453 status = "disabled";
974 }; 454 };
975 455
976 system_counter: timer@ 456 system_counter: timer@306a0000 {
977 compatible = " 457 compatible = "nxp,sysctr-timer";
978 reg = <0x306a0 458 reg = <0x306a0000 0x20000>;
979 interrupts = < 459 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&osc 460 clocks = <&osc_24m>;
981 clock-names = 461 clock-names = "per";
982 }; 462 };
983 <<
984 gpt6: timer@306e0000 { <<
985 compatible = " <<
986 reg = <0x306e0 <<
987 interrupts = < <<
988 clocks = <&clk <<
989 clock-names = <<
990 }; <<
991 <<
992 gpt5: timer@306f0000 { <<
993 compatible = " <<
994 reg = <0x306f0 <<
995 interrupts = < <<
996 clocks = <&clk <<
997 clock-names = <<
998 }; <<
999 <<
1000 gpt4: timer@30700000 <<
1001 compatible = <<
1002 reg = <0x3070 <<
1003 interrupts = <<
1004 clocks = <&cl <<
1005 clock-names = <<
1006 }; <<
1007 }; 463 };
1008 464
1009 aips3: bus@30800000 { 465 aips3: bus@30800000 {
1010 compatible = "fsl,aip 466 compatible = "fsl,aips-bus", "simple-bus";
1011 reg = <0x30800000 0x4 467 reg = <0x30800000 0x400000>;
1012 #address-cells = <1>; 468 #address-cells = <1>;
1013 #size-cells = <1>; 469 #size-cells = <1>;
1014 ranges; 470 ranges;
1015 471
1016 spba-bus@30800000 { !! 472 ecspi1: spi@30820000 {
1017 compatible = <<
1018 reg = <0x3080 <<
1019 #address-cell 473 #address-cells = <1>;
1020 #size-cells = !! 474 #size-cells = <0>;
1021 ranges; !! 475 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1022 !! 476 reg = <0x30820000 0x10000>;
1023 ecspi1: spi@3 !! 477 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1024 #addr !! 478 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
1025 #size !! 479 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1026 compa !! 480 clock-names = "ipg", "per";
1027 reg = !! 481 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1028 inter !! 482 dma-names = "rx", "tx";
1029 clock !! 483 status = "disabled";
1030 !! 484 };
1031 clock <<
1032 assig <<
1033 assig <<
1034 assig <<
1035 dmas <<
1036 dma-n <<
1037 statu <<
1038 }; <<
1039 <<
1040 ecspi2: spi@3 <<
1041 #addr <<
1042 #size <<
1043 compa <<
1044 reg = <<
1045 inter <<
1046 clock <<
1047 <<
1048 clock <<
1049 assig <<
1050 assig <<
1051 assig <<
1052 dmas <<
1053 dma-n <<
1054 statu <<
1055 }; <<
1056 <<
1057 ecspi3: spi@3 <<
1058 #addr <<
1059 #size <<
1060 compa <<
1061 reg = <<
1062 inter <<
1063 clock <<
1064 <<
1065 clock <<
1066 assig <<
1067 assig <<
1068 assig <<
1069 dmas <<
1070 dma-n <<
1071 statu <<
1072 }; <<
1073 485
1074 uart1: serial !! 486 ecspi2: spi@30830000 {
1075 compa !! 487 #address-cells = <1>;
1076 reg = !! 488 #size-cells = <0>;
1077 inter !! 489 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1078 clock !! 490 reg = <0x30830000 0x10000>;
1079 !! 491 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1080 clock !! 492 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1081 dmas !! 493 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1082 dma-n !! 494 clock-names = "ipg", "per";
1083 statu !! 495 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1084 }; !! 496 dma-names = "rx", "tx";
>> 497 status = "disabled";
>> 498 };
1085 499
1086 uart3: serial !! 500 ecspi3: spi@30840000 {
1087 compa !! 501 #address-cells = <1>;
1088 reg = !! 502 #size-cells = <0>;
1089 inter !! 503 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1090 clock !! 504 reg = <0x30840000 0x10000>;
1091 !! 505 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1092 clock !! 506 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1093 dmas !! 507 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1094 dma-n !! 508 clock-names = "ipg", "per";
1095 statu !! 509 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1096 }; !! 510 dma-names = "rx", "tx";
>> 511 status = "disabled";
>> 512 };
1097 513
1098 uart2: serial !! 514 uart1: serial@30860000 {
1099 compa !! 515 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1100 reg = !! 516 reg = <0x30860000 0x10000>;
1101 inter !! 517 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1102 clock !! 518 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1103 !! 519 <&clk IMX8MP_CLK_UART1_ROOT>;
1104 clock !! 520 clock-names = "ipg", "per";
1105 dmas !! 521 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1106 dma-n !! 522 dma-names = "rx", "tx";
1107 statu !! 523 status = "disabled";
1108 }; !! 524 };
1109 525
1110 flexcan1: can !! 526 uart3: serial@30880000 {
1111 compa !! 527 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1112 reg = !! 528 reg = <0x30880000 0x10000>;
1113 inter !! 529 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1114 clock !! 530 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1115 !! 531 <&clk IMX8MP_CLK_UART3_ROOT>;
1116 clock !! 532 clock-names = "ipg", "per";
1117 assig !! 533 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1118 assig !! 534 dma-names = "rx", "tx";
1119 assig !! 535 status = "disabled";
1120 fsl,c !! 536 };
1121 fsl,s <<
1122 statu <<
1123 }; <<
1124 537
1125 flexcan2: can !! 538 uart2: serial@30890000 {
1126 compa !! 539 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1127 reg = !! 540 reg = <0x30890000 0x10000>;
1128 inter !! 541 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1129 clock !! 542 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1130 !! 543 <&clk IMX8MP_CLK_UART2_ROOT>;
1131 clock !! 544 clock-names = "ipg", "per";
1132 assig !! 545 status = "disabled";
1133 assig <<
1134 assig <<
1135 fsl,c <<
1136 fsl,s <<
1137 statu <<
1138 }; <<
1139 }; 546 };
1140 547
1141 crypto: crypto@309000 548 crypto: crypto@30900000 {
1142 compatible = 549 compatible = "fsl,sec-v4.0";
1143 #address-cell 550 #address-cells = <1>;
1144 #size-cells = 551 #size-cells = <1>;
1145 reg = <0x3090 552 reg = <0x30900000 0x40000>;
1146 ranges = <0 0 553 ranges = <0 0x30900000 0x40000>;
1147 interrupts = 554 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&cl 555 clocks = <&clk IMX8MP_CLK_AHB>,
1149 <&cl 556 <&clk IMX8MP_CLK_IPG_ROOT>;
1150 clock-names = 557 clock-names = "aclk", "ipg";
1151 558
1152 sec_jr0: jr@1 559 sec_jr0: jr@1000 {
1153 compa 560 compatible = "fsl,sec-v4.0-job-ring";
1154 reg = 561 reg = <0x1000 0x1000>;
1155 inter 562 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1156 statu <<
1157 }; 563 };
1158 564
1159 sec_jr1: jr@2 565 sec_jr1: jr@2000 {
1160 compa 566 compatible = "fsl,sec-v4.0-job-ring";
1161 reg = 567 reg = <0x2000 0x1000>;
1162 inter 568 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1163 }; 569 };
1164 570
1165 sec_jr2: jr@3 571 sec_jr2: jr@3000 {
1166 compa 572 compatible = "fsl,sec-v4.0-job-ring";
1167 reg = 573 reg = <0x3000 0x1000>;
1168 inter 574 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1169 }; 575 };
1170 }; 576 };
1171 577
1172 i2c1: i2c@30a20000 { 578 i2c1: i2c@30a20000 {
1173 compatible = 579 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1174 #address-cell 580 #address-cells = <1>;
1175 #size-cells = 581 #size-cells = <0>;
1176 reg = <0x30a2 582 reg = <0x30a20000 0x10000>;
1177 interrupts = 583 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cl 584 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1179 status = "dis 585 status = "disabled";
1180 }; 586 };
1181 587
1182 i2c2: i2c@30a30000 { 588 i2c2: i2c@30a30000 {
1183 compatible = 589 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1184 #address-cell 590 #address-cells = <1>;
1185 #size-cells = 591 #size-cells = <0>;
1186 reg = <0x30a3 592 reg = <0x30a30000 0x10000>;
1187 interrupts = 593 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&cl 594 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1189 status = "dis 595 status = "disabled";
1190 }; 596 };
1191 597
1192 i2c3: i2c@30a40000 { 598 i2c3: i2c@30a40000 {
1193 compatible = 599 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1194 #address-cell 600 #address-cells = <1>;
1195 #size-cells = 601 #size-cells = <0>;
1196 reg = <0x30a4 602 reg = <0x30a40000 0x10000>;
1197 interrupts = 603 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&cl 604 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1199 status = "dis 605 status = "disabled";
1200 }; 606 };
1201 607
1202 i2c4: i2c@30a50000 { 608 i2c4: i2c@30a50000 {
1203 compatible = 609 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1204 #address-cell 610 #address-cells = <1>;
1205 #size-cells = 611 #size-cells = <0>;
1206 reg = <0x30a5 612 reg = <0x30a50000 0x10000>;
1207 interrupts = 613 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cl 614 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1209 status = "dis 615 status = "disabled";
1210 }; 616 };
1211 617
1212 uart4: serial@30a6000 618 uart4: serial@30a60000 {
1213 compatible = 619 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1214 reg = <0x30a6 620 reg = <0x30a60000 0x10000>;
1215 interrupts = 621 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&cl 622 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1217 <&cl 623 <&clk IMX8MP_CLK_UART4_ROOT>;
1218 clock-names = 624 clock-names = "ipg", "per";
1219 dmas = <&sdma 625 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1220 dma-names = " 626 dma-names = "rx", "tx";
1221 status = "dis 627 status = "disabled";
1222 }; 628 };
1223 629
1224 mu: mailbox@30aa0000 630 mu: mailbox@30aa0000 {
1225 compatible = 631 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1226 reg = <0x30aa 632 reg = <0x30aa0000 0x10000>;
1227 interrupts = 633 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&cl 634 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1229 #mbox-cells = 635 #mbox-cells = <2>;
1230 }; 636 };
1231 637
1232 mu2: mailbox@30e60000 <<
1233 compatible = <<
1234 reg = <0x30e6 <<
1235 interrupts = <<
1236 #mbox-cells = <<
1237 status = "dis <<
1238 }; <<
1239 <<
1240 i2c5: i2c@30ad0000 { 638 i2c5: i2c@30ad0000 {
1241 compatible = 639 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1242 #address-cell 640 #address-cells = <1>;
1243 #size-cells = 641 #size-cells = <0>;
1244 reg = <0x30ad 642 reg = <0x30ad0000 0x10000>;
1245 interrupts = 643 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&cl 644 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1247 status = "dis 645 status = "disabled";
1248 }; 646 };
1249 647
1250 i2c6: i2c@30ae0000 { 648 i2c6: i2c@30ae0000 {
1251 compatible = 649 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1252 #address-cell 650 #address-cells = <1>;
1253 #size-cells = 651 #size-cells = <0>;
1254 reg = <0x30ae 652 reg = <0x30ae0000 0x10000>;
1255 interrupts = 653 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cl 654 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1257 status = "dis 655 status = "disabled";
1258 }; 656 };
1259 657
1260 usdhc1: mmc@30b40000 658 usdhc1: mmc@30b40000 {
1261 compatible = !! 659 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
1262 reg = <0x30b4 660 reg = <0x30b40000 0x10000>;
1263 interrupts = 661 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cl !! 662 clocks = <&clk IMX8MP_CLK_DUMMY>,
1265 <&cl 663 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1266 <&cl 664 <&clk IMX8MP_CLK_USDHC1_ROOT>;
1267 clock-names = 665 clock-names = "ipg", "ahb", "per";
1268 fsl,tuning-st 666 fsl,tuning-start-tap = <20>;
1269 fsl,tuning-st !! 667 fsl,tuning-step= <2>;
1270 bus-width = < 668 bus-width = <4>;
1271 status = "dis 669 status = "disabled";
1272 }; 670 };
1273 671
1274 usdhc2: mmc@30b50000 672 usdhc2: mmc@30b50000 {
1275 compatible = !! 673 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
1276 reg = <0x30b5 674 reg = <0x30b50000 0x10000>;
1277 interrupts = 675 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&cl !! 676 clocks = <&clk IMX8MP_CLK_DUMMY>,
1279 <&cl 677 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1280 <&cl 678 <&clk IMX8MP_CLK_USDHC2_ROOT>;
1281 clock-names = 679 clock-names = "ipg", "ahb", "per";
1282 fsl,tuning-st 680 fsl,tuning-start-tap = <20>;
1283 fsl,tuning-st !! 681 fsl,tuning-step= <2>;
1284 bus-width = < 682 bus-width = <4>;
1285 status = "dis 683 status = "disabled";
1286 }; 684 };
1287 685
1288 usdhc3: mmc@30b60000 686 usdhc3: mmc@30b60000 {
1289 compatible = !! 687 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
1290 reg = <0x30b6 688 reg = <0x30b60000 0x10000>;
1291 interrupts = 689 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cl !! 690 clocks = <&clk IMX8MP_CLK_DUMMY>,
1293 <&cl 691 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1294 <&cl 692 <&clk IMX8MP_CLK_USDHC3_ROOT>;
1295 clock-names = 693 clock-names = "ipg", "ahb", "per";
1296 fsl,tuning-st 694 fsl,tuning-start-tap = <20>;
1297 fsl,tuning-st !! 695 fsl,tuning-step= <2>;
1298 bus-width = < 696 bus-width = <4>;
1299 status = "dis 697 status = "disabled";
1300 }; 698 };
1301 699
1302 flexspi: spi@30bb0000 <<
1303 compatible = <<
1304 reg = <0x30bb <<
1305 reg-names = " <<
1306 interrupts = <<
1307 clocks = <&cl <<
1308 <&cl <<
1309 clock-names = <<
1310 assigned-cloc <<
1311 assigned-cloc <<
1312 #address-cell <<
1313 #size-cells = <<
1314 status = "dis <<
1315 }; <<
1316 <<
1317 sdma1: dma-controller 700 sdma1: dma-controller@30bd0000 {
1318 compatible = 701 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1319 reg = <0x30bd 702 reg = <0x30bd0000 0x10000>;
1320 interrupts = 703 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&cl 704 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1322 <&cl 705 <&clk IMX8MP_CLK_AHB>;
1323 clock-names = 706 clock-names = "ipg", "ahb";
1324 #dma-cells = 707 #dma-cells = <3>;
1325 fsl,sdma-ram- 708 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1326 }; 709 };
1327 710
1328 fec: ethernet@30be000 711 fec: ethernet@30be0000 {
1329 compatible = 712 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1330 reg = <0x30be 713 reg = <0x30be0000 0x10000>;
1331 interrupts = 714 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1332 715 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1333 716 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1334 717 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&cl 718 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1336 <&cl 719 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1337 <&cl 720 <&clk IMX8MP_CLK_ENET_TIMER>,
1338 <&cl 721 <&clk IMX8MP_CLK_ENET_REF>,
1339 <&cl 722 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1340 clock-names = 723 clock-names = "ipg", "ahb", "ptp",
1341 724 "enet_clk_ref", "enet_out";
1342 assigned-cloc 725 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1343 726 <&clk IMX8MP_CLK_ENET_TIMER>,
1344 727 <&clk IMX8MP_CLK_ENET_REF>,
1345 728 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1346 assigned-cloc 729 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1347 730 <&clk IMX8MP_SYS_PLL2_100M>,
1348 731 <&clk IMX8MP_SYS_PLL2_125M>,
1349 732 <&clk IMX8MP_SYS_PLL2_50M>;
1350 assigned-cloc 733 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1351 fsl,num-tx-qu 734 fsl,num-tx-queues = <3>;
1352 fsl,num-rx-qu 735 fsl,num-rx-queues = <3>;
1353 nvmem-cells = <<
1354 nvmem-cell-na <<
1355 fsl,stop-mode <<
1356 status = "dis <<
1357 }; <<
1358 <<
1359 eqos: ethernet@30bf00 <<
1360 compatible = <<
1361 reg = <0x30bf <<
1362 interrupts = <<
1363 <<
1364 interrupt-nam <<
1365 clocks = <&cl <<
1366 <&cl <<
1367 <&cl <<
1368 <&cl <<
1369 clock-names = <<
1370 assigned-cloc <<
1371 <<
1372 <<
1373 assigned-cloc <<
1374 <<
1375 <<
1376 assigned-cloc <<
1377 nvmem-cells = <<
1378 nvmem-cell-na <<
1379 intf_mode = < <<
1380 status = "dis 736 status = "disabled";
1381 }; 737 };
1382 }; 738 };
1383 739
1384 aips5: bus@30c00000 { <<
1385 compatible = "fsl,aip <<
1386 reg = <0x30c00000 0x4 <<
1387 #address-cells = <1>; <<
1388 #size-cells = <1>; <<
1389 ranges; <<
1390 <<
1391 spba-bus@30c00000 { <<
1392 compatible = <<
1393 reg = <0x30c0 <<
1394 #address-cell <<
1395 #size-cells = <<
1396 ranges; <<
1397 <<
1398 sai1: sai@30c <<
1399 compa <<
1400 reg = <<
1401 #soun <<
1402 clock <<
1403 <<
1404 <<
1405 <<
1406 <<
1407 clock <<
1408 dmas <<
1409 dma-n <<
1410 inter <<
1411 statu <<
1412 }; <<
1413 <<
1414 sai2: sai@30c <<
1415 compa <<
1416 reg = <<
1417 #soun <<
1418 clock <<
1419 <<
1420 <<
1421 <<
1422 <<
1423 clock <<
1424 dmas <<
1425 dma-n <<
1426 inter <<
1427 statu <<
1428 }; <<
1429 <<
1430 sai3: sai@30c <<
1431 compa <<
1432 reg = <<
1433 #soun <<
1434 clock <<
1435 <<
1436 <<
1437 <<
1438 <<
1439 clock <<
1440 dmas <<
1441 dma-n <<
1442 inter <<
1443 statu <<
1444 }; <<
1445 <<
1446 sai5: sai@30c <<
1447 compa <<
1448 reg = <<
1449 #soun <<
1450 clock <<
1451 <<
1452 <<
1453 <<
1454 <<
1455 clock <<
1456 dmas <<
1457 dma-n <<
1458 inter <<
1459 statu <<
1460 }; <<
1461 <<
1462 sai6: sai@30c <<
1463 compa <<
1464 reg = <<
1465 #soun <<
1466 clock <<
1467 <<
1468 <<
1469 <<
1470 <<
1471 clock <<
1472 dmas <<
1473 dma-n <<
1474 inter <<
1475 statu <<
1476 }; <<
1477 <<
1478 sai7: sai@30c <<
1479 compa <<
1480 reg = <<
1481 #soun <<
1482 clock <<
1483 <<
1484 <<
1485 <<
1486 <<
1487 clock <<
1488 dmas <<
1489 dma-n <<
1490 inter <<
1491 statu <<
1492 }; <<
1493 <<
1494 easrc: easrc@ <<
1495 compa <<
1496 reg = <<
1497 inter <<
1498 clock <<
1499 clock <<
1500 dmas <<
1501 <<
1502 <<
1503 <<
1504 dma-n <<
1505 <<
1506 <<
1507 <<
1508 firmw <<
1509 fsl,a <<
1510 fsl,a <<
1511 statu <<
1512 }; <<
1513 <<
1514 micfil: audio <<
1515 compa <<
1516 reg = <<
1517 #soun <<
1518 inter <<
1519 <<
1520 <<
1521 <<
1522 clock <<
1523 <<
1524 <<
1525 <<
1526 <<
1527 clock <<
1528 <<
1529 dmas <<
1530 dma-n <<
1531 statu <<
1532 }; <<
1533 <<
1534 aud2htx: aud2 <<
1535 compa <<
1536 reg = <<
1537 inter <<
1538 clock <<
1539 clock <<
1540 dmas <<
1541 dma-n <<
1542 statu <<
1543 }; <<
1544 <<
1545 xcvr: xcvr@30 <<
1546 compa <<
1547 reg = <<
1548 <<
1549 <<
1550 <<
1551 reg-n <<
1552 <<
1553 inter <<
1554 <<
1555 <<
1556 <<
1557 <<
1558 <<
1559 clock <<
1560 <<
1561 <<
1562 <<
1563 clock <<
1564 dmas <<
1565 dma-n <<
1566 reset <<
1567 statu <<
1568 }; <<
1569 }; <<
1570 <<
1571 sdma3: dma-controller <<
1572 compatible = <<
1573 reg = <0x30e0 <<
1574 #dma-cells = <<
1575 clocks = <&au <<
1576 <&cl <<
1577 clock-names = <<
1578 interrupts = <<
1579 fsl,sdma-ram- <<
1580 }; <<
1581 <<
1582 sdma2: dma-controller <<
1583 compatible = <<
1584 reg = <0x30e1 <<
1585 #dma-cells = <<
1586 clocks = <&au <<
1587 <&cl <<
1588 clock-names = <<
1589 interrupts = <<
1590 fsl,sdma-ram- <<
1591 }; <<
1592 <<
1593 audio_blk_ctrl: clock <<
1594 compatible = <<
1595 reg = <0x30e2 <<
1596 #clock-cells <<
1597 #reset-cells <<
1598 clocks = <&cl <<
1599 <&cl <<
1600 <&cl <<
1601 <&cl <<
1602 <&cl <<
1603 <&cl <<
1604 <&cl <<
1605 clock-names = <<
1606 <<
1607 <<
1608 power-domains <<
1609 assigned-cloc <<
1610 <<
1611 assigned-cloc <<
1612 }; <<
1613 }; <<
1614 <<
1615 noc: interconnect@32700000 { <<
1616 compatible = "fsl,imx <<
1617 reg = <0x32700000 0x1 <<
1618 clocks = <&clk IMX8MP <<
1619 #interconnect-cells = <<
1620 operating-points-v2 = <<
1621 <<
1622 noc_opp_table: opp-ta <<
1623 compatible = <<
1624 <<
1625 opp-200000000 <<
1626 opp-h <<
1627 }; <<
1628 <<
1629 opp-100000000 <<
1630 opp-h <<
1631 }; <<
1632 }; <<
1633 }; <<
1634 <<
1635 aips4: bus@32c00000 { <<
1636 compatible = "fsl,aip <<
1637 reg = <0x32c00000 0x4 <<
1638 #address-cells = <1>; <<
1639 #size-cells = <1>; <<
1640 ranges; <<
1641 <<
1642 isi_0: isi@32e00000 { <<
1643 compatible = <<
1644 reg = <0x32e0 <<
1645 interrupts = <<
1646 <<
1647 clocks = <&cl <<
1648 <&cl <<
1649 clock-names = <<
1650 fsl,blk-ctrl <<
1651 power-domains <<
1652 status = "dis <<
1653 <<
1654 ports { <<
1655 #addr <<
1656 #size <<
1657 <<
1658 port@ <<
1659 <<
1660 <<
1661 <<
1662 <<
1663 <<
1664 }; <<
1665 <<
1666 port@ <<
1667 <<
1668 <<
1669 <<
1670 <<
1671 <<
1672 }; <<
1673 }; <<
1674 }; <<
1675 <<
1676 isp_0: isp@32e10000 { <<
1677 compatible = <<
1678 reg = <0x32e1 <<
1679 interrupts = <<
1680 clocks = <&cl <<
1681 <&cl <<
1682 <&cl <<
1683 clock-names = <<
1684 power-domains <<
1685 fsl,blk-ctrl <<
1686 status = "dis <<
1687 <<
1688 ports { <<
1689 #addr <<
1690 #size <<
1691 <<
1692 port@ <<
1693 <<
1694 }; <<
1695 }; <<
1696 }; <<
1697 <<
1698 isp_1: isp@32e20000 { <<
1699 compatible = <<
1700 reg = <0x32e2 <<
1701 interrupts = <<
1702 clocks = <&cl <<
1703 <&cl <<
1704 <&cl <<
1705 clock-names = <<
1706 power-domains <<
1707 fsl,blk-ctrl <<
1708 status = "dis <<
1709 <<
1710 ports { <<
1711 #addr <<
1712 #size <<
1713 <<
1714 port@ <<
1715 <<
1716 }; <<
1717 }; <<
1718 }; <<
1719 <<
1720 dewarp: dwe@32e30000 <<
1721 compatible = <<
1722 reg = <0x32e3 <<
1723 interrupts = <<
1724 clocks = <&cl <<
1725 <&cl <<
1726 clock-names = <<
1727 power-domains <<
1728 }; <<
1729 <<
1730 mipi_csi_0: csi@32e40 <<
1731 compatible = <<
1732 reg = <0x32e4 <<
1733 interrupts = <<
1734 clock-frequen <<
1735 clocks = <&cl <<
1736 <&cl <<
1737 <&cl <<
1738 <&cl <<
1739 clock-names = <<
1740 assigned-cloc <<
1741 <<
1742 assigned-cloc <<
1743 <<
1744 power-domains <<
1745 status = "dis <<
1746 <<
1747 ports { <<
1748 #addr <<
1749 #size <<
1750 <<
1751 port@ <<
1752 <<
1753 }; <<
1754 <<
1755 port@ <<
1756 <<
1757 <<
1758 <<
1759 <<
1760 <<
1761 }; <<
1762 }; <<
1763 }; <<
1764 <<
1765 mipi_csi_1: csi@32e50 <<
1766 compatible = <<
1767 reg = <0x32e5 <<
1768 interrupts = <<
1769 clock-frequen <<
1770 clocks = <&cl <<
1771 <&cl <<
1772 <&cl <<
1773 <&cl <<
1774 clock-names = <<
1775 assigned-cloc <<
1776 <<
1777 assigned-cloc <<
1778 <<
1779 power-domains <<
1780 status = "dis <<
1781 <<
1782 ports { <<
1783 #addr <<
1784 #size <<
1785 <<
1786 port@ <<
1787 <<
1788 }; <<
1789 <<
1790 port@ <<
1791 <<
1792 <<
1793 <<
1794 <<
1795 <<
1796 }; <<
1797 }; <<
1798 }; <<
1799 <<
1800 mipi_dsi: dsi@32e6000 <<
1801 compatible = <<
1802 reg = <0x32e6 <<
1803 clocks = <&cl <<
1804 <&cl <<
1805 clock-names = <<
1806 assigned-cloc <<
1807 <<
1808 assigned-cloc <<
1809 <<
1810 assigned-cloc <<
1811 samsung,pll-c <<
1812 interrupts = <<
1813 power-domains <<
1814 status = "dis <<
1815 <<
1816 ports { <<
1817 #addr <<
1818 #size <<
1819 <<
1820 port@ <<
1821 <<
1822 <<
1823 <<
1824 <<
1825 <<
1826 }; <<
1827 <<
1828 port@ <<
1829 <<
1830 <<
1831 <<
1832 <<
1833 }; <<
1834 }; <<
1835 }; <<
1836 <<
1837 lcdif1: display-contr <<
1838 compatible = <<
1839 reg = <0x32e8 <<
1840 clocks = <&cl <<
1841 <&cl <<
1842 <&cl <<
1843 clock-names = <<
1844 interrupts = <<
1845 power-domains <<
1846 status = "dis <<
1847 <<
1848 port { <<
1849 lcdif <<
1850 <<
1851 }; <<
1852 }; <<
1853 }; <<
1854 <<
1855 lcdif2: display-contr <<
1856 compatible = <<
1857 reg = <0x32e9 <<
1858 interrupts = <<
1859 clocks = <&cl <<
1860 <&cl <<
1861 <&cl <<
1862 clock-names = <<
1863 power-domains <<
1864 status = "dis <<
1865 <<
1866 port { <<
1867 lcdif <<
1868 <<
1869 }; <<
1870 }; <<
1871 }; <<
1872 <<
1873 media_blk_ctrl: blk-c <<
1874 compatible = <<
1875 <<
1876 reg = <0x32ec <<
1877 #address-cell <<
1878 #size-cells = <<
1879 power-domains <<
1880 <<
1881 <<
1882 <<
1883 <<
1884 <<
1885 <<
1886 <<
1887 <<
1888 <<
1889 power-domain- <<
1890 <<
1891 <<
1892 <<
1893 interconnects <<
1894 <&noc <<
1895 <&noc <<
1896 <&noc <<
1897 <&noc <<
1898 <&noc <<
1899 <&noc <<
1900 <&noc <<
1901 <&noc <<
1902 interconnect- <<
1903 <<
1904 <<
1905 clocks = <&cl <<
1906 <&cl <<
1907 <&cl <<
1908 <&cl <<
1909 <&cl <<
1910 <&cl <<
1911 <&cl <<
1912 <&cl <<
1913 clock-names = <<
1914 <<
1915 <<
1916 /* <<
1917 * The ISP ma <<
1918 * and 500MHz <<
1919 * point hasn <<
1920 * IMX8MP_CLK <<
1921 */ <<
1922 assigned-cloc <<
1923 <<
1924 <<
1925 <<
1926 <<
1927 <<
1928 assigned-cloc <<
1929 <<
1930 <<
1931 <<
1932 <<
1933 assigned-cloc <<
1934 <<
1935 <<
1936 #power-domain <<
1937 <<
1938 lvds_bridge: <<
1939 compa <<
1940 reg = <<
1941 reg-n <<
1942 clock <<
1943 clock <<
1944 assig <<
1945 assig <<
1946 statu <<
1947 <<
1948 ports <<
1949 <<
1950 <<
1951 <<
1952 <<
1953 <<
1954 <<
1955 <<
1956 <<
1957 <<
1958 <<
1959 <<
1960 <<
1961 <<
1962 <<
1963 <<
1964 <<
1965 <<
1966 <<
1967 <<
1968 <<
1969 <<
1970 <<
1971 <<
1972 <<
1973 }; <<
1974 }; <<
1975 }; <<
1976 <<
1977 pcie_phy: pcie-phy@32 <<
1978 compatible = <<
1979 reg = <0x32f0 <<
1980 resets = <&sr <<
1981 <&sr <<
1982 reset-names = <<
1983 power-domains <<
1984 #phy-cells = <<
1985 status = "dis <<
1986 }; <<
1987 <<
1988 hsio_blk_ctrl: blk-ct <<
1989 compatible = <<
1990 reg = <0x32f1 <<
1991 clocks = <&cl <<
1992 <&cl <<
1993 clock-names = <<
1994 power-domains <<
1995 <<
1996 <<
1997 power-domain- <<
1998 <<
1999 interconnects <<
2000 <<
2001 <<
2002 <<
2003 interconnect- <<
2004 #power-domain <<
2005 #clock-cells <<
2006 }; <<
2007 <<
2008 hdmi_blk_ctrl: blk-ct <<
2009 compatible = <<
2010 reg = <0x32fc <<
2011 clocks = <&cl <<
2012 <&cl <<
2013 <&cl <<
2014 <&cl <<
2015 <&cl <<
2016 clock-names = <<
2017 power-domains <<
2018 <<
2019 <<
2020 <<
2021 <<
2022 power-domain- <<
2023 <<
2024 <<
2025 <<
2026 #power-domain <<
2027 }; <<
2028 <<
2029 irqsteer_hdmi: interr <<
2030 compatible = <<
2031 reg = <0x32fc <<
2032 interrupts = <<
2033 interrupt-con <<
2034 #interrupt-ce <<
2035 fsl,channel = <<
2036 fsl,num-irqs <<
2037 clocks = <&cl <<
2038 clock-names = <<
2039 power-domains <<
2040 }; <<
2041 <<
2042 hdmi_pvi: display-bri <<
2043 compatible = <<
2044 reg = <0x32fc <<
2045 interrupt-par <<
2046 interrupts = <<
2047 power-domains <<
2048 status = "dis <<
2049 <<
2050 ports { <<
2051 #addr <<
2052 #size <<
2053 <<
2054 port@ <<
2055 <<
2056 <<
2057 <<
2058 <<
2059 }; <<
2060 <<
2061 port@ <<
2062 <<
2063 <<
2064 <<
2065 <<
2066 }; <<
2067 }; <<
2068 }; <<
2069 <<
2070 lcdif3: display-contr <<
2071 compatible = <<
2072 reg = <0x32fc <<
2073 interrupt-par <<
2074 interrupts = <<
2075 clocks = <&hd <<
2076 <&cl <<
2077 <&cl <<
2078 clock-names = <<
2079 power-domains <<
2080 status = "dis <<
2081 <<
2082 port { <<
2083 lcdif <<
2084 <<
2085 }; <<
2086 }; <<
2087 }; <<
2088 <<
2089 hdmi_tx: hdmi@32fd800 <<
2090 compatible = <<
2091 reg = <0x32fd <<
2092 interrupt-par <<
2093 interrupts = <<
2094 clocks = <&cl <<
2095 <&cl <<
2096 <&cl <<
2097 <&hd <<
2098 clock-names = <<
2099 assigned-cloc <<
2100 assigned-cloc <<
2101 power-domains <<
2102 reg-io-width <<
2103 status = "dis <<
2104 <<
2105 ports { <<
2106 #addr <<
2107 #size <<
2108 <<
2109 port@ <<
2110 <<
2111 <<
2112 <<
2113 <<
2114 <<
2115 }; <<
2116 <<
2117 port@ <<
2118 <<
2119 <<
2120 }; <<
2121 }; <<
2122 }; <<
2123 <<
2124 hdmi_tx_phy: phy@32fd <<
2125 compatible = <<
2126 reg = <0x32fd <<
2127 clocks = <&cl <<
2128 <&cl <<
2129 clock-names = <<
2130 assigned-cloc <<
2131 assigned-cloc <<
2132 power-domains <<
2133 #clock-cells <<
2134 #phy-cells = <<
2135 status = "dis <<
2136 }; <<
2137 }; <<
2138 <<
2139 pcie: pcie@33800000 { <<
2140 compatible = "fsl,imx <<
2141 reg = <0x33800000 0x4 <<
2142 reg-names = "dbi", "c <<
2143 clocks = <&clk IMX8MP <<
2144 <&clk IMX8MP <<
2145 <&clk IMX8MP <<
2146 clock-names = "pcie", <<
2147 assigned-clocks = <&c <<
2148 assigned-clock-rates <<
2149 assigned-clock-parent <<
2150 #address-cells = <3>; <<
2151 #size-cells = <2>; <<
2152 device_type = "pci"; <<
2153 bus-range = <0x00 0xf <<
2154 ranges = <0x81000000 <<
2155 <0x82000000 <<
2156 num-lanes = <1>; <<
2157 num-viewport = <4>; <<
2158 interrupts = <GIC_SPI <<
2159 interrupt-names = "ms <<
2160 #interrupt-cells = <1 <<
2161 interrupt-map-mask = <<
2162 interrupt-map = <0 0 <<
2163 <0 0 <<
2164 <0 0 <<
2165 <0 0 <<
2166 fsl,max-link-speed = <<
2167 linux,pci-domain = <0 <<
2168 power-domains = <&hsi <<
2169 resets = <&src IMX8MP <<
2170 <&src IMX8MP <<
2171 reset-names = "apps", <<
2172 phys = <&pcie_phy>; <<
2173 phy-names = "pcie-phy <<
2174 status = "disabled"; <<
2175 }; <<
2176 <<
2177 pcie_ep: pcie-ep@33800000 { <<
2178 compatible = "fsl,imx <<
2179 reg = <0x33800000 0x0 <<
2180 reg-names = "dbi", "a <<
2181 clocks = <&clk IMX8MP <<
2182 <&clk IMX8MP <<
2183 <&clk IMX8MP <<
2184 clock-names = "pcie", <<
2185 assigned-clocks = <&c <<
2186 assigned-clock-rates <<
2187 assigned-clock-parent <<
2188 num-lanes = <1>; <<
2189 interrupts = <GIC_SPI <<
2190 interrupt-names = "dm <<
2191 fsl,max-link-speed = <<
2192 power-domains = <&hsi <<
2193 resets = <&src IMX8MP <<
2194 <&src IMX8MP <<
2195 reset-names = "apps", <<
2196 phys = <&pcie_phy>; <<
2197 phy-names = "pcie-phy <<
2198 num-ib-windows = <4>; <<
2199 num-ob-windows = <4>; <<
2200 status = "disabled"; <<
2201 }; <<
2202 <<
2203 gpu3d: gpu@38000000 { <<
2204 compatible = "vivante <<
2205 reg = <0x38000000 0x8 <<
2206 interrupts = <GIC_SPI <<
2207 clocks = <&clk IMX8MP <<
2208 <&clk IMX8MP <<
2209 <&clk IMX8MP <<
2210 <&clk IMX8MP <<
2211 clock-names = "core", <<
2212 assigned-clocks = <&c <<
2213 <&c <<
2214 assigned-clock-parent <<
2215 <<
2216 assigned-clock-rates <<
2217 power-domains = <&pgc <<
2218 }; <<
2219 <<
2220 gpu2d: gpu@38008000 { <<
2221 compatible = "vivante <<
2222 reg = <0x38008000 0x8 <<
2223 interrupts = <GIC_SPI <<
2224 clocks = <&clk IMX8MP <<
2225 <&clk IMX8MP <<
2226 <&clk IMX8MP <<
2227 clock-names = "core", <<
2228 assigned-clocks = <&c <<
2229 assigned-clock-parent <<
2230 assigned-clock-rates <<
2231 power-domains = <&pgc <<
2232 }; <<
2233 <<
2234 vpu_g1: video-codec@38300000 <<
2235 compatible = "nxp,imx <<
2236 reg = <0x38300000 0x1 <<
2237 interrupts = <GIC_SPI <<
2238 clocks = <&clk IMX8MP <<
2239 assigned-clocks = <&c <<
2240 assigned-clock-parent <<
2241 assigned-clock-rates <<
2242 power-domains = <&vpu <<
2243 }; <<
2244 <<
2245 vpu_g2: video-codec@38310000 <<
2246 compatible = "nxp,imx <<
2247 reg = <0x38310000 0x1 <<
2248 interrupts = <GIC_SPI <<
2249 clocks = <&clk IMX8MP <<
2250 assigned-clocks = <&c <<
2251 assigned-clock-parent <<
2252 assigned-clock-rates <<
2253 power-domains = <&vpu <<
2254 }; <<
2255 <<
2256 vpumix_blk_ctrl: blk-ctrl@383 <<
2257 compatible = "fsl,imx <<
2258 reg = <0x38330000 0x1 <<
2259 #power-domain-cells = <<
2260 power-domains = <&pgc <<
2261 <&pgc <<
2262 power-domain-names = <<
2263 clocks = <&clk IMX8MP <<
2264 <&clk IMX8MP <<
2265 <&clk IMX8MP <<
2266 clock-names = "g1", " <<
2267 assigned-clocks = <&c <<
2268 assigned-clock-parent <<
2269 assigned-clock-rates <<
2270 interconnects = <&noc <<
2271 <&noc <<
2272 <&noc <<
2273 interconnect-names = <<
2274 }; <<
2275 <<
2276 npu: npu@38500000 { <<
2277 compatible = "vivante <<
2278 reg = <0x38500000 0x2 <<
2279 interrupts = <GIC_SPI <<
2280 clocks = <&clk IMX8MP <<
2281 <&clk IMX8MP <<
2282 <&clk IMX8MP <<
2283 <&clk IMX8MP <<
2284 clock-names = "core", <<
2285 power-domains = <&pgc <<
2286 }; <<
2287 <<
2288 gic: interrupt-controller@388 740 gic: interrupt-controller@38800000 {
2289 compatible = "arm,gic 741 compatible = "arm,gic-v3";
2290 reg = <0x38800000 0x1 742 reg = <0x38800000 0x10000>,
2291 <0x38880000 0xc 743 <0x38880000 0xc0000>;
2292 #interrupt-cells = <3 744 #interrupt-cells = <3>;
2293 interrupt-controller; 745 interrupt-controller;
2294 interrupts = <GIC_PPI 746 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2295 interrupt-parent = <& 747 interrupt-parent = <&gic>;
2296 }; 748 };
2297 749
2298 edacmc: memory-controller@3d4 <<
2299 compatible = "snps,dd <<
2300 reg = <0x3d400000 0x4 <<
2301 interrupts = <GIC_SPI <<
2302 }; <<
2303 <<
2304 ddr-pmu@3d800000 { 750 ddr-pmu@3d800000 {
2305 compatible = "fsl,imx 751 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2306 reg = <0x3d800000 0x4 752 reg = <0x3d800000 0x400000>;
2307 interrupts = <GIC_SPI 753 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2308 }; <<
2309 <<
2310 usb3_phy0: usb-phy@381f0040 { <<
2311 compatible = "fsl,imx <<
2312 reg = <0x381f0040 0x4 <<
2313 clocks = <&clk IMX8MP <<
2314 clock-names = "phy"; <<
2315 assigned-clocks = <&c <<
2316 assigned-clock-parent <<
2317 power-domains = <&hsi <<
2318 #phy-cells = <0>; <<
2319 status = "disabled"; <<
2320 }; <<
2321 <<
2322 usb3_0: usb@32f10100 { <<
2323 compatible = "fsl,imx <<
2324 reg = <0x32f10100 0x8 <<
2325 <0x381f0000 0x2 <<
2326 clocks = <&clk IMX8MP <<
2327 <&clk IMX8MP <<
2328 clock-names = "hsio", <<
2329 interrupts = <GIC_SPI <<
2330 power-domains = <&hsi <<
2331 #address-cells = <1>; <<
2332 #size-cells = <1>; <<
2333 dma-ranges = <0x40000 <<
2334 ranges; <<
2335 status = "disabled"; <<
2336 <<
2337 usb_dwc3_0: usb@38100 <<
2338 compatible = <<
2339 reg = <0x3810 <<
2340 clocks = <&cl <<
2341 <&cl <<
2342 <&cl <<
2343 clock-names = <<
2344 interrupts = <<
2345 phys = <&usb3 <<
2346 phy-names = " <<
2347 snps,gfladj-r <<
2348 snps,parkmode <<
2349 }; <<
2350 <<
2351 }; <<
2352 <<
2353 usb3_phy1: usb-phy@382f0040 { <<
2354 compatible = "fsl,imx <<
2355 reg = <0x382f0040 0x4 <<
2356 clocks = <&clk IMX8MP <<
2357 clock-names = "phy"; <<
2358 assigned-clocks = <&c <<
2359 assigned-clock-parent <<
2360 power-domains = <&hsi <<
2361 #phy-cells = <0>; <<
2362 status = "disabled"; <<
2363 }; <<
2364 <<
2365 usb3_1: usb@32f10108 { <<
2366 compatible = "fsl,imx <<
2367 reg = <0x32f10108 0x8 <<
2368 <0x382f0000 0x2 <<
2369 clocks = <&clk IMX8MP <<
2370 <&clk IMX8MP <<
2371 clock-names = "hsio", <<
2372 interrupts = <GIC_SPI <<
2373 power-domains = <&hsi <<
2374 #address-cells = <1>; <<
2375 #size-cells = <1>; <<
2376 dma-ranges = <0x40000 <<
2377 ranges; <<
2378 status = "disabled"; <<
2379 <<
2380 usb_dwc3_1: usb@38200 <<
2381 compatible = <<
2382 reg = <0x3820 <<
2383 clocks = <&cl <<
2384 <&cl <<
2385 <&cl <<
2386 clock-names = <<
2387 interrupts = <<
2388 phys = <&usb3 <<
2389 phy-names = " <<
2390 snps,gfladj-r <<
2391 snps,parkmode <<
2392 }; <<
2393 }; <<
2394 <<
2395 dsp: dsp@3b6e8000 { <<
2396 compatible = "fsl,imx <<
2397 reg = <0x3b6e8000 0x8 <<
2398 mbox-names = "txdb0", <<
2399 "rxdb0", "rxd <<
2400 mboxes = <&mu2 2 0>, <<
2401 <&mu2 3 0>, < <<
2402 memory-region = <&dsp <<
2403 status = "disabled"; <<
2404 }; 754 };
2405 }; 755 };
2406 }; 756 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.