1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mp-clock.h> 6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h> <<
8 #include <dt-bindings/reset/imx8mp-reset.h> <<
9 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp. <<
12 #include <dt-bindings/interrupt-controller/arm 9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h> 10 #include <dt-bindings/thermal/thermal.h>
14 11
15 #include "imx8mp-pinfunc.h" 12 #include "imx8mp-pinfunc.h"
16 13
17 / { 14 / {
18 interrupt-parent = <&gic>; 15 interrupt-parent = <&gic>;
19 #address-cells = <2>; 16 #address-cells = <2>;
20 #size-cells = <2>; 17 #size-cells = <2>;
21 18
22 aliases { 19 aliases {
23 ethernet0 = &fec; 20 ethernet0 = &fec;
24 ethernet1 = &eqos; 21 ethernet1 = &eqos;
25 gpio0 = &gpio1; 22 gpio0 = &gpio1;
26 gpio1 = &gpio2; 23 gpio1 = &gpio2;
27 gpio2 = &gpio3; 24 gpio2 = &gpio3;
28 gpio3 = &gpio4; 25 gpio3 = &gpio4;
29 gpio4 = &gpio5; 26 gpio4 = &gpio5;
30 i2c0 = &i2c1; 27 i2c0 = &i2c1;
31 i2c1 = &i2c2; 28 i2c1 = &i2c2;
32 i2c2 = &i2c3; 29 i2c2 = &i2c3;
33 i2c3 = &i2c4; 30 i2c3 = &i2c4;
34 i2c4 = &i2c5; 31 i2c4 = &i2c5;
35 i2c5 = &i2c6; 32 i2c5 = &i2c6;
36 mmc0 = &usdhc1; 33 mmc0 = &usdhc1;
37 mmc1 = &usdhc2; 34 mmc1 = &usdhc2;
38 mmc2 = &usdhc3; 35 mmc2 = &usdhc3;
39 serial0 = &uart1; 36 serial0 = &uart1;
40 serial1 = &uart2; 37 serial1 = &uart2;
41 serial2 = &uart3; 38 serial2 = &uart3;
42 serial3 = &uart4; 39 serial3 = &uart4;
43 spi0 = &flexspi; 40 spi0 = &flexspi;
44 }; 41 };
45 42
46 cpus { 43 cpus {
47 #address-cells = <1>; 44 #address-cells = <1>;
48 #size-cells = <0>; 45 #size-cells = <0>;
49 46
50 A53_0: cpu@0 { 47 A53_0: cpu@0 {
51 device_type = "cpu"; 48 device_type = "cpu";
52 compatible = "arm,cort 49 compatible = "arm,cortex-a53";
53 reg = <0x0>; 50 reg = <0x0>;
54 clock-latency = <61036 51 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_ 52 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci" 53 enable-method = "psci";
57 i-cache-size = <0x8000 54 i-cache-size = <0x8000>;
58 i-cache-line-size = <6 55 i-cache-line-size = <64>;
59 i-cache-sets = <256>; 56 i-cache-sets = <256>;
60 d-cache-size = <0x8000 57 d-cache-size = <0x8000>;
61 d-cache-line-size = <6 58 d-cache-line-size = <64>;
62 d-cache-sets = <128>; 59 d-cache-sets = <128>;
63 next-level-cache = <&A 60 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_sp <<
65 nvmem-cell-names = "sp <<
66 operating-points-v2 = <<
67 #cooling-cells = <2>; 61 #cooling-cells = <2>;
68 }; 62 };
69 63
70 A53_1: cpu@1 { 64 A53_1: cpu@1 {
71 device_type = "cpu"; 65 device_type = "cpu";
72 compatible = "arm,cort 66 compatible = "arm,cortex-a53";
73 reg = <0x1>; 67 reg = <0x1>;
74 clock-latency = <61036 68 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_ 69 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci" 70 enable-method = "psci";
77 i-cache-size = <0x8000 71 i-cache-size = <0x8000>;
78 i-cache-line-size = <6 72 i-cache-line-size = <64>;
79 i-cache-sets = <256>; 73 i-cache-sets = <256>;
80 d-cache-size = <0x8000 74 d-cache-size = <0x8000>;
81 d-cache-line-size = <6 75 d-cache-line-size = <64>;
82 d-cache-sets = <128>; 76 d-cache-sets = <128>;
83 next-level-cache = <&A 77 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <<
85 #cooling-cells = <2>; 78 #cooling-cells = <2>;
86 }; 79 };
87 80
88 A53_2: cpu@2 { 81 A53_2: cpu@2 {
89 device_type = "cpu"; 82 device_type = "cpu";
90 compatible = "arm,cort 83 compatible = "arm,cortex-a53";
91 reg = <0x2>; 84 reg = <0x2>;
92 clock-latency = <61036 85 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_ 86 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci" 87 enable-method = "psci";
95 i-cache-size = <0x8000 88 i-cache-size = <0x8000>;
96 i-cache-line-size = <6 89 i-cache-line-size = <64>;
97 i-cache-sets = <256>; 90 i-cache-sets = <256>;
98 d-cache-size = <0x8000 91 d-cache-size = <0x8000>;
99 d-cache-line-size = <6 92 d-cache-line-size = <64>;
100 d-cache-sets = <128>; 93 d-cache-sets = <128>;
101 next-level-cache = <&A 94 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <<
103 #cooling-cells = <2>; 95 #cooling-cells = <2>;
104 }; 96 };
105 97
106 A53_3: cpu@3 { 98 A53_3: cpu@3 {
107 device_type = "cpu"; 99 device_type = "cpu";
108 compatible = "arm,cort 100 compatible = "arm,cortex-a53";
109 reg = <0x3>; 101 reg = <0x3>;
110 clock-latency = <61036 102 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_ 103 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci" 104 enable-method = "psci";
113 i-cache-size = <0x8000 105 i-cache-size = <0x8000>;
114 i-cache-line-size = <6 106 i-cache-line-size = <64>;
115 i-cache-sets = <256>; 107 i-cache-sets = <256>;
116 d-cache-size = <0x8000 108 d-cache-size = <0x8000>;
117 d-cache-line-size = <6 109 d-cache-line-size = <64>;
118 d-cache-sets = <128>; 110 d-cache-sets = <128>;
119 next-level-cache = <&A 111 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <<
121 #cooling-cells = <2>; 112 #cooling-cells = <2>;
122 }; 113 };
123 114
124 A53_L2: l2-cache0 { 115 A53_L2: l2-cache0 {
125 compatible = "cache"; 116 compatible = "cache";
126 cache-unified; <<
127 cache-level = <2>; 117 cache-level = <2>;
128 cache-size = <0x80000> 118 cache-size = <0x80000>;
129 cache-line-size = <64> 119 cache-line-size = <64>;
130 cache-sets = <512>; 120 cache-sets = <512>;
131 }; 121 };
132 }; 122 };
133 123
134 a53_opp_table: opp-table { <<
135 compatible = "operating-points <<
136 opp-shared; <<
137 <<
138 opp-1200000000 { <<
139 opp-hz = /bits/ 64 <12 <<
140 opp-microvolt = <85000 <<
141 opp-supported-hw = <0x <<
142 clock-latency-ns = <15 <<
143 opp-suspend; <<
144 }; <<
145 <<
146 opp-1600000000 { <<
147 opp-hz = /bits/ 64 <16 <<
148 opp-microvolt = <95000 <<
149 opp-supported-hw = <0x <<
150 clock-latency-ns = <15 <<
151 opp-suspend; <<
152 }; <<
153 <<
154 opp-1800000000 { <<
155 opp-hz = /bits/ 64 <18 <<
156 opp-microvolt = <10000 <<
157 opp-supported-hw = <0x <<
158 clock-latency-ns = <15 <<
159 opp-suspend; <<
160 }; <<
161 }; <<
162 <<
163 osc_32k: clock-osc-32k { 124 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock"; 125 compatible = "fixed-clock";
165 #clock-cells = <0>; 126 #clock-cells = <0>;
166 clock-frequency = <32768>; 127 clock-frequency = <32768>;
167 clock-output-names = "osc_32k" 128 clock-output-names = "osc_32k";
168 }; 129 };
169 130
170 osc_24m: clock-osc-24m { 131 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock"; 132 compatible = "fixed-clock";
172 #clock-cells = <0>; 133 #clock-cells = <0>;
173 clock-frequency = <24000000>; 134 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m" 135 clock-output-names = "osc_24m";
175 }; 136 };
176 137
177 clk_ext1: clock-ext1 { 138 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock"; 139 compatible = "fixed-clock";
179 #clock-cells = <0>; 140 #clock-cells = <0>;
180 clock-frequency = <133000000>; 141 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1 142 clock-output-names = "clk_ext1";
182 }; 143 };
183 144
184 clk_ext2: clock-ext2 { 145 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock"; 146 compatible = "fixed-clock";
186 #clock-cells = <0>; 147 #clock-cells = <0>;
187 clock-frequency = <133000000>; 148 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2 149 clock-output-names = "clk_ext2";
189 }; 150 };
190 151
191 clk_ext3: clock-ext3 { 152 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock"; 153 compatible = "fixed-clock";
193 #clock-cells = <0>; 154 #clock-cells = <0>;
194 clock-frequency = <133000000>; 155 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3 156 clock-output-names = "clk_ext3";
196 }; 157 };
197 158
198 clk_ext4: clock-ext4 { 159 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock"; 160 compatible = "fixed-clock";
200 #clock-cells = <0>; 161 #clock-cells = <0>;
201 clock-frequency = <133000000>; !! 162 clock-frequency= <133000000>;
202 clock-output-names = "clk_ext4 163 clock-output-names = "clk_ext4";
203 }; 164 };
204 165
205 funnel { <<
206 /* <<
207 * non-configurable funnel don <<
208 * bus. As such no need to ad <<
209 */ <<
210 compatible = "arm,coresight-st <<
211 <<
212 in-ports { <<
213 #address-cells = <1>; <<
214 #size-cells = <0>; <<
215 <<
216 port@0 { <<
217 reg = <0>; <<
218 <<
219 ca_funnel_in_p <<
220 remote <<
221 }; <<
222 }; <<
223 <<
224 port@1 { <<
225 reg = <1>; <<
226 <<
227 ca_funnel_in_p <<
228 remote <<
229 }; <<
230 }; <<
231 <<
232 port@2 { <<
233 reg = <2>; <<
234 <<
235 ca_funnel_in_p <<
236 remote <<
237 }; <<
238 }; <<
239 <<
240 port@3 { <<
241 reg = <3>; <<
242 <<
243 ca_fun <<
244 remote <<
245 }; <<
246 }; <<
247 }; <<
248 <<
249 out-ports { <<
250 port { <<
251 <<
252 ca_funnel_out_ <<
253 remote <<
254 }; <<
255 }; <<
256 }; <<
257 }; <<
258 <<
259 reserved-memory { 166 reserved-memory {
260 #address-cells = <2>; 167 #address-cells = <2>;
261 #size-cells = <2>; 168 #size-cells = <2>;
262 ranges; 169 ranges;
263 170
264 dsp_reserved: dsp@92400000 { 171 dsp_reserved: dsp@92400000 {
265 reg = <0 0x92400000 0 172 reg = <0 0x92400000 0 0x2000000>;
266 no-map; 173 no-map;
267 status = "disabled"; <<
268 }; 174 };
269 }; 175 };
270 176
271 pmu { 177 pmu {
272 compatible = "arm,cortex-a53-p 178 compatible = "arm,cortex-a53-pmu";
273 interrupts = <GIC_PPI 7 179 interrupts = <GIC_PPI 7
274 (GIC_CPU_MASK_SIM 180 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
275 }; 181 };
276 182
277 psci { 183 psci {
278 compatible = "arm,psci-1.0"; 184 compatible = "arm,psci-1.0";
279 method = "smc"; 185 method = "smc";
280 }; 186 };
281 187
282 thermal-zones { 188 thermal-zones {
283 cpu-thermal { 189 cpu-thermal {
284 polling-delay-passive 190 polling-delay-passive = <250>;
285 polling-delay = <2000> 191 polling-delay = <2000>;
286 thermal-sensors = <&tm 192 thermal-sensors = <&tmu 0>;
287 trips { 193 trips {
288 cpu_alert0: tr 194 cpu_alert0: trip0 {
289 temper 195 temperature = <85000>;
290 hyster 196 hysteresis = <2000>;
291 type = 197 type = "passive";
292 }; 198 };
293 199
294 cpu_crit0: tri 200 cpu_crit0: trip1 {
295 temper 201 temperature = <95000>;
296 hyster 202 hysteresis = <2000>;
297 type = 203 type = "critical";
298 }; 204 };
299 }; 205 };
300 206
301 cooling-maps { 207 cooling-maps {
302 map0 { 208 map0 {
303 trip = 209 trip = <&cpu_alert0>;
304 coolin 210 cooling-device =
305 211 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
306 212 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
307 213 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
308 214 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
309 }; 215 };
310 }; 216 };
311 }; 217 };
312 218
313 soc-thermal { 219 soc-thermal {
314 polling-delay-passive 220 polling-delay-passive = <250>;
315 polling-delay = <2000> 221 polling-delay = <2000>;
316 thermal-sensors = <&tm 222 thermal-sensors = <&tmu 1>;
317 trips { 223 trips {
318 soc_alert0: tr 224 soc_alert0: trip0 {
319 temper 225 temperature = <85000>;
320 hyster 226 hysteresis = <2000>;
321 type = 227 type = "passive";
322 }; 228 };
323 229
324 soc_crit0: tri 230 soc_crit0: trip1 {
325 temper 231 temperature = <95000>;
326 hyster 232 hysteresis = <2000>;
327 type = 233 type = "critical";
328 }; 234 };
329 }; 235 };
330 236
331 cooling-maps { 237 cooling-maps {
332 map0 { 238 map0 {
333 trip = 239 trip = <&soc_alert0>;
334 coolin 240 cooling-device =
335 241 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
336 242 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
337 243 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
338 244 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 }; 245 };
340 }; 246 };
341 }; 247 };
342 }; 248 };
343 249
344 timer { 250 timer {
345 compatible = "arm,armv8-timer" 251 compatible = "arm,armv8-timer";
346 interrupts = <GIC_PPI 13 (GIC_ 252 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
347 <GIC_PPI 14 (GIC_ 253 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
348 <GIC_PPI 11 (GIC_ 254 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
349 <GIC_PPI 10 (GIC_ 255 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
350 clock-frequency = <8000000>; 256 clock-frequency = <8000000>;
351 arm,no-tick-in-suspend; 257 arm,no-tick-in-suspend;
352 }; 258 };
353 259
354 soc: soc@0 { !! 260 soc@0 {
355 compatible = "fsl,imx8mp-soc", 261 compatible = "fsl,imx8mp-soc", "simple-bus";
356 #address-cells = <1>; 262 #address-cells = <1>;
357 #size-cells = <1>; 263 #size-cells = <1>;
358 ranges = <0x0 0x0 0x0 0x3e0000 264 ranges = <0x0 0x0 0x0 0x3e000000>;
359 nvmem-cells = <&imx8mp_uid>; 265 nvmem-cells = <&imx8mp_uid>;
360 nvmem-cell-names = "soc_unique 266 nvmem-cell-names = "soc_unique_id";
361 267
362 etm0: etm@28440000 { <<
363 compatible = "arm,core <<
364 reg = <0x28440000 0x10 <<
365 cpu = <&A53_0>; <<
366 clocks = <&clk IMX8MP_ <<
367 clock-names = "apb_pcl <<
368 <<
369 out-ports { <<
370 port { <<
371 etm0_o <<
372 <<
373 }; <<
374 }; <<
375 }; <<
376 }; <<
377 <<
378 etm1: etm@28540000 { <<
379 compatible = "arm,core <<
380 reg = <0x28540000 0x10 <<
381 cpu = <&A53_1>; <<
382 clocks = <&clk IMX8MP_ <<
383 clock-names = "apb_pcl <<
384 <<
385 out-ports { <<
386 port { <<
387 etm1_o <<
388 <<
389 }; <<
390 }; <<
391 }; <<
392 }; <<
393 <<
394 etm2: etm@28640000 { <<
395 compatible = "arm,core <<
396 reg = <0x28640000 0x10 <<
397 cpu = <&A53_2>; <<
398 clocks = <&clk IMX8MP_ <<
399 clock-names = "apb_pcl <<
400 <<
401 out-ports { <<
402 port { <<
403 etm2_o <<
404 <<
405 }; <<
406 }; <<
407 }; <<
408 }; <<
409 <<
410 etm3: etm@28740000 { <<
411 compatible = "arm,core <<
412 reg = <0x28740000 0x10 <<
413 cpu = <&A53_3>; <<
414 clocks = <&clk IMX8MP_ <<
415 clock-names = "apb_pcl <<
416 <<
417 out-ports { <<
418 port { <<
419 etm3_o <<
420 <<
421 }; <<
422 }; <<
423 }; <<
424 }; <<
425 <<
426 funnel@28c03000 { <<
427 compatible = "arm,core <<
428 reg = <0x28c03000 0x10 <<
429 clocks = <&clk IMX8MP_ <<
430 clock-names = "apb_pcl <<
431 <<
432 in-ports { <<
433 #address-cells <<
434 #size-cells = <<
435 <<
436 port@0 { <<
437 reg = <<
438 <<
439 hugo_f <<
440 <<
441 }; <<
442 }; <<
443 <<
444 port@1 { <<
445 reg = <<
446 <<
447 hugo_f <<
448 /* M7 <<
449 }; <<
450 }; <<
451 <<
452 port@2 { <<
453 reg = <<
454 <<
455 hugo_f <<
456 /* DSP <<
457 }; <<
458 }; <<
459 /* the other i <<
460 }; <<
461 <<
462 out-ports { <<
463 port { <<
464 hugo_f <<
465 <<
466 }; <<
467 }; <<
468 }; <<
469 }; <<
470 <<
471 etf@28c04000 { <<
472 compatible = "arm,core <<
473 reg = <0x28c04000 0x10 <<
474 clocks = <&clk IMX8MP_ <<
475 clock-names = "apb_pcl <<
476 <<
477 in-ports { <<
478 port { <<
479 etf_in <<
480 <<
481 }; <<
482 }; <<
483 }; <<
484 <<
485 out-ports { <<
486 port { <<
487 etf_ou <<
488 <<
489 }; <<
490 }; <<
491 }; <<
492 }; <<
493 <<
494 etr@28c06000 { <<
495 compatible = "arm,core <<
496 reg = <0x28c06000 0x10 <<
497 clocks = <&clk IMX8MP_ <<
498 clock-names = "apb_pcl <<
499 <<
500 in-ports { <<
501 port { <<
502 etr_in <<
503 <<
504 }; <<
505 }; <<
506 }; <<
507 }; <<
508 <<
509 aips1: bus@30000000 { 268 aips1: bus@30000000 {
510 compatible = "fsl,aips 269 compatible = "fsl,aips-bus", "simple-bus";
511 reg = <0x30000000 0x40 270 reg = <0x30000000 0x400000>;
512 #address-cells = <1>; 271 #address-cells = <1>;
513 #size-cells = <1>; 272 #size-cells = <1>;
514 ranges; 273 ranges;
515 274
516 gpio1: gpio@30200000 { 275 gpio1: gpio@30200000 {
517 compatible = " 276 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
518 reg = <0x30200 277 reg = <0x30200000 0x10000>;
519 interrupts = < 278 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
520 < 279 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clk 280 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
522 gpio-controlle 281 gpio-controller;
523 #gpio-cells = 282 #gpio-cells = <2>;
524 interrupt-cont 283 interrupt-controller;
525 #interrupt-cel 284 #interrupt-cells = <2>;
526 gpio-ranges = 285 gpio-ranges = <&iomuxc 0 5 30>;
527 }; 286 };
528 287
529 gpio2: gpio@30210000 { 288 gpio2: gpio@30210000 {
530 compatible = " 289 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
531 reg = <0x30210 290 reg = <0x30210000 0x10000>;
532 interrupts = < 291 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
533 < 292 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clk 293 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
535 gpio-controlle 294 gpio-controller;
536 #gpio-cells = 295 #gpio-cells = <2>;
537 interrupt-cont 296 interrupt-controller;
538 #interrupt-cel 297 #interrupt-cells = <2>;
539 gpio-ranges = 298 gpio-ranges = <&iomuxc 0 35 21>;
540 }; 299 };
541 300
542 gpio3: gpio@30220000 { 301 gpio3: gpio@30220000 {
543 compatible = " 302 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
544 reg = <0x30220 303 reg = <0x30220000 0x10000>;
545 interrupts = < 304 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
546 < 305 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clk 306 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
548 gpio-controlle 307 gpio-controller;
549 #gpio-cells = 308 #gpio-cells = <2>;
550 interrupt-cont 309 interrupt-controller;
551 #interrupt-cel 310 #interrupt-cells = <2>;
552 gpio-ranges = 311 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
553 }; 312 };
554 313
555 gpio4: gpio@30230000 { 314 gpio4: gpio@30230000 {
556 compatible = " 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
557 reg = <0x30230 316 reg = <0x30230000 0x10000>;
558 interrupts = < 317 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
559 < 318 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clk 319 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
561 gpio-controlle 320 gpio-controller;
562 #gpio-cells = 321 #gpio-cells = <2>;
563 interrupt-cont 322 interrupt-controller;
564 #interrupt-cel 323 #interrupt-cells = <2>;
565 gpio-ranges = 324 gpio-ranges = <&iomuxc 0 82 32>;
566 }; 325 };
567 326
568 gpio5: gpio@30240000 { 327 gpio5: gpio@30240000 {
569 compatible = " 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
570 reg = <0x30240 329 reg = <0x30240000 0x10000>;
571 interrupts = < 330 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
572 < 331 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk 332 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
574 gpio-controlle 333 gpio-controller;
575 #gpio-cells = 334 #gpio-cells = <2>;
576 interrupt-cont 335 interrupt-controller;
577 #interrupt-cel 336 #interrupt-cells = <2>;
578 gpio-ranges = 337 gpio-ranges = <&iomuxc 0 114 30>;
579 }; 338 };
580 339
581 tmu: tmu@30260000 { 340 tmu: tmu@30260000 {
582 compatible = " 341 compatible = "fsl,imx8mp-tmu";
583 reg = <0x30260 342 reg = <0x30260000 0x10000>;
584 clocks = <&clk 343 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
585 nvmem-cells = <<
586 nvmem-cell-nam <<
587 #thermal-senso 344 #thermal-sensor-cells = <1>;
588 }; 345 };
589 346
590 wdog1: watchdog@302800 347 wdog1: watchdog@30280000 {
591 compatible = " 348 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
592 reg = <0x30280 349 reg = <0x30280000 0x10000>;
593 interrupts = < 350 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clk 351 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
595 status = "disa 352 status = "disabled";
596 }; 353 };
597 354
598 wdog2: watchdog@302900 355 wdog2: watchdog@30290000 {
599 compatible = " 356 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
600 reg = <0x30290 357 reg = <0x30290000 0x10000>;
601 interrupts = < 358 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk 359 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
603 status = "disa 360 status = "disabled";
604 }; 361 };
605 362
606 wdog3: watchdog@302a00 363 wdog3: watchdog@302a0000 {
607 compatible = " 364 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
608 reg = <0x302a0 365 reg = <0x302a0000 0x10000>;
609 interrupts = < 366 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clk 367 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
611 status = "disa 368 status = "disabled";
612 }; 369 };
613 370
614 gpt1: timer@302d0000 { <<
615 compatible = " <<
616 reg = <0x302d0 <<
617 interrupts = < <<
618 clocks = <&clk <<
619 clock-names = <<
620 }; <<
621 <<
622 gpt2: timer@302e0000 { <<
623 compatible = " <<
624 reg = <0x302e0 <<
625 interrupts = < <<
626 clocks = <&clk <<
627 clock-names = <<
628 }; <<
629 <<
630 gpt3: timer@302f0000 { <<
631 compatible = " <<
632 reg = <0x302f0 <<
633 interrupts = < <<
634 clocks = <&clk <<
635 clock-names = <<
636 }; <<
637 <<
638 iomuxc: pinctrl@303300 371 iomuxc: pinctrl@30330000 {
639 compatible = " 372 compatible = "fsl,imx8mp-iomuxc";
640 reg = <0x30330 373 reg = <0x30330000 0x10000>;
641 }; 374 };
642 375
643 gpr: syscon@30340000 { !! 376 gpr: iomuxc-gpr@30340000 {
644 compatible = " 377 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
645 reg = <0x30340 378 reg = <0x30340000 0x10000>;
646 }; 379 };
647 380
648 ocotp: efuse@30350000 381 ocotp: efuse@30350000 {
649 compatible = " 382 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
650 reg = <0x30350 383 reg = <0x30350000 0x10000>;
651 clocks = <&clk 384 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
652 /* For nvmem s 385 /* For nvmem subnodes */
653 #address-cells 386 #address-cells = <1>;
654 #size-cells = 387 #size-cells = <1>;
655 388
656 /* !! 389 imx8mp_uid: unique-id@420 {
657 * The registe <<
658 * Fusemap Des <<
659 * Assuming <<
660 * reg = <AD <<
661 * then <<
662 * Fuse Addr <<
663 * Note that i <<
664 * each subseq <<
665 * +0x10 in Fu <<
666 * reg = <0x8 <<
667 * 0x430). <<
668 */ <<
669 imx8mp_uid: un <<
670 reg = 390 reg = <0x8 0x8>;
671 }; 391 };
672 392
673 cpu_speed_grad !! 393 cpu_speed_grade: speed-grade@10 {
674 reg = 394 reg = <0x10 4>;
675 }; 395 };
676 396
677 eth_mac1: mac- !! 397 eth_mac1: mac-address@90 {
678 reg = 398 reg = <0x90 6>;
679 }; 399 };
680 400
681 eth_mac2: mac- !! 401 eth_mac2: mac-address@96 {
682 reg = 402 reg = <0x96 6>;
683 }; 403 };
684 <<
685 tmu_calib: cal <<
686 reg = <<
687 }; <<
688 }; 404 };
689 405
690 anatop: clock-controll !! 406 anatop: anatop@30360000 {
691 compatible = " !! 407 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
>> 408 "syscon";
692 reg = <0x30360 409 reg = <0x30360000 0x10000>;
693 #clock-cells = <<
694 }; 410 };
695 411
696 snvs: snvs@30370000 { 412 snvs: snvs@30370000 {
697 compatible = " 413 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 reg = <0x30370 414 reg = <0x30370000 0x10000>;
699 415
700 snvs_rtc: snvs 416 snvs_rtc: snvs-rtc-lp {
701 compat 417 compatible = "fsl,sec-v4.0-mon-rtc-lp";
702 regmap !! 418 regmap =<&snvs>;
703 offset 419 offset = <0x34>;
704 interr 420 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
705 421 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
706 clocks 422 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
707 clock- 423 clock-names = "snvs-rtc";
708 }; 424 };
709 425
710 snvs_pwrkey: s 426 snvs_pwrkey: snvs-powerkey {
711 compat 427 compatible = "fsl,sec-v4.0-pwrkey";
712 regmap 428 regmap = <&snvs>;
713 interr 429 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
714 clocks 430 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
715 clock- 431 clock-names = "snvs-pwrkey";
716 linux, 432 linux,keycode = <KEY_POWER>;
717 wakeup 433 wakeup-source;
718 status 434 status = "disabled";
719 }; 435 };
720 <<
721 snvs_lpgpr: sn <<
722 compat <<
723 <<
724 }; <<
725 }; 436 };
726 437
727 clk: clock-controller@ 438 clk: clock-controller@30380000 {
728 compatible = " 439 compatible = "fsl,imx8mp-ccm";
729 reg = <0x30380 440 reg = <0x30380000 0x10000>;
730 interrupts = < <<
731 < <<
732 #clock-cells = 441 #clock-cells = <1>;
733 clocks = <&osc 442 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
734 <&clk 443 <&clk_ext3>, <&clk_ext4>;
735 clock-names = 444 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
736 445 "clk_ext3", "clk_ext4";
737 assigned-clock 446 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 447 <&clk IMX8MP_CLK_A53_CORE>,
739 448 <&clk IMX8MP_CLK_NOC>,
740 449 <&clk IMX8MP_CLK_NOC_IO>,
741 !! 450 <&clk IMX8MP_CLK_GIC>,
>> 451 <&clk IMX8MP_CLK_AUDIO_AHB>,
>> 452 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
>> 453 <&clk IMX8MP_AUDIO_PLL1>,
>> 454 <&clk IMX8MP_AUDIO_PLL2>;
742 assigned-clock 455 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 456 <&clk IMX8MP_ARM_PLL_OUT>,
744 457 <&clk IMX8MP_SYS_PLL2_1000M>,
745 458 <&clk IMX8MP_SYS_PLL1_800M>,
746 !! 459 <&clk IMX8MP_SYS_PLL2_500M>,
>> 460 <&clk IMX8MP_SYS_PLL1_800M>,
>> 461 <&clk IMX8MP_SYS_PLL1_800M>;
747 assigned-clock 462 assigned-clock-rates = <0>, <0>,
748 463 <1000000000>,
749 464 <800000000>,
750 !! 465 <500000000>,
>> 466 <400000000>,
>> 467 <800000000>,
>> 468 <393216000>,
>> 469 <361267200>;
751 }; 470 };
752 471
753 src: reset-controller@ 472 src: reset-controller@30390000 {
754 compatible = " 473 compatible = "fsl,imx8mp-src", "syscon";
755 reg = <0x30390 474 reg = <0x30390000 0x10000>;
756 interrupts = < 475 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
757 #reset-cells = 476 #reset-cells = <1>;
758 }; 477 };
759 <<
760 gpc: gpc@303a0000 { <<
761 compatible = " <<
762 reg = <0x303a0 <<
763 interrupt-pare <<
764 interrupts = < <<
765 interrupt-cont <<
766 #interrupt-cel <<
767 <<
768 pgc { <<
769 #addre <<
770 #size- <<
771 <<
772 pgc_mi <<
773 <<
774 <<
775 }; <<
776 <<
777 pgc_pc <<
778 <<
779 <<
780 }; <<
781 <<
782 pgc_us <<
783 <<
784 <<
785 }; <<
786 <<
787 pgc_us <<
788 <<
789 <<
790 }; <<
791 <<
792 pgc_ml <<
793 <<
794 <<
795 <<
796 <<
797 <<
798 <<
799 <<
800 <<
801 <<
802 <<
803 <<
804 <<
805 <<
806 <<
807 }; <<
808 <<
809 pgc_au <<
810 <<
811 <<
812 <<
813 <<
814 <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 }; <<
821 <<
822 pgc_gp <<
823 <<
824 <<
825 <<
826 <<
827 }; <<
828 <<
829 pgc_gp <<
830 <<
831 <<
832 <<
833 <<
834 <<
835 <<
836 <<
837 <<
838 <<
839 }; <<
840 <<
841 pgc_vp <<
842 <<
843 <<
844 <<
845 }; <<
846 <<
847 pgc_gp <<
848 <<
849 <<
850 <<
851 <<
852 <<
853 }; <<
854 <<
855 pgc_me <<
856 <<
857 <<
858 <<
859 <<
860 }; <<
861 <<
862 pgc_vp <<
863 <<
864 <<
865 <<
866 <<
867 }; <<
868 <<
869 pgc_vp <<
870 <<
871 <<
872 <<
873 <<
874 <<
875 }; <<
876 <<
877 pgc_vp <<
878 <<
879 <<
880 <<
881 <<
882 }; <<
883 <<
884 pgc_hd <<
885 <<
886 <<
887 <<
888 <<
889 <<
890 <<
891 <<
892 <<
893 <<
894 }; <<
895 <<
896 pgc_hd <<
897 <<
898 <<
899 }; <<
900 <<
901 pgc_mi <<
902 <<
903 <<
904 }; <<
905 <<
906 pgc_hs <<
907 <<
908 <<
909 <<
910 <<
911 <<
912 <<
913 <<
914 }; <<
915 <<
916 pgc_is <<
917 <<
918 <<
919 <<
920 }; <<
921 }; <<
922 }; <<
923 }; 478 };
924 479
925 aips2: bus@30400000 { 480 aips2: bus@30400000 {
926 compatible = "fsl,aips 481 compatible = "fsl,aips-bus", "simple-bus";
927 reg = <0x30400000 0x40 482 reg = <0x30400000 0x400000>;
928 #address-cells = <1>; 483 #address-cells = <1>;
929 #size-cells = <1>; 484 #size-cells = <1>;
930 ranges; 485 ranges;
931 486
932 pwm1: pwm@30660000 { 487 pwm1: pwm@30660000 {
933 compatible = " 488 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
934 reg = <0x30660 489 reg = <0x30660000 0x10000>;
935 interrupts = < 490 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clk 491 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
937 <&clk 492 <&clk IMX8MP_CLK_PWM1_ROOT>;
938 clock-names = 493 clock-names = "ipg", "per";
939 #pwm-cells = < !! 494 #pwm-cells = <2>;
940 status = "disa 495 status = "disabled";
941 }; 496 };
942 497
943 pwm2: pwm@30670000 { 498 pwm2: pwm@30670000 {
944 compatible = " 499 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
945 reg = <0x30670 500 reg = <0x30670000 0x10000>;
946 interrupts = < 501 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clk 502 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
948 <&clk 503 <&clk IMX8MP_CLK_PWM2_ROOT>;
949 clock-names = 504 clock-names = "ipg", "per";
950 #pwm-cells = < !! 505 #pwm-cells = <2>;
951 status = "disa 506 status = "disabled";
952 }; 507 };
953 508
954 pwm3: pwm@30680000 { 509 pwm3: pwm@30680000 {
955 compatible = " 510 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
956 reg = <0x30680 511 reg = <0x30680000 0x10000>;
957 interrupts = < 512 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clk 513 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
959 <&clk 514 <&clk IMX8MP_CLK_PWM3_ROOT>;
960 clock-names = 515 clock-names = "ipg", "per";
961 #pwm-cells = < !! 516 #pwm-cells = <2>;
962 status = "disa 517 status = "disabled";
963 }; 518 };
964 519
965 pwm4: pwm@30690000 { 520 pwm4: pwm@30690000 {
966 compatible = " 521 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
967 reg = <0x30690 522 reg = <0x30690000 0x10000>;
968 interrupts = < 523 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clk 524 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
970 <&clk 525 <&clk IMX8MP_CLK_PWM4_ROOT>;
971 clock-names = 526 clock-names = "ipg", "per";
972 #pwm-cells = < !! 527 #pwm-cells = <2>;
973 status = "disa 528 status = "disabled";
974 }; 529 };
975 530
976 system_counter: timer@ 531 system_counter: timer@306a0000 {
977 compatible = " 532 compatible = "nxp,sysctr-timer";
978 reg = <0x306a0 533 reg = <0x306a0000 0x20000>;
979 interrupts = < 534 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&osc 535 clocks = <&osc_24m>;
981 clock-names = 536 clock-names = "per";
982 }; 537 };
983 <<
984 gpt6: timer@306e0000 { <<
985 compatible = " <<
986 reg = <0x306e0 <<
987 interrupts = < <<
988 clocks = <&clk <<
989 clock-names = <<
990 }; <<
991 <<
992 gpt5: timer@306f0000 { <<
993 compatible = " <<
994 reg = <0x306f0 <<
995 interrupts = < <<
996 clocks = <&clk <<
997 clock-names = <<
998 }; <<
999 <<
1000 gpt4: timer@30700000 <<
1001 compatible = <<
1002 reg = <0x3070 <<
1003 interrupts = <<
1004 clocks = <&cl <<
1005 clock-names = <<
1006 }; <<
1007 }; 538 };
1008 539
1009 aips3: bus@30800000 { 540 aips3: bus@30800000 {
1010 compatible = "fsl,aip 541 compatible = "fsl,aips-bus", "simple-bus";
1011 reg = <0x30800000 0x4 542 reg = <0x30800000 0x400000>;
1012 #address-cells = <1>; 543 #address-cells = <1>;
1013 #size-cells = <1>; 544 #size-cells = <1>;
1014 ranges; 545 ranges;
1015 546
1016 spba-bus@30800000 { !! 547 ecspi1: spi@30820000 {
1017 compatible = <<
1018 reg = <0x3080 <<
1019 #address-cell 548 #address-cells = <1>;
1020 #size-cells = !! 549 #size-cells = <0>;
1021 ranges; !! 550 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1022 !! 551 reg = <0x30820000 0x10000>;
1023 ecspi1: spi@3 !! 552 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1024 #addr !! 553 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
1025 #size !! 554 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1026 compa !! 555 clock-names = "ipg", "per";
1027 reg = !! 556 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1028 inter !! 557 dma-names = "rx", "tx";
1029 clock !! 558 status = "disabled";
1030 !! 559 };
1031 clock <<
1032 assig <<
1033 assig <<
1034 assig <<
1035 dmas <<
1036 dma-n <<
1037 statu <<
1038 }; <<
1039 560
1040 ecspi2: spi@3 !! 561 ecspi2: spi@30830000 {
1041 #addr !! 562 #address-cells = <1>;
1042 #size !! 563 #size-cells = <0>;
1043 compa !! 564 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1044 reg = !! 565 reg = <0x30830000 0x10000>;
1045 inter !! 566 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1046 clock !! 567 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1047 !! 568 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1048 clock !! 569 clock-names = "ipg", "per";
1049 assig !! 570 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1050 assig !! 571 dma-names = "rx", "tx";
1051 assig !! 572 status = "disabled";
1052 dmas !! 573 };
1053 dma-n <<
1054 statu <<
1055 }; <<
1056 574
1057 ecspi3: spi@3 !! 575 ecspi3: spi@30840000 {
1058 #addr !! 576 #address-cells = <1>;
1059 #size !! 577 #size-cells = <0>;
1060 compa !! 578 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1061 reg = !! 579 reg = <0x30840000 0x10000>;
1062 inter !! 580 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1063 clock !! 581 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1064 !! 582 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1065 clock !! 583 clock-names = "ipg", "per";
1066 assig !! 584 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1067 assig !! 585 dma-names = "rx", "tx";
1068 assig !! 586 status = "disabled";
1069 dmas !! 587 };
1070 dma-n <<
1071 statu <<
1072 }; <<
1073 588
1074 uart1: serial !! 589 uart1: serial@30860000 {
1075 compa !! 590 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1076 reg = !! 591 reg = <0x30860000 0x10000>;
1077 inter !! 592 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1078 clock !! 593 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1079 !! 594 <&clk IMX8MP_CLK_UART1_ROOT>;
1080 clock !! 595 clock-names = "ipg", "per";
1081 dmas !! 596 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1082 dma-n !! 597 dma-names = "rx", "tx";
1083 statu !! 598 status = "disabled";
1084 }; !! 599 };
1085 600
1086 uart3: serial !! 601 uart3: serial@30880000 {
1087 compa !! 602 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1088 reg = !! 603 reg = <0x30880000 0x10000>;
1089 inter !! 604 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1090 clock !! 605 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1091 !! 606 <&clk IMX8MP_CLK_UART3_ROOT>;
1092 clock !! 607 clock-names = "ipg", "per";
1093 dmas !! 608 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1094 dma-n !! 609 dma-names = "rx", "tx";
1095 statu !! 610 status = "disabled";
1096 }; !! 611 };
1097 612
1098 uart2: serial !! 613 uart2: serial@30890000 {
1099 compa !! 614 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1100 reg = !! 615 reg = <0x30890000 0x10000>;
1101 inter !! 616 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1102 clock !! 617 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1103 !! 618 <&clk IMX8MP_CLK_UART2_ROOT>;
1104 clock !! 619 clock-names = "ipg", "per";
1105 dmas !! 620 status = "disabled";
1106 dma-n !! 621 };
1107 statu <<
1108 }; <<
1109 622
1110 flexcan1: can !! 623 flexcan1: can@308c0000 {
1111 compa !! 624 compatible = "fsl,imx8mp-flexcan";
1112 reg = !! 625 reg = <0x308c0000 0x10000>;
1113 inter !! 626 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1114 clock !! 627 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1115 !! 628 <&clk IMX8MP_CLK_CAN1_ROOT>;
1116 clock !! 629 clock-names = "ipg", "per";
1117 assig !! 630 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1118 assig !! 631 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1119 assig !! 632 assigned-clock-rates = <40000000>;
1120 fsl,c !! 633 fsl,clk-source = /bits/ 8 <0>;
1121 fsl,s !! 634 fsl,stop-mode = <&gpr 0x10 4>;
1122 statu !! 635 status = "disabled";
1123 }; !! 636 };
1124 637
1125 flexcan2: can !! 638 flexcan2: can@308d0000 {
1126 compa !! 639 compatible = "fsl,imx8mp-flexcan";
1127 reg = !! 640 reg = <0x308d0000 0x10000>;
1128 inter !! 641 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1129 clock !! 642 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1130 !! 643 <&clk IMX8MP_CLK_CAN2_ROOT>;
1131 clock !! 644 clock-names = "ipg", "per";
1132 assig !! 645 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1133 assig !! 646 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1134 assig !! 647 assigned-clock-rates = <40000000>;
1135 fsl,c !! 648 fsl,clk-source = /bits/ 8 <0>;
1136 fsl,s !! 649 fsl,stop-mode = <&gpr 0x10 5>;
1137 statu !! 650 status = "disabled";
1138 }; <<
1139 }; 651 };
1140 652
1141 crypto: crypto@309000 653 crypto: crypto@30900000 {
1142 compatible = 654 compatible = "fsl,sec-v4.0";
1143 #address-cell 655 #address-cells = <1>;
1144 #size-cells = 656 #size-cells = <1>;
1145 reg = <0x3090 657 reg = <0x30900000 0x40000>;
1146 ranges = <0 0 658 ranges = <0 0x30900000 0x40000>;
1147 interrupts = 659 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&cl 660 clocks = <&clk IMX8MP_CLK_AHB>,
1149 <&cl 661 <&clk IMX8MP_CLK_IPG_ROOT>;
1150 clock-names = 662 clock-names = "aclk", "ipg";
1151 663
1152 sec_jr0: jr@1 664 sec_jr0: jr@1000 {
1153 compa 665 compatible = "fsl,sec-v4.0-job-ring";
1154 reg = 666 reg = <0x1000 0x1000>;
1155 inter 667 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1156 statu <<
1157 }; 668 };
1158 669
1159 sec_jr1: jr@2 670 sec_jr1: jr@2000 {
1160 compa 671 compatible = "fsl,sec-v4.0-job-ring";
1161 reg = 672 reg = <0x2000 0x1000>;
1162 inter 673 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1163 }; 674 };
1164 675
1165 sec_jr2: jr@3 676 sec_jr2: jr@3000 {
1166 compa 677 compatible = "fsl,sec-v4.0-job-ring";
1167 reg = 678 reg = <0x3000 0x1000>;
1168 inter 679 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1169 }; 680 };
1170 }; 681 };
1171 682
1172 i2c1: i2c@30a20000 { 683 i2c1: i2c@30a20000 {
1173 compatible = 684 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1174 #address-cell 685 #address-cells = <1>;
1175 #size-cells = 686 #size-cells = <0>;
1176 reg = <0x30a2 687 reg = <0x30a20000 0x10000>;
1177 interrupts = 688 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cl 689 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1179 status = "dis 690 status = "disabled";
1180 }; 691 };
1181 692
1182 i2c2: i2c@30a30000 { 693 i2c2: i2c@30a30000 {
1183 compatible = 694 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1184 #address-cell 695 #address-cells = <1>;
1185 #size-cells = 696 #size-cells = <0>;
1186 reg = <0x30a3 697 reg = <0x30a30000 0x10000>;
1187 interrupts = 698 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&cl 699 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1189 status = "dis 700 status = "disabled";
1190 }; 701 };
1191 702
1192 i2c3: i2c@30a40000 { 703 i2c3: i2c@30a40000 {
1193 compatible = 704 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1194 #address-cell 705 #address-cells = <1>;
1195 #size-cells = 706 #size-cells = <0>;
1196 reg = <0x30a4 707 reg = <0x30a40000 0x10000>;
1197 interrupts = 708 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&cl 709 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1199 status = "dis 710 status = "disabled";
1200 }; 711 };
1201 712
1202 i2c4: i2c@30a50000 { 713 i2c4: i2c@30a50000 {
1203 compatible = 714 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1204 #address-cell 715 #address-cells = <1>;
1205 #size-cells = 716 #size-cells = <0>;
1206 reg = <0x30a5 717 reg = <0x30a50000 0x10000>;
1207 interrupts = 718 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cl 719 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1209 status = "dis 720 status = "disabled";
1210 }; 721 };
1211 722
1212 uart4: serial@30a6000 723 uart4: serial@30a60000 {
1213 compatible = 724 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1214 reg = <0x30a6 725 reg = <0x30a60000 0x10000>;
1215 interrupts = 726 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&cl 727 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1217 <&cl 728 <&clk IMX8MP_CLK_UART4_ROOT>;
1218 clock-names = 729 clock-names = "ipg", "per";
1219 dmas = <&sdma 730 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1220 dma-names = " 731 dma-names = "rx", "tx";
1221 status = "dis 732 status = "disabled";
1222 }; 733 };
1223 734
1224 mu: mailbox@30aa0000 735 mu: mailbox@30aa0000 {
1225 compatible = 736 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1226 reg = <0x30aa 737 reg = <0x30aa0000 0x10000>;
1227 interrupts = 738 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&cl 739 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1229 #mbox-cells = 740 #mbox-cells = <2>;
1230 }; 741 };
1231 742
1232 mu2: mailbox@30e60000 743 mu2: mailbox@30e60000 {
1233 compatible = 744 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1234 reg = <0x30e6 745 reg = <0x30e60000 0x10000>;
1235 interrupts = 746 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1236 #mbox-cells = 747 #mbox-cells = <2>;
1237 status = "dis 748 status = "disabled";
1238 }; 749 };
1239 750
1240 i2c5: i2c@30ad0000 { 751 i2c5: i2c@30ad0000 {
1241 compatible = 752 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1242 #address-cell 753 #address-cells = <1>;
1243 #size-cells = 754 #size-cells = <0>;
1244 reg = <0x30ad 755 reg = <0x30ad0000 0x10000>;
1245 interrupts = 756 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&cl 757 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1247 status = "dis 758 status = "disabled";
1248 }; 759 };
1249 760
1250 i2c6: i2c@30ae0000 { 761 i2c6: i2c@30ae0000 {
1251 compatible = 762 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1252 #address-cell 763 #address-cells = <1>;
1253 #size-cells = 764 #size-cells = <0>;
1254 reg = <0x30ae 765 reg = <0x30ae0000 0x10000>;
1255 interrupts = 766 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cl 767 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1257 status = "dis 768 status = "disabled";
1258 }; 769 };
1259 770
1260 usdhc1: mmc@30b40000 771 usdhc1: mmc@30b40000 {
1261 compatible = !! 772 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
1262 reg = <0x30b4 773 reg = <0x30b40000 0x10000>;
1263 interrupts = 774 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cl !! 775 clocks = <&clk IMX8MP_CLK_DUMMY>,
1265 <&cl 776 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1266 <&cl 777 <&clk IMX8MP_CLK_USDHC1_ROOT>;
1267 clock-names = 778 clock-names = "ipg", "ahb", "per";
1268 fsl,tuning-st 779 fsl,tuning-start-tap = <20>;
1269 fsl,tuning-st !! 780 fsl,tuning-step= <2>;
1270 bus-width = < 781 bus-width = <4>;
1271 status = "dis 782 status = "disabled";
1272 }; 783 };
1273 784
1274 usdhc2: mmc@30b50000 785 usdhc2: mmc@30b50000 {
1275 compatible = !! 786 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
1276 reg = <0x30b5 787 reg = <0x30b50000 0x10000>;
1277 interrupts = 788 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&cl !! 789 clocks = <&clk IMX8MP_CLK_DUMMY>,
1279 <&cl 790 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1280 <&cl 791 <&clk IMX8MP_CLK_USDHC2_ROOT>;
1281 clock-names = 792 clock-names = "ipg", "ahb", "per";
1282 fsl,tuning-st 793 fsl,tuning-start-tap = <20>;
1283 fsl,tuning-st !! 794 fsl,tuning-step= <2>;
1284 bus-width = < 795 bus-width = <4>;
1285 status = "dis 796 status = "disabled";
1286 }; 797 };
1287 798
1288 usdhc3: mmc@30b60000 799 usdhc3: mmc@30b60000 {
1289 compatible = !! 800 compatible = "fsl,imx8mp-usdhc", "fsl,imx7d-usdhc";
1290 reg = <0x30b6 801 reg = <0x30b60000 0x10000>;
1291 interrupts = 802 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cl !! 803 clocks = <&clk IMX8MP_CLK_DUMMY>,
1293 <&cl 804 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1294 <&cl 805 <&clk IMX8MP_CLK_USDHC3_ROOT>;
1295 clock-names = 806 clock-names = "ipg", "ahb", "per";
1296 fsl,tuning-st 807 fsl,tuning-start-tap = <20>;
1297 fsl,tuning-st !! 808 fsl,tuning-step= <2>;
1298 bus-width = < 809 bus-width = <4>;
1299 status = "dis 810 status = "disabled";
1300 }; 811 };
1301 812
1302 flexspi: spi@30bb0000 813 flexspi: spi@30bb0000 {
1303 compatible = 814 compatible = "nxp,imx8mp-fspi";
1304 reg = <0x30bb 815 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1305 reg-names = " 816 reg-names = "fspi_base", "fspi_mmap";
1306 interrupts = 817 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&cl 818 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1308 <&cl 819 <&clk IMX8MP_CLK_QSPI_ROOT>;
1309 clock-names = 820 clock-names = "fspi_en", "fspi";
1310 assigned-cloc 821 assigned-clock-rates = <80000000>;
1311 assigned-cloc 822 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1312 #address-cell 823 #address-cells = <1>;
1313 #size-cells = 824 #size-cells = <0>;
1314 status = "dis 825 status = "disabled";
1315 }; 826 };
1316 827
1317 sdma1: dma-controller 828 sdma1: dma-controller@30bd0000 {
1318 compatible = 829 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1319 reg = <0x30bd 830 reg = <0x30bd0000 0x10000>;
1320 interrupts = 831 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&cl 832 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1322 <&cl 833 <&clk IMX8MP_CLK_AHB>;
1323 clock-names = 834 clock-names = "ipg", "ahb";
1324 #dma-cells = 835 #dma-cells = <3>;
1325 fsl,sdma-ram- 836 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1326 }; 837 };
1327 838
1328 fec: ethernet@30be000 839 fec: ethernet@30be0000 {
1329 compatible = 840 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1330 reg = <0x30be 841 reg = <0x30be0000 0x10000>;
1331 interrupts = 842 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1332 843 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1333 844 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1334 845 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&cl 846 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1336 <&cl 847 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1337 <&cl 848 <&clk IMX8MP_CLK_ENET_TIMER>,
1338 <&cl 849 <&clk IMX8MP_CLK_ENET_REF>,
1339 <&cl 850 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1340 clock-names = 851 clock-names = "ipg", "ahb", "ptp",
1341 852 "enet_clk_ref", "enet_out";
1342 assigned-cloc 853 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1343 854 <&clk IMX8MP_CLK_ENET_TIMER>,
1344 855 <&clk IMX8MP_CLK_ENET_REF>,
1345 856 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1346 assigned-cloc 857 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1347 858 <&clk IMX8MP_SYS_PLL2_100M>,
1348 859 <&clk IMX8MP_SYS_PLL2_125M>,
1349 860 <&clk IMX8MP_SYS_PLL2_50M>;
1350 assigned-cloc 861 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1351 fsl,num-tx-qu 862 fsl,num-tx-queues = <3>;
1352 fsl,num-rx-qu 863 fsl,num-rx-queues = <3>;
1353 nvmem-cells = 864 nvmem-cells = <ð_mac1>;
1354 nvmem-cell-na 865 nvmem-cell-names = "mac-address";
1355 fsl,stop-mode 866 fsl,stop-mode = <&gpr 0x10 3>;
1356 status = "dis 867 status = "disabled";
1357 }; 868 };
1358 869
1359 eqos: ethernet@30bf00 870 eqos: ethernet@30bf0000 {
1360 compatible = 871 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1361 reg = <0x30bf 872 reg = <0x30bf0000 0x10000>;
1362 interrupts = 873 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1363 874 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1364 interrupt-nam 875 interrupt-names = "macirq", "eth_wake_irq";
1365 clocks = <&cl 876 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1366 <&cl 877 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1367 <&cl 878 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1368 <&cl 879 <&clk IMX8MP_CLK_ENET_QOS>;
1369 clock-names = 880 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1370 assigned-cloc 881 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1371 882 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1372 883 <&clk IMX8MP_CLK_ENET_QOS>;
1373 assigned-cloc 884 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1374 885 <&clk IMX8MP_SYS_PLL2_100M>,
1375 886 <&clk IMX8MP_SYS_PLL2_125M>;
1376 assigned-cloc 887 assigned-clock-rates = <0>, <100000000>, <125000000>;
1377 nvmem-cells = 888 nvmem-cells = <ð_mac2>;
1378 nvmem-cell-na 889 nvmem-cell-names = "mac-address";
1379 intf_mode = < 890 intf_mode = <&gpr 0x4>;
1380 status = "dis 891 status = "disabled";
1381 }; 892 };
1382 }; 893 };
1383 894
1384 aips5: bus@30c00000 { <<
1385 compatible = "fsl,aip <<
1386 reg = <0x30c00000 0x4 <<
1387 #address-cells = <1>; <<
1388 #size-cells = <1>; <<
1389 ranges; <<
1390 <<
1391 spba-bus@30c00000 { <<
1392 compatible = <<
1393 reg = <0x30c0 <<
1394 #address-cell <<
1395 #size-cells = <<
1396 ranges; <<
1397 <<
1398 sai1: sai@30c <<
1399 compa <<
1400 reg = <<
1401 #soun <<
1402 clock <<
1403 <<
1404 <<
1405 <<
1406 <<
1407 clock <<
1408 dmas <<
1409 dma-n <<
1410 inter <<
1411 statu <<
1412 }; <<
1413 <<
1414 sai2: sai@30c <<
1415 compa <<
1416 reg = <<
1417 #soun <<
1418 clock <<
1419 <<
1420 <<
1421 <<
1422 <<
1423 clock <<
1424 dmas <<
1425 dma-n <<
1426 inter <<
1427 statu <<
1428 }; <<
1429 <<
1430 sai3: sai@30c <<
1431 compa <<
1432 reg = <<
1433 #soun <<
1434 clock <<
1435 <<
1436 <<
1437 <<
1438 <<
1439 clock <<
1440 dmas <<
1441 dma-n <<
1442 inter <<
1443 statu <<
1444 }; <<
1445 <<
1446 sai5: sai@30c <<
1447 compa <<
1448 reg = <<
1449 #soun <<
1450 clock <<
1451 <<
1452 <<
1453 <<
1454 <<
1455 clock <<
1456 dmas <<
1457 dma-n <<
1458 inter <<
1459 statu <<
1460 }; <<
1461 <<
1462 sai6: sai@30c <<
1463 compa <<
1464 reg = <<
1465 #soun <<
1466 clock <<
1467 <<
1468 <<
1469 <<
1470 <<
1471 clock <<
1472 dmas <<
1473 dma-n <<
1474 inter <<
1475 statu <<
1476 }; <<
1477 <<
1478 sai7: sai@30c <<
1479 compa <<
1480 reg = <<
1481 #soun <<
1482 clock <<
1483 <<
1484 <<
1485 <<
1486 <<
1487 clock <<
1488 dmas <<
1489 dma-n <<
1490 inter <<
1491 statu <<
1492 }; <<
1493 <<
1494 easrc: easrc@ <<
1495 compa <<
1496 reg = <<
1497 inter <<
1498 clock <<
1499 clock <<
1500 dmas <<
1501 <<
1502 <<
1503 <<
1504 dma-n <<
1505 <<
1506 <<
1507 <<
1508 firmw <<
1509 fsl,a <<
1510 fsl,a <<
1511 statu <<
1512 }; <<
1513 <<
1514 micfil: audio <<
1515 compa <<
1516 reg = <<
1517 #soun <<
1518 inter <<
1519 <<
1520 <<
1521 <<
1522 clock <<
1523 <<
1524 <<
1525 <<
1526 <<
1527 clock <<
1528 <<
1529 dmas <<
1530 dma-n <<
1531 statu <<
1532 }; <<
1533 <<
1534 aud2htx: aud2 <<
1535 compa <<
1536 reg = <<
1537 inter <<
1538 clock <<
1539 clock <<
1540 dmas <<
1541 dma-n <<
1542 statu <<
1543 }; <<
1544 <<
1545 xcvr: xcvr@30 <<
1546 compa <<
1547 reg = <<
1548 <<
1549 <<
1550 <<
1551 reg-n <<
1552 <<
1553 inter <<
1554 <<
1555 <<
1556 <<
1557 <<
1558 <<
1559 clock <<
1560 <<
1561 <<
1562 <<
1563 clock <<
1564 dmas <<
1565 dma-n <<
1566 reset <<
1567 statu <<
1568 }; <<
1569 }; <<
1570 <<
1571 sdma3: dma-controller <<
1572 compatible = <<
1573 reg = <0x30e0 <<
1574 #dma-cells = <<
1575 clocks = <&au <<
1576 <&cl <<
1577 clock-names = <<
1578 interrupts = <<
1579 fsl,sdma-ram- <<
1580 }; <<
1581 <<
1582 sdma2: dma-controller <<
1583 compatible = <<
1584 reg = <0x30e1 <<
1585 #dma-cells = <<
1586 clocks = <&au <<
1587 <&cl <<
1588 clock-names = <<
1589 interrupts = <<
1590 fsl,sdma-ram- <<
1591 }; <<
1592 <<
1593 audio_blk_ctrl: clock <<
1594 compatible = <<
1595 reg = <0x30e2 <<
1596 #clock-cells <<
1597 #reset-cells <<
1598 clocks = <&cl <<
1599 <&cl <<
1600 <&cl <<
1601 <&cl <<
1602 <&cl <<
1603 <&cl <<
1604 <&cl <<
1605 clock-names = <<
1606 <<
1607 <<
1608 power-domains <<
1609 assigned-cloc <<
1610 <<
1611 assigned-cloc <<
1612 }; <<
1613 }; <<
1614 <<
1615 noc: interconnect@32700000 { <<
1616 compatible = "fsl,imx <<
1617 reg = <0x32700000 0x1 <<
1618 clocks = <&clk IMX8MP <<
1619 #interconnect-cells = <<
1620 operating-points-v2 = <<
1621 <<
1622 noc_opp_table: opp-ta <<
1623 compatible = <<
1624 <<
1625 opp-200000000 <<
1626 opp-h <<
1627 }; <<
1628 <<
1629 opp-100000000 <<
1630 opp-h <<
1631 }; <<
1632 }; <<
1633 }; <<
1634 <<
1635 aips4: bus@32c00000 { <<
1636 compatible = "fsl,aip <<
1637 reg = <0x32c00000 0x4 <<
1638 #address-cells = <1>; <<
1639 #size-cells = <1>; <<
1640 ranges; <<
1641 <<
1642 isi_0: isi@32e00000 { <<
1643 compatible = <<
1644 reg = <0x32e0 <<
1645 interrupts = <<
1646 <<
1647 clocks = <&cl <<
1648 <&cl <<
1649 clock-names = <<
1650 fsl,blk-ctrl <<
1651 power-domains <<
1652 status = "dis <<
1653 <<
1654 ports { <<
1655 #addr <<
1656 #size <<
1657 <<
1658 port@ <<
1659 <<
1660 <<
1661 <<
1662 <<
1663 <<
1664 }; <<
1665 <<
1666 port@ <<
1667 <<
1668 <<
1669 <<
1670 <<
1671 <<
1672 }; <<
1673 }; <<
1674 }; <<
1675 <<
1676 isp_0: isp@32e10000 { <<
1677 compatible = <<
1678 reg = <0x32e1 <<
1679 interrupts = <<
1680 clocks = <&cl <<
1681 <&cl <<
1682 <&cl <<
1683 clock-names = <<
1684 power-domains <<
1685 fsl,blk-ctrl <<
1686 status = "dis <<
1687 <<
1688 ports { <<
1689 #addr <<
1690 #size <<
1691 <<
1692 port@ <<
1693 <<
1694 }; <<
1695 }; <<
1696 }; <<
1697 <<
1698 isp_1: isp@32e20000 { <<
1699 compatible = <<
1700 reg = <0x32e2 <<
1701 interrupts = <<
1702 clocks = <&cl <<
1703 <&cl <<
1704 <&cl <<
1705 clock-names = <<
1706 power-domains <<
1707 fsl,blk-ctrl <<
1708 status = "dis <<
1709 <<
1710 ports { <<
1711 #addr <<
1712 #size <<
1713 <<
1714 port@ <<
1715 <<
1716 }; <<
1717 }; <<
1718 }; <<
1719 <<
1720 dewarp: dwe@32e30000 <<
1721 compatible = <<
1722 reg = <0x32e3 <<
1723 interrupts = <<
1724 clocks = <&cl <<
1725 <&cl <<
1726 clock-names = <<
1727 power-domains <<
1728 }; <<
1729 <<
1730 mipi_csi_0: csi@32e40 <<
1731 compatible = <<
1732 reg = <0x32e4 <<
1733 interrupts = <<
1734 clock-frequen <<
1735 clocks = <&cl <<
1736 <&cl <<
1737 <&cl <<
1738 <&cl <<
1739 clock-names = <<
1740 assigned-cloc <<
1741 <<
1742 assigned-cloc <<
1743 <<
1744 power-domains <<
1745 status = "dis <<
1746 <<
1747 ports { <<
1748 #addr <<
1749 #size <<
1750 <<
1751 port@ <<
1752 <<
1753 }; <<
1754 <<
1755 port@ <<
1756 <<
1757 <<
1758 <<
1759 <<
1760 <<
1761 }; <<
1762 }; <<
1763 }; <<
1764 <<
1765 mipi_csi_1: csi@32e50 <<
1766 compatible = <<
1767 reg = <0x32e5 <<
1768 interrupts = <<
1769 clock-frequen <<
1770 clocks = <&cl <<
1771 <&cl <<
1772 <&cl <<
1773 <&cl <<
1774 clock-names = <<
1775 assigned-cloc <<
1776 <<
1777 assigned-cloc <<
1778 <<
1779 power-domains <<
1780 status = "dis <<
1781 <<
1782 ports { <<
1783 #addr <<
1784 #size <<
1785 <<
1786 port@ <<
1787 <<
1788 }; <<
1789 <<
1790 port@ <<
1791 <<
1792 <<
1793 <<
1794 <<
1795 <<
1796 }; <<
1797 }; <<
1798 }; <<
1799 <<
1800 mipi_dsi: dsi@32e6000 <<
1801 compatible = <<
1802 reg = <0x32e6 <<
1803 clocks = <&cl <<
1804 <&cl <<
1805 clock-names = <<
1806 assigned-cloc <<
1807 <<
1808 assigned-cloc <<
1809 <<
1810 assigned-cloc <<
1811 samsung,pll-c <<
1812 interrupts = <<
1813 power-domains <<
1814 status = "dis <<
1815 <<
1816 ports { <<
1817 #addr <<
1818 #size <<
1819 <<
1820 port@ <<
1821 <<
1822 <<
1823 <<
1824 <<
1825 <<
1826 }; <<
1827 <<
1828 port@ <<
1829 <<
1830 <<
1831 <<
1832 <<
1833 }; <<
1834 }; <<
1835 }; <<
1836 <<
1837 lcdif1: display-contr <<
1838 compatible = <<
1839 reg = <0x32e8 <<
1840 clocks = <&cl <<
1841 <&cl <<
1842 <&cl <<
1843 clock-names = <<
1844 interrupts = <<
1845 power-domains <<
1846 status = "dis <<
1847 <<
1848 port { <<
1849 lcdif <<
1850 <<
1851 }; <<
1852 }; <<
1853 }; <<
1854 <<
1855 lcdif2: display-contr <<
1856 compatible = <<
1857 reg = <0x32e9 <<
1858 interrupts = <<
1859 clocks = <&cl <<
1860 <&cl <<
1861 <&cl <<
1862 clock-names = <<
1863 power-domains <<
1864 status = "dis <<
1865 <<
1866 port { <<
1867 lcdif <<
1868 <<
1869 }; <<
1870 }; <<
1871 }; <<
1872 <<
1873 media_blk_ctrl: blk-c <<
1874 compatible = <<
1875 <<
1876 reg = <0x32ec <<
1877 #address-cell <<
1878 #size-cells = <<
1879 power-domains <<
1880 <<
1881 <<
1882 <<
1883 <<
1884 <<
1885 <<
1886 <<
1887 <<
1888 <<
1889 power-domain- <<
1890 <<
1891 <<
1892 <<
1893 interconnects <<
1894 <&noc <<
1895 <&noc <<
1896 <&noc <<
1897 <&noc <<
1898 <&noc <<
1899 <&noc <<
1900 <&noc <<
1901 <&noc <<
1902 interconnect- <<
1903 <<
1904 <<
1905 clocks = <&cl <<
1906 <&cl <<
1907 <&cl <<
1908 <&cl <<
1909 <&cl <<
1910 <&cl <<
1911 <&cl <<
1912 <&cl <<
1913 clock-names = <<
1914 <<
1915 <<
1916 /* <<
1917 * The ISP ma <<
1918 * and 500MHz <<
1919 * point hasn <<
1920 * IMX8MP_CLK <<
1921 */ <<
1922 assigned-cloc <<
1923 <<
1924 <<
1925 <<
1926 <<
1927 <<
1928 assigned-cloc <<
1929 <<
1930 <<
1931 <<
1932 <<
1933 assigned-cloc <<
1934 <<
1935 <<
1936 #power-domain <<
1937 <<
1938 lvds_bridge: <<
1939 compa <<
1940 reg = <<
1941 reg-n <<
1942 clock <<
1943 clock <<
1944 assig <<
1945 assig <<
1946 statu <<
1947 <<
1948 ports <<
1949 <<
1950 <<
1951 <<
1952 <<
1953 <<
1954 <<
1955 <<
1956 <<
1957 <<
1958 <<
1959 <<
1960 <<
1961 <<
1962 <<
1963 <<
1964 <<
1965 <<
1966 <<
1967 <<
1968 <<
1969 <<
1970 <<
1971 <<
1972 <<
1973 }; <<
1974 }; <<
1975 }; <<
1976 <<
1977 pcie_phy: pcie-phy@32 <<
1978 compatible = <<
1979 reg = <0x32f0 <<
1980 resets = <&sr <<
1981 <&sr <<
1982 reset-names = <<
1983 power-domains <<
1984 #phy-cells = <<
1985 status = "dis <<
1986 }; <<
1987 <<
1988 hsio_blk_ctrl: blk-ct <<
1989 compatible = <<
1990 reg = <0x32f1 <<
1991 clocks = <&cl <<
1992 <&cl <<
1993 clock-names = <<
1994 power-domains <<
1995 <<
1996 <<
1997 power-domain- <<
1998 <<
1999 interconnects <<
2000 <<
2001 <<
2002 <<
2003 interconnect- <<
2004 #power-domain <<
2005 #clock-cells <<
2006 }; <<
2007 <<
2008 hdmi_blk_ctrl: blk-ct <<
2009 compatible = <<
2010 reg = <0x32fc <<
2011 clocks = <&cl <<
2012 <&cl <<
2013 <&cl <<
2014 <&cl <<
2015 <&cl <<
2016 clock-names = <<
2017 power-domains <<
2018 <<
2019 <<
2020 <<
2021 <<
2022 power-domain- <<
2023 <<
2024 <<
2025 <<
2026 #power-domain <<
2027 }; <<
2028 <<
2029 irqsteer_hdmi: interr <<
2030 compatible = <<
2031 reg = <0x32fc <<
2032 interrupts = <<
2033 interrupt-con <<
2034 #interrupt-ce <<
2035 fsl,channel = <<
2036 fsl,num-irqs <<
2037 clocks = <&cl <<
2038 clock-names = <<
2039 power-domains <<
2040 }; <<
2041 <<
2042 hdmi_pvi: display-bri <<
2043 compatible = <<
2044 reg = <0x32fc <<
2045 interrupt-par <<
2046 interrupts = <<
2047 power-domains <<
2048 status = "dis <<
2049 <<
2050 ports { <<
2051 #addr <<
2052 #size <<
2053 <<
2054 port@ <<
2055 <<
2056 <<
2057 <<
2058 <<
2059 }; <<
2060 <<
2061 port@ <<
2062 <<
2063 <<
2064 <<
2065 <<
2066 }; <<
2067 }; <<
2068 }; <<
2069 <<
2070 lcdif3: display-contr <<
2071 compatible = <<
2072 reg = <0x32fc <<
2073 interrupt-par <<
2074 interrupts = <<
2075 clocks = <&hd <<
2076 <&cl <<
2077 <&cl <<
2078 clock-names = <<
2079 power-domains <<
2080 status = "dis <<
2081 <<
2082 port { <<
2083 lcdif <<
2084 <<
2085 }; <<
2086 }; <<
2087 }; <<
2088 <<
2089 hdmi_tx: hdmi@32fd800 <<
2090 compatible = <<
2091 reg = <0x32fd <<
2092 interrupt-par <<
2093 interrupts = <<
2094 clocks = <&cl <<
2095 <&cl <<
2096 <&cl <<
2097 <&hd <<
2098 clock-names = <<
2099 assigned-cloc <<
2100 assigned-cloc <<
2101 power-domains <<
2102 reg-io-width <<
2103 status = "dis <<
2104 <<
2105 ports { <<
2106 #addr <<
2107 #size <<
2108 <<
2109 port@ <<
2110 <<
2111 <<
2112 <<
2113 <<
2114 <<
2115 }; <<
2116 <<
2117 port@ <<
2118 <<
2119 <<
2120 }; <<
2121 }; <<
2122 }; <<
2123 <<
2124 hdmi_tx_phy: phy@32fd <<
2125 compatible = <<
2126 reg = <0x32fd <<
2127 clocks = <&cl <<
2128 <&cl <<
2129 clock-names = <<
2130 assigned-cloc <<
2131 assigned-cloc <<
2132 power-domains <<
2133 #clock-cells <<
2134 #phy-cells = <<
2135 status = "dis <<
2136 }; <<
2137 }; <<
2138 <<
2139 pcie: pcie@33800000 { <<
2140 compatible = "fsl,imx <<
2141 reg = <0x33800000 0x4 <<
2142 reg-names = "dbi", "c <<
2143 clocks = <&clk IMX8MP <<
2144 <&clk IMX8MP <<
2145 <&clk IMX8MP <<
2146 clock-names = "pcie", <<
2147 assigned-clocks = <&c <<
2148 assigned-clock-rates <<
2149 assigned-clock-parent <<
2150 #address-cells = <3>; <<
2151 #size-cells = <2>; <<
2152 device_type = "pci"; <<
2153 bus-range = <0x00 0xf <<
2154 ranges = <0x81000000 <<
2155 <0x82000000 <<
2156 num-lanes = <1>; <<
2157 num-viewport = <4>; <<
2158 interrupts = <GIC_SPI <<
2159 interrupt-names = "ms <<
2160 #interrupt-cells = <1 <<
2161 interrupt-map-mask = <<
2162 interrupt-map = <0 0 <<
2163 <0 0 <<
2164 <0 0 <<
2165 <0 0 <<
2166 fsl,max-link-speed = <<
2167 linux,pci-domain = <0 <<
2168 power-domains = <&hsi <<
2169 resets = <&src IMX8MP <<
2170 <&src IMX8MP <<
2171 reset-names = "apps", <<
2172 phys = <&pcie_phy>; <<
2173 phy-names = "pcie-phy <<
2174 status = "disabled"; <<
2175 }; <<
2176 <<
2177 pcie_ep: pcie-ep@33800000 { <<
2178 compatible = "fsl,imx <<
2179 reg = <0x33800000 0x0 <<
2180 reg-names = "dbi", "a <<
2181 clocks = <&clk IMX8MP <<
2182 <&clk IMX8MP <<
2183 <&clk IMX8MP <<
2184 clock-names = "pcie", <<
2185 assigned-clocks = <&c <<
2186 assigned-clock-rates <<
2187 assigned-clock-parent <<
2188 num-lanes = <1>; <<
2189 interrupts = <GIC_SPI <<
2190 interrupt-names = "dm <<
2191 fsl,max-link-speed = <<
2192 power-domains = <&hsi <<
2193 resets = <&src IMX8MP <<
2194 <&src IMX8MP <<
2195 reset-names = "apps", <<
2196 phys = <&pcie_phy>; <<
2197 phy-names = "pcie-phy <<
2198 num-ib-windows = <4>; <<
2199 num-ob-windows = <4>; <<
2200 status = "disabled"; <<
2201 }; <<
2202 <<
2203 gpu3d: gpu@38000000 { <<
2204 compatible = "vivante <<
2205 reg = <0x38000000 0x8 <<
2206 interrupts = <GIC_SPI <<
2207 clocks = <&clk IMX8MP <<
2208 <&clk IMX8MP <<
2209 <&clk IMX8MP <<
2210 <&clk IMX8MP <<
2211 clock-names = "core", <<
2212 assigned-clocks = <&c <<
2213 <&c <<
2214 assigned-clock-parent <<
2215 <<
2216 assigned-clock-rates <<
2217 power-domains = <&pgc <<
2218 }; <<
2219 <<
2220 gpu2d: gpu@38008000 { <<
2221 compatible = "vivante <<
2222 reg = <0x38008000 0x8 <<
2223 interrupts = <GIC_SPI <<
2224 clocks = <&clk IMX8MP <<
2225 <&clk IMX8MP <<
2226 <&clk IMX8MP <<
2227 clock-names = "core", <<
2228 assigned-clocks = <&c <<
2229 assigned-clock-parent <<
2230 assigned-clock-rates <<
2231 power-domains = <&pgc <<
2232 }; <<
2233 <<
2234 vpu_g1: video-codec@38300000 <<
2235 compatible = "nxp,imx <<
2236 reg = <0x38300000 0x1 <<
2237 interrupts = <GIC_SPI <<
2238 clocks = <&clk IMX8MP <<
2239 assigned-clocks = <&c <<
2240 assigned-clock-parent <<
2241 assigned-clock-rates <<
2242 power-domains = <&vpu <<
2243 }; <<
2244 <<
2245 vpu_g2: video-codec@38310000 <<
2246 compatible = "nxp,imx <<
2247 reg = <0x38310000 0x1 <<
2248 interrupts = <GIC_SPI <<
2249 clocks = <&clk IMX8MP <<
2250 assigned-clocks = <&c <<
2251 assigned-clock-parent <<
2252 assigned-clock-rates <<
2253 power-domains = <&vpu <<
2254 }; <<
2255 <<
2256 vpumix_blk_ctrl: blk-ctrl@383 <<
2257 compatible = "fsl,imx <<
2258 reg = <0x38330000 0x1 <<
2259 #power-domain-cells = <<
2260 power-domains = <&pgc <<
2261 <&pgc <<
2262 power-domain-names = <<
2263 clocks = <&clk IMX8MP <<
2264 <&clk IMX8MP <<
2265 <&clk IMX8MP <<
2266 clock-names = "g1", " <<
2267 assigned-clocks = <&c <<
2268 assigned-clock-parent <<
2269 assigned-clock-rates <<
2270 interconnects = <&noc <<
2271 <&noc <<
2272 <&noc <<
2273 interconnect-names = <<
2274 }; <<
2275 <<
2276 npu: npu@38500000 { <<
2277 compatible = "vivante <<
2278 reg = <0x38500000 0x2 <<
2279 interrupts = <GIC_SPI <<
2280 clocks = <&clk IMX8MP <<
2281 <&clk IMX8MP <<
2282 <&clk IMX8MP <<
2283 <&clk IMX8MP <<
2284 clock-names = "core", <<
2285 power-domains = <&pgc <<
2286 }; <<
2287 <<
2288 gic: interrupt-controller@388 895 gic: interrupt-controller@38800000 {
2289 compatible = "arm,gic 896 compatible = "arm,gic-v3";
2290 reg = <0x38800000 0x1 897 reg = <0x38800000 0x10000>,
2291 <0x38880000 0xc 898 <0x38880000 0xc0000>;
2292 #interrupt-cells = <3 899 #interrupt-cells = <3>;
2293 interrupt-controller; 900 interrupt-controller;
2294 interrupts = <GIC_PPI 901 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2295 interrupt-parent = <& 902 interrupt-parent = <&gic>;
2296 }; 903 };
2297 904
2298 edacmc: memory-controller@3d4 <<
2299 compatible = "snps,dd <<
2300 reg = <0x3d400000 0x4 <<
2301 interrupts = <GIC_SPI <<
2302 }; <<
2303 <<
2304 ddr-pmu@3d800000 { 905 ddr-pmu@3d800000 {
2305 compatible = "fsl,imx 906 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2306 reg = <0x3d800000 0x4 907 reg = <0x3d800000 0x400000>;
2307 interrupts = <GIC_SPI 908 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2308 }; 909 };
2309 910
2310 usb3_phy0: usb-phy@381f0040 { 911 usb3_phy0: usb-phy@381f0040 {
2311 compatible = "fsl,imx 912 compatible = "fsl,imx8mp-usb-phy";
2312 reg = <0x381f0040 0x4 913 reg = <0x381f0040 0x40>;
2313 clocks = <&clk IMX8MP 914 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2314 clock-names = "phy"; 915 clock-names = "phy";
2315 assigned-clocks = <&c 916 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2316 assigned-clock-parent 917 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2317 power-domains = <&hsi <<
2318 #phy-cells = <0>; 918 #phy-cells = <0>;
2319 status = "disabled"; 919 status = "disabled";
2320 }; 920 };
2321 921
2322 usb3_0: usb@32f10100 { 922 usb3_0: usb@32f10100 {
2323 compatible = "fsl,imx 923 compatible = "fsl,imx8mp-dwc3";
2324 reg = <0x32f10100 0x8 924 reg = <0x32f10100 0x8>,
2325 <0x381f0000 0x2 925 <0x381f0000 0x20>;
2326 clocks = <&clk IMX8MP 926 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2327 <&clk IMX8MP !! 927 <&clk IMX8MP_CLK_USB_ROOT>;
2328 clock-names = "hsio", 928 clock-names = "hsio", "suspend";
2329 interrupts = <GIC_SPI 929 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&hsi <<
2331 #address-cells = <1>; 930 #address-cells = <1>;
2332 #size-cells = <1>; 931 #size-cells = <1>;
2333 dma-ranges = <0x40000 932 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2334 ranges; 933 ranges;
2335 status = "disabled"; 934 status = "disabled";
2336 935
2337 usb_dwc3_0: usb@38100 936 usb_dwc3_0: usb@38100000 {
2338 compatible = 937 compatible = "snps,dwc3";
2339 reg = <0x3810 938 reg = <0x38100000 0x10000>;
2340 clocks = <&cl !! 939 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
2341 <&cl 940 <&clk IMX8MP_CLK_USB_CORE_REF>,
2342 <&cl !! 941 <&clk IMX8MP_CLK_USB_ROOT>;
2343 clock-names = 942 clock-names = "bus_early", "ref", "suspend";
>> 943 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
>> 944 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
>> 945 assigned-clock-rates = <500000000>;
2344 interrupts = 946 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
2345 phys = <&usb3 947 phys = <&usb3_phy0>, <&usb3_phy0>;
2346 phy-names = " 948 phy-names = "usb2-phy", "usb3-phy";
2347 snps,gfladj-r !! 949 snps,dis-u2-freeclk-exists-quirk;
2348 snps,parkmode <<
2349 }; 950 };
2350 951
2351 }; 952 };
2352 953
2353 usb3_phy1: usb-phy@382f0040 { 954 usb3_phy1: usb-phy@382f0040 {
2354 compatible = "fsl,imx 955 compatible = "fsl,imx8mp-usb-phy";
2355 reg = <0x382f0040 0x4 956 reg = <0x382f0040 0x40>;
2356 clocks = <&clk IMX8MP 957 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2357 clock-names = "phy"; 958 clock-names = "phy";
2358 assigned-clocks = <&c 959 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2359 assigned-clock-parent 960 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2360 power-domains = <&hsi <<
2361 #phy-cells = <0>; 961 #phy-cells = <0>;
2362 status = "disabled"; 962 status = "disabled";
2363 }; 963 };
2364 964
2365 usb3_1: usb@32f10108 { 965 usb3_1: usb@32f10108 {
2366 compatible = "fsl,imx 966 compatible = "fsl,imx8mp-dwc3";
2367 reg = <0x32f10108 0x8 967 reg = <0x32f10108 0x8>,
2368 <0x382f0000 0x2 968 <0x382f0000 0x20>;
2369 clocks = <&clk IMX8MP 969 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2370 <&clk IMX8MP !! 970 <&clk IMX8MP_CLK_USB_ROOT>;
2371 clock-names = "hsio", 971 clock-names = "hsio", "suspend";
2372 interrupts = <GIC_SPI 972 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2373 power-domains = <&hsi <<
2374 #address-cells = <1>; 973 #address-cells = <1>;
2375 #size-cells = <1>; 974 #size-cells = <1>;
2376 dma-ranges = <0x40000 975 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2377 ranges; 976 ranges;
2378 status = "disabled"; 977 status = "disabled";
2379 978
2380 usb_dwc3_1: usb@38200 979 usb_dwc3_1: usb@38200000 {
2381 compatible = 980 compatible = "snps,dwc3";
2382 reg = <0x3820 981 reg = <0x38200000 0x10000>;
2383 clocks = <&cl !! 982 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
2384 <&cl 983 <&clk IMX8MP_CLK_USB_CORE_REF>,
2385 <&cl !! 984 <&clk IMX8MP_CLK_USB_ROOT>;
2386 clock-names = 985 clock-names = "bus_early", "ref", "suspend";
>> 986 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
>> 987 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
>> 988 assigned-clock-rates = <500000000>;
2387 interrupts = 989 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
2388 phys = <&usb3 990 phys = <&usb3_phy1>, <&usb3_phy1>;
2389 phy-names = " 991 phy-names = "usb2-phy", "usb3-phy";
2390 snps,gfladj-r !! 992 snps,dis-u2-freeclk-exists-quirk;
2391 snps,parkmode <<
2392 }; 993 };
2393 }; 994 };
2394 995
2395 dsp: dsp@3b6e8000 { 996 dsp: dsp@3b6e8000 {
2396 compatible = "fsl,imx 997 compatible = "fsl,imx8mp-dsp";
2397 reg = <0x3b6e8000 0x8 998 reg = <0x3b6e8000 0x88000>;
2398 mbox-names = "txdb0", 999 mbox-names = "txdb0", "txdb1",
2399 "rxdb0", "rxd 1000 "rxdb0", "rxdb1";
2400 mboxes = <&mu2 2 0>, 1001 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2401 <&mu2 3 0>, < 1002 <&mu2 3 0>, <&mu2 3 1>;
2402 memory-region = <&dsp 1003 memory-region = <&dsp_reserved>;
2403 status = "disabled"; 1004 status = "disabled";
2404 }; 1005 };
2405 }; 1006 };
2406 }; 1007 };
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