1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mp-clock.h> 6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h> 7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h> <<
9 #include <dt-bindings/gpio/gpio.h> 8 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h> 9 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp. <<
12 #include <dt-bindings/interrupt-controller/arm 10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h> 11 #include <dt-bindings/thermal/thermal.h>
14 12
15 #include "imx8mp-pinfunc.h" 13 #include "imx8mp-pinfunc.h"
16 14
17 / { 15 / {
18 interrupt-parent = <&gic>; 16 interrupt-parent = <&gic>;
19 #address-cells = <2>; 17 #address-cells = <2>;
20 #size-cells = <2>; 18 #size-cells = <2>;
21 19
22 aliases { 20 aliases {
23 ethernet0 = &fec; 21 ethernet0 = &fec;
24 ethernet1 = &eqos; 22 ethernet1 = &eqos;
25 gpio0 = &gpio1; 23 gpio0 = &gpio1;
26 gpio1 = &gpio2; 24 gpio1 = &gpio2;
27 gpio2 = &gpio3; 25 gpio2 = &gpio3;
28 gpio3 = &gpio4; 26 gpio3 = &gpio4;
29 gpio4 = &gpio5; 27 gpio4 = &gpio5;
30 i2c0 = &i2c1; 28 i2c0 = &i2c1;
31 i2c1 = &i2c2; 29 i2c1 = &i2c2;
32 i2c2 = &i2c3; 30 i2c2 = &i2c3;
33 i2c3 = &i2c4; 31 i2c3 = &i2c4;
34 i2c4 = &i2c5; 32 i2c4 = &i2c5;
35 i2c5 = &i2c6; 33 i2c5 = &i2c6;
36 mmc0 = &usdhc1; 34 mmc0 = &usdhc1;
37 mmc1 = &usdhc2; 35 mmc1 = &usdhc2;
38 mmc2 = &usdhc3; 36 mmc2 = &usdhc3;
39 serial0 = &uart1; 37 serial0 = &uart1;
40 serial1 = &uart2; 38 serial1 = &uart2;
41 serial2 = &uart3; 39 serial2 = &uart3;
42 serial3 = &uart4; 40 serial3 = &uart4;
43 spi0 = &flexspi; 41 spi0 = &flexspi;
44 }; 42 };
45 43
46 cpus { 44 cpus {
47 #address-cells = <1>; 45 #address-cells = <1>;
48 #size-cells = <0>; 46 #size-cells = <0>;
49 47
50 A53_0: cpu@0 { 48 A53_0: cpu@0 {
51 device_type = "cpu"; 49 device_type = "cpu";
52 compatible = "arm,cort 50 compatible = "arm,cortex-a53";
53 reg = <0x0>; 51 reg = <0x0>;
54 clock-latency = <61036 52 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_ 53 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci" 54 enable-method = "psci";
57 i-cache-size = <0x8000 55 i-cache-size = <0x8000>;
58 i-cache-line-size = <6 56 i-cache-line-size = <64>;
59 i-cache-sets = <256>; 57 i-cache-sets = <256>;
60 d-cache-size = <0x8000 58 d-cache-size = <0x8000>;
61 d-cache-line-size = <6 59 d-cache-line-size = <64>;
62 d-cache-sets = <128>; 60 d-cache-sets = <128>;
63 next-level-cache = <&A 61 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_sp 62 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "sp 63 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = 64 operating-points-v2 = <&a53_opp_table>;
67 #cooling-cells = <2>; 65 #cooling-cells = <2>;
68 }; 66 };
69 67
70 A53_1: cpu@1 { 68 A53_1: cpu@1 {
71 device_type = "cpu"; 69 device_type = "cpu";
72 compatible = "arm,cort 70 compatible = "arm,cortex-a53";
73 reg = <0x1>; 71 reg = <0x1>;
74 clock-latency = <61036 72 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_ 73 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci" 74 enable-method = "psci";
77 i-cache-size = <0x8000 75 i-cache-size = <0x8000>;
78 i-cache-line-size = <6 76 i-cache-line-size = <64>;
79 i-cache-sets = <256>; 77 i-cache-sets = <256>;
80 d-cache-size = <0x8000 78 d-cache-size = <0x8000>;
81 d-cache-line-size = <6 79 d-cache-line-size = <64>;
82 d-cache-sets = <128>; 80 d-cache-sets = <128>;
83 next-level-cache = <&A 81 next-level-cache = <&A53_L2>;
84 operating-points-v2 = 82 operating-points-v2 = <&a53_opp_table>;
85 #cooling-cells = <2>; 83 #cooling-cells = <2>;
86 }; 84 };
87 85
88 A53_2: cpu@2 { 86 A53_2: cpu@2 {
89 device_type = "cpu"; 87 device_type = "cpu";
90 compatible = "arm,cort 88 compatible = "arm,cortex-a53";
91 reg = <0x2>; 89 reg = <0x2>;
92 clock-latency = <61036 90 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_ 91 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci" 92 enable-method = "psci";
95 i-cache-size = <0x8000 93 i-cache-size = <0x8000>;
96 i-cache-line-size = <6 94 i-cache-line-size = <64>;
97 i-cache-sets = <256>; 95 i-cache-sets = <256>;
98 d-cache-size = <0x8000 96 d-cache-size = <0x8000>;
99 d-cache-line-size = <6 97 d-cache-line-size = <64>;
100 d-cache-sets = <128>; 98 d-cache-sets = <128>;
101 next-level-cache = <&A 99 next-level-cache = <&A53_L2>;
102 operating-points-v2 = 100 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>; 101 #cooling-cells = <2>;
104 }; 102 };
105 103
106 A53_3: cpu@3 { 104 A53_3: cpu@3 {
107 device_type = "cpu"; 105 device_type = "cpu";
108 compatible = "arm,cort 106 compatible = "arm,cortex-a53";
109 reg = <0x3>; 107 reg = <0x3>;
110 clock-latency = <61036 108 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_ 109 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci" 110 enable-method = "psci";
113 i-cache-size = <0x8000 111 i-cache-size = <0x8000>;
114 i-cache-line-size = <6 112 i-cache-line-size = <64>;
115 i-cache-sets = <256>; 113 i-cache-sets = <256>;
116 d-cache-size = <0x8000 114 d-cache-size = <0x8000>;
117 d-cache-line-size = <6 115 d-cache-line-size = <64>;
118 d-cache-sets = <128>; 116 d-cache-sets = <128>;
119 next-level-cache = <&A 117 next-level-cache = <&A53_L2>;
120 operating-points-v2 = 118 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>; 119 #cooling-cells = <2>;
122 }; 120 };
123 121
124 A53_L2: l2-cache0 { 122 A53_L2: l2-cache0 {
125 compatible = "cache"; 123 compatible = "cache";
126 cache-unified; <<
127 cache-level = <2>; 124 cache-level = <2>;
128 cache-size = <0x80000> 125 cache-size = <0x80000>;
129 cache-line-size = <64> 126 cache-line-size = <64>;
130 cache-sets = <512>; 127 cache-sets = <512>;
131 }; 128 };
132 }; 129 };
133 130
134 a53_opp_table: opp-table { 131 a53_opp_table: opp-table {
135 compatible = "operating-points 132 compatible = "operating-points-v2";
136 opp-shared; 133 opp-shared;
137 134
138 opp-1200000000 { 135 opp-1200000000 {
139 opp-hz = /bits/ 64 <12 136 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <85000 137 opp-microvolt = <850000>;
141 opp-supported-hw = <0x 138 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <15 139 clock-latency-ns = <150000>;
143 opp-suspend; 140 opp-suspend;
144 }; 141 };
145 142
146 opp-1600000000 { 143 opp-1600000000 {
147 opp-hz = /bits/ 64 <16 144 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <95000 145 opp-microvolt = <950000>;
149 opp-supported-hw = <0x 146 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <15 147 clock-latency-ns = <150000>;
151 opp-suspend; 148 opp-suspend;
152 }; 149 };
153 150
154 opp-1800000000 { 151 opp-1800000000 {
155 opp-hz = /bits/ 64 <18 152 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <10000 153 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x 154 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <15 155 clock-latency-ns = <150000>;
159 opp-suspend; 156 opp-suspend;
160 }; 157 };
161 }; 158 };
162 159
163 osc_32k: clock-osc-32k { 160 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock"; 161 compatible = "fixed-clock";
165 #clock-cells = <0>; 162 #clock-cells = <0>;
166 clock-frequency = <32768>; 163 clock-frequency = <32768>;
167 clock-output-names = "osc_32k" 164 clock-output-names = "osc_32k";
168 }; 165 };
169 166
170 osc_24m: clock-osc-24m { 167 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock"; 168 compatible = "fixed-clock";
172 #clock-cells = <0>; 169 #clock-cells = <0>;
173 clock-frequency = <24000000>; 170 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m" 171 clock-output-names = "osc_24m";
175 }; 172 };
176 173
177 clk_ext1: clock-ext1 { 174 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock"; 175 compatible = "fixed-clock";
179 #clock-cells = <0>; 176 #clock-cells = <0>;
180 clock-frequency = <133000000>; 177 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1 178 clock-output-names = "clk_ext1";
182 }; 179 };
183 180
184 clk_ext2: clock-ext2 { 181 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock"; 182 compatible = "fixed-clock";
186 #clock-cells = <0>; 183 #clock-cells = <0>;
187 clock-frequency = <133000000>; 184 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2 185 clock-output-names = "clk_ext2";
189 }; 186 };
190 187
191 clk_ext3: clock-ext3 { 188 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock"; 189 compatible = "fixed-clock";
193 #clock-cells = <0>; 190 #clock-cells = <0>;
194 clock-frequency = <133000000>; 191 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3 192 clock-output-names = "clk_ext3";
196 }; 193 };
197 194
198 clk_ext4: clock-ext4 { 195 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock"; 196 compatible = "fixed-clock";
200 #clock-cells = <0>; 197 #clock-cells = <0>;
201 clock-frequency = <133000000>; 198 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext4 199 clock-output-names = "clk_ext4";
203 }; 200 };
204 201
205 funnel { <<
206 /* <<
207 * non-configurable funnel don <<
208 * bus. As such no need to ad <<
209 */ <<
210 compatible = "arm,coresight-st <<
211 <<
212 in-ports { <<
213 #address-cells = <1>; <<
214 #size-cells = <0>; <<
215 <<
216 port@0 { <<
217 reg = <0>; <<
218 <<
219 ca_funnel_in_p <<
220 remote <<
221 }; <<
222 }; <<
223 <<
224 port@1 { <<
225 reg = <1>; <<
226 <<
227 ca_funnel_in_p <<
228 remote <<
229 }; <<
230 }; <<
231 <<
232 port@2 { <<
233 reg = <2>; <<
234 <<
235 ca_funnel_in_p <<
236 remote <<
237 }; <<
238 }; <<
239 <<
240 port@3 { <<
241 reg = <3>; <<
242 <<
243 ca_fun <<
244 remote <<
245 }; <<
246 }; <<
247 }; <<
248 <<
249 out-ports { <<
250 port { <<
251 <<
252 ca_funnel_out_ <<
253 remote <<
254 }; <<
255 }; <<
256 }; <<
257 }; <<
258 <<
259 reserved-memory { 202 reserved-memory {
260 #address-cells = <2>; 203 #address-cells = <2>;
261 #size-cells = <2>; 204 #size-cells = <2>;
262 ranges; 205 ranges;
263 206
264 dsp_reserved: dsp@92400000 { 207 dsp_reserved: dsp@92400000 {
265 reg = <0 0x92400000 0 208 reg = <0 0x92400000 0 0x2000000>;
266 no-map; 209 no-map;
267 status = "disabled"; <<
268 }; 210 };
269 }; 211 };
270 212
271 pmu { 213 pmu {
272 compatible = "arm,cortex-a53-p 214 compatible = "arm,cortex-a53-pmu";
273 interrupts = <GIC_PPI 7 215 interrupts = <GIC_PPI 7
274 (GIC_CPU_MASK_SIM 216 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
275 }; 217 };
276 218
277 psci { 219 psci {
278 compatible = "arm,psci-1.0"; 220 compatible = "arm,psci-1.0";
279 method = "smc"; 221 method = "smc";
280 }; 222 };
281 223
282 thermal-zones { 224 thermal-zones {
283 cpu-thermal { 225 cpu-thermal {
284 polling-delay-passive 226 polling-delay-passive = <250>;
285 polling-delay = <2000> 227 polling-delay = <2000>;
286 thermal-sensors = <&tm 228 thermal-sensors = <&tmu 0>;
287 trips { 229 trips {
288 cpu_alert0: tr 230 cpu_alert0: trip0 {
289 temper 231 temperature = <85000>;
290 hyster 232 hysteresis = <2000>;
291 type = 233 type = "passive";
292 }; 234 };
293 235
294 cpu_crit0: tri 236 cpu_crit0: trip1 {
295 temper 237 temperature = <95000>;
296 hyster 238 hysteresis = <2000>;
297 type = 239 type = "critical";
298 }; 240 };
299 }; 241 };
300 242
301 cooling-maps { 243 cooling-maps {
302 map0 { 244 map0 {
303 trip = 245 trip = <&cpu_alert0>;
304 coolin 246 cooling-device =
305 247 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
306 248 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
307 249 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
308 250 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
309 }; 251 };
310 }; 252 };
311 }; 253 };
312 254
313 soc-thermal { 255 soc-thermal {
314 polling-delay-passive 256 polling-delay-passive = <250>;
315 polling-delay = <2000> 257 polling-delay = <2000>;
316 thermal-sensors = <&tm 258 thermal-sensors = <&tmu 1>;
317 trips { 259 trips {
318 soc_alert0: tr 260 soc_alert0: trip0 {
319 temper 261 temperature = <85000>;
320 hyster 262 hysteresis = <2000>;
321 type = 263 type = "passive";
322 }; 264 };
323 265
324 soc_crit0: tri 266 soc_crit0: trip1 {
325 temper 267 temperature = <95000>;
326 hyster 268 hysteresis = <2000>;
327 type = 269 type = "critical";
328 }; 270 };
329 }; 271 };
330 272
331 cooling-maps { 273 cooling-maps {
332 map0 { 274 map0 {
333 trip = 275 trip = <&soc_alert0>;
334 coolin 276 cooling-device =
335 277 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
336 278 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
337 279 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
338 280 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 }; 281 };
340 }; 282 };
341 }; 283 };
342 }; 284 };
343 285
344 timer { 286 timer {
345 compatible = "arm,armv8-timer" 287 compatible = "arm,armv8-timer";
346 interrupts = <GIC_PPI 13 (GIC_ 288 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
347 <GIC_PPI 14 (GIC_ 289 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
348 <GIC_PPI 11 (GIC_ 290 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
349 <GIC_PPI 10 (GIC_ 291 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
350 clock-frequency = <8000000>; 292 clock-frequency = <8000000>;
351 arm,no-tick-in-suspend; 293 arm,no-tick-in-suspend;
352 }; 294 };
353 295
354 soc: soc@0 { 296 soc: soc@0 {
355 compatible = "fsl,imx8mp-soc", 297 compatible = "fsl,imx8mp-soc", "simple-bus";
356 #address-cells = <1>; 298 #address-cells = <1>;
357 #size-cells = <1>; 299 #size-cells = <1>;
358 ranges = <0x0 0x0 0x0 0x3e0000 300 ranges = <0x0 0x0 0x0 0x3e000000>;
359 nvmem-cells = <&imx8mp_uid>; 301 nvmem-cells = <&imx8mp_uid>;
360 nvmem-cell-names = "soc_unique 302 nvmem-cell-names = "soc_unique_id";
361 303
362 etm0: etm@28440000 { <<
363 compatible = "arm,core <<
364 reg = <0x28440000 0x10 <<
365 cpu = <&A53_0>; <<
366 clocks = <&clk IMX8MP_ <<
367 clock-names = "apb_pcl <<
368 <<
369 out-ports { <<
370 port { <<
371 etm0_o <<
372 <<
373 }; <<
374 }; <<
375 }; <<
376 }; <<
377 <<
378 etm1: etm@28540000 { <<
379 compatible = "arm,core <<
380 reg = <0x28540000 0x10 <<
381 cpu = <&A53_1>; <<
382 clocks = <&clk IMX8MP_ <<
383 clock-names = "apb_pcl <<
384 <<
385 out-ports { <<
386 port { <<
387 etm1_o <<
388 <<
389 }; <<
390 }; <<
391 }; <<
392 }; <<
393 <<
394 etm2: etm@28640000 { <<
395 compatible = "arm,core <<
396 reg = <0x28640000 0x10 <<
397 cpu = <&A53_2>; <<
398 clocks = <&clk IMX8MP_ <<
399 clock-names = "apb_pcl <<
400 <<
401 out-ports { <<
402 port { <<
403 etm2_o <<
404 <<
405 }; <<
406 }; <<
407 }; <<
408 }; <<
409 <<
410 etm3: etm@28740000 { <<
411 compatible = "arm,core <<
412 reg = <0x28740000 0x10 <<
413 cpu = <&A53_3>; <<
414 clocks = <&clk IMX8MP_ <<
415 clock-names = "apb_pcl <<
416 <<
417 out-ports { <<
418 port { <<
419 etm3_o <<
420 <<
421 }; <<
422 }; <<
423 }; <<
424 }; <<
425 <<
426 funnel@28c03000 { <<
427 compatible = "arm,core <<
428 reg = <0x28c03000 0x10 <<
429 clocks = <&clk IMX8MP_ <<
430 clock-names = "apb_pcl <<
431 <<
432 in-ports { <<
433 #address-cells <<
434 #size-cells = <<
435 <<
436 port@0 { <<
437 reg = <<
438 <<
439 hugo_f <<
440 <<
441 }; <<
442 }; <<
443 <<
444 port@1 { <<
445 reg = <<
446 <<
447 hugo_f <<
448 /* M7 <<
449 }; <<
450 }; <<
451 <<
452 port@2 { <<
453 reg = <<
454 <<
455 hugo_f <<
456 /* DSP <<
457 }; <<
458 }; <<
459 /* the other i <<
460 }; <<
461 <<
462 out-ports { <<
463 port { <<
464 hugo_f <<
465 <<
466 }; <<
467 }; <<
468 }; <<
469 }; <<
470 <<
471 etf@28c04000 { <<
472 compatible = "arm,core <<
473 reg = <0x28c04000 0x10 <<
474 clocks = <&clk IMX8MP_ <<
475 clock-names = "apb_pcl <<
476 <<
477 in-ports { <<
478 port { <<
479 etf_in <<
480 <<
481 }; <<
482 }; <<
483 }; <<
484 <<
485 out-ports { <<
486 port { <<
487 etf_ou <<
488 <<
489 }; <<
490 }; <<
491 }; <<
492 }; <<
493 <<
494 etr@28c06000 { <<
495 compatible = "arm,core <<
496 reg = <0x28c06000 0x10 <<
497 clocks = <&clk IMX8MP_ <<
498 clock-names = "apb_pcl <<
499 <<
500 in-ports { <<
501 port { <<
502 etr_in <<
503 <<
504 }; <<
505 }; <<
506 }; <<
507 }; <<
508 <<
509 aips1: bus@30000000 { 304 aips1: bus@30000000 {
510 compatible = "fsl,aips 305 compatible = "fsl,aips-bus", "simple-bus";
511 reg = <0x30000000 0x40 306 reg = <0x30000000 0x400000>;
512 #address-cells = <1>; 307 #address-cells = <1>;
513 #size-cells = <1>; 308 #size-cells = <1>;
514 ranges; 309 ranges;
515 310
516 gpio1: gpio@30200000 { 311 gpio1: gpio@30200000 {
517 compatible = " 312 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
518 reg = <0x30200 313 reg = <0x30200000 0x10000>;
519 interrupts = < 314 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
520 < 315 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clk 316 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
522 gpio-controlle 317 gpio-controller;
523 #gpio-cells = 318 #gpio-cells = <2>;
524 interrupt-cont 319 interrupt-controller;
525 #interrupt-cel 320 #interrupt-cells = <2>;
526 gpio-ranges = 321 gpio-ranges = <&iomuxc 0 5 30>;
527 }; 322 };
528 323
529 gpio2: gpio@30210000 { 324 gpio2: gpio@30210000 {
530 compatible = " 325 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
531 reg = <0x30210 326 reg = <0x30210000 0x10000>;
532 interrupts = < 327 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
533 < 328 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clk 329 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
535 gpio-controlle 330 gpio-controller;
536 #gpio-cells = 331 #gpio-cells = <2>;
537 interrupt-cont 332 interrupt-controller;
538 #interrupt-cel 333 #interrupt-cells = <2>;
539 gpio-ranges = 334 gpio-ranges = <&iomuxc 0 35 21>;
540 }; 335 };
541 336
542 gpio3: gpio@30220000 { 337 gpio3: gpio@30220000 {
543 compatible = " 338 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
544 reg = <0x30220 339 reg = <0x30220000 0x10000>;
545 interrupts = < 340 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
546 < 341 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clk 342 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
548 gpio-controlle 343 gpio-controller;
549 #gpio-cells = 344 #gpio-cells = <2>;
550 interrupt-cont 345 interrupt-controller;
551 #interrupt-cel 346 #interrupt-cells = <2>;
552 gpio-ranges = 347 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
553 }; 348 };
554 349
555 gpio4: gpio@30230000 { 350 gpio4: gpio@30230000 {
556 compatible = " 351 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
557 reg = <0x30230 352 reg = <0x30230000 0x10000>;
558 interrupts = < 353 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
559 < 354 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clk 355 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
561 gpio-controlle 356 gpio-controller;
562 #gpio-cells = 357 #gpio-cells = <2>;
563 interrupt-cont 358 interrupt-controller;
564 #interrupt-cel 359 #interrupt-cells = <2>;
565 gpio-ranges = 360 gpio-ranges = <&iomuxc 0 82 32>;
566 }; 361 };
567 362
568 gpio5: gpio@30240000 { 363 gpio5: gpio@30240000 {
569 compatible = " 364 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
570 reg = <0x30240 365 reg = <0x30240000 0x10000>;
571 interrupts = < 366 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
572 < 367 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk 368 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
574 gpio-controlle 369 gpio-controller;
575 #gpio-cells = 370 #gpio-cells = <2>;
576 interrupt-cont 371 interrupt-controller;
577 #interrupt-cel 372 #interrupt-cells = <2>;
578 gpio-ranges = 373 gpio-ranges = <&iomuxc 0 114 30>;
579 }; 374 };
580 375
581 tmu: tmu@30260000 { 376 tmu: tmu@30260000 {
582 compatible = " 377 compatible = "fsl,imx8mp-tmu";
583 reg = <0x30260 378 reg = <0x30260000 0x10000>;
584 clocks = <&clk 379 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
585 nvmem-cells = <<
586 nvmem-cell-nam <<
587 #thermal-senso 380 #thermal-sensor-cells = <1>;
588 }; 381 };
589 382
590 wdog1: watchdog@302800 383 wdog1: watchdog@30280000 {
591 compatible = " 384 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
592 reg = <0x30280 385 reg = <0x30280000 0x10000>;
593 interrupts = < 386 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clk 387 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
595 status = "disa 388 status = "disabled";
596 }; 389 };
597 390
598 wdog2: watchdog@302900 391 wdog2: watchdog@30290000 {
599 compatible = " 392 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
600 reg = <0x30290 393 reg = <0x30290000 0x10000>;
601 interrupts = < 394 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk 395 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
603 status = "disa 396 status = "disabled";
604 }; 397 };
605 398
606 wdog3: watchdog@302a00 399 wdog3: watchdog@302a0000 {
607 compatible = " 400 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
608 reg = <0x302a0 401 reg = <0x302a0000 0x10000>;
609 interrupts = < 402 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clk 403 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
611 status = "disa 404 status = "disabled";
612 }; 405 };
613 406
614 gpt1: timer@302d0000 { <<
615 compatible = " <<
616 reg = <0x302d0 <<
617 interrupts = < <<
618 clocks = <&clk <<
619 clock-names = <<
620 }; <<
621 <<
622 gpt2: timer@302e0000 { <<
623 compatible = " <<
624 reg = <0x302e0 <<
625 interrupts = < <<
626 clocks = <&clk <<
627 clock-names = <<
628 }; <<
629 <<
630 gpt3: timer@302f0000 { <<
631 compatible = " <<
632 reg = <0x302f0 <<
633 interrupts = < <<
634 clocks = <&clk <<
635 clock-names = <<
636 }; <<
637 <<
638 iomuxc: pinctrl@303300 407 iomuxc: pinctrl@30330000 {
639 compatible = " 408 compatible = "fsl,imx8mp-iomuxc";
640 reg = <0x30330 409 reg = <0x30330000 0x10000>;
641 }; 410 };
642 411
643 gpr: syscon@30340000 { !! 412 gpr: iomuxc-gpr@30340000 {
644 compatible = " 413 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
645 reg = <0x30340 414 reg = <0x30340000 0x10000>;
646 }; 415 };
647 416
648 ocotp: efuse@30350000 417 ocotp: efuse@30350000 {
649 compatible = " 418 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
650 reg = <0x30350 419 reg = <0x30350000 0x10000>;
651 clocks = <&clk 420 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
652 /* For nvmem s 421 /* For nvmem subnodes */
653 #address-cells 422 #address-cells = <1>;
654 #size-cells = 423 #size-cells = <1>;
655 424
656 /* !! 425 imx8mp_uid: unique-id@420 {
657 * The registe <<
658 * Fusemap Des <<
659 * Assuming <<
660 * reg = <AD <<
661 * then <<
662 * Fuse Addr <<
663 * Note that i <<
664 * each subseq <<
665 * +0x10 in Fu <<
666 * reg = <0x8 <<
667 * 0x430). <<
668 */ <<
669 imx8mp_uid: un <<
670 reg = 426 reg = <0x8 0x8>;
671 }; 427 };
672 428
673 cpu_speed_grad !! 429 cpu_speed_grade: speed-grade@10 {
674 reg = 430 reg = <0x10 4>;
675 }; 431 };
676 432
677 eth_mac1: mac- !! 433 eth_mac1: mac-address@90 {
678 reg = 434 reg = <0x90 6>;
679 }; 435 };
680 436
681 eth_mac2: mac- !! 437 eth_mac2: mac-address@96 {
682 reg = 438 reg = <0x96 6>;
683 }; 439 };
684 <<
685 tmu_calib: cal <<
686 reg = <<
687 }; <<
688 }; 440 };
689 441
690 anatop: clock-controll !! 442 anatop: anatop@30360000 {
691 compatible = " !! 443 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop",
>> 444 "syscon";
692 reg = <0x30360 445 reg = <0x30360000 0x10000>;
693 #clock-cells = <<
694 }; 446 };
695 447
696 snvs: snvs@30370000 { 448 snvs: snvs@30370000 {
697 compatible = " 449 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 reg = <0x30370 450 reg = <0x30370000 0x10000>;
699 451
700 snvs_rtc: snvs 452 snvs_rtc: snvs-rtc-lp {
701 compat 453 compatible = "fsl,sec-v4.0-mon-rtc-lp";
702 regmap !! 454 regmap =<&snvs>;
703 offset 455 offset = <0x34>;
704 interr 456 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
705 457 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
706 clocks 458 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
707 clock- 459 clock-names = "snvs-rtc";
708 }; 460 };
709 461
710 snvs_pwrkey: s 462 snvs_pwrkey: snvs-powerkey {
711 compat 463 compatible = "fsl,sec-v4.0-pwrkey";
712 regmap 464 regmap = <&snvs>;
713 interr 465 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
714 clocks 466 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
715 clock- 467 clock-names = "snvs-pwrkey";
716 linux, 468 linux,keycode = <KEY_POWER>;
717 wakeup 469 wakeup-source;
718 status 470 status = "disabled";
719 }; 471 };
720 <<
721 snvs_lpgpr: sn <<
722 compat <<
723 <<
724 }; <<
725 }; 472 };
726 473
727 clk: clock-controller@ 474 clk: clock-controller@30380000 {
728 compatible = " 475 compatible = "fsl,imx8mp-ccm";
729 reg = <0x30380 476 reg = <0x30380000 0x10000>;
730 interrupts = < <<
731 < <<
732 #clock-cells = 477 #clock-cells = <1>;
733 clocks = <&osc 478 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
734 <&clk 479 <&clk_ext3>, <&clk_ext4>;
735 clock-names = 480 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
736 481 "clk_ext3", "clk_ext4";
737 assigned-clock 482 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 483 <&clk IMX8MP_CLK_A53_CORE>,
739 484 <&clk IMX8MP_CLK_NOC>,
740 485 <&clk IMX8MP_CLK_NOC_IO>,
741 !! 486 <&clk IMX8MP_CLK_GIC>,
>> 487 <&clk IMX8MP_CLK_AUDIO_AHB>,
>> 488 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
>> 489 <&clk IMX8MP_AUDIO_PLL1>,
>> 490 <&clk IMX8MP_AUDIO_PLL2>;
742 assigned-clock 491 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 492 <&clk IMX8MP_ARM_PLL_OUT>,
744 493 <&clk IMX8MP_SYS_PLL2_1000M>,
745 494 <&clk IMX8MP_SYS_PLL1_800M>,
746 !! 495 <&clk IMX8MP_SYS_PLL2_500M>,
>> 496 <&clk IMX8MP_SYS_PLL1_800M>,
>> 497 <&clk IMX8MP_SYS_PLL1_800M>;
747 assigned-clock 498 assigned-clock-rates = <0>, <0>,
748 499 <1000000000>,
749 500 <800000000>,
750 !! 501 <500000000>,
>> 502 <400000000>,
>> 503 <800000000>,
>> 504 <393216000>,
>> 505 <361267200>;
751 }; 506 };
752 507
753 src: reset-controller@ 508 src: reset-controller@30390000 {
754 compatible = " 509 compatible = "fsl,imx8mp-src", "syscon";
755 reg = <0x30390 510 reg = <0x30390000 0x10000>;
756 interrupts = < 511 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
757 #reset-cells = 512 #reset-cells = <1>;
758 }; 513 };
759 514
760 gpc: gpc@303a0000 { 515 gpc: gpc@303a0000 {
761 compatible = " 516 compatible = "fsl,imx8mp-gpc";
762 reg = <0x303a0 517 reg = <0x303a0000 0x1000>;
763 interrupt-pare 518 interrupt-parent = <&gic>;
764 interrupts = < <<
765 interrupt-cont 519 interrupt-controller;
766 #interrupt-cel 520 #interrupt-cells = <3>;
767 521
768 pgc { 522 pgc {
769 #addre 523 #address-cells = <1>;
770 #size- 524 #size-cells = <0>;
771 525
772 pgc_mi 526 pgc_mipi_phy1: power-domain@0 {
773 527 #power-domain-cells = <0>;
774 528 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
775 }; 529 };
776 530
777 pgc_pc 531 pgc_pcie_phy: power-domain@1 {
778 532 #power-domain-cells = <0>;
779 533 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
780 }; 534 };
781 535
782 pgc_us 536 pgc_usb1_phy: power-domain@2 {
783 537 #power-domain-cells = <0>;
784 538 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
785 }; 539 };
786 540
787 pgc_us 541 pgc_usb2_phy: power-domain@3 {
788 542 #power-domain-cells = <0>;
789 543 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
790 }; 544 };
791 545
792 pgc_ml <<
793 <<
794 <<
795 <<
796 <<
797 <<
798 <<
799 <<
800 <<
801 <<
802 <<
803 <<
804 <<
805 <<
806 <<
807 }; <<
808 <<
809 pgc_au <<
810 <<
811 <<
812 <<
813 <<
814 <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 }; <<
821 <<
822 pgc_gp 546 pgc_gpu2d: power-domain@6 {
823 547 #power-domain-cells = <0>;
824 548 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
825 549 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
826 550 power-domains = <&pgc_gpumix>;
827 }; 551 };
828 552
829 pgc_gp 553 pgc_gpumix: power-domain@7 {
830 554 #power-domain-cells = <0>;
831 555 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
832 556 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
833 557 <&clk IMX8MP_CLK_GPU_AHB>;
834 558 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
835 559 <&clk IMX8MP_CLK_GPU_AHB>;
836 560 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
837 561 <&clk IMX8MP_SYS_PLL1_800M>;
838 562 assigned-clock-rates = <800000000>, <400000000>;
839 }; 563 };
840 564
841 pgc_vp <<
842 <<
843 <<
844 <<
845 }; <<
846 <<
847 pgc_gp 565 pgc_gpu3d: power-domain@9 {
848 566 #power-domain-cells = <0>;
849 567 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
850 568 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
851 569 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
852 570 power-domains = <&pgc_gpumix>;
853 }; 571 };
854 572
855 pgc_me 573 pgc_mediamix: power-domain@10 {
856 574 #power-domain-cells = <0>;
857 575 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
858 576 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
859 577 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
860 }; 578 };
861 579
862 pgc_vp <<
863 <<
864 <<
865 <<
866 <<
867 }; <<
868 <<
869 pgc_vp <<
870 <<
871 <<
872 <<
873 <<
874 <<
875 }; <<
876 <<
877 pgc_vp <<
878 <<
879 <<
880 <<
881 <<
882 }; <<
883 <<
884 pgc_hd <<
885 <<
886 <<
887 <<
888 <<
889 <<
890 <<
891 <<
892 <<
893 <<
894 }; <<
895 <<
896 pgc_hd <<
897 <<
898 <<
899 }; <<
900 <<
901 pgc_mi 580 pgc_mipi_phy2: power-domain@16 {
902 581 #power-domain-cells = <0>;
903 582 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
904 }; 583 };
905 584
906 pgc_hs !! 585 pgc_hsiomix: power-domains@17 {
907 586 #power-domain-cells = <0>;
908 587 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
909 588 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
910 589 <&clk IMX8MP_CLK_HSIO_ROOT>;
911 590 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
912 591 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
913 592 assigned-clock-rates = <500000000>;
914 }; 593 };
915 594
916 pgc_is 595 pgc_ispdwp: power-domain@18 {
917 596 #power-domain-cells = <0>;
918 597 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
919 598 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
920 }; 599 };
921 }; 600 };
922 }; 601 };
923 }; 602 };
924 603
925 aips2: bus@30400000 { 604 aips2: bus@30400000 {
926 compatible = "fsl,aips 605 compatible = "fsl,aips-bus", "simple-bus";
927 reg = <0x30400000 0x40 606 reg = <0x30400000 0x400000>;
928 #address-cells = <1>; 607 #address-cells = <1>;
929 #size-cells = <1>; 608 #size-cells = <1>;
930 ranges; 609 ranges;
931 610
932 pwm1: pwm@30660000 { 611 pwm1: pwm@30660000 {
933 compatible = " 612 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
934 reg = <0x30660 613 reg = <0x30660000 0x10000>;
935 interrupts = < 614 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clk 615 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
937 <&clk 616 <&clk IMX8MP_CLK_PWM1_ROOT>;
938 clock-names = 617 clock-names = "ipg", "per";
939 #pwm-cells = < 618 #pwm-cells = <3>;
940 status = "disa 619 status = "disabled";
941 }; 620 };
942 621
943 pwm2: pwm@30670000 { 622 pwm2: pwm@30670000 {
944 compatible = " 623 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
945 reg = <0x30670 624 reg = <0x30670000 0x10000>;
946 interrupts = < 625 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clk 626 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
948 <&clk 627 <&clk IMX8MP_CLK_PWM2_ROOT>;
949 clock-names = 628 clock-names = "ipg", "per";
950 #pwm-cells = < 629 #pwm-cells = <3>;
951 status = "disa 630 status = "disabled";
952 }; 631 };
953 632
954 pwm3: pwm@30680000 { 633 pwm3: pwm@30680000 {
955 compatible = " 634 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
956 reg = <0x30680 635 reg = <0x30680000 0x10000>;
957 interrupts = < 636 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clk 637 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
959 <&clk 638 <&clk IMX8MP_CLK_PWM3_ROOT>;
960 clock-names = 639 clock-names = "ipg", "per";
961 #pwm-cells = < 640 #pwm-cells = <3>;
962 status = "disa 641 status = "disabled";
963 }; 642 };
964 643
965 pwm4: pwm@30690000 { 644 pwm4: pwm@30690000 {
966 compatible = " 645 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
967 reg = <0x30690 646 reg = <0x30690000 0x10000>;
968 interrupts = < 647 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clk 648 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
970 <&clk 649 <&clk IMX8MP_CLK_PWM4_ROOT>;
971 clock-names = 650 clock-names = "ipg", "per";
972 #pwm-cells = < 651 #pwm-cells = <3>;
973 status = "disa 652 status = "disabled";
974 }; 653 };
975 654
976 system_counter: timer@ 655 system_counter: timer@306a0000 {
977 compatible = " 656 compatible = "nxp,sysctr-timer";
978 reg = <0x306a0 657 reg = <0x306a0000 0x20000>;
979 interrupts = < 658 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&osc 659 clocks = <&osc_24m>;
981 clock-names = 660 clock-names = "per";
982 }; 661 };
983 <<
984 gpt6: timer@306e0000 { <<
985 compatible = " <<
986 reg = <0x306e0 <<
987 interrupts = < <<
988 clocks = <&clk <<
989 clock-names = <<
990 }; <<
991 <<
992 gpt5: timer@306f0000 { <<
993 compatible = " <<
994 reg = <0x306f0 <<
995 interrupts = < <<
996 clocks = <&clk <<
997 clock-names = <<
998 }; <<
999 <<
1000 gpt4: timer@30700000 <<
1001 compatible = <<
1002 reg = <0x3070 <<
1003 interrupts = <<
1004 clocks = <&cl <<
1005 clock-names = <<
1006 }; <<
1007 }; 662 };
1008 663
1009 aips3: bus@30800000 { 664 aips3: bus@30800000 {
1010 compatible = "fsl,aip 665 compatible = "fsl,aips-bus", "simple-bus";
1011 reg = <0x30800000 0x4 666 reg = <0x30800000 0x400000>;
1012 #address-cells = <1>; 667 #address-cells = <1>;
1013 #size-cells = <1>; 668 #size-cells = <1>;
1014 ranges; 669 ranges;
1015 670
1016 spba-bus@30800000 { !! 671 ecspi1: spi@30820000 {
1017 compatible = <<
1018 reg = <0x3080 <<
1019 #address-cell 672 #address-cells = <1>;
1020 #size-cells = !! 673 #size-cells = <0>;
1021 ranges; !! 674 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1022 !! 675 reg = <0x30820000 0x10000>;
1023 ecspi1: spi@3 !! 676 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1024 #addr !! 677 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
1025 #size !! 678 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1026 compa !! 679 clock-names = "ipg", "per";
1027 reg = !! 680 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1028 inter !! 681 dma-names = "rx", "tx";
1029 clock !! 682 status = "disabled";
1030 !! 683 };
1031 clock <<
1032 assig <<
1033 assig <<
1034 assig <<
1035 dmas <<
1036 dma-n <<
1037 statu <<
1038 }; <<
1039 684
1040 ecspi2: spi@3 !! 685 ecspi2: spi@30830000 {
1041 #addr !! 686 #address-cells = <1>;
1042 #size !! 687 #size-cells = <0>;
1043 compa !! 688 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1044 reg = !! 689 reg = <0x30830000 0x10000>;
1045 inter !! 690 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1046 clock !! 691 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1047 !! 692 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1048 clock !! 693 clock-names = "ipg", "per";
1049 assig !! 694 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1050 assig !! 695 dma-names = "rx", "tx";
1051 assig !! 696 status = "disabled";
1052 dmas !! 697 };
1053 dma-n <<
1054 statu <<
1055 }; <<
1056 698
1057 ecspi3: spi@3 !! 699 ecspi3: spi@30840000 {
1058 #addr !! 700 #address-cells = <1>;
1059 #size !! 701 #size-cells = <0>;
1060 compa !! 702 compatible = "fsl,imx8mp-ecspi", "fsl,imx51-ecspi";
1061 reg = !! 703 reg = <0x30840000 0x10000>;
1062 inter !! 704 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1063 clock !! 705 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1064 !! 706 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1065 clock !! 707 clock-names = "ipg", "per";
1066 assig !! 708 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1067 assig !! 709 dma-names = "rx", "tx";
1068 assig !! 710 status = "disabled";
1069 dmas !! 711 };
1070 dma-n <<
1071 statu <<
1072 }; <<
1073 712
1074 uart1: serial !! 713 uart1: serial@30860000 {
1075 compa !! 714 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1076 reg = !! 715 reg = <0x30860000 0x10000>;
1077 inter !! 716 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1078 clock !! 717 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1079 !! 718 <&clk IMX8MP_CLK_UART1_ROOT>;
1080 clock !! 719 clock-names = "ipg", "per";
1081 dmas !! 720 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1082 dma-n !! 721 dma-names = "rx", "tx";
1083 statu !! 722 status = "disabled";
1084 }; !! 723 };
1085 724
1086 uart3: serial !! 725 uart3: serial@30880000 {
1087 compa !! 726 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1088 reg = !! 727 reg = <0x30880000 0x10000>;
1089 inter !! 728 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1090 clock !! 729 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1091 !! 730 <&clk IMX8MP_CLK_UART3_ROOT>;
1092 clock !! 731 clock-names = "ipg", "per";
1093 dmas !! 732 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1094 dma-n !! 733 dma-names = "rx", "tx";
1095 statu !! 734 status = "disabled";
1096 }; !! 735 };
1097 736
1098 uart2: serial !! 737 uart2: serial@30890000 {
1099 compa !! 738 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1100 reg = !! 739 reg = <0x30890000 0x10000>;
1101 inter !! 740 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1102 clock !! 741 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1103 !! 742 <&clk IMX8MP_CLK_UART2_ROOT>;
1104 clock !! 743 clock-names = "ipg", "per";
1105 dmas !! 744 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1106 dma-n !! 745 dma-names = "rx", "tx";
1107 statu !! 746 status = "disabled";
1108 }; !! 747 };
1109 748
1110 flexcan1: can !! 749 flexcan1: can@308c0000 {
1111 compa !! 750 compatible = "fsl,imx8mp-flexcan";
1112 reg = !! 751 reg = <0x308c0000 0x10000>;
1113 inter !! 752 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1114 clock !! 753 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1115 !! 754 <&clk IMX8MP_CLK_CAN1_ROOT>;
1116 clock !! 755 clock-names = "ipg", "per";
1117 assig !! 756 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1118 assig !! 757 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1119 assig !! 758 assigned-clock-rates = <40000000>;
1120 fsl,c !! 759 fsl,clk-source = /bits/ 8 <0>;
1121 fsl,s !! 760 fsl,stop-mode = <&gpr 0x10 4>;
1122 statu !! 761 status = "disabled";
1123 }; !! 762 };
1124 763
1125 flexcan2: can !! 764 flexcan2: can@308d0000 {
1126 compa !! 765 compatible = "fsl,imx8mp-flexcan";
1127 reg = !! 766 reg = <0x308d0000 0x10000>;
1128 inter !! 767 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1129 clock !! 768 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1130 !! 769 <&clk IMX8MP_CLK_CAN2_ROOT>;
1131 clock !! 770 clock-names = "ipg", "per";
1132 assig !! 771 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1133 assig !! 772 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1134 assig !! 773 assigned-clock-rates = <40000000>;
1135 fsl,c !! 774 fsl,clk-source = /bits/ 8 <0>;
1136 fsl,s !! 775 fsl,stop-mode = <&gpr 0x10 5>;
1137 statu !! 776 status = "disabled";
1138 }; <<
1139 }; 777 };
1140 778
1141 crypto: crypto@309000 779 crypto: crypto@30900000 {
1142 compatible = 780 compatible = "fsl,sec-v4.0";
1143 #address-cell 781 #address-cells = <1>;
1144 #size-cells = 782 #size-cells = <1>;
1145 reg = <0x3090 783 reg = <0x30900000 0x40000>;
1146 ranges = <0 0 784 ranges = <0 0x30900000 0x40000>;
1147 interrupts = 785 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&cl 786 clocks = <&clk IMX8MP_CLK_AHB>,
1149 <&cl 787 <&clk IMX8MP_CLK_IPG_ROOT>;
1150 clock-names = 788 clock-names = "aclk", "ipg";
1151 789
1152 sec_jr0: jr@1 790 sec_jr0: jr@1000 {
1153 compa 791 compatible = "fsl,sec-v4.0-job-ring";
1154 reg = 792 reg = <0x1000 0x1000>;
1155 inter 793 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1156 statu 794 status = "disabled";
1157 }; 795 };
1158 796
1159 sec_jr1: jr@2 797 sec_jr1: jr@2000 {
1160 compa 798 compatible = "fsl,sec-v4.0-job-ring";
1161 reg = 799 reg = <0x2000 0x1000>;
1162 inter 800 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1163 }; 801 };
1164 802
1165 sec_jr2: jr@3 803 sec_jr2: jr@3000 {
1166 compa 804 compatible = "fsl,sec-v4.0-job-ring";
1167 reg = 805 reg = <0x3000 0x1000>;
1168 inter 806 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1169 }; 807 };
1170 }; 808 };
1171 809
1172 i2c1: i2c@30a20000 { 810 i2c1: i2c@30a20000 {
1173 compatible = 811 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1174 #address-cell 812 #address-cells = <1>;
1175 #size-cells = 813 #size-cells = <0>;
1176 reg = <0x30a2 814 reg = <0x30a20000 0x10000>;
1177 interrupts = 815 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cl 816 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1179 status = "dis 817 status = "disabled";
1180 }; 818 };
1181 819
1182 i2c2: i2c@30a30000 { 820 i2c2: i2c@30a30000 {
1183 compatible = 821 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1184 #address-cell 822 #address-cells = <1>;
1185 #size-cells = 823 #size-cells = <0>;
1186 reg = <0x30a3 824 reg = <0x30a30000 0x10000>;
1187 interrupts = 825 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&cl 826 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1189 status = "dis 827 status = "disabled";
1190 }; 828 };
1191 829
1192 i2c3: i2c@30a40000 { 830 i2c3: i2c@30a40000 {
1193 compatible = 831 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1194 #address-cell 832 #address-cells = <1>;
1195 #size-cells = 833 #size-cells = <0>;
1196 reg = <0x30a4 834 reg = <0x30a40000 0x10000>;
1197 interrupts = 835 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&cl 836 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1199 status = "dis 837 status = "disabled";
1200 }; 838 };
1201 839
1202 i2c4: i2c@30a50000 { 840 i2c4: i2c@30a50000 {
1203 compatible = 841 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1204 #address-cell 842 #address-cells = <1>;
1205 #size-cells = 843 #size-cells = <0>;
1206 reg = <0x30a5 844 reg = <0x30a50000 0x10000>;
1207 interrupts = 845 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cl 846 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1209 status = "dis 847 status = "disabled";
1210 }; 848 };
1211 849
1212 uart4: serial@30a6000 850 uart4: serial@30a60000 {
1213 compatible = 851 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1214 reg = <0x30a6 852 reg = <0x30a60000 0x10000>;
1215 interrupts = 853 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&cl 854 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1217 <&cl 855 <&clk IMX8MP_CLK_UART4_ROOT>;
1218 clock-names = 856 clock-names = "ipg", "per";
1219 dmas = <&sdma 857 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1220 dma-names = " 858 dma-names = "rx", "tx";
1221 status = "dis 859 status = "disabled";
1222 }; 860 };
1223 861
1224 mu: mailbox@30aa0000 862 mu: mailbox@30aa0000 {
1225 compatible = 863 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1226 reg = <0x30aa 864 reg = <0x30aa0000 0x10000>;
1227 interrupts = 865 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&cl 866 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1229 #mbox-cells = 867 #mbox-cells = <2>;
1230 }; 868 };
1231 869
1232 mu2: mailbox@30e60000 870 mu2: mailbox@30e60000 {
1233 compatible = 871 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1234 reg = <0x30e6 872 reg = <0x30e60000 0x10000>;
1235 interrupts = 873 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1236 #mbox-cells = 874 #mbox-cells = <2>;
1237 status = "dis 875 status = "disabled";
1238 }; 876 };
1239 877
1240 i2c5: i2c@30ad0000 { 878 i2c5: i2c@30ad0000 {
1241 compatible = 879 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1242 #address-cell 880 #address-cells = <1>;
1243 #size-cells = 881 #size-cells = <0>;
1244 reg = <0x30ad 882 reg = <0x30ad0000 0x10000>;
1245 interrupts = 883 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&cl 884 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1247 status = "dis 885 status = "disabled";
1248 }; 886 };
1249 887
1250 i2c6: i2c@30ae0000 { 888 i2c6: i2c@30ae0000 {
1251 compatible = 889 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1252 #address-cell 890 #address-cells = <1>;
1253 #size-cells = 891 #size-cells = <0>;
1254 reg = <0x30ae 892 reg = <0x30ae0000 0x10000>;
1255 interrupts = 893 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cl 894 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1257 status = "dis 895 status = "disabled";
1258 }; 896 };
1259 897
1260 usdhc1: mmc@30b40000 898 usdhc1: mmc@30b40000 {
1261 compatible = 899 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1262 reg = <0x30b4 900 reg = <0x30b40000 0x10000>;
1263 interrupts = 901 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cl !! 902 clocks = <&clk IMX8MP_CLK_DUMMY>,
1265 <&cl 903 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1266 <&cl 904 <&clk IMX8MP_CLK_USDHC1_ROOT>;
1267 clock-names = 905 clock-names = "ipg", "ahb", "per";
1268 fsl,tuning-st 906 fsl,tuning-start-tap = <20>;
1269 fsl,tuning-st 907 fsl,tuning-step = <2>;
1270 bus-width = < 908 bus-width = <4>;
1271 status = "dis 909 status = "disabled";
1272 }; 910 };
1273 911
1274 usdhc2: mmc@30b50000 912 usdhc2: mmc@30b50000 {
1275 compatible = 913 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1276 reg = <0x30b5 914 reg = <0x30b50000 0x10000>;
1277 interrupts = 915 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&cl !! 916 clocks = <&clk IMX8MP_CLK_DUMMY>,
1279 <&cl 917 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1280 <&cl 918 <&clk IMX8MP_CLK_USDHC2_ROOT>;
1281 clock-names = 919 clock-names = "ipg", "ahb", "per";
1282 fsl,tuning-st 920 fsl,tuning-start-tap = <20>;
1283 fsl,tuning-st 921 fsl,tuning-step = <2>;
1284 bus-width = < 922 bus-width = <4>;
1285 status = "dis 923 status = "disabled";
1286 }; 924 };
1287 925
1288 usdhc3: mmc@30b60000 926 usdhc3: mmc@30b60000 {
1289 compatible = 927 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1290 reg = <0x30b6 928 reg = <0x30b60000 0x10000>;
1291 interrupts = 929 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cl !! 930 clocks = <&clk IMX8MP_CLK_DUMMY>,
1293 <&cl 931 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1294 <&cl 932 <&clk IMX8MP_CLK_USDHC3_ROOT>;
1295 clock-names = 933 clock-names = "ipg", "ahb", "per";
1296 fsl,tuning-st 934 fsl,tuning-start-tap = <20>;
1297 fsl,tuning-st 935 fsl,tuning-step = <2>;
1298 bus-width = < 936 bus-width = <4>;
1299 status = "dis 937 status = "disabled";
1300 }; 938 };
1301 939
1302 flexspi: spi@30bb0000 940 flexspi: spi@30bb0000 {
1303 compatible = 941 compatible = "nxp,imx8mp-fspi";
1304 reg = <0x30bb 942 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1305 reg-names = " 943 reg-names = "fspi_base", "fspi_mmap";
1306 interrupts = 944 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&cl 945 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1308 <&cl 946 <&clk IMX8MP_CLK_QSPI_ROOT>;
1309 clock-names = 947 clock-names = "fspi_en", "fspi";
1310 assigned-cloc 948 assigned-clock-rates = <80000000>;
1311 assigned-cloc 949 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1312 #address-cell 950 #address-cells = <1>;
1313 #size-cells = 951 #size-cells = <0>;
1314 status = "dis 952 status = "disabled";
1315 }; 953 };
1316 954
1317 sdma1: dma-controller 955 sdma1: dma-controller@30bd0000 {
1318 compatible = 956 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1319 reg = <0x30bd 957 reg = <0x30bd0000 0x10000>;
1320 interrupts = 958 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&cl 959 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1322 <&cl 960 <&clk IMX8MP_CLK_AHB>;
1323 clock-names = 961 clock-names = "ipg", "ahb";
1324 #dma-cells = 962 #dma-cells = <3>;
1325 fsl,sdma-ram- 963 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1326 }; 964 };
1327 965
1328 fec: ethernet@30be000 966 fec: ethernet@30be0000 {
1329 compatible = 967 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1330 reg = <0x30be 968 reg = <0x30be0000 0x10000>;
1331 interrupts = 969 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1332 970 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1333 971 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1334 972 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&cl 973 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1336 <&cl 974 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1337 <&cl 975 <&clk IMX8MP_CLK_ENET_TIMER>,
1338 <&cl 976 <&clk IMX8MP_CLK_ENET_REF>,
1339 <&cl 977 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1340 clock-names = 978 clock-names = "ipg", "ahb", "ptp",
1341 979 "enet_clk_ref", "enet_out";
1342 assigned-cloc 980 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1343 981 <&clk IMX8MP_CLK_ENET_TIMER>,
1344 982 <&clk IMX8MP_CLK_ENET_REF>,
1345 983 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1346 assigned-cloc 984 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1347 985 <&clk IMX8MP_SYS_PLL2_100M>,
1348 986 <&clk IMX8MP_SYS_PLL2_125M>,
1349 987 <&clk IMX8MP_SYS_PLL2_50M>;
1350 assigned-cloc 988 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1351 fsl,num-tx-qu 989 fsl,num-tx-queues = <3>;
1352 fsl,num-rx-qu 990 fsl,num-rx-queues = <3>;
1353 nvmem-cells = 991 nvmem-cells = <ð_mac1>;
1354 nvmem-cell-na 992 nvmem-cell-names = "mac-address";
1355 fsl,stop-mode 993 fsl,stop-mode = <&gpr 0x10 3>;
1356 status = "dis 994 status = "disabled";
1357 }; 995 };
1358 996
1359 eqos: ethernet@30bf00 997 eqos: ethernet@30bf0000 {
1360 compatible = 998 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1361 reg = <0x30bf 999 reg = <0x30bf0000 0x10000>;
1362 interrupts = 1000 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1363 1001 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1364 interrupt-nam 1002 interrupt-names = "macirq", "eth_wake_irq";
1365 clocks = <&cl 1003 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1366 <&cl 1004 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1367 <&cl 1005 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1368 <&cl 1006 <&clk IMX8MP_CLK_ENET_QOS>;
1369 clock-names = 1007 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1370 assigned-cloc 1008 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1371 1009 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1372 1010 <&clk IMX8MP_CLK_ENET_QOS>;
1373 assigned-cloc 1011 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1374 1012 <&clk IMX8MP_SYS_PLL2_100M>,
1375 1013 <&clk IMX8MP_SYS_PLL2_125M>;
1376 assigned-cloc 1014 assigned-clock-rates = <0>, <100000000>, <125000000>;
1377 nvmem-cells = 1015 nvmem-cells = <ð_mac2>;
1378 nvmem-cell-na 1016 nvmem-cell-names = "mac-address";
1379 intf_mode = < 1017 intf_mode = <&gpr 0x4>;
1380 status = "dis 1018 status = "disabled";
1381 }; 1019 };
1382 }; 1020 };
1383 1021
1384 aips5: bus@30c00000 { <<
1385 compatible = "fsl,aip <<
1386 reg = <0x30c00000 0x4 <<
1387 #address-cells = <1>; <<
1388 #size-cells = <1>; <<
1389 ranges; <<
1390 <<
1391 spba-bus@30c00000 { <<
1392 compatible = <<
1393 reg = <0x30c0 <<
1394 #address-cell <<
1395 #size-cells = <<
1396 ranges; <<
1397 <<
1398 sai1: sai@30c <<
1399 compa <<
1400 reg = <<
1401 #soun <<
1402 clock <<
1403 <<
1404 <<
1405 <<
1406 <<
1407 clock <<
1408 dmas <<
1409 dma-n <<
1410 inter <<
1411 statu <<
1412 }; <<
1413 <<
1414 sai2: sai@30c <<
1415 compa <<
1416 reg = <<
1417 #soun <<
1418 clock <<
1419 <<
1420 <<
1421 <<
1422 <<
1423 clock <<
1424 dmas <<
1425 dma-n <<
1426 inter <<
1427 statu <<
1428 }; <<
1429 <<
1430 sai3: sai@30c <<
1431 compa <<
1432 reg = <<
1433 #soun <<
1434 clock <<
1435 <<
1436 <<
1437 <<
1438 <<
1439 clock <<
1440 dmas <<
1441 dma-n <<
1442 inter <<
1443 statu <<
1444 }; <<
1445 <<
1446 sai5: sai@30c <<
1447 compa <<
1448 reg = <<
1449 #soun <<
1450 clock <<
1451 <<
1452 <<
1453 <<
1454 <<
1455 clock <<
1456 dmas <<
1457 dma-n <<
1458 inter <<
1459 statu <<
1460 }; <<
1461 <<
1462 sai6: sai@30c <<
1463 compa <<
1464 reg = <<
1465 #soun <<
1466 clock <<
1467 <<
1468 <<
1469 <<
1470 <<
1471 clock <<
1472 dmas <<
1473 dma-n <<
1474 inter <<
1475 statu <<
1476 }; <<
1477 <<
1478 sai7: sai@30c <<
1479 compa <<
1480 reg = <<
1481 #soun <<
1482 clock <<
1483 <<
1484 <<
1485 <<
1486 <<
1487 clock <<
1488 dmas <<
1489 dma-n <<
1490 inter <<
1491 statu <<
1492 }; <<
1493 <<
1494 easrc: easrc@ <<
1495 compa <<
1496 reg = <<
1497 inter <<
1498 clock <<
1499 clock <<
1500 dmas <<
1501 <<
1502 <<
1503 <<
1504 dma-n <<
1505 <<
1506 <<
1507 <<
1508 firmw <<
1509 fsl,a <<
1510 fsl,a <<
1511 statu <<
1512 }; <<
1513 <<
1514 micfil: audio <<
1515 compa <<
1516 reg = <<
1517 #soun <<
1518 inter <<
1519 <<
1520 <<
1521 <<
1522 clock <<
1523 <<
1524 <<
1525 <<
1526 <<
1527 clock <<
1528 <<
1529 dmas <<
1530 dma-n <<
1531 statu <<
1532 }; <<
1533 <<
1534 aud2htx: aud2 <<
1535 compa <<
1536 reg = <<
1537 inter <<
1538 clock <<
1539 clock <<
1540 dmas <<
1541 dma-n <<
1542 statu <<
1543 }; <<
1544 <<
1545 xcvr: xcvr@30 <<
1546 compa <<
1547 reg = <<
1548 <<
1549 <<
1550 <<
1551 reg-n <<
1552 <<
1553 inter <<
1554 <<
1555 <<
1556 <<
1557 <<
1558 <<
1559 clock <<
1560 <<
1561 <<
1562 <<
1563 clock <<
1564 dmas <<
1565 dma-n <<
1566 reset <<
1567 statu <<
1568 }; <<
1569 }; <<
1570 <<
1571 sdma3: dma-controller <<
1572 compatible = <<
1573 reg = <0x30e0 <<
1574 #dma-cells = <<
1575 clocks = <&au <<
1576 <&cl <<
1577 clock-names = <<
1578 interrupts = <<
1579 fsl,sdma-ram- <<
1580 }; <<
1581 <<
1582 sdma2: dma-controller <<
1583 compatible = <<
1584 reg = <0x30e1 <<
1585 #dma-cells = <<
1586 clocks = <&au <<
1587 <&cl <<
1588 clock-names = <<
1589 interrupts = <<
1590 fsl,sdma-ram- <<
1591 }; <<
1592 <<
1593 audio_blk_ctrl: clock <<
1594 compatible = <<
1595 reg = <0x30e2 <<
1596 #clock-cells <<
1597 #reset-cells <<
1598 clocks = <&cl <<
1599 <&cl <<
1600 <&cl <<
1601 <&cl <<
1602 <&cl <<
1603 <&cl <<
1604 <&cl <<
1605 clock-names = <<
1606 <<
1607 <<
1608 power-domains <<
1609 assigned-cloc <<
1610 <<
1611 assigned-cloc <<
1612 }; <<
1613 }; <<
1614 <<
1615 noc: interconnect@32700000 { 1022 noc: interconnect@32700000 {
1616 compatible = "fsl,imx 1023 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1617 reg = <0x32700000 0x1 1024 reg = <0x32700000 0x100000>;
1618 clocks = <&clk IMX8MP 1025 clocks = <&clk IMX8MP_CLK_NOC>;
1619 #interconnect-cells = 1026 #interconnect-cells = <1>;
1620 operating-points-v2 = 1027 operating-points-v2 = <&noc_opp_table>;
1621 1028
1622 noc_opp_table: opp-ta 1029 noc_opp_table: opp-table {
1623 compatible = 1030 compatible = "operating-points-v2";
1624 1031
1625 opp-200000000 !! 1032 opp-200M {
1626 opp-h 1033 opp-hz = /bits/ 64 <200000000>;
1627 }; 1034 };
1628 1035
1629 opp-100000000 !! 1036 opp-1000M {
1630 opp-h 1037 opp-hz = /bits/ 64 <1000000000>;
1631 }; 1038 };
1632 }; 1039 };
1633 }; 1040 };
1634 1041
1635 aips4: bus@32c00000 { 1042 aips4: bus@32c00000 {
1636 compatible = "fsl,aip 1043 compatible = "fsl,aips-bus", "simple-bus";
1637 reg = <0x32c00000 0x4 1044 reg = <0x32c00000 0x400000>;
1638 #address-cells = <1>; 1045 #address-cells = <1>;
1639 #size-cells = <1>; 1046 #size-cells = <1>;
1640 ranges; 1047 ranges;
1641 1048
1642 isi_0: isi@32e00000 { <<
1643 compatible = <<
1644 reg = <0x32e0 <<
1645 interrupts = <<
1646 <<
1647 clocks = <&cl <<
1648 <&cl <<
1649 clock-names = <<
1650 fsl,blk-ctrl <<
1651 power-domains <<
1652 status = "dis <<
1653 <<
1654 ports { <<
1655 #addr <<
1656 #size <<
1657 <<
1658 port@ <<
1659 <<
1660 <<
1661 <<
1662 <<
1663 <<
1664 }; <<
1665 <<
1666 port@ <<
1667 <<
1668 <<
1669 <<
1670 <<
1671 <<
1672 }; <<
1673 }; <<
1674 }; <<
1675 <<
1676 isp_0: isp@32e10000 { <<
1677 compatible = <<
1678 reg = <0x32e1 <<
1679 interrupts = <<
1680 clocks = <&cl <<
1681 <&cl <<
1682 <&cl <<
1683 clock-names = <<
1684 power-domains <<
1685 fsl,blk-ctrl <<
1686 status = "dis <<
1687 <<
1688 ports { <<
1689 #addr <<
1690 #size <<
1691 <<
1692 port@ <<
1693 <<
1694 }; <<
1695 }; <<
1696 }; <<
1697 <<
1698 isp_1: isp@32e20000 { <<
1699 compatible = <<
1700 reg = <0x32e2 <<
1701 interrupts = <<
1702 clocks = <&cl <<
1703 <&cl <<
1704 <&cl <<
1705 clock-names = <<
1706 power-domains <<
1707 fsl,blk-ctrl <<
1708 status = "dis <<
1709 <<
1710 ports { <<
1711 #addr <<
1712 #size <<
1713 <<
1714 port@ <<
1715 <<
1716 }; <<
1717 }; <<
1718 }; <<
1719 <<
1720 dewarp: dwe@32e30000 <<
1721 compatible = <<
1722 reg = <0x32e3 <<
1723 interrupts = <<
1724 clocks = <&cl <<
1725 <&cl <<
1726 clock-names = <<
1727 power-domains <<
1728 }; <<
1729 <<
1730 mipi_csi_0: csi@32e40 <<
1731 compatible = <<
1732 reg = <0x32e4 <<
1733 interrupts = <<
1734 clock-frequen <<
1735 clocks = <&cl <<
1736 <&cl <<
1737 <&cl <<
1738 <&cl <<
1739 clock-names = <<
1740 assigned-cloc <<
1741 <<
1742 assigned-cloc <<
1743 <<
1744 power-domains <<
1745 status = "dis <<
1746 <<
1747 ports { <<
1748 #addr <<
1749 #size <<
1750 <<
1751 port@ <<
1752 <<
1753 }; <<
1754 <<
1755 port@ <<
1756 <<
1757 <<
1758 <<
1759 <<
1760 <<
1761 }; <<
1762 }; <<
1763 }; <<
1764 <<
1765 mipi_csi_1: csi@32e50 <<
1766 compatible = <<
1767 reg = <0x32e5 <<
1768 interrupts = <<
1769 clock-frequen <<
1770 clocks = <&cl <<
1771 <&cl <<
1772 <&cl <<
1773 <&cl <<
1774 clock-names = <<
1775 assigned-cloc <<
1776 <<
1777 assigned-cloc <<
1778 <<
1779 power-domains <<
1780 status = "dis <<
1781 <<
1782 ports { <<
1783 #addr <<
1784 #size <<
1785 <<
1786 port@ <<
1787 <<
1788 }; <<
1789 <<
1790 port@ <<
1791 <<
1792 <<
1793 <<
1794 <<
1795 <<
1796 }; <<
1797 }; <<
1798 }; <<
1799 <<
1800 mipi_dsi: dsi@32e6000 <<
1801 compatible = <<
1802 reg = <0x32e6 <<
1803 clocks = <&cl <<
1804 <&cl <<
1805 clock-names = <<
1806 assigned-cloc <<
1807 <<
1808 assigned-cloc <<
1809 <<
1810 assigned-cloc <<
1811 samsung,pll-c <<
1812 interrupts = <<
1813 power-domains <<
1814 status = "dis <<
1815 <<
1816 ports { <<
1817 #addr <<
1818 #size <<
1819 <<
1820 port@ <<
1821 <<
1822 <<
1823 <<
1824 <<
1825 <<
1826 }; <<
1827 <<
1828 port@ <<
1829 <<
1830 <<
1831 <<
1832 <<
1833 }; <<
1834 }; <<
1835 }; <<
1836 <<
1837 lcdif1: display-contr <<
1838 compatible = <<
1839 reg = <0x32e8 <<
1840 clocks = <&cl <<
1841 <&cl <<
1842 <&cl <<
1843 clock-names = <<
1844 interrupts = <<
1845 power-domains <<
1846 status = "dis <<
1847 <<
1848 port { <<
1849 lcdif <<
1850 <<
1851 }; <<
1852 }; <<
1853 }; <<
1854 <<
1855 lcdif2: display-contr <<
1856 compatible = <<
1857 reg = <0x32e9 <<
1858 interrupts = <<
1859 clocks = <&cl <<
1860 <&cl <<
1861 <&cl <<
1862 clock-names = <<
1863 power-domains <<
1864 status = "dis <<
1865 <<
1866 port { <<
1867 lcdif <<
1868 <<
1869 }; <<
1870 }; <<
1871 }; <<
1872 <<
1873 media_blk_ctrl: blk-c 1049 media_blk_ctrl: blk-ctrl@32ec0000 {
1874 compatible = 1050 compatible = "fsl,imx8mp-media-blk-ctrl",
1875 1051 "syscon";
1876 reg = <0x32ec 1052 reg = <0x32ec0000 0x10000>;
1877 #address-cell <<
1878 #size-cells = <<
1879 power-domains 1053 power-domains = <&pgc_mediamix>,
1880 1054 <&pgc_mipi_phy1>,
1881 1055 <&pgc_mipi_phy1>,
1882 1056 <&pgc_mediamix>,
1883 1057 <&pgc_mediamix>,
1884 1058 <&pgc_mipi_phy2>,
1885 1059 <&pgc_mediamix>,
1886 1060 <&pgc_ispdwp>,
1887 1061 <&pgc_ispdwp>,
1888 1062 <&pgc_mipi_phy2>;
1889 power-domain- 1063 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1890 1064 "lcdif1", "isi", "mipi-csi2",
1891 1065 "lcdif2", "isp", "dwe",
1892 1066 "mipi-dsi2";
1893 interconnects <<
1894 <&noc <<
1895 <&noc <<
1896 <&noc <<
1897 <&noc <<
1898 <&noc <<
1899 <&noc <<
1900 <&noc <<
1901 <&noc <<
1902 interconnect- <<
1903 <<
1904 <<
1905 clocks = <&cl 1067 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1906 <&cl 1068 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1907 <&cl 1069 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1908 <&cl 1070 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1909 <&cl 1071 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1910 <&cl 1072 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1911 <&cl 1073 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1912 <&cl 1074 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1913 clock-names = 1075 clock-names = "apb", "axi", "cam1", "cam2",
1914 1076 "disp1", "disp2", "isp", "phy";
1915 1077
1916 /* <<
1917 * The ISP ma <<
1918 * and 500MHz <<
1919 * point hasn <<
1920 * IMX8MP_CLK <<
1921 */ <<
1922 assigned-cloc 1078 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1923 !! 1079 <&clk IMX8MP_CLK_MEDIA_APB>;
1924 <<
1925 <<
1926 <<
1927 <<
1928 assigned-cloc 1080 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1929 !! 1081 <&clk IMX8MP_SYS_PLL1_800M>;
1930 !! 1082 assigned-clock-rates = <500000000>, <200000000>;
1931 <<
1932 <<
1933 assigned-cloc <<
1934 <<
1935 <<
1936 #power-domain <<
1937 <<
1938 lvds_bridge: <<
1939 compa <<
1940 reg = <<
1941 reg-n <<
1942 clock <<
1943 clock <<
1944 assig <<
1945 assig <<
1946 statu <<
1947 1083
1948 ports !! 1084 #power-domain-cells = <1>;
1949 <<
1950 <<
1951 <<
1952 <<
1953 <<
1954 <<
1955 <<
1956 <<
1957 <<
1958 <<
1959 <<
1960 <<
1961 <<
1962 <<
1963 <<
1964 <<
1965 <<
1966 <<
1967 <<
1968 <<
1969 <<
1970 <<
1971 <<
1972 <<
1973 }; <<
1974 }; <<
1975 }; <<
1976 <<
1977 pcie_phy: pcie-phy@32 <<
1978 compatible = <<
1979 reg = <0x32f0 <<
1980 resets = <&sr <<
1981 <&sr <<
1982 reset-names = <<
1983 power-domains <<
1984 #phy-cells = <<
1985 status = "dis <<
1986 }; 1085 };
1987 1086
1988 hsio_blk_ctrl: blk-ct 1087 hsio_blk_ctrl: blk-ctrl@32f10000 {
1989 compatible = 1088 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1990 reg = <0x32f1 1089 reg = <0x32f10000 0x24>;
1991 clocks = <&cl 1090 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1992 <&cl 1091 <&clk IMX8MP_CLK_PCIE_ROOT>;
1993 clock-names = 1092 clock-names = "usb", "pcie";
1994 power-domains 1093 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1995 1094 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1996 1095 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1997 power-domain- 1096 power-domain-names = "bus", "usb", "usb-phy1",
1998 1097 "usb-phy2", "pcie", "pcie-phy";
1999 interconnects <<
2000 <<
2001 <<
2002 <<
2003 interconnect- <<
2004 #power-domain 1098 #power-domain-cells = <1>;
2005 #clock-cells <<
2006 }; 1099 };
2007 <<
2008 hdmi_blk_ctrl: blk-ct <<
2009 compatible = <<
2010 reg = <0x32fc <<
2011 clocks = <&cl <<
2012 <&cl <<
2013 <&cl <<
2014 <&cl <<
2015 <&cl <<
2016 clock-names = <<
2017 power-domains <<
2018 <<
2019 <<
2020 <<
2021 <<
2022 power-domain- <<
2023 <<
2024 <<
2025 <<
2026 #power-domain <<
2027 }; <<
2028 <<
2029 irqsteer_hdmi: interr <<
2030 compatible = <<
2031 reg = <0x32fc <<
2032 interrupts = <<
2033 interrupt-con <<
2034 #interrupt-ce <<
2035 fsl,channel = <<
2036 fsl,num-irqs <<
2037 clocks = <&cl <<
2038 clock-names = <<
2039 power-domains <<
2040 }; <<
2041 <<
2042 hdmi_pvi: display-bri <<
2043 compatible = <<
2044 reg = <0x32fc <<
2045 interrupt-par <<
2046 interrupts = <<
2047 power-domains <<
2048 status = "dis <<
2049 <<
2050 ports { <<
2051 #addr <<
2052 #size <<
2053 <<
2054 port@ <<
2055 <<
2056 <<
2057 <<
2058 <<
2059 }; <<
2060 <<
2061 port@ <<
2062 <<
2063 <<
2064 <<
2065 <<
2066 }; <<
2067 }; <<
2068 }; <<
2069 <<
2070 lcdif3: display-contr <<
2071 compatible = <<
2072 reg = <0x32fc <<
2073 interrupt-par <<
2074 interrupts = <<
2075 clocks = <&hd <<
2076 <&cl <<
2077 <&cl <<
2078 clock-names = <<
2079 power-domains <<
2080 status = "dis <<
2081 <<
2082 port { <<
2083 lcdif <<
2084 <<
2085 }; <<
2086 }; <<
2087 }; <<
2088 <<
2089 hdmi_tx: hdmi@32fd800 <<
2090 compatible = <<
2091 reg = <0x32fd <<
2092 interrupt-par <<
2093 interrupts = <<
2094 clocks = <&cl <<
2095 <&cl <<
2096 <&cl <<
2097 <&hd <<
2098 clock-names = <<
2099 assigned-cloc <<
2100 assigned-cloc <<
2101 power-domains <<
2102 reg-io-width <<
2103 status = "dis <<
2104 <<
2105 ports { <<
2106 #addr <<
2107 #size <<
2108 <<
2109 port@ <<
2110 <<
2111 <<
2112 <<
2113 <<
2114 <<
2115 }; <<
2116 <<
2117 port@ <<
2118 <<
2119 <<
2120 }; <<
2121 }; <<
2122 }; <<
2123 <<
2124 hdmi_tx_phy: phy@32fd <<
2125 compatible = <<
2126 reg = <0x32fd <<
2127 clocks = <&cl <<
2128 <&cl <<
2129 clock-names = <<
2130 assigned-cloc <<
2131 assigned-cloc <<
2132 power-domains <<
2133 #clock-cells <<
2134 #phy-cells = <<
2135 status = "dis <<
2136 }; <<
2137 }; <<
2138 <<
2139 pcie: pcie@33800000 { <<
2140 compatible = "fsl,imx <<
2141 reg = <0x33800000 0x4 <<
2142 reg-names = "dbi", "c <<
2143 clocks = <&clk IMX8MP <<
2144 <&clk IMX8MP <<
2145 <&clk IMX8MP <<
2146 clock-names = "pcie", <<
2147 assigned-clocks = <&c <<
2148 assigned-clock-rates <<
2149 assigned-clock-parent <<
2150 #address-cells = <3>; <<
2151 #size-cells = <2>; <<
2152 device_type = "pci"; <<
2153 bus-range = <0x00 0xf <<
2154 ranges = <0x81000000 <<
2155 <0x82000000 <<
2156 num-lanes = <1>; <<
2157 num-viewport = <4>; <<
2158 interrupts = <GIC_SPI <<
2159 interrupt-names = "ms <<
2160 #interrupt-cells = <1 <<
2161 interrupt-map-mask = <<
2162 interrupt-map = <0 0 <<
2163 <0 0 <<
2164 <0 0 <<
2165 <0 0 <<
2166 fsl,max-link-speed = <<
2167 linux,pci-domain = <0 <<
2168 power-domains = <&hsi <<
2169 resets = <&src IMX8MP <<
2170 <&src IMX8MP <<
2171 reset-names = "apps", <<
2172 phys = <&pcie_phy>; <<
2173 phy-names = "pcie-phy <<
2174 status = "disabled"; <<
2175 }; <<
2176 <<
2177 pcie_ep: pcie-ep@33800000 { <<
2178 compatible = "fsl,imx <<
2179 reg = <0x33800000 0x0 <<
2180 reg-names = "dbi", "a <<
2181 clocks = <&clk IMX8MP <<
2182 <&clk IMX8MP <<
2183 <&clk IMX8MP <<
2184 clock-names = "pcie", <<
2185 assigned-clocks = <&c <<
2186 assigned-clock-rates <<
2187 assigned-clock-parent <<
2188 num-lanes = <1>; <<
2189 interrupts = <GIC_SPI <<
2190 interrupt-names = "dm <<
2191 fsl,max-link-speed = <<
2192 power-domains = <&hsi <<
2193 resets = <&src IMX8MP <<
2194 <&src IMX8MP <<
2195 reset-names = "apps", <<
2196 phys = <&pcie_phy>; <<
2197 phy-names = "pcie-phy <<
2198 num-ib-windows = <4>; <<
2199 num-ob-windows = <4>; <<
2200 status = "disabled"; <<
2201 }; 1100 };
2202 1101
2203 gpu3d: gpu@38000000 { 1102 gpu3d: gpu@38000000 {
2204 compatible = "vivante 1103 compatible = "vivante,gc";
2205 reg = <0x38000000 0x8 1104 reg = <0x38000000 0x8000>;
2206 interrupts = <GIC_SPI 1105 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
2207 clocks = <&clk IMX8MP 1106 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
2208 <&clk IMX8MP 1107 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
2209 <&clk IMX8MP 1108 <&clk IMX8MP_CLK_GPU_ROOT>,
2210 <&clk IMX8MP 1109 <&clk IMX8MP_CLK_GPU_AHB>;
2211 clock-names = "core", 1110 clock-names = "core", "shader", "bus", "reg";
2212 assigned-clocks = <&c 1111 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
2213 <&c 1112 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
2214 assigned-clock-parent 1113 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
2215 1114 <&clk IMX8MP_SYS_PLL1_800M>;
2216 assigned-clock-rates 1115 assigned-clock-rates = <800000000>, <800000000>;
2217 power-domains = <&pgc 1116 power-domains = <&pgc_gpu3d>;
2218 }; 1117 };
2219 1118
2220 gpu2d: gpu@38008000 { 1119 gpu2d: gpu@38008000 {
2221 compatible = "vivante 1120 compatible = "vivante,gc";
2222 reg = <0x38008000 0x8 1121 reg = <0x38008000 0x8000>;
2223 interrupts = <GIC_SPI 1122 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
2224 clocks = <&clk IMX8MP 1123 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
2225 <&clk IMX8MP 1124 <&clk IMX8MP_CLK_GPU_ROOT>,
2226 <&clk IMX8MP 1125 <&clk IMX8MP_CLK_GPU_AHB>;
2227 clock-names = "core", 1126 clock-names = "core", "bus", "reg";
2228 assigned-clocks = <&c 1127 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
2229 assigned-clock-parent 1128 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2230 assigned-clock-rates 1129 assigned-clock-rates = <800000000>;
2231 power-domains = <&pgc 1130 power-domains = <&pgc_gpu2d>;
2232 }; 1131 };
2233 1132
2234 vpu_g1: video-codec@38300000 <<
2235 compatible = "nxp,imx <<
2236 reg = <0x38300000 0x1 <<
2237 interrupts = <GIC_SPI <<
2238 clocks = <&clk IMX8MP <<
2239 assigned-clocks = <&c <<
2240 assigned-clock-parent <<
2241 assigned-clock-rates <<
2242 power-domains = <&vpu <<
2243 }; <<
2244 <<
2245 vpu_g2: video-codec@38310000 <<
2246 compatible = "nxp,imx <<
2247 reg = <0x38310000 0x1 <<
2248 interrupts = <GIC_SPI <<
2249 clocks = <&clk IMX8MP <<
2250 assigned-clocks = <&c <<
2251 assigned-clock-parent <<
2252 assigned-clock-rates <<
2253 power-domains = <&vpu <<
2254 }; <<
2255 <<
2256 vpumix_blk_ctrl: blk-ctrl@383 <<
2257 compatible = "fsl,imx <<
2258 reg = <0x38330000 0x1 <<
2259 #power-domain-cells = <<
2260 power-domains = <&pgc <<
2261 <&pgc <<
2262 power-domain-names = <<
2263 clocks = <&clk IMX8MP <<
2264 <&clk IMX8MP <<
2265 <&clk IMX8MP <<
2266 clock-names = "g1", " <<
2267 assigned-clocks = <&c <<
2268 assigned-clock-parent <<
2269 assigned-clock-rates <<
2270 interconnects = <&noc <<
2271 <&noc <<
2272 <&noc <<
2273 interconnect-names = <<
2274 }; <<
2275 <<
2276 npu: npu@38500000 { <<
2277 compatible = "vivante <<
2278 reg = <0x38500000 0x2 <<
2279 interrupts = <GIC_SPI <<
2280 clocks = <&clk IMX8MP <<
2281 <&clk IMX8MP <<
2282 <&clk IMX8MP <<
2283 <&clk IMX8MP <<
2284 clock-names = "core", <<
2285 power-domains = <&pgc <<
2286 }; <<
2287 <<
2288 gic: interrupt-controller@388 1133 gic: interrupt-controller@38800000 {
2289 compatible = "arm,gic 1134 compatible = "arm,gic-v3";
2290 reg = <0x38800000 0x1 1135 reg = <0x38800000 0x10000>,
2291 <0x38880000 0xc 1136 <0x38880000 0xc0000>;
2292 #interrupt-cells = <3 1137 #interrupt-cells = <3>;
2293 interrupt-controller; 1138 interrupt-controller;
2294 interrupts = <GIC_PPI 1139 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2295 interrupt-parent = <& 1140 interrupt-parent = <&gic>;
2296 }; 1141 };
2297 1142
2298 edacmc: memory-controller@3d4 1143 edacmc: memory-controller@3d400000 {
2299 compatible = "snps,dd 1144 compatible = "snps,ddrc-3.80a";
2300 reg = <0x3d400000 0x4 1145 reg = <0x3d400000 0x400000>;
2301 interrupts = <GIC_SPI 1146 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2302 }; 1147 };
2303 1148
2304 ddr-pmu@3d800000 { 1149 ddr-pmu@3d800000 {
2305 compatible = "fsl,imx 1150 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2306 reg = <0x3d800000 0x4 1151 reg = <0x3d800000 0x400000>;
2307 interrupts = <GIC_SPI 1152 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2308 }; 1153 };
2309 1154
2310 usb3_phy0: usb-phy@381f0040 { 1155 usb3_phy0: usb-phy@381f0040 {
2311 compatible = "fsl,imx 1156 compatible = "fsl,imx8mp-usb-phy";
2312 reg = <0x381f0040 0x4 1157 reg = <0x381f0040 0x40>;
2313 clocks = <&clk IMX8MP 1158 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2314 clock-names = "phy"; 1159 clock-names = "phy";
2315 assigned-clocks = <&c 1160 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2316 assigned-clock-parent 1161 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2317 power-domains = <&hsi 1162 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2318 #phy-cells = <0>; 1163 #phy-cells = <0>;
2319 status = "disabled"; 1164 status = "disabled";
2320 }; 1165 };
2321 1166
2322 usb3_0: usb@32f10100 { 1167 usb3_0: usb@32f10100 {
2323 compatible = "fsl,imx 1168 compatible = "fsl,imx8mp-dwc3";
2324 reg = <0x32f10100 0x8 1169 reg = <0x32f10100 0x8>,
2325 <0x381f0000 0x2 1170 <0x381f0000 0x20>;
2326 clocks = <&clk IMX8MP 1171 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2327 <&clk IMX8MP !! 1172 <&clk IMX8MP_CLK_USB_ROOT>;
2328 clock-names = "hsio", 1173 clock-names = "hsio", "suspend";
2329 interrupts = <GIC_SPI 1174 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&hsi 1175 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2331 #address-cells = <1>; 1176 #address-cells = <1>;
2332 #size-cells = <1>; 1177 #size-cells = <1>;
2333 dma-ranges = <0x40000 1178 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2334 ranges; 1179 ranges;
2335 status = "disabled"; 1180 status = "disabled";
2336 1181
2337 usb_dwc3_0: usb@38100 1182 usb_dwc3_0: usb@38100000 {
2338 compatible = 1183 compatible = "snps,dwc3";
2339 reg = <0x3810 1184 reg = <0x38100000 0x10000>;
2340 clocks = <&cl !! 1185 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
2341 <&cl 1186 <&clk IMX8MP_CLK_USB_CORE_REF>,
2342 <&cl !! 1187 <&clk IMX8MP_CLK_USB_ROOT>;
2343 clock-names = 1188 clock-names = "bus_early", "ref", "suspend";
2344 interrupts = 1189 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
2345 phys = <&usb3 1190 phys = <&usb3_phy0>, <&usb3_phy0>;
2346 phy-names = " 1191 phy-names = "usb2-phy", "usb3-phy";
2347 snps,gfladj-r 1192 snps,gfladj-refclk-lpm-sel-quirk;
2348 snps,parkmode <<
2349 }; 1193 };
2350 1194
2351 }; 1195 };
2352 1196
2353 usb3_phy1: usb-phy@382f0040 { 1197 usb3_phy1: usb-phy@382f0040 {
2354 compatible = "fsl,imx 1198 compatible = "fsl,imx8mp-usb-phy";
2355 reg = <0x382f0040 0x4 1199 reg = <0x382f0040 0x40>;
2356 clocks = <&clk IMX8MP 1200 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2357 clock-names = "phy"; 1201 clock-names = "phy";
2358 assigned-clocks = <&c 1202 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2359 assigned-clock-parent 1203 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2360 power-domains = <&hsi 1204 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2361 #phy-cells = <0>; 1205 #phy-cells = <0>;
2362 status = "disabled"; 1206 status = "disabled";
2363 }; 1207 };
2364 1208
2365 usb3_1: usb@32f10108 { 1209 usb3_1: usb@32f10108 {
2366 compatible = "fsl,imx 1210 compatible = "fsl,imx8mp-dwc3";
2367 reg = <0x32f10108 0x8 1211 reg = <0x32f10108 0x8>,
2368 <0x382f0000 0x2 1212 <0x382f0000 0x20>;
2369 clocks = <&clk IMX8MP 1213 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2370 <&clk IMX8MP !! 1214 <&clk IMX8MP_CLK_USB_ROOT>;
2371 clock-names = "hsio", 1215 clock-names = "hsio", "suspend";
2372 interrupts = <GIC_SPI 1216 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2373 power-domains = <&hsi 1217 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2374 #address-cells = <1>; 1218 #address-cells = <1>;
2375 #size-cells = <1>; 1219 #size-cells = <1>;
2376 dma-ranges = <0x40000 1220 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2377 ranges; 1221 ranges;
2378 status = "disabled"; 1222 status = "disabled";
2379 1223
2380 usb_dwc3_1: usb@38200 1224 usb_dwc3_1: usb@38200000 {
2381 compatible = 1225 compatible = "snps,dwc3";
2382 reg = <0x3820 1226 reg = <0x38200000 0x10000>;
2383 clocks = <&cl !! 1227 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
2384 <&cl 1228 <&clk IMX8MP_CLK_USB_CORE_REF>,
2385 <&cl !! 1229 <&clk IMX8MP_CLK_USB_ROOT>;
2386 clock-names = 1230 clock-names = "bus_early", "ref", "suspend";
2387 interrupts = 1231 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
2388 phys = <&usb3 1232 phys = <&usb3_phy1>, <&usb3_phy1>;
2389 phy-names = " 1233 phy-names = "usb2-phy", "usb3-phy";
2390 snps,gfladj-r 1234 snps,gfladj-refclk-lpm-sel-quirk;
2391 snps,parkmode <<
2392 }; 1235 };
2393 }; 1236 };
2394 1237
2395 dsp: dsp@3b6e8000 { 1238 dsp: dsp@3b6e8000 {
2396 compatible = "fsl,imx 1239 compatible = "fsl,imx8mp-dsp";
2397 reg = <0x3b6e8000 0x8 1240 reg = <0x3b6e8000 0x88000>;
2398 mbox-names = "txdb0", 1241 mbox-names = "txdb0", "txdb1",
2399 "rxdb0", "rxd 1242 "rxdb0", "rxdb1";
2400 mboxes = <&mu2 2 0>, 1243 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2401 <&mu2 3 0>, < 1244 <&mu2 3 0>, <&mu2 3 1>;
2402 memory-region = <&dsp 1245 memory-region = <&dsp_reserved>;
2403 status = "disabled"; 1246 status = "disabled";
2404 }; 1247 };
2405 }; 1248 };
2406 }; 1249 };
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