1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mp-clock.h> 6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h> 7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h> 8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp. 11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 #include "imx8mp-pinfunc.h" 15 #include "imx8mp-pinfunc.h"
16 16
17 / { 17 / {
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
23 ethernet0 = &fec; 23 ethernet0 = &fec;
24 ethernet1 = &eqos; 24 ethernet1 = &eqos;
25 gpio0 = &gpio1; 25 gpio0 = &gpio1;
26 gpio1 = &gpio2; 26 gpio1 = &gpio2;
27 gpio2 = &gpio3; 27 gpio2 = &gpio3;
28 gpio3 = &gpio4; 28 gpio3 = &gpio4;
29 gpio4 = &gpio5; 29 gpio4 = &gpio5;
30 i2c0 = &i2c1; 30 i2c0 = &i2c1;
31 i2c1 = &i2c2; 31 i2c1 = &i2c2;
32 i2c2 = &i2c3; 32 i2c2 = &i2c3;
33 i2c3 = &i2c4; 33 i2c3 = &i2c4;
34 i2c4 = &i2c5; 34 i2c4 = &i2c5;
35 i2c5 = &i2c6; 35 i2c5 = &i2c6;
36 mmc0 = &usdhc1; 36 mmc0 = &usdhc1;
37 mmc1 = &usdhc2; 37 mmc1 = &usdhc2;
38 mmc2 = &usdhc3; 38 mmc2 = &usdhc3;
39 serial0 = &uart1; 39 serial0 = &uart1;
40 serial1 = &uart2; 40 serial1 = &uart2;
41 serial2 = &uart3; 41 serial2 = &uart3;
42 serial3 = &uart4; 42 serial3 = &uart4;
43 spi0 = &flexspi; 43 spi0 = &flexspi;
44 }; 44 };
45 45
46 cpus { 46 cpus {
47 #address-cells = <1>; 47 #address-cells = <1>;
48 #size-cells = <0>; 48 #size-cells = <0>;
49 49
50 A53_0: cpu@0 { 50 A53_0: cpu@0 {
51 device_type = "cpu"; 51 device_type = "cpu";
52 compatible = "arm,cort 52 compatible = "arm,cortex-a53";
53 reg = <0x0>; 53 reg = <0x0>;
54 clock-latency = <61036 54 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_ 55 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci" 56 enable-method = "psci";
57 i-cache-size = <0x8000 57 i-cache-size = <0x8000>;
58 i-cache-line-size = <6 58 i-cache-line-size = <64>;
59 i-cache-sets = <256>; 59 i-cache-sets = <256>;
60 d-cache-size = <0x8000 60 d-cache-size = <0x8000>;
61 d-cache-line-size = <6 61 d-cache-line-size = <64>;
62 d-cache-sets = <128>; 62 d-cache-sets = <128>;
63 next-level-cache = <&A 63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_sp 64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "sp 65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = 66 operating-points-v2 = <&a53_opp_table>;
67 #cooling-cells = <2>; 67 #cooling-cells = <2>;
68 }; 68 };
69 69
70 A53_1: cpu@1 { 70 A53_1: cpu@1 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
73 reg = <0x1>; 73 reg = <0x1>;
74 clock-latency = <61036 74 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_ 75 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci" 76 enable-method = "psci";
77 i-cache-size = <0x8000 77 i-cache-size = <0x8000>;
78 i-cache-line-size = <6 78 i-cache-line-size = <64>;
79 i-cache-sets = <256>; 79 i-cache-sets = <256>;
80 d-cache-size = <0x8000 80 d-cache-size = <0x8000>;
81 d-cache-line-size = <6 81 d-cache-line-size = <64>;
82 d-cache-sets = <128>; 82 d-cache-sets = <128>;
83 next-level-cache = <&A 83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = 84 operating-points-v2 = <&a53_opp_table>;
85 #cooling-cells = <2>; 85 #cooling-cells = <2>;
86 }; 86 };
87 87
88 A53_2: cpu@2 { 88 A53_2: cpu@2 {
89 device_type = "cpu"; 89 device_type = "cpu";
90 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
91 reg = <0x2>; 91 reg = <0x2>;
92 clock-latency = <61036 92 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_ 93 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci" 94 enable-method = "psci";
95 i-cache-size = <0x8000 95 i-cache-size = <0x8000>;
96 i-cache-line-size = <6 96 i-cache-line-size = <64>;
97 i-cache-sets = <256>; 97 i-cache-sets = <256>;
98 d-cache-size = <0x8000 98 d-cache-size = <0x8000>;
99 d-cache-line-size = <6 99 d-cache-line-size = <64>;
100 d-cache-sets = <128>; 100 d-cache-sets = <128>;
101 next-level-cache = <&A 101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = 102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>; 103 #cooling-cells = <2>;
104 }; 104 };
105 105
106 A53_3: cpu@3 { 106 A53_3: cpu@3 {
107 device_type = "cpu"; 107 device_type = "cpu";
108 compatible = "arm,cort 108 compatible = "arm,cortex-a53";
109 reg = <0x3>; 109 reg = <0x3>;
110 clock-latency = <61036 110 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_ 111 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci" 112 enable-method = "psci";
113 i-cache-size = <0x8000 113 i-cache-size = <0x8000>;
114 i-cache-line-size = <6 114 i-cache-line-size = <64>;
115 i-cache-sets = <256>; 115 i-cache-sets = <256>;
116 d-cache-size = <0x8000 116 d-cache-size = <0x8000>;
117 d-cache-line-size = <6 117 d-cache-line-size = <64>;
118 d-cache-sets = <128>; 118 d-cache-sets = <128>;
119 next-level-cache = <&A 119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = 120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>; 121 #cooling-cells = <2>;
122 }; 122 };
123 123
124 A53_L2: l2-cache0 { 124 A53_L2: l2-cache0 {
125 compatible = "cache"; 125 compatible = "cache";
126 cache-unified; 126 cache-unified;
127 cache-level = <2>; 127 cache-level = <2>;
128 cache-size = <0x80000> 128 cache-size = <0x80000>;
129 cache-line-size = <64> 129 cache-line-size = <64>;
130 cache-sets = <512>; 130 cache-sets = <512>;
131 }; 131 };
132 }; 132 };
133 133
134 a53_opp_table: opp-table { 134 a53_opp_table: opp-table {
135 compatible = "operating-points 135 compatible = "operating-points-v2";
136 opp-shared; 136 opp-shared;
137 137
138 opp-1200000000 { 138 opp-1200000000 {
139 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <85000 140 opp-microvolt = <850000>;
141 opp-supported-hw = <0x 141 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <15 142 clock-latency-ns = <150000>;
143 opp-suspend; 143 opp-suspend;
144 }; 144 };
145 145
146 opp-1600000000 { 146 opp-1600000000 {
147 opp-hz = /bits/ 64 <16 147 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <95000 148 opp-microvolt = <950000>;
149 opp-supported-hw = <0x 149 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <15 150 clock-latency-ns = <150000>;
151 opp-suspend; 151 opp-suspend;
152 }; 152 };
153 153
154 opp-1800000000 { 154 opp-1800000000 {
155 opp-hz = /bits/ 64 <18 155 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <10000 156 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x 157 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <15 158 clock-latency-ns = <150000>;
159 opp-suspend; 159 opp-suspend;
160 }; 160 };
161 }; 161 };
162 162
163 osc_32k: clock-osc-32k { 163 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock"; 164 compatible = "fixed-clock";
165 #clock-cells = <0>; 165 #clock-cells = <0>;
166 clock-frequency = <32768>; 166 clock-frequency = <32768>;
167 clock-output-names = "osc_32k" 167 clock-output-names = "osc_32k";
168 }; 168 };
169 169
170 osc_24m: clock-osc-24m { 170 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock"; 171 compatible = "fixed-clock";
172 #clock-cells = <0>; 172 #clock-cells = <0>;
173 clock-frequency = <24000000>; 173 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m" 174 clock-output-names = "osc_24m";
175 }; 175 };
176 176
177 clk_ext1: clock-ext1 { 177 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock"; 178 compatible = "fixed-clock";
179 #clock-cells = <0>; 179 #clock-cells = <0>;
180 clock-frequency = <133000000>; 180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1 181 clock-output-names = "clk_ext1";
182 }; 182 };
183 183
184 clk_ext2: clock-ext2 { 184 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock"; 185 compatible = "fixed-clock";
186 #clock-cells = <0>; 186 #clock-cells = <0>;
187 clock-frequency = <133000000>; 187 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2 188 clock-output-names = "clk_ext2";
189 }; 189 };
190 190
191 clk_ext3: clock-ext3 { 191 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock"; 192 compatible = "fixed-clock";
193 #clock-cells = <0>; 193 #clock-cells = <0>;
194 clock-frequency = <133000000>; 194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3 195 clock-output-names = "clk_ext3";
196 }; 196 };
197 197
198 clk_ext4: clock-ext4 { 198 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock"; 199 compatible = "fixed-clock";
200 #clock-cells = <0>; 200 #clock-cells = <0>;
201 clock-frequency = <133000000>; 201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext4 202 clock-output-names = "clk_ext4";
203 }; 203 };
204 204
205 funnel { <<
206 /* <<
207 * non-configurable funnel don <<
208 * bus. As such no need to ad <<
209 */ <<
210 compatible = "arm,coresight-st <<
211 <<
212 in-ports { <<
213 #address-cells = <1>; <<
214 #size-cells = <0>; <<
215 <<
216 port@0 { <<
217 reg = <0>; <<
218 <<
219 ca_funnel_in_p <<
220 remote <<
221 }; <<
222 }; <<
223 <<
224 port@1 { <<
225 reg = <1>; <<
226 <<
227 ca_funnel_in_p <<
228 remote <<
229 }; <<
230 }; <<
231 <<
232 port@2 { <<
233 reg = <2>; <<
234 <<
235 ca_funnel_in_p <<
236 remote <<
237 }; <<
238 }; <<
239 <<
240 port@3 { <<
241 reg = <3>; <<
242 <<
243 ca_fun <<
244 remote <<
245 }; <<
246 }; <<
247 }; <<
248 <<
249 out-ports { <<
250 port { <<
251 <<
252 ca_funnel_out_ <<
253 remote <<
254 }; <<
255 }; <<
256 }; <<
257 }; <<
258 <<
259 reserved-memory { 205 reserved-memory {
260 #address-cells = <2>; 206 #address-cells = <2>;
261 #size-cells = <2>; 207 #size-cells = <2>;
262 ranges; 208 ranges;
263 209
264 dsp_reserved: dsp@92400000 { 210 dsp_reserved: dsp@92400000 {
265 reg = <0 0x92400000 0 211 reg = <0 0x92400000 0 0x2000000>;
266 no-map; 212 no-map;
267 status = "disabled"; <<
268 }; 213 };
269 }; 214 };
270 215
271 pmu { 216 pmu {
272 compatible = "arm,cortex-a53-p 217 compatible = "arm,cortex-a53-pmu";
273 interrupts = <GIC_PPI 7 218 interrupts = <GIC_PPI 7
274 (GIC_CPU_MASK_SIM 219 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
275 }; 220 };
276 221
277 psci { 222 psci {
278 compatible = "arm,psci-1.0"; 223 compatible = "arm,psci-1.0";
279 method = "smc"; 224 method = "smc";
280 }; 225 };
281 226
282 thermal-zones { 227 thermal-zones {
283 cpu-thermal { 228 cpu-thermal {
284 polling-delay-passive 229 polling-delay-passive = <250>;
285 polling-delay = <2000> 230 polling-delay = <2000>;
286 thermal-sensors = <&tm 231 thermal-sensors = <&tmu 0>;
287 trips { 232 trips {
288 cpu_alert0: tr 233 cpu_alert0: trip0 {
289 temper 234 temperature = <85000>;
290 hyster 235 hysteresis = <2000>;
291 type = 236 type = "passive";
292 }; 237 };
293 238
294 cpu_crit0: tri 239 cpu_crit0: trip1 {
295 temper 240 temperature = <95000>;
296 hyster 241 hysteresis = <2000>;
297 type = 242 type = "critical";
298 }; 243 };
299 }; 244 };
300 245
301 cooling-maps { 246 cooling-maps {
302 map0 { 247 map0 {
303 trip = 248 trip = <&cpu_alert0>;
304 coolin 249 cooling-device =
305 250 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
306 251 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
307 252 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
308 253 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
309 }; 254 };
310 }; 255 };
311 }; 256 };
312 257
313 soc-thermal { 258 soc-thermal {
314 polling-delay-passive 259 polling-delay-passive = <250>;
315 polling-delay = <2000> 260 polling-delay = <2000>;
316 thermal-sensors = <&tm 261 thermal-sensors = <&tmu 1>;
317 trips { 262 trips {
318 soc_alert0: tr 263 soc_alert0: trip0 {
319 temper 264 temperature = <85000>;
320 hyster 265 hysteresis = <2000>;
321 type = 266 type = "passive";
322 }; 267 };
323 268
324 soc_crit0: tri 269 soc_crit0: trip1 {
325 temper 270 temperature = <95000>;
326 hyster 271 hysteresis = <2000>;
327 type = 272 type = "critical";
328 }; 273 };
329 }; 274 };
330 275
331 cooling-maps { 276 cooling-maps {
332 map0 { 277 map0 {
333 trip = 278 trip = <&soc_alert0>;
334 coolin 279 cooling-device =
335 280 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
336 281 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
337 282 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
338 283 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 }; 284 };
340 }; 285 };
341 }; 286 };
342 }; 287 };
343 288
344 timer { 289 timer {
345 compatible = "arm,armv8-timer" 290 compatible = "arm,armv8-timer";
346 interrupts = <GIC_PPI 13 (GIC_ 291 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
347 <GIC_PPI 14 (GIC_ 292 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
348 <GIC_PPI 11 (GIC_ 293 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
349 <GIC_PPI 10 (GIC_ 294 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
350 clock-frequency = <8000000>; 295 clock-frequency = <8000000>;
351 arm,no-tick-in-suspend; 296 arm,no-tick-in-suspend;
352 }; 297 };
353 298
354 soc: soc@0 { 299 soc: soc@0 {
355 compatible = "fsl,imx8mp-soc", 300 compatible = "fsl,imx8mp-soc", "simple-bus";
356 #address-cells = <1>; 301 #address-cells = <1>;
357 #size-cells = <1>; 302 #size-cells = <1>;
358 ranges = <0x0 0x0 0x0 0x3e0000 303 ranges = <0x0 0x0 0x0 0x3e000000>;
359 nvmem-cells = <&imx8mp_uid>; 304 nvmem-cells = <&imx8mp_uid>;
360 nvmem-cell-names = "soc_unique 305 nvmem-cell-names = "soc_unique_id";
361 306
362 etm0: etm@28440000 { <<
363 compatible = "arm,core <<
364 reg = <0x28440000 0x10 <<
365 cpu = <&A53_0>; <<
366 clocks = <&clk IMX8MP_ <<
367 clock-names = "apb_pcl <<
368 <<
369 out-ports { <<
370 port { <<
371 etm0_o <<
372 <<
373 }; <<
374 }; <<
375 }; <<
376 }; <<
377 <<
378 etm1: etm@28540000 { <<
379 compatible = "arm,core <<
380 reg = <0x28540000 0x10 <<
381 cpu = <&A53_1>; <<
382 clocks = <&clk IMX8MP_ <<
383 clock-names = "apb_pcl <<
384 <<
385 out-ports { <<
386 port { <<
387 etm1_o <<
388 <<
389 }; <<
390 }; <<
391 }; <<
392 }; <<
393 <<
394 etm2: etm@28640000 { <<
395 compatible = "arm,core <<
396 reg = <0x28640000 0x10 <<
397 cpu = <&A53_2>; <<
398 clocks = <&clk IMX8MP_ <<
399 clock-names = "apb_pcl <<
400 <<
401 out-ports { <<
402 port { <<
403 etm2_o <<
404 <<
405 }; <<
406 }; <<
407 }; <<
408 }; <<
409 <<
410 etm3: etm@28740000 { <<
411 compatible = "arm,core <<
412 reg = <0x28740000 0x10 <<
413 cpu = <&A53_3>; <<
414 clocks = <&clk IMX8MP_ <<
415 clock-names = "apb_pcl <<
416 <<
417 out-ports { <<
418 port { <<
419 etm3_o <<
420 <<
421 }; <<
422 }; <<
423 }; <<
424 }; <<
425 <<
426 funnel@28c03000 { <<
427 compatible = "arm,core <<
428 reg = <0x28c03000 0x10 <<
429 clocks = <&clk IMX8MP_ <<
430 clock-names = "apb_pcl <<
431 <<
432 in-ports { <<
433 #address-cells <<
434 #size-cells = <<
435 <<
436 port@0 { <<
437 reg = <<
438 <<
439 hugo_f <<
440 <<
441 }; <<
442 }; <<
443 <<
444 port@1 { <<
445 reg = <<
446 <<
447 hugo_f <<
448 /* M7 <<
449 }; <<
450 }; <<
451 <<
452 port@2 { <<
453 reg = <<
454 <<
455 hugo_f <<
456 /* DSP <<
457 }; <<
458 }; <<
459 /* the other i <<
460 }; <<
461 <<
462 out-ports { <<
463 port { <<
464 hugo_f <<
465 <<
466 }; <<
467 }; <<
468 }; <<
469 }; <<
470 <<
471 etf@28c04000 { <<
472 compatible = "arm,core <<
473 reg = <0x28c04000 0x10 <<
474 clocks = <&clk IMX8MP_ <<
475 clock-names = "apb_pcl <<
476 <<
477 in-ports { <<
478 port { <<
479 etf_in <<
480 <<
481 }; <<
482 }; <<
483 }; <<
484 <<
485 out-ports { <<
486 port { <<
487 etf_ou <<
488 <<
489 }; <<
490 }; <<
491 }; <<
492 }; <<
493 <<
494 etr@28c06000 { <<
495 compatible = "arm,core <<
496 reg = <0x28c06000 0x10 <<
497 clocks = <&clk IMX8MP_ <<
498 clock-names = "apb_pcl <<
499 <<
500 in-ports { <<
501 port { <<
502 etr_in <<
503 <<
504 }; <<
505 }; <<
506 }; <<
507 }; <<
508 <<
509 aips1: bus@30000000 { 307 aips1: bus@30000000 {
510 compatible = "fsl,aips 308 compatible = "fsl,aips-bus", "simple-bus";
511 reg = <0x30000000 0x40 309 reg = <0x30000000 0x400000>;
512 #address-cells = <1>; 310 #address-cells = <1>;
513 #size-cells = <1>; 311 #size-cells = <1>;
514 ranges; 312 ranges;
515 313
516 gpio1: gpio@30200000 { 314 gpio1: gpio@30200000 {
517 compatible = " 315 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
518 reg = <0x30200 316 reg = <0x30200000 0x10000>;
519 interrupts = < 317 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
520 < 318 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clk 319 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
522 gpio-controlle 320 gpio-controller;
523 #gpio-cells = 321 #gpio-cells = <2>;
524 interrupt-cont 322 interrupt-controller;
525 #interrupt-cel 323 #interrupt-cells = <2>;
526 gpio-ranges = 324 gpio-ranges = <&iomuxc 0 5 30>;
527 }; 325 };
528 326
529 gpio2: gpio@30210000 { 327 gpio2: gpio@30210000 {
530 compatible = " 328 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
531 reg = <0x30210 329 reg = <0x30210000 0x10000>;
532 interrupts = < 330 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
533 < 331 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clk 332 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
535 gpio-controlle 333 gpio-controller;
536 #gpio-cells = 334 #gpio-cells = <2>;
537 interrupt-cont 335 interrupt-controller;
538 #interrupt-cel 336 #interrupt-cells = <2>;
539 gpio-ranges = 337 gpio-ranges = <&iomuxc 0 35 21>;
540 }; 338 };
541 339
542 gpio3: gpio@30220000 { 340 gpio3: gpio@30220000 {
543 compatible = " 341 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
544 reg = <0x30220 342 reg = <0x30220000 0x10000>;
545 interrupts = < 343 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
546 < 344 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clk 345 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
548 gpio-controlle 346 gpio-controller;
549 #gpio-cells = 347 #gpio-cells = <2>;
550 interrupt-cont 348 interrupt-controller;
551 #interrupt-cel 349 #interrupt-cells = <2>;
552 gpio-ranges = 350 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
553 }; 351 };
554 352
555 gpio4: gpio@30230000 { 353 gpio4: gpio@30230000 {
556 compatible = " 354 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
557 reg = <0x30230 355 reg = <0x30230000 0x10000>;
558 interrupts = < 356 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
559 < 357 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clk 358 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
561 gpio-controlle 359 gpio-controller;
562 #gpio-cells = 360 #gpio-cells = <2>;
563 interrupt-cont 361 interrupt-controller;
564 #interrupt-cel 362 #interrupt-cells = <2>;
565 gpio-ranges = 363 gpio-ranges = <&iomuxc 0 82 32>;
566 }; 364 };
567 365
568 gpio5: gpio@30240000 { 366 gpio5: gpio@30240000 {
569 compatible = " 367 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
570 reg = <0x30240 368 reg = <0x30240000 0x10000>;
571 interrupts = < 369 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
572 < 370 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk 371 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
574 gpio-controlle 372 gpio-controller;
575 #gpio-cells = 373 #gpio-cells = <2>;
576 interrupt-cont 374 interrupt-controller;
577 #interrupt-cel 375 #interrupt-cells = <2>;
578 gpio-ranges = 376 gpio-ranges = <&iomuxc 0 114 30>;
579 }; 377 };
580 378
581 tmu: tmu@30260000 { 379 tmu: tmu@30260000 {
582 compatible = " 380 compatible = "fsl,imx8mp-tmu";
583 reg = <0x30260 381 reg = <0x30260000 0x10000>;
584 clocks = <&clk 382 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
585 nvmem-cells = <<
586 nvmem-cell-nam <<
587 #thermal-senso 383 #thermal-sensor-cells = <1>;
588 }; 384 };
589 385
590 wdog1: watchdog@302800 386 wdog1: watchdog@30280000 {
591 compatible = " 387 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
592 reg = <0x30280 388 reg = <0x30280000 0x10000>;
593 interrupts = < 389 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clk 390 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
595 status = "disa 391 status = "disabled";
596 }; 392 };
597 393
598 wdog2: watchdog@302900 394 wdog2: watchdog@30290000 {
599 compatible = " 395 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
600 reg = <0x30290 396 reg = <0x30290000 0x10000>;
601 interrupts = < 397 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk 398 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
603 status = "disa 399 status = "disabled";
604 }; 400 };
605 401
606 wdog3: watchdog@302a00 402 wdog3: watchdog@302a0000 {
607 compatible = " 403 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
608 reg = <0x302a0 404 reg = <0x302a0000 0x10000>;
609 interrupts = < 405 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clk 406 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
611 status = "disa 407 status = "disabled";
612 }; 408 };
613 409
614 gpt1: timer@302d0000 { <<
615 compatible = " <<
616 reg = <0x302d0 <<
617 interrupts = < <<
618 clocks = <&clk <<
619 clock-names = <<
620 }; <<
621 <<
622 gpt2: timer@302e0000 { <<
623 compatible = " <<
624 reg = <0x302e0 <<
625 interrupts = < <<
626 clocks = <&clk <<
627 clock-names = <<
628 }; <<
629 <<
630 gpt3: timer@302f0000 { <<
631 compatible = " <<
632 reg = <0x302f0 <<
633 interrupts = < <<
634 clocks = <&clk <<
635 clock-names = <<
636 }; <<
637 <<
638 iomuxc: pinctrl@303300 410 iomuxc: pinctrl@30330000 {
639 compatible = " 411 compatible = "fsl,imx8mp-iomuxc";
640 reg = <0x30330 412 reg = <0x30330000 0x10000>;
641 }; 413 };
642 414
643 gpr: syscon@30340000 { !! 415 gpr: iomuxc-gpr@30340000 {
644 compatible = " 416 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
645 reg = <0x30340 417 reg = <0x30340000 0x10000>;
646 }; 418 };
647 419
648 ocotp: efuse@30350000 420 ocotp: efuse@30350000 {
649 compatible = " 421 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
650 reg = <0x30350 422 reg = <0x30350000 0x10000>;
651 clocks = <&clk 423 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
652 /* For nvmem s 424 /* For nvmem subnodes */
653 #address-cells 425 #address-cells = <1>;
654 #size-cells = 426 #size-cells = <1>;
655 427
656 /* !! 428 imx8mp_uid: unique-id@8 {
657 * The registe <<
658 * Fusemap Des <<
659 * Assuming <<
660 * reg = <AD <<
661 * then <<
662 * Fuse Addr <<
663 * Note that i <<
664 * each subseq <<
665 * +0x10 in Fu <<
666 * reg = <0x8 <<
667 * 0x430). <<
668 */ <<
669 imx8mp_uid: un <<
670 reg = 429 reg = <0x8 0x8>;
671 }; 430 };
672 431
673 cpu_speed_grad !! 432 cpu_speed_grade: speed-grade@10 {
674 reg = 433 reg = <0x10 4>;
675 }; 434 };
676 435
677 eth_mac1: mac- !! 436 eth_mac1: mac-address@90 {
678 reg = 437 reg = <0x90 6>;
679 }; 438 };
680 439
681 eth_mac2: mac- !! 440 eth_mac2: mac-address@96 {
682 reg = 441 reg = <0x96 6>;
683 }; 442 };
684 <<
685 tmu_calib: cal <<
686 reg = <<
687 }; <<
688 }; 443 };
689 444
690 anatop: clock-controll 445 anatop: clock-controller@30360000 {
691 compatible = " 446 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
692 reg = <0x30360 447 reg = <0x30360000 0x10000>;
693 #clock-cells = 448 #clock-cells = <1>;
694 }; 449 };
695 450
696 snvs: snvs@30370000 { 451 snvs: snvs@30370000 {
697 compatible = " 452 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 reg = <0x30370 453 reg = <0x30370000 0x10000>;
699 454
700 snvs_rtc: snvs 455 snvs_rtc: snvs-rtc-lp {
701 compat 456 compatible = "fsl,sec-v4.0-mon-rtc-lp";
702 regmap !! 457 regmap =<&snvs>;
703 offset 458 offset = <0x34>;
704 interr 459 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
705 460 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
706 clocks 461 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
707 clock- 462 clock-names = "snvs-rtc";
708 }; 463 };
709 464
710 snvs_pwrkey: s 465 snvs_pwrkey: snvs-powerkey {
711 compat 466 compatible = "fsl,sec-v4.0-pwrkey";
712 regmap 467 regmap = <&snvs>;
713 interr 468 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
714 clocks 469 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
715 clock- 470 clock-names = "snvs-pwrkey";
716 linux, 471 linux,keycode = <KEY_POWER>;
717 wakeup 472 wakeup-source;
718 status 473 status = "disabled";
719 }; 474 };
720 475
721 snvs_lpgpr: sn 476 snvs_lpgpr: snvs-lpgpr {
722 compat 477 compatible = "fsl,imx8mp-snvs-lpgpr",
723 478 "fsl,imx7d-snvs-lpgpr";
724 }; 479 };
725 }; 480 };
726 481
727 clk: clock-controller@ 482 clk: clock-controller@30380000 {
728 compatible = " 483 compatible = "fsl,imx8mp-ccm";
729 reg = <0x30380 484 reg = <0x30380000 0x10000>;
730 interrupts = < <<
731 < <<
732 #clock-cells = 485 #clock-cells = <1>;
733 clocks = <&osc 486 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
734 <&clk 487 <&clk_ext3>, <&clk_ext4>;
735 clock-names = 488 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
736 489 "clk_ext3", "clk_ext4";
737 assigned-clock 490 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 491 <&clk IMX8MP_CLK_A53_CORE>,
739 492 <&clk IMX8MP_CLK_NOC>,
740 493 <&clk IMX8MP_CLK_NOC_IO>,
741 !! 494 <&clk IMX8MP_CLK_GIC>,
>> 495 <&clk IMX8MP_CLK_AUDIO_AHB>,
>> 496 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>,
>> 497 <&clk IMX8MP_AUDIO_PLL1>,
>> 498 <&clk IMX8MP_AUDIO_PLL2>;
742 assigned-clock 499 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 500 <&clk IMX8MP_ARM_PLL_OUT>,
744 501 <&clk IMX8MP_SYS_PLL2_1000M>,
745 502 <&clk IMX8MP_SYS_PLL1_800M>,
746 !! 503 <&clk IMX8MP_SYS_PLL2_500M>,
>> 504 <&clk IMX8MP_SYS_PLL1_800M>,
>> 505 <&clk IMX8MP_SYS_PLL1_800M>;
747 assigned-clock 506 assigned-clock-rates = <0>, <0>,
748 507 <1000000000>,
749 508 <800000000>,
750 !! 509 <500000000>,
>> 510 <400000000>,
>> 511 <800000000>,
>> 512 <393216000>,
>> 513 <361267200>;
751 }; 514 };
752 515
753 src: reset-controller@ 516 src: reset-controller@30390000 {
754 compatible = " 517 compatible = "fsl,imx8mp-src", "syscon";
755 reg = <0x30390 518 reg = <0x30390000 0x10000>;
756 interrupts = < 519 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
757 #reset-cells = 520 #reset-cells = <1>;
758 }; 521 };
759 522
760 gpc: gpc@303a0000 { 523 gpc: gpc@303a0000 {
761 compatible = " 524 compatible = "fsl,imx8mp-gpc";
762 reg = <0x303a0 525 reg = <0x303a0000 0x1000>;
763 interrupt-pare 526 interrupt-parent = <&gic>;
764 interrupts = < 527 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
765 interrupt-cont 528 interrupt-controller;
766 #interrupt-cel 529 #interrupt-cells = <3>;
767 530
768 pgc { 531 pgc {
769 #addre 532 #address-cells = <1>;
770 #size- 533 #size-cells = <0>;
771 534
772 pgc_mi 535 pgc_mipi_phy1: power-domain@0 {
773 536 #power-domain-cells = <0>;
774 537 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
775 }; 538 };
776 539
777 pgc_pc 540 pgc_pcie_phy: power-domain@1 {
778 541 #power-domain-cells = <0>;
779 542 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
780 }; 543 };
781 544
782 pgc_us 545 pgc_usb1_phy: power-domain@2 {
783 546 #power-domain-cells = <0>;
784 547 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
785 }; 548 };
786 549
787 pgc_us 550 pgc_usb2_phy: power-domain@3 {
788 551 #power-domain-cells = <0>;
789 552 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
790 }; 553 };
791 554
792 pgc_ml <<
793 <<
794 <<
795 <<
796 <<
797 <<
798 <<
799 <<
800 <<
801 <<
802 <<
803 <<
804 <<
805 <<
806 <<
807 }; <<
808 <<
809 pgc_au <<
810 <<
811 <<
812 <<
813 <<
814 <<
815 <<
816 <<
817 <<
818 <<
819 <<
820 }; <<
821 <<
822 pgc_gp 555 pgc_gpu2d: power-domain@6 {
823 556 #power-domain-cells = <0>;
824 557 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
825 558 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
826 559 power-domains = <&pgc_gpumix>;
827 }; 560 };
828 561
829 pgc_gp 562 pgc_gpumix: power-domain@7 {
830 563 #power-domain-cells = <0>;
831 564 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
832 565 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
833 566 <&clk IMX8MP_CLK_GPU_AHB>;
834 567 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
835 568 <&clk IMX8MP_CLK_GPU_AHB>;
836 569 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
837 570 <&clk IMX8MP_SYS_PLL1_800M>;
838 571 assigned-clock-rates = <800000000>, <400000000>;
839 }; 572 };
840 573
841 pgc_vp <<
842 <<
843 <<
844 <<
845 }; <<
846 <<
847 pgc_gp 574 pgc_gpu3d: power-domain@9 {
848 575 #power-domain-cells = <0>;
849 576 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
850 577 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
851 578 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
852 579 power-domains = <&pgc_gpumix>;
853 }; 580 };
854 581
855 pgc_me 582 pgc_mediamix: power-domain@10 {
856 583 #power-domain-cells = <0>;
857 584 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
858 585 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
859 586 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
860 }; 587 };
861 588
862 pgc_vp !! 589 pgc_mipi_phy2: power-domain@16 {
863 590 #power-domain-cells = <0>;
864 !! 591 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
865 <<
866 <<
867 }; 592 };
868 593
869 pgc_vp !! 594 pgc_hsiomix: power-domain@17 {
870 595 #power-domain-cells = <0>;
871 !! 596 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
872 !! 597 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
873 !! 598 <&clk IMX8MP_CLK_HSIO_ROOT>;
874 !! 599 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
>> 600 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
>> 601 assigned-clock-rates = <500000000>;
875 }; 602 };
876 603
877 pgc_vp !! 604 pgc_ispdwp: power-domain@18 {
878 605 #power-domain-cells = <0>;
879 !! 606 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
880 !! 607 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
881 <<
882 }; 608 };
883 609
884 pgc_hd !! 610 pgc_vpumix: power-domain@19 {
885 611 #power-domain-cells = <0>;
886 !! 612 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
887 !! 613 clocks =<&clk IMX8MP_CLK_VPU_ROOT>;
888 <<
889 <<
890 <<
891 <<
892 <<
893 <<
894 }; 614 };
895 615
896 pgc_hd !! 616 pgc_vpu_g1: power-domain@20 {
897 617 #power-domain-cells = <0>;
898 !! 618 power-domains = <&pgc_vpumix>;
>> 619 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
>> 620 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
899 }; 621 };
900 622
901 pgc_mi !! 623 pgc_vpu_g2: power-domain@21 {
902 624 #power-domain-cells = <0>;
903 !! 625 power-domains = <&pgc_vpumix>;
>> 626 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
>> 627 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
904 }; 628 };
905 629
906 pgc_hs !! 630 pgc_vpu_vc8000e: power-domain@22 {
907 631 #power-domain-cells = <0>;
908 !! 632 power-domains = <&pgc_vpumix>;
909 !! 633 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
910 !! 634 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
911 <<
912 <<
913 <<
914 }; 635 };
915 636
916 pgc_is !! 637 pgc_mlmix: power-domain@24 {
917 638 #power-domain-cells = <0>;
918 !! 639 reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
919 !! 640 clocks = <&clk IMX8MP_CLK_ML_AXI>,
>> 641 <&clk IMX8MP_CLK_ML_AHB>,
>> 642 <&clk IMX8MP_CLK_NPU_ROOT>;
920 }; 643 };
921 }; 644 };
922 }; 645 };
923 }; 646 };
924 647
925 aips2: bus@30400000 { 648 aips2: bus@30400000 {
926 compatible = "fsl,aips 649 compatible = "fsl,aips-bus", "simple-bus";
927 reg = <0x30400000 0x40 650 reg = <0x30400000 0x400000>;
928 #address-cells = <1>; 651 #address-cells = <1>;
929 #size-cells = <1>; 652 #size-cells = <1>;
930 ranges; 653 ranges;
931 654
932 pwm1: pwm@30660000 { 655 pwm1: pwm@30660000 {
933 compatible = " 656 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
934 reg = <0x30660 657 reg = <0x30660000 0x10000>;
935 interrupts = < 658 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clk 659 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
937 <&clk 660 <&clk IMX8MP_CLK_PWM1_ROOT>;
938 clock-names = 661 clock-names = "ipg", "per";
939 #pwm-cells = < 662 #pwm-cells = <3>;
940 status = "disa 663 status = "disabled";
941 }; 664 };
942 665
943 pwm2: pwm@30670000 { 666 pwm2: pwm@30670000 {
944 compatible = " 667 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
945 reg = <0x30670 668 reg = <0x30670000 0x10000>;
946 interrupts = < 669 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clk 670 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
948 <&clk 671 <&clk IMX8MP_CLK_PWM2_ROOT>;
949 clock-names = 672 clock-names = "ipg", "per";
950 #pwm-cells = < 673 #pwm-cells = <3>;
951 status = "disa 674 status = "disabled";
952 }; 675 };
953 676
954 pwm3: pwm@30680000 { 677 pwm3: pwm@30680000 {
955 compatible = " 678 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
956 reg = <0x30680 679 reg = <0x30680000 0x10000>;
957 interrupts = < 680 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clk 681 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
959 <&clk 682 <&clk IMX8MP_CLK_PWM3_ROOT>;
960 clock-names = 683 clock-names = "ipg", "per";
961 #pwm-cells = < 684 #pwm-cells = <3>;
962 status = "disa 685 status = "disabled";
963 }; 686 };
964 687
965 pwm4: pwm@30690000 { 688 pwm4: pwm@30690000 {
966 compatible = " 689 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
967 reg = <0x30690 690 reg = <0x30690000 0x10000>;
968 interrupts = < 691 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clk 692 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
970 <&clk 693 <&clk IMX8MP_CLK_PWM4_ROOT>;
971 clock-names = 694 clock-names = "ipg", "per";
972 #pwm-cells = < 695 #pwm-cells = <3>;
973 status = "disa 696 status = "disabled";
974 }; 697 };
975 698
976 system_counter: timer@ 699 system_counter: timer@306a0000 {
977 compatible = " 700 compatible = "nxp,sysctr-timer";
978 reg = <0x306a0 701 reg = <0x306a0000 0x20000>;
979 interrupts = < 702 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&osc 703 clocks = <&osc_24m>;
981 clock-names = 704 clock-names = "per";
982 }; 705 };
983 <<
984 gpt6: timer@306e0000 { <<
985 compatible = " <<
986 reg = <0x306e0 <<
987 interrupts = < <<
988 clocks = <&clk <<
989 clock-names = <<
990 }; <<
991 <<
992 gpt5: timer@306f0000 { <<
993 compatible = " <<
994 reg = <0x306f0 <<
995 interrupts = < <<
996 clocks = <&clk <<
997 clock-names = <<
998 }; <<
999 <<
1000 gpt4: timer@30700000 <<
1001 compatible = <<
1002 reg = <0x3070 <<
1003 interrupts = <<
1004 clocks = <&cl <<
1005 clock-names = <<
1006 }; <<
1007 }; 706 };
1008 707
1009 aips3: bus@30800000 { 708 aips3: bus@30800000 {
1010 compatible = "fsl,aip 709 compatible = "fsl,aips-bus", "simple-bus";
1011 reg = <0x30800000 0x4 710 reg = <0x30800000 0x400000>;
1012 #address-cells = <1>; 711 #address-cells = <1>;
1013 #size-cells = <1>; 712 #size-cells = <1>;
1014 ranges; 713 ranges;
1015 714
1016 spba-bus@30800000 { !! 715 ecspi1: spi@30820000 {
1017 compatible = <<
1018 reg = <0x3080 <<
1019 #address-cell 716 #address-cells = <1>;
1020 #size-cells = !! 717 #size-cells = <0>;
1021 ranges; !! 718 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1022 !! 719 reg = <0x30820000 0x10000>;
1023 ecspi1: spi@3 !! 720 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1024 #addr !! 721 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
1025 #size !! 722 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1026 compa !! 723 clock-names = "ipg", "per";
1027 reg = !! 724 assigned-clock-rates = <80000000>;
1028 inter !! 725 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1029 clock !! 726 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1030 !! 727 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1031 clock !! 728 dma-names = "rx", "tx";
1032 assig !! 729 status = "disabled";
1033 assig !! 730 };
1034 assig <<
1035 dmas <<
1036 dma-n <<
1037 statu <<
1038 }; <<
1039 731
1040 ecspi2: spi@3 !! 732 ecspi2: spi@30830000 {
1041 #addr !! 733 #address-cells = <1>;
1042 #size !! 734 #size-cells = <0>;
1043 compa !! 735 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1044 reg = !! 736 reg = <0x30830000 0x10000>;
1045 inter !! 737 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1046 clock !! 738 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1047 !! 739 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1048 clock !! 740 clock-names = "ipg", "per";
1049 assig !! 741 assigned-clock-rates = <80000000>;
1050 assig !! 742 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1051 assig !! 743 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1052 dmas !! 744 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1053 dma-n !! 745 dma-names = "rx", "tx";
1054 statu !! 746 status = "disabled";
1055 }; !! 747 };
1056 748
1057 ecspi3: spi@3 !! 749 ecspi3: spi@30840000 {
1058 #addr !! 750 #address-cells = <1>;
1059 #size !! 751 #size-cells = <0>;
1060 compa !! 752 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1061 reg = !! 753 reg = <0x30840000 0x10000>;
1062 inter !! 754 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1063 clock !! 755 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1064 !! 756 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1065 clock !! 757 clock-names = "ipg", "per";
1066 assig !! 758 assigned-clock-rates = <80000000>;
1067 assig !! 759 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1068 assig !! 760 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1069 dmas !! 761 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1070 dma-n !! 762 dma-names = "rx", "tx";
1071 statu !! 763 status = "disabled";
1072 }; !! 764 };
1073 765
1074 uart1: serial !! 766 uart1: serial@30860000 {
1075 compa !! 767 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1076 reg = !! 768 reg = <0x30860000 0x10000>;
1077 inter !! 769 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1078 clock !! 770 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1079 !! 771 <&clk IMX8MP_CLK_UART1_ROOT>;
1080 clock !! 772 clock-names = "ipg", "per";
1081 dmas !! 773 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1082 dma-n !! 774 dma-names = "rx", "tx";
1083 statu !! 775 status = "disabled";
1084 }; !! 776 };
1085 777
1086 uart3: serial !! 778 uart3: serial@30880000 {
1087 compa !! 779 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1088 reg = !! 780 reg = <0x30880000 0x10000>;
1089 inter !! 781 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1090 clock !! 782 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1091 !! 783 <&clk IMX8MP_CLK_UART3_ROOT>;
1092 clock !! 784 clock-names = "ipg", "per";
1093 dmas !! 785 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1094 dma-n !! 786 dma-names = "rx", "tx";
1095 statu !! 787 status = "disabled";
1096 }; !! 788 };
1097 789
1098 uart2: serial !! 790 uart2: serial@30890000 {
1099 compa !! 791 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1100 reg = !! 792 reg = <0x30890000 0x10000>;
1101 inter !! 793 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1102 clock !! 794 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1103 !! 795 <&clk IMX8MP_CLK_UART2_ROOT>;
1104 clock !! 796 clock-names = "ipg", "per";
1105 dmas !! 797 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1106 dma-n !! 798 dma-names = "rx", "tx";
1107 statu !! 799 status = "disabled";
1108 }; !! 800 };
1109 801
1110 flexcan1: can !! 802 flexcan1: can@308c0000 {
1111 compa !! 803 compatible = "fsl,imx8mp-flexcan";
1112 reg = !! 804 reg = <0x308c0000 0x10000>;
1113 inter !! 805 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1114 clock !! 806 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1115 !! 807 <&clk IMX8MP_CLK_CAN1_ROOT>;
1116 clock !! 808 clock-names = "ipg", "per";
1117 assig !! 809 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1118 assig !! 810 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1119 assig !! 811 assigned-clock-rates = <40000000>;
1120 fsl,c !! 812 fsl,clk-source = /bits/ 8 <0>;
1121 fsl,s !! 813 fsl,stop-mode = <&gpr 0x10 4>;
1122 statu !! 814 status = "disabled";
1123 }; !! 815 };
1124 816
1125 flexcan2: can !! 817 flexcan2: can@308d0000 {
1126 compa !! 818 compatible = "fsl,imx8mp-flexcan";
1127 reg = !! 819 reg = <0x308d0000 0x10000>;
1128 inter !! 820 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1129 clock !! 821 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1130 !! 822 <&clk IMX8MP_CLK_CAN2_ROOT>;
1131 clock !! 823 clock-names = "ipg", "per";
1132 assig !! 824 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1133 assig !! 825 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1134 assig !! 826 assigned-clock-rates = <40000000>;
1135 fsl,c !! 827 fsl,clk-source = /bits/ 8 <0>;
1136 fsl,s !! 828 fsl,stop-mode = <&gpr 0x10 5>;
1137 statu !! 829 status = "disabled";
1138 }; <<
1139 }; 830 };
1140 831
1141 crypto: crypto@309000 832 crypto: crypto@30900000 {
1142 compatible = 833 compatible = "fsl,sec-v4.0";
1143 #address-cell 834 #address-cells = <1>;
1144 #size-cells = 835 #size-cells = <1>;
1145 reg = <0x3090 836 reg = <0x30900000 0x40000>;
1146 ranges = <0 0 837 ranges = <0 0x30900000 0x40000>;
1147 interrupts = 838 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&cl 839 clocks = <&clk IMX8MP_CLK_AHB>,
1149 <&cl 840 <&clk IMX8MP_CLK_IPG_ROOT>;
1150 clock-names = 841 clock-names = "aclk", "ipg";
1151 842
1152 sec_jr0: jr@1 843 sec_jr0: jr@1000 {
1153 compa 844 compatible = "fsl,sec-v4.0-job-ring";
1154 reg = 845 reg = <0x1000 0x1000>;
1155 inter 846 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1156 statu 847 status = "disabled";
1157 }; 848 };
1158 849
1159 sec_jr1: jr@2 850 sec_jr1: jr@2000 {
1160 compa 851 compatible = "fsl,sec-v4.0-job-ring";
1161 reg = 852 reg = <0x2000 0x1000>;
1162 inter 853 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1163 }; 854 };
1164 855
1165 sec_jr2: jr@3 856 sec_jr2: jr@3000 {
1166 compa 857 compatible = "fsl,sec-v4.0-job-ring";
1167 reg = 858 reg = <0x3000 0x1000>;
1168 inter 859 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1169 }; 860 };
1170 }; 861 };
1171 862
1172 i2c1: i2c@30a20000 { 863 i2c1: i2c@30a20000 {
1173 compatible = 864 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1174 #address-cell 865 #address-cells = <1>;
1175 #size-cells = 866 #size-cells = <0>;
1176 reg = <0x30a2 867 reg = <0x30a20000 0x10000>;
1177 interrupts = 868 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cl 869 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1179 status = "dis 870 status = "disabled";
1180 }; 871 };
1181 872
1182 i2c2: i2c@30a30000 { 873 i2c2: i2c@30a30000 {
1183 compatible = 874 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1184 #address-cell 875 #address-cells = <1>;
1185 #size-cells = 876 #size-cells = <0>;
1186 reg = <0x30a3 877 reg = <0x30a30000 0x10000>;
1187 interrupts = 878 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&cl 879 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1189 status = "dis 880 status = "disabled";
1190 }; 881 };
1191 882
1192 i2c3: i2c@30a40000 { 883 i2c3: i2c@30a40000 {
1193 compatible = 884 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1194 #address-cell 885 #address-cells = <1>;
1195 #size-cells = 886 #size-cells = <0>;
1196 reg = <0x30a4 887 reg = <0x30a40000 0x10000>;
1197 interrupts = 888 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&cl 889 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1199 status = "dis 890 status = "disabled";
1200 }; 891 };
1201 892
1202 i2c4: i2c@30a50000 { 893 i2c4: i2c@30a50000 {
1203 compatible = 894 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1204 #address-cell 895 #address-cells = <1>;
1205 #size-cells = 896 #size-cells = <0>;
1206 reg = <0x30a5 897 reg = <0x30a50000 0x10000>;
1207 interrupts = 898 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cl 899 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1209 status = "dis 900 status = "disabled";
1210 }; 901 };
1211 902
1212 uart4: serial@30a6000 903 uart4: serial@30a60000 {
1213 compatible = 904 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1214 reg = <0x30a6 905 reg = <0x30a60000 0x10000>;
1215 interrupts = 906 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&cl 907 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1217 <&cl 908 <&clk IMX8MP_CLK_UART4_ROOT>;
1218 clock-names = 909 clock-names = "ipg", "per";
1219 dmas = <&sdma 910 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1220 dma-names = " 911 dma-names = "rx", "tx";
1221 status = "dis 912 status = "disabled";
1222 }; 913 };
1223 914
1224 mu: mailbox@30aa0000 915 mu: mailbox@30aa0000 {
1225 compatible = 916 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1226 reg = <0x30aa 917 reg = <0x30aa0000 0x10000>;
1227 interrupts = 918 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&cl 919 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1229 #mbox-cells = 920 #mbox-cells = <2>;
1230 }; 921 };
1231 922
1232 mu2: mailbox@30e60000 923 mu2: mailbox@30e60000 {
1233 compatible = 924 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1234 reg = <0x30e6 925 reg = <0x30e60000 0x10000>;
1235 interrupts = 926 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1236 #mbox-cells = 927 #mbox-cells = <2>;
1237 status = "dis 928 status = "disabled";
1238 }; 929 };
1239 930
1240 i2c5: i2c@30ad0000 { 931 i2c5: i2c@30ad0000 {
1241 compatible = 932 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1242 #address-cell 933 #address-cells = <1>;
1243 #size-cells = 934 #size-cells = <0>;
1244 reg = <0x30ad 935 reg = <0x30ad0000 0x10000>;
1245 interrupts = 936 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&cl 937 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1247 status = "dis 938 status = "disabled";
1248 }; 939 };
1249 940
1250 i2c6: i2c@30ae0000 { 941 i2c6: i2c@30ae0000 {
1251 compatible = 942 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1252 #address-cell 943 #address-cells = <1>;
1253 #size-cells = 944 #size-cells = <0>;
1254 reg = <0x30ae 945 reg = <0x30ae0000 0x10000>;
1255 interrupts = 946 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cl 947 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1257 status = "dis 948 status = "disabled";
1258 }; 949 };
1259 950
1260 usdhc1: mmc@30b40000 951 usdhc1: mmc@30b40000 {
1261 compatible = 952 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1262 reg = <0x30b4 953 reg = <0x30b40000 0x10000>;
1263 interrupts = 954 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cl !! 955 clocks = <&clk IMX8MP_CLK_DUMMY>,
1265 <&cl 956 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1266 <&cl 957 <&clk IMX8MP_CLK_USDHC1_ROOT>;
1267 clock-names = 958 clock-names = "ipg", "ahb", "per";
1268 fsl,tuning-st 959 fsl,tuning-start-tap = <20>;
1269 fsl,tuning-st 960 fsl,tuning-step = <2>;
1270 bus-width = < 961 bus-width = <4>;
1271 status = "dis 962 status = "disabled";
1272 }; 963 };
1273 964
1274 usdhc2: mmc@30b50000 965 usdhc2: mmc@30b50000 {
1275 compatible = 966 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1276 reg = <0x30b5 967 reg = <0x30b50000 0x10000>;
1277 interrupts = 968 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&cl !! 969 clocks = <&clk IMX8MP_CLK_DUMMY>,
1279 <&cl 970 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1280 <&cl 971 <&clk IMX8MP_CLK_USDHC2_ROOT>;
1281 clock-names = 972 clock-names = "ipg", "ahb", "per";
1282 fsl,tuning-st 973 fsl,tuning-start-tap = <20>;
1283 fsl,tuning-st 974 fsl,tuning-step = <2>;
1284 bus-width = < 975 bus-width = <4>;
1285 status = "dis 976 status = "disabled";
1286 }; 977 };
1287 978
1288 usdhc3: mmc@30b60000 979 usdhc3: mmc@30b60000 {
1289 compatible = 980 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1290 reg = <0x30b6 981 reg = <0x30b60000 0x10000>;
1291 interrupts = 982 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cl !! 983 clocks = <&clk IMX8MP_CLK_DUMMY>,
1293 <&cl 984 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1294 <&cl 985 <&clk IMX8MP_CLK_USDHC3_ROOT>;
1295 clock-names = 986 clock-names = "ipg", "ahb", "per";
1296 fsl,tuning-st 987 fsl,tuning-start-tap = <20>;
1297 fsl,tuning-st 988 fsl,tuning-step = <2>;
1298 bus-width = < 989 bus-width = <4>;
1299 status = "dis 990 status = "disabled";
1300 }; 991 };
1301 992
1302 flexspi: spi@30bb0000 993 flexspi: spi@30bb0000 {
1303 compatible = 994 compatible = "nxp,imx8mp-fspi";
1304 reg = <0x30bb 995 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1305 reg-names = " 996 reg-names = "fspi_base", "fspi_mmap";
1306 interrupts = 997 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&cl 998 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1308 <&cl 999 <&clk IMX8MP_CLK_QSPI_ROOT>;
1309 clock-names = 1000 clock-names = "fspi_en", "fspi";
1310 assigned-cloc 1001 assigned-clock-rates = <80000000>;
1311 assigned-cloc 1002 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1312 #address-cell 1003 #address-cells = <1>;
1313 #size-cells = 1004 #size-cells = <0>;
1314 status = "dis 1005 status = "disabled";
1315 }; 1006 };
1316 1007
1317 sdma1: dma-controller 1008 sdma1: dma-controller@30bd0000 {
1318 compatible = 1009 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1319 reg = <0x30bd 1010 reg = <0x30bd0000 0x10000>;
1320 interrupts = 1011 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&cl 1012 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1322 <&cl 1013 <&clk IMX8MP_CLK_AHB>;
1323 clock-names = 1014 clock-names = "ipg", "ahb";
1324 #dma-cells = 1015 #dma-cells = <3>;
1325 fsl,sdma-ram- 1016 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1326 }; 1017 };
1327 1018
1328 fec: ethernet@30be000 1019 fec: ethernet@30be0000 {
1329 compatible = 1020 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1330 reg = <0x30be 1021 reg = <0x30be0000 0x10000>;
1331 interrupts = 1022 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1332 1023 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1333 1024 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1334 1025 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&cl 1026 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1336 <&cl 1027 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1337 <&cl 1028 <&clk IMX8MP_CLK_ENET_TIMER>,
1338 <&cl 1029 <&clk IMX8MP_CLK_ENET_REF>,
1339 <&cl 1030 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1340 clock-names = 1031 clock-names = "ipg", "ahb", "ptp",
1341 1032 "enet_clk_ref", "enet_out";
1342 assigned-cloc 1033 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1343 1034 <&clk IMX8MP_CLK_ENET_TIMER>,
1344 1035 <&clk IMX8MP_CLK_ENET_REF>,
1345 1036 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1346 assigned-cloc 1037 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1347 1038 <&clk IMX8MP_SYS_PLL2_100M>,
1348 1039 <&clk IMX8MP_SYS_PLL2_125M>,
1349 1040 <&clk IMX8MP_SYS_PLL2_50M>;
1350 assigned-cloc 1041 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1351 fsl,num-tx-qu 1042 fsl,num-tx-queues = <3>;
1352 fsl,num-rx-qu 1043 fsl,num-rx-queues = <3>;
1353 nvmem-cells = 1044 nvmem-cells = <ð_mac1>;
1354 nvmem-cell-na 1045 nvmem-cell-names = "mac-address";
1355 fsl,stop-mode 1046 fsl,stop-mode = <&gpr 0x10 3>;
1356 status = "dis 1047 status = "disabled";
1357 }; 1048 };
1358 1049
1359 eqos: ethernet@30bf00 1050 eqos: ethernet@30bf0000 {
1360 compatible = 1051 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1361 reg = <0x30bf 1052 reg = <0x30bf0000 0x10000>;
1362 interrupts = 1053 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1363 1054 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1364 interrupt-nam 1055 interrupt-names = "macirq", "eth_wake_irq";
1365 clocks = <&cl 1056 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1366 <&cl 1057 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1367 <&cl 1058 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1368 <&cl 1059 <&clk IMX8MP_CLK_ENET_QOS>;
1369 clock-names = 1060 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1370 assigned-cloc 1061 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1371 1062 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1372 1063 <&clk IMX8MP_CLK_ENET_QOS>;
1373 assigned-cloc 1064 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1374 1065 <&clk IMX8MP_SYS_PLL2_100M>,
1375 1066 <&clk IMX8MP_SYS_PLL2_125M>;
1376 assigned-cloc 1067 assigned-clock-rates = <0>, <100000000>, <125000000>;
1377 nvmem-cells = 1068 nvmem-cells = <ð_mac2>;
1378 nvmem-cell-na 1069 nvmem-cell-names = "mac-address";
1379 intf_mode = < 1070 intf_mode = <&gpr 0x4>;
1380 status = "dis 1071 status = "disabled";
1381 }; 1072 };
1382 }; 1073 };
1383 1074
1384 aips5: bus@30c00000 { <<
1385 compatible = "fsl,aip <<
1386 reg = <0x30c00000 0x4 <<
1387 #address-cells = <1>; <<
1388 #size-cells = <1>; <<
1389 ranges; <<
1390 <<
1391 spba-bus@30c00000 { <<
1392 compatible = <<
1393 reg = <0x30c0 <<
1394 #address-cell <<
1395 #size-cells = <<
1396 ranges; <<
1397 <<
1398 sai1: sai@30c <<
1399 compa <<
1400 reg = <<
1401 #soun <<
1402 clock <<
1403 <<
1404 <<
1405 <<
1406 <<
1407 clock <<
1408 dmas <<
1409 dma-n <<
1410 inter <<
1411 statu <<
1412 }; <<
1413 <<
1414 sai2: sai@30c <<
1415 compa <<
1416 reg = <<
1417 #soun <<
1418 clock <<
1419 <<
1420 <<
1421 <<
1422 <<
1423 clock <<
1424 dmas <<
1425 dma-n <<
1426 inter <<
1427 statu <<
1428 }; <<
1429 <<
1430 sai3: sai@30c <<
1431 compa <<
1432 reg = <<
1433 #soun <<
1434 clock <<
1435 <<
1436 <<
1437 <<
1438 <<
1439 clock <<
1440 dmas <<
1441 dma-n <<
1442 inter <<
1443 statu <<
1444 }; <<
1445 <<
1446 sai5: sai@30c <<
1447 compa <<
1448 reg = <<
1449 #soun <<
1450 clock <<
1451 <<
1452 <<
1453 <<
1454 <<
1455 clock <<
1456 dmas <<
1457 dma-n <<
1458 inter <<
1459 statu <<
1460 }; <<
1461 <<
1462 sai6: sai@30c <<
1463 compa <<
1464 reg = <<
1465 #soun <<
1466 clock <<
1467 <<
1468 <<
1469 <<
1470 <<
1471 clock <<
1472 dmas <<
1473 dma-n <<
1474 inter <<
1475 statu <<
1476 }; <<
1477 <<
1478 sai7: sai@30c <<
1479 compa <<
1480 reg = <<
1481 #soun <<
1482 clock <<
1483 <<
1484 <<
1485 <<
1486 <<
1487 clock <<
1488 dmas <<
1489 dma-n <<
1490 inter <<
1491 statu <<
1492 }; <<
1493 <<
1494 easrc: easrc@ <<
1495 compa <<
1496 reg = <<
1497 inter <<
1498 clock <<
1499 clock <<
1500 dmas <<
1501 <<
1502 <<
1503 <<
1504 dma-n <<
1505 <<
1506 <<
1507 <<
1508 firmw <<
1509 fsl,a <<
1510 fsl,a <<
1511 statu <<
1512 }; <<
1513 <<
1514 micfil: audio <<
1515 compa <<
1516 reg = <<
1517 #soun <<
1518 inter <<
1519 <<
1520 <<
1521 <<
1522 clock <<
1523 <<
1524 <<
1525 <<
1526 <<
1527 clock <<
1528 <<
1529 dmas <<
1530 dma-n <<
1531 statu <<
1532 }; <<
1533 <<
1534 aud2htx: aud2 <<
1535 compa <<
1536 reg = <<
1537 inter <<
1538 clock <<
1539 clock <<
1540 dmas <<
1541 dma-n <<
1542 statu <<
1543 }; <<
1544 <<
1545 xcvr: xcvr@30 <<
1546 compa <<
1547 reg = <<
1548 <<
1549 <<
1550 <<
1551 reg-n <<
1552 <<
1553 inter <<
1554 <<
1555 <<
1556 <<
1557 <<
1558 <<
1559 clock <<
1560 <<
1561 <<
1562 <<
1563 clock <<
1564 dmas <<
1565 dma-n <<
1566 reset <<
1567 statu <<
1568 }; <<
1569 }; <<
1570 <<
1571 sdma3: dma-controller <<
1572 compatible = <<
1573 reg = <0x30e0 <<
1574 #dma-cells = <<
1575 clocks = <&au <<
1576 <&cl <<
1577 clock-names = <<
1578 interrupts = <<
1579 fsl,sdma-ram- <<
1580 }; <<
1581 <<
1582 sdma2: dma-controller <<
1583 compatible = <<
1584 reg = <0x30e1 <<
1585 #dma-cells = <<
1586 clocks = <&au <<
1587 <&cl <<
1588 clock-names = <<
1589 interrupts = <<
1590 fsl,sdma-ram- <<
1591 }; <<
1592 <<
1593 audio_blk_ctrl: clock <<
1594 compatible = <<
1595 reg = <0x30e2 <<
1596 #clock-cells <<
1597 #reset-cells <<
1598 clocks = <&cl <<
1599 <&cl <<
1600 <&cl <<
1601 <&cl <<
1602 <&cl <<
1603 <&cl <<
1604 <&cl <<
1605 clock-names = <<
1606 <<
1607 <<
1608 power-domains <<
1609 assigned-cloc <<
1610 <<
1611 assigned-cloc <<
1612 }; <<
1613 }; <<
1614 <<
1615 noc: interconnect@32700000 { 1075 noc: interconnect@32700000 {
1616 compatible = "fsl,imx 1076 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1617 reg = <0x32700000 0x1 1077 reg = <0x32700000 0x100000>;
1618 clocks = <&clk IMX8MP 1078 clocks = <&clk IMX8MP_CLK_NOC>;
1619 #interconnect-cells = 1079 #interconnect-cells = <1>;
1620 operating-points-v2 = 1080 operating-points-v2 = <&noc_opp_table>;
1621 1081
1622 noc_opp_table: opp-ta 1082 noc_opp_table: opp-table {
1623 compatible = 1083 compatible = "operating-points-v2";
1624 1084
1625 opp-200000000 1085 opp-200000000 {
1626 opp-h 1086 opp-hz = /bits/ 64 <200000000>;
1627 }; 1087 };
1628 1088
1629 opp-100000000 1089 opp-1000000000 {
1630 opp-h 1090 opp-hz = /bits/ 64 <1000000000>;
1631 }; 1091 };
1632 }; 1092 };
1633 }; 1093 };
1634 1094
1635 aips4: bus@32c00000 { 1095 aips4: bus@32c00000 {
1636 compatible = "fsl,aip 1096 compatible = "fsl,aips-bus", "simple-bus";
1637 reg = <0x32c00000 0x4 1097 reg = <0x32c00000 0x400000>;
1638 #address-cells = <1>; 1098 #address-cells = <1>;
1639 #size-cells = <1>; 1099 #size-cells = <1>;
1640 ranges; 1100 ranges;
1641 1101
1642 isi_0: isi@32e00000 { <<
1643 compatible = <<
1644 reg = <0x32e0 <<
1645 interrupts = <<
1646 <<
1647 clocks = <&cl <<
1648 <&cl <<
1649 clock-names = <<
1650 fsl,blk-ctrl <<
1651 power-domains <<
1652 status = "dis <<
1653 <<
1654 ports { <<
1655 #addr <<
1656 #size <<
1657 <<
1658 port@ <<
1659 <<
1660 <<
1661 <<
1662 <<
1663 <<
1664 }; <<
1665 <<
1666 port@ <<
1667 <<
1668 <<
1669 <<
1670 <<
1671 <<
1672 }; <<
1673 }; <<
1674 }; <<
1675 <<
1676 isp_0: isp@32e10000 { <<
1677 compatible = <<
1678 reg = <0x32e1 <<
1679 interrupts = <<
1680 clocks = <&cl <<
1681 <&cl <<
1682 <&cl <<
1683 clock-names = <<
1684 power-domains <<
1685 fsl,blk-ctrl <<
1686 status = "dis <<
1687 <<
1688 ports { <<
1689 #addr <<
1690 #size <<
1691 <<
1692 port@ <<
1693 <<
1694 }; <<
1695 }; <<
1696 }; <<
1697 <<
1698 isp_1: isp@32e20000 { <<
1699 compatible = <<
1700 reg = <0x32e2 <<
1701 interrupts = <<
1702 clocks = <&cl <<
1703 <&cl <<
1704 <&cl <<
1705 clock-names = <<
1706 power-domains <<
1707 fsl,blk-ctrl <<
1708 status = "dis <<
1709 <<
1710 ports { <<
1711 #addr <<
1712 #size <<
1713 <<
1714 port@ <<
1715 <<
1716 }; <<
1717 }; <<
1718 }; <<
1719 <<
1720 dewarp: dwe@32e30000 <<
1721 compatible = <<
1722 reg = <0x32e3 <<
1723 interrupts = <<
1724 clocks = <&cl <<
1725 <&cl <<
1726 clock-names = <<
1727 power-domains <<
1728 }; <<
1729 <<
1730 mipi_csi_0: csi@32e40 <<
1731 compatible = <<
1732 reg = <0x32e4 <<
1733 interrupts = <<
1734 clock-frequen <<
1735 clocks = <&cl <<
1736 <&cl <<
1737 <&cl <<
1738 <&cl <<
1739 clock-names = <<
1740 assigned-cloc <<
1741 <<
1742 assigned-cloc <<
1743 <<
1744 power-domains <<
1745 status = "dis <<
1746 <<
1747 ports { <<
1748 #addr <<
1749 #size <<
1750 <<
1751 port@ <<
1752 <<
1753 }; <<
1754 <<
1755 port@ <<
1756 <<
1757 <<
1758 <<
1759 <<
1760 <<
1761 }; <<
1762 }; <<
1763 }; <<
1764 <<
1765 mipi_csi_1: csi@32e50 <<
1766 compatible = <<
1767 reg = <0x32e5 <<
1768 interrupts = <<
1769 clock-frequen <<
1770 clocks = <&cl <<
1771 <&cl <<
1772 <&cl <<
1773 <&cl <<
1774 clock-names = <<
1775 assigned-cloc <<
1776 <<
1777 assigned-cloc <<
1778 <<
1779 power-domains <<
1780 status = "dis <<
1781 <<
1782 ports { <<
1783 #addr <<
1784 #size <<
1785 <<
1786 port@ <<
1787 <<
1788 }; <<
1789 <<
1790 port@ <<
1791 <<
1792 <<
1793 <<
1794 <<
1795 <<
1796 }; <<
1797 }; <<
1798 }; <<
1799 <<
1800 mipi_dsi: dsi@32e6000 <<
1801 compatible = <<
1802 reg = <0x32e6 <<
1803 clocks = <&cl <<
1804 <&cl <<
1805 clock-names = <<
1806 assigned-cloc <<
1807 <<
1808 assigned-cloc <<
1809 <<
1810 assigned-cloc <<
1811 samsung,pll-c <<
1812 interrupts = <<
1813 power-domains <<
1814 status = "dis <<
1815 <<
1816 ports { <<
1817 #addr <<
1818 #size <<
1819 <<
1820 port@ <<
1821 <<
1822 <<
1823 <<
1824 <<
1825 <<
1826 }; <<
1827 <<
1828 port@ <<
1829 <<
1830 <<
1831 <<
1832 <<
1833 }; <<
1834 }; <<
1835 }; <<
1836 <<
1837 lcdif1: display-contr <<
1838 compatible = <<
1839 reg = <0x32e8 <<
1840 clocks = <&cl <<
1841 <&cl <<
1842 <&cl <<
1843 clock-names = <<
1844 interrupts = <<
1845 power-domains <<
1846 status = "dis <<
1847 <<
1848 port { <<
1849 lcdif <<
1850 <<
1851 }; <<
1852 }; <<
1853 }; <<
1854 <<
1855 lcdif2: display-contr <<
1856 compatible = <<
1857 reg = <0x32e9 <<
1858 interrupts = <<
1859 clocks = <&cl <<
1860 <&cl <<
1861 <&cl <<
1862 clock-names = <<
1863 power-domains <<
1864 status = "dis <<
1865 <<
1866 port { <<
1867 lcdif <<
1868 <<
1869 }; <<
1870 }; <<
1871 }; <<
1872 <<
1873 media_blk_ctrl: blk-c 1102 media_blk_ctrl: blk-ctrl@32ec0000 {
1874 compatible = 1103 compatible = "fsl,imx8mp-media-blk-ctrl",
1875 1104 "syscon";
1876 reg = <0x32ec 1105 reg = <0x32ec0000 0x10000>;
1877 #address-cell <<
1878 #size-cells = <<
1879 power-domains 1106 power-domains = <&pgc_mediamix>,
1880 1107 <&pgc_mipi_phy1>,
1881 1108 <&pgc_mipi_phy1>,
1882 1109 <&pgc_mediamix>,
1883 1110 <&pgc_mediamix>,
1884 1111 <&pgc_mipi_phy2>,
1885 1112 <&pgc_mediamix>,
1886 1113 <&pgc_ispdwp>,
1887 1114 <&pgc_ispdwp>,
1888 1115 <&pgc_mipi_phy2>;
1889 power-domain- 1116 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1890 1117 "lcdif1", "isi", "mipi-csi2",
1891 1118 "lcdif2", "isp", "dwe",
1892 1119 "mipi-dsi2";
1893 interconnects 1120 interconnects =
1894 <&noc 1121 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1895 <&noc 1122 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1896 <&noc 1123 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1897 <&noc 1124 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1898 <&noc 1125 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1899 <&noc 1126 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1900 <&noc 1127 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1901 <&noc 1128 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1902 interconnect- 1129 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1903 1130 "isi1", "isi2", "isp0", "isp1",
1904 1131 "dwe";
1905 clocks = <&cl 1132 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1906 <&cl 1133 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1907 <&cl 1134 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1908 <&cl 1135 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1909 <&cl 1136 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1910 <&cl 1137 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1911 <&cl 1138 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1912 <&cl 1139 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1913 clock-names = 1140 clock-names = "apb", "axi", "cam1", "cam2",
1914 1141 "disp1", "disp2", "isp", "phy";
1915 1142
1916 /* <<
1917 * The ISP ma <<
1918 * and 500MHz <<
1919 * point hasn <<
1920 * IMX8MP_CLK <<
1921 */ <<
1922 assigned-cloc 1143 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1923 !! 1144 <&clk IMX8MP_CLK_MEDIA_APB>;
1924 <<
1925 <<
1926 <<
1927 <<
1928 assigned-cloc 1145 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1929 !! 1146 <&clk IMX8MP_SYS_PLL1_800M>;
1930 !! 1147 assigned-clock-rates = <500000000>, <200000000>;
1931 <<
1932 <<
1933 assigned-cloc <<
1934 <<
1935 <<
1936 #power-domain <<
1937 <<
1938 lvds_bridge: <<
1939 compa <<
1940 reg = <<
1941 reg-n <<
1942 clock <<
1943 clock <<
1944 assig <<
1945 assig <<
1946 statu <<
1947 1148
1948 ports !! 1149 #power-domain-cells = <1>;
1949 <<
1950 <<
1951 <<
1952 <<
1953 <<
1954 <<
1955 <<
1956 <<
1957 <<
1958 <<
1959 <<
1960 <<
1961 <<
1962 <<
1963 <<
1964 <<
1965 <<
1966 <<
1967 <<
1968 <<
1969 <<
1970 <<
1971 <<
1972 <<
1973 }; <<
1974 }; <<
1975 }; 1150 };
1976 1151
1977 pcie_phy: pcie-phy@32 1152 pcie_phy: pcie-phy@32f00000 {
1978 compatible = 1153 compatible = "fsl,imx8mp-pcie-phy";
1979 reg = <0x32f0 1154 reg = <0x32f00000 0x10000>;
1980 resets = <&sr 1155 resets = <&src IMX8MP_RESET_PCIEPHY>,
1981 <&sr 1156 <&src IMX8MP_RESET_PCIEPHY_PERST>;
1982 reset-names = 1157 reset-names = "pciephy", "perst";
1983 power-domains 1158 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1984 #phy-cells = 1159 #phy-cells = <0>;
1985 status = "dis 1160 status = "disabled";
1986 }; 1161 };
1987 1162
1988 hsio_blk_ctrl: blk-ct 1163 hsio_blk_ctrl: blk-ctrl@32f10000 {
1989 compatible = 1164 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1990 reg = <0x32f1 1165 reg = <0x32f10000 0x24>;
1991 clocks = <&cl 1166 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1992 <&cl 1167 <&clk IMX8MP_CLK_PCIE_ROOT>;
1993 clock-names = 1168 clock-names = "usb", "pcie";
1994 power-domains 1169 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1995 1170 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1996 1171 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1997 power-domain- 1172 power-domain-names = "bus", "usb", "usb-phy1",
1998 1173 "usb-phy2", "pcie", "pcie-phy";
1999 interconnects 1174 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
2000 1175 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
2001 1176 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
2002 1177 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
2003 interconnect- 1178 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2004 #power-domain 1179 #power-domain-cells = <1>;
2005 #clock-cells <<
2006 }; <<
2007 <<
2008 hdmi_blk_ctrl: blk-ct <<
2009 compatible = <<
2010 reg = <0x32fc <<
2011 clocks = <&cl <<
2012 <&cl <<
2013 <&cl <<
2014 <&cl <<
2015 <&cl <<
2016 clock-names = <<
2017 power-domains <<
2018 <<
2019 <<
2020 <<
2021 <<
2022 power-domain- <<
2023 <<
2024 <<
2025 <<
2026 #power-domain <<
2027 }; <<
2028 <<
2029 irqsteer_hdmi: interr <<
2030 compatible = <<
2031 reg = <0x32fc <<
2032 interrupts = <<
2033 interrupt-con <<
2034 #interrupt-ce <<
2035 fsl,channel = <<
2036 fsl,num-irqs <<
2037 clocks = <&cl <<
2038 clock-names = <<
2039 power-domains <<
2040 }; <<
2041 <<
2042 hdmi_pvi: display-bri <<
2043 compatible = <<
2044 reg = <0x32fc <<
2045 interrupt-par <<
2046 interrupts = <<
2047 power-domains <<
2048 status = "dis <<
2049 <<
2050 ports { <<
2051 #addr <<
2052 #size <<
2053 <<
2054 port@ <<
2055 <<
2056 <<
2057 <<
2058 <<
2059 }; <<
2060 <<
2061 port@ <<
2062 <<
2063 <<
2064 <<
2065 <<
2066 }; <<
2067 }; <<
2068 }; <<
2069 <<
2070 lcdif3: display-contr <<
2071 compatible = <<
2072 reg = <0x32fc <<
2073 interrupt-par <<
2074 interrupts = <<
2075 clocks = <&hd <<
2076 <&cl <<
2077 <&cl <<
2078 clock-names = <<
2079 power-domains <<
2080 status = "dis <<
2081 <<
2082 port { <<
2083 lcdif <<
2084 <<
2085 }; <<
2086 }; <<
2087 }; <<
2088 <<
2089 hdmi_tx: hdmi@32fd800 <<
2090 compatible = <<
2091 reg = <0x32fd <<
2092 interrupt-par <<
2093 interrupts = <<
2094 clocks = <&cl <<
2095 <&cl <<
2096 <&cl <<
2097 <&hd <<
2098 clock-names = <<
2099 assigned-cloc <<
2100 assigned-cloc <<
2101 power-domains <<
2102 reg-io-width <<
2103 status = "dis <<
2104 <<
2105 ports { <<
2106 #addr <<
2107 #size <<
2108 <<
2109 port@ <<
2110 <<
2111 <<
2112 <<
2113 <<
2114 <<
2115 }; <<
2116 <<
2117 port@ <<
2118 <<
2119 <<
2120 }; <<
2121 }; <<
2122 }; <<
2123 <<
2124 hdmi_tx_phy: phy@32fd <<
2125 compatible = <<
2126 reg = <0x32fd <<
2127 clocks = <&cl <<
2128 <&cl <<
2129 clock-names = <<
2130 assigned-cloc <<
2131 assigned-cloc <<
2132 power-domains <<
2133 #clock-cells <<
2134 #phy-cells = <<
2135 status = "dis <<
2136 }; 1180 };
2137 }; 1181 };
2138 1182
2139 pcie: pcie@33800000 { 1183 pcie: pcie@33800000 {
2140 compatible = "fsl,imx 1184 compatible = "fsl,imx8mp-pcie";
2141 reg = <0x33800000 0x4 1185 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
2142 reg-names = "dbi", "c 1186 reg-names = "dbi", "config";
2143 clocks = <&clk IMX8MP <<
2144 <&clk IMX8MP <<
2145 <&clk IMX8MP <<
2146 clock-names = "pcie", <<
2147 assigned-clocks = <&c <<
2148 assigned-clock-rates <<
2149 assigned-clock-parent <<
2150 #address-cells = <3>; 1187 #address-cells = <3>;
2151 #size-cells = <2>; 1188 #size-cells = <2>;
2152 device_type = "pci"; 1189 device_type = "pci";
2153 bus-range = <0x00 0xf 1190 bus-range = <0x00 0xff>;
2154 ranges = <0x81000000 !! 1191 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
2155 <0x82000000 !! 1192 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2156 num-lanes = <1>; 1193 num-lanes = <1>;
2157 num-viewport = <4>; 1194 num-viewport = <4>;
2158 interrupts = <GIC_SPI 1195 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2159 interrupt-names = "ms 1196 interrupt-names = "msi";
2160 #interrupt-cells = <1 1197 #interrupt-cells = <1>;
2161 interrupt-map-mask = 1198 interrupt-map-mask = <0 0 0 0x7>;
2162 interrupt-map = <0 0 1199 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2163 <0 0 1200 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2164 <0 0 1201 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2165 <0 0 1202 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
2166 fsl,max-link-speed = 1203 fsl,max-link-speed = <3>;
2167 linux,pci-domain = <0 1204 linux,pci-domain = <0>;
2168 power-domains = <&hsi 1205 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2169 resets = <&src IMX8MP 1206 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
2170 <&src IMX8MP 1207 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
2171 reset-names = "apps", 1208 reset-names = "apps", "turnoff";
2172 phys = <&pcie_phy>; 1209 phys = <&pcie_phy>;
2173 phy-names = "pcie-phy 1210 phy-names = "pcie-phy";
2174 status = "disabled"; 1211 status = "disabled";
2175 }; 1212 };
2176 1213
2177 pcie_ep: pcie-ep@33800000 { <<
2178 compatible = "fsl,imx <<
2179 reg = <0x33800000 0x0 <<
2180 reg-names = "dbi", "a <<
2181 clocks = <&clk IMX8MP <<
2182 <&clk IMX8MP <<
2183 <&clk IMX8MP <<
2184 clock-names = "pcie", <<
2185 assigned-clocks = <&c <<
2186 assigned-clock-rates <<
2187 assigned-clock-parent <<
2188 num-lanes = <1>; <<
2189 interrupts = <GIC_SPI <<
2190 interrupt-names = "dm <<
2191 fsl,max-link-speed = <<
2192 power-domains = <&hsi <<
2193 resets = <&src IMX8MP <<
2194 <&src IMX8MP <<
2195 reset-names = "apps", <<
2196 phys = <&pcie_phy>; <<
2197 phy-names = "pcie-phy <<
2198 num-ib-windows = <4>; <<
2199 num-ob-windows = <4>; <<
2200 status = "disabled"; <<
2201 }; <<
2202 <<
2203 gpu3d: gpu@38000000 { 1214 gpu3d: gpu@38000000 {
2204 compatible = "vivante 1215 compatible = "vivante,gc";
2205 reg = <0x38000000 0x8 1216 reg = <0x38000000 0x8000>;
2206 interrupts = <GIC_SPI 1217 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
2207 clocks = <&clk IMX8MP 1218 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
2208 <&clk IMX8MP 1219 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
2209 <&clk IMX8MP 1220 <&clk IMX8MP_CLK_GPU_ROOT>,
2210 <&clk IMX8MP 1221 <&clk IMX8MP_CLK_GPU_AHB>;
2211 clock-names = "core", 1222 clock-names = "core", "shader", "bus", "reg";
2212 assigned-clocks = <&c 1223 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
2213 <&c 1224 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
2214 assigned-clock-parent 1225 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
2215 1226 <&clk IMX8MP_SYS_PLL1_800M>;
2216 assigned-clock-rates 1227 assigned-clock-rates = <800000000>, <800000000>;
2217 power-domains = <&pgc 1228 power-domains = <&pgc_gpu3d>;
2218 }; 1229 };
2219 1230
2220 gpu2d: gpu@38008000 { 1231 gpu2d: gpu@38008000 {
2221 compatible = "vivante 1232 compatible = "vivante,gc";
2222 reg = <0x38008000 0x8 1233 reg = <0x38008000 0x8000>;
2223 interrupts = <GIC_SPI 1234 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
2224 clocks = <&clk IMX8MP 1235 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
2225 <&clk IMX8MP 1236 <&clk IMX8MP_CLK_GPU_ROOT>,
2226 <&clk IMX8MP 1237 <&clk IMX8MP_CLK_GPU_AHB>;
2227 clock-names = "core", 1238 clock-names = "core", "bus", "reg";
2228 assigned-clocks = <&c 1239 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
2229 assigned-clock-parent 1240 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2230 assigned-clock-rates 1241 assigned-clock-rates = <800000000>;
2231 power-domains = <&pgc 1242 power-domains = <&pgc_gpu2d>;
2232 }; 1243 };
2233 1244
2234 vpu_g1: video-codec@38300000 <<
2235 compatible = "nxp,imx <<
2236 reg = <0x38300000 0x1 <<
2237 interrupts = <GIC_SPI <<
2238 clocks = <&clk IMX8MP <<
2239 assigned-clocks = <&c <<
2240 assigned-clock-parent <<
2241 assigned-clock-rates <<
2242 power-domains = <&vpu <<
2243 }; <<
2244 <<
2245 vpu_g2: video-codec@38310000 <<
2246 compatible = "nxp,imx <<
2247 reg = <0x38310000 0x1 <<
2248 interrupts = <GIC_SPI <<
2249 clocks = <&clk IMX8MP <<
2250 assigned-clocks = <&c <<
2251 assigned-clock-parent <<
2252 assigned-clock-rates <<
2253 power-domains = <&vpu <<
2254 }; <<
2255 <<
2256 vpumix_blk_ctrl: blk-ctrl@383 1245 vpumix_blk_ctrl: blk-ctrl@38330000 {
2257 compatible = "fsl,imx 1246 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
2258 reg = <0x38330000 0x1 1247 reg = <0x38330000 0x100>;
2259 #power-domain-cells = 1248 #power-domain-cells = <1>;
2260 power-domains = <&pgc 1249 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2261 <&pgc 1250 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
2262 power-domain-names = 1251 power-domain-names = "bus", "g1", "g2", "vc8000e";
2263 clocks = <&clk IMX8MP 1252 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
2264 <&clk IMX8MP 1253 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
2265 <&clk IMX8MP 1254 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
2266 clock-names = "g1", " 1255 clock-names = "g1", "g2", "vc8000e";
2267 assigned-clocks = <&c <<
2268 assigned-clock-parent <<
2269 assigned-clock-rates <<
2270 interconnects = <&noc 1256 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
2271 <&noc 1257 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
2272 <&noc 1258 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
2273 interconnect-names = 1259 interconnect-names = "g1", "g2", "vc8000e";
2274 }; 1260 };
2275 1261
2276 npu: npu@38500000 { <<
2277 compatible = "vivante <<
2278 reg = <0x38500000 0x2 <<
2279 interrupts = <GIC_SPI <<
2280 clocks = <&clk IMX8MP <<
2281 <&clk IMX8MP <<
2282 <&clk IMX8MP <<
2283 <&clk IMX8MP <<
2284 clock-names = "core", <<
2285 power-domains = <&pgc <<
2286 }; <<
2287 <<
2288 gic: interrupt-controller@388 1262 gic: interrupt-controller@38800000 {
2289 compatible = "arm,gic 1263 compatible = "arm,gic-v3";
2290 reg = <0x38800000 0x1 1264 reg = <0x38800000 0x10000>,
2291 <0x38880000 0xc 1265 <0x38880000 0xc0000>;
2292 #interrupt-cells = <3 1266 #interrupt-cells = <3>;
2293 interrupt-controller; 1267 interrupt-controller;
2294 interrupts = <GIC_PPI 1268 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2295 interrupt-parent = <& 1269 interrupt-parent = <&gic>;
2296 }; 1270 };
2297 1271
2298 edacmc: memory-controller@3d4 1272 edacmc: memory-controller@3d400000 {
2299 compatible = "snps,dd 1273 compatible = "snps,ddrc-3.80a";
2300 reg = <0x3d400000 0x4 1274 reg = <0x3d400000 0x400000>;
2301 interrupts = <GIC_SPI 1275 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2302 }; 1276 };
2303 1277
2304 ddr-pmu@3d800000 { 1278 ddr-pmu@3d800000 {
2305 compatible = "fsl,imx 1279 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2306 reg = <0x3d800000 0x4 1280 reg = <0x3d800000 0x400000>;
2307 interrupts = <GIC_SPI 1281 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2308 }; 1282 };
2309 1283
2310 usb3_phy0: usb-phy@381f0040 { 1284 usb3_phy0: usb-phy@381f0040 {
2311 compatible = "fsl,imx 1285 compatible = "fsl,imx8mp-usb-phy";
2312 reg = <0x381f0040 0x4 1286 reg = <0x381f0040 0x40>;
2313 clocks = <&clk IMX8MP 1287 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2314 clock-names = "phy"; 1288 clock-names = "phy";
2315 assigned-clocks = <&c 1289 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2316 assigned-clock-parent 1290 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2317 power-domains = <&hsi 1291 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2318 #phy-cells = <0>; 1292 #phy-cells = <0>;
2319 status = "disabled"; 1293 status = "disabled";
2320 }; 1294 };
2321 1295
2322 usb3_0: usb@32f10100 { 1296 usb3_0: usb@32f10100 {
2323 compatible = "fsl,imx 1297 compatible = "fsl,imx8mp-dwc3";
2324 reg = <0x32f10100 0x8 1298 reg = <0x32f10100 0x8>,
2325 <0x381f0000 0x2 1299 <0x381f0000 0x20>;
2326 clocks = <&clk IMX8MP 1300 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2327 <&clk IMX8MP 1301 <&clk IMX8MP_CLK_USB_SUSP>;
2328 clock-names = "hsio", 1302 clock-names = "hsio", "suspend";
2329 interrupts = <GIC_SPI 1303 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&hsi 1304 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2331 #address-cells = <1>; 1305 #address-cells = <1>;
2332 #size-cells = <1>; 1306 #size-cells = <1>;
2333 dma-ranges = <0x40000 1307 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2334 ranges; 1308 ranges;
2335 status = "disabled"; 1309 status = "disabled";
2336 1310
2337 usb_dwc3_0: usb@38100 1311 usb_dwc3_0: usb@38100000 {
2338 compatible = 1312 compatible = "snps,dwc3";
2339 reg = <0x3810 1313 reg = <0x38100000 0x10000>;
2340 clocks = <&cl 1314 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2341 <&cl 1315 <&clk IMX8MP_CLK_USB_CORE_REF>,
2342 <&cl 1316 <&clk IMX8MP_CLK_USB_SUSP>;
2343 clock-names = 1317 clock-names = "bus_early", "ref", "suspend";
2344 interrupts = 1318 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
2345 phys = <&usb3 1319 phys = <&usb3_phy0>, <&usb3_phy0>;
2346 phy-names = " 1320 phy-names = "usb2-phy", "usb3-phy";
2347 snps,gfladj-r 1321 snps,gfladj-refclk-lpm-sel-quirk;
2348 snps,parkmode <<
2349 }; 1322 };
2350 1323
2351 }; 1324 };
2352 1325
2353 usb3_phy1: usb-phy@382f0040 { 1326 usb3_phy1: usb-phy@382f0040 {
2354 compatible = "fsl,imx 1327 compatible = "fsl,imx8mp-usb-phy";
2355 reg = <0x382f0040 0x4 1328 reg = <0x382f0040 0x40>;
2356 clocks = <&clk IMX8MP 1329 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2357 clock-names = "phy"; 1330 clock-names = "phy";
2358 assigned-clocks = <&c 1331 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2359 assigned-clock-parent 1332 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2360 power-domains = <&hsi 1333 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2361 #phy-cells = <0>; 1334 #phy-cells = <0>;
2362 status = "disabled"; 1335 status = "disabled";
2363 }; 1336 };
2364 1337
2365 usb3_1: usb@32f10108 { 1338 usb3_1: usb@32f10108 {
2366 compatible = "fsl,imx 1339 compatible = "fsl,imx8mp-dwc3";
2367 reg = <0x32f10108 0x8 1340 reg = <0x32f10108 0x8>,
2368 <0x382f0000 0x2 1341 <0x382f0000 0x20>;
2369 clocks = <&clk IMX8MP 1342 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2370 <&clk IMX8MP 1343 <&clk IMX8MP_CLK_USB_SUSP>;
2371 clock-names = "hsio", 1344 clock-names = "hsio", "suspend";
2372 interrupts = <GIC_SPI 1345 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2373 power-domains = <&hsi 1346 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2374 #address-cells = <1>; 1347 #address-cells = <1>;
2375 #size-cells = <1>; 1348 #size-cells = <1>;
2376 dma-ranges = <0x40000 1349 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2377 ranges; 1350 ranges;
2378 status = "disabled"; 1351 status = "disabled";
2379 1352
2380 usb_dwc3_1: usb@38200 1353 usb_dwc3_1: usb@38200000 {
2381 compatible = 1354 compatible = "snps,dwc3";
2382 reg = <0x3820 1355 reg = <0x38200000 0x10000>;
2383 clocks = <&cl 1356 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2384 <&cl 1357 <&clk IMX8MP_CLK_USB_CORE_REF>,
2385 <&cl 1358 <&clk IMX8MP_CLK_USB_SUSP>;
2386 clock-names = 1359 clock-names = "bus_early", "ref", "suspend";
2387 interrupts = 1360 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
2388 phys = <&usb3 1361 phys = <&usb3_phy1>, <&usb3_phy1>;
2389 phy-names = " 1362 phy-names = "usb2-phy", "usb3-phy";
2390 snps,gfladj-r 1363 snps,gfladj-refclk-lpm-sel-quirk;
2391 snps,parkmode <<
2392 }; 1364 };
2393 }; 1365 };
2394 1366
2395 dsp: dsp@3b6e8000 { 1367 dsp: dsp@3b6e8000 {
2396 compatible = "fsl,imx 1368 compatible = "fsl,imx8mp-dsp";
2397 reg = <0x3b6e8000 0x8 1369 reg = <0x3b6e8000 0x88000>;
2398 mbox-names = "txdb0", 1370 mbox-names = "txdb0", "txdb1",
2399 "rxdb0", "rxd 1371 "rxdb0", "rxdb1";
2400 mboxes = <&mu2 2 0>, 1372 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2401 <&mu2 3 0>, < 1373 <&mu2 3 0>, <&mu2 3 1>;
2402 memory-region = <&dsp 1374 memory-region = <&dsp_reserved>;
2403 status = "disabled"; 1375 status = "disabled";
2404 }; 1376 };
2405 }; 1377 };
2406 }; 1378 };
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