1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2019 NXP 3 * Copyright 2019 NXP
4 */ 4 */
5 5
6 #include <dt-bindings/clock/imx8mp-clock.h> 6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h> 7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h> 8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h> 10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp. 11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm 12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h> 13 #include <dt-bindings/thermal/thermal.h>
14 14
15 #include "imx8mp-pinfunc.h" 15 #include "imx8mp-pinfunc.h"
16 16
17 / { 17 / {
18 interrupt-parent = <&gic>; 18 interrupt-parent = <&gic>;
19 #address-cells = <2>; 19 #address-cells = <2>;
20 #size-cells = <2>; 20 #size-cells = <2>;
21 21
22 aliases { 22 aliases {
23 ethernet0 = &fec; 23 ethernet0 = &fec;
24 ethernet1 = &eqos; 24 ethernet1 = &eqos;
25 gpio0 = &gpio1; 25 gpio0 = &gpio1;
26 gpio1 = &gpio2; 26 gpio1 = &gpio2;
27 gpio2 = &gpio3; 27 gpio2 = &gpio3;
28 gpio3 = &gpio4; 28 gpio3 = &gpio4;
29 gpio4 = &gpio5; 29 gpio4 = &gpio5;
30 i2c0 = &i2c1; 30 i2c0 = &i2c1;
31 i2c1 = &i2c2; 31 i2c1 = &i2c2;
32 i2c2 = &i2c3; 32 i2c2 = &i2c3;
33 i2c3 = &i2c4; 33 i2c3 = &i2c4;
34 i2c4 = &i2c5; 34 i2c4 = &i2c5;
35 i2c5 = &i2c6; 35 i2c5 = &i2c6;
36 mmc0 = &usdhc1; 36 mmc0 = &usdhc1;
37 mmc1 = &usdhc2; 37 mmc1 = &usdhc2;
38 mmc2 = &usdhc3; 38 mmc2 = &usdhc3;
39 serial0 = &uart1; 39 serial0 = &uart1;
40 serial1 = &uart2; 40 serial1 = &uart2;
41 serial2 = &uart3; 41 serial2 = &uart3;
42 serial3 = &uart4; 42 serial3 = &uart4;
43 spi0 = &flexspi; 43 spi0 = &flexspi;
44 }; 44 };
45 45
46 cpus { 46 cpus {
47 #address-cells = <1>; 47 #address-cells = <1>;
48 #size-cells = <0>; 48 #size-cells = <0>;
49 49
50 A53_0: cpu@0 { 50 A53_0: cpu@0 {
51 device_type = "cpu"; 51 device_type = "cpu";
52 compatible = "arm,cort 52 compatible = "arm,cortex-a53";
53 reg = <0x0>; 53 reg = <0x0>;
54 clock-latency = <61036 54 clock-latency = <61036>;
55 clocks = <&clk IMX8MP_ 55 clocks = <&clk IMX8MP_CLK_ARM>;
56 enable-method = "psci" 56 enable-method = "psci";
57 i-cache-size = <0x8000 57 i-cache-size = <0x8000>;
58 i-cache-line-size = <6 58 i-cache-line-size = <64>;
59 i-cache-sets = <256>; 59 i-cache-sets = <256>;
60 d-cache-size = <0x8000 60 d-cache-size = <0x8000>;
61 d-cache-line-size = <6 61 d-cache-line-size = <64>;
62 d-cache-sets = <128>; 62 d-cache-sets = <128>;
63 next-level-cache = <&A 63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_sp 64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "sp 65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = 66 operating-points-v2 = <&a53_opp_table>;
67 #cooling-cells = <2>; 67 #cooling-cells = <2>;
68 }; 68 };
69 69
70 A53_1: cpu@1 { 70 A53_1: cpu@1 {
71 device_type = "cpu"; 71 device_type = "cpu";
72 compatible = "arm,cort 72 compatible = "arm,cortex-a53";
73 reg = <0x1>; 73 reg = <0x1>;
74 clock-latency = <61036 74 clock-latency = <61036>;
75 clocks = <&clk IMX8MP_ 75 clocks = <&clk IMX8MP_CLK_ARM>;
76 enable-method = "psci" 76 enable-method = "psci";
77 i-cache-size = <0x8000 77 i-cache-size = <0x8000>;
78 i-cache-line-size = <6 78 i-cache-line-size = <64>;
79 i-cache-sets = <256>; 79 i-cache-sets = <256>;
80 d-cache-size = <0x8000 80 d-cache-size = <0x8000>;
81 d-cache-line-size = <6 81 d-cache-line-size = <64>;
82 d-cache-sets = <128>; 82 d-cache-sets = <128>;
83 next-level-cache = <&A 83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = 84 operating-points-v2 = <&a53_opp_table>;
85 #cooling-cells = <2>; 85 #cooling-cells = <2>;
86 }; 86 };
87 87
88 A53_2: cpu@2 { 88 A53_2: cpu@2 {
89 device_type = "cpu"; 89 device_type = "cpu";
90 compatible = "arm,cort 90 compatible = "arm,cortex-a53";
91 reg = <0x2>; 91 reg = <0x2>;
92 clock-latency = <61036 92 clock-latency = <61036>;
93 clocks = <&clk IMX8MP_ 93 clocks = <&clk IMX8MP_CLK_ARM>;
94 enable-method = "psci" 94 enable-method = "psci";
95 i-cache-size = <0x8000 95 i-cache-size = <0x8000>;
96 i-cache-line-size = <6 96 i-cache-line-size = <64>;
97 i-cache-sets = <256>; 97 i-cache-sets = <256>;
98 d-cache-size = <0x8000 98 d-cache-size = <0x8000>;
99 d-cache-line-size = <6 99 d-cache-line-size = <64>;
100 d-cache-sets = <128>; 100 d-cache-sets = <128>;
101 next-level-cache = <&A 101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = 102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>; 103 #cooling-cells = <2>;
104 }; 104 };
105 105
106 A53_3: cpu@3 { 106 A53_3: cpu@3 {
107 device_type = "cpu"; 107 device_type = "cpu";
108 compatible = "arm,cort 108 compatible = "arm,cortex-a53";
109 reg = <0x3>; 109 reg = <0x3>;
110 clock-latency = <61036 110 clock-latency = <61036>;
111 clocks = <&clk IMX8MP_ 111 clocks = <&clk IMX8MP_CLK_ARM>;
112 enable-method = "psci" 112 enable-method = "psci";
113 i-cache-size = <0x8000 113 i-cache-size = <0x8000>;
114 i-cache-line-size = <6 114 i-cache-line-size = <64>;
115 i-cache-sets = <256>; 115 i-cache-sets = <256>;
116 d-cache-size = <0x8000 116 d-cache-size = <0x8000>;
117 d-cache-line-size = <6 117 d-cache-line-size = <64>;
118 d-cache-sets = <128>; 118 d-cache-sets = <128>;
119 next-level-cache = <&A 119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = 120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>; 121 #cooling-cells = <2>;
122 }; 122 };
123 123
124 A53_L2: l2-cache0 { 124 A53_L2: l2-cache0 {
125 compatible = "cache"; 125 compatible = "cache";
126 cache-unified; 126 cache-unified;
127 cache-level = <2>; 127 cache-level = <2>;
128 cache-size = <0x80000> 128 cache-size = <0x80000>;
129 cache-line-size = <64> 129 cache-line-size = <64>;
130 cache-sets = <512>; 130 cache-sets = <512>;
131 }; 131 };
132 }; 132 };
133 133
134 a53_opp_table: opp-table { 134 a53_opp_table: opp-table {
135 compatible = "operating-points 135 compatible = "operating-points-v2";
136 opp-shared; 136 opp-shared;
137 137
138 opp-1200000000 { 138 opp-1200000000 {
139 opp-hz = /bits/ 64 <12 139 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <85000 140 opp-microvolt = <850000>;
141 opp-supported-hw = <0x 141 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <15 142 clock-latency-ns = <150000>;
143 opp-suspend; 143 opp-suspend;
144 }; 144 };
145 145
146 opp-1600000000 { 146 opp-1600000000 {
147 opp-hz = /bits/ 64 <16 147 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <95000 148 opp-microvolt = <950000>;
149 opp-supported-hw = <0x 149 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <15 150 clock-latency-ns = <150000>;
151 opp-suspend; 151 opp-suspend;
152 }; 152 };
153 153
154 opp-1800000000 { 154 opp-1800000000 {
155 opp-hz = /bits/ 64 <18 155 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <10000 156 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x 157 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <15 158 clock-latency-ns = <150000>;
159 opp-suspend; 159 opp-suspend;
160 }; 160 };
161 }; 161 };
162 162
163 osc_32k: clock-osc-32k { 163 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock"; 164 compatible = "fixed-clock";
165 #clock-cells = <0>; 165 #clock-cells = <0>;
166 clock-frequency = <32768>; 166 clock-frequency = <32768>;
167 clock-output-names = "osc_32k" 167 clock-output-names = "osc_32k";
168 }; 168 };
169 169
170 osc_24m: clock-osc-24m { 170 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock"; 171 compatible = "fixed-clock";
172 #clock-cells = <0>; 172 #clock-cells = <0>;
173 clock-frequency = <24000000>; 173 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m" 174 clock-output-names = "osc_24m";
175 }; 175 };
176 176
177 clk_ext1: clock-ext1 { 177 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock"; 178 compatible = "fixed-clock";
179 #clock-cells = <0>; 179 #clock-cells = <0>;
180 clock-frequency = <133000000>; 180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1 181 clock-output-names = "clk_ext1";
182 }; 182 };
183 183
184 clk_ext2: clock-ext2 { 184 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock"; 185 compatible = "fixed-clock";
186 #clock-cells = <0>; 186 #clock-cells = <0>;
187 clock-frequency = <133000000>; 187 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2 188 clock-output-names = "clk_ext2";
189 }; 189 };
190 190
191 clk_ext3: clock-ext3 { 191 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock"; 192 compatible = "fixed-clock";
193 #clock-cells = <0>; 193 #clock-cells = <0>;
194 clock-frequency = <133000000>; 194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3 195 clock-output-names = "clk_ext3";
196 }; 196 };
197 197
198 clk_ext4: clock-ext4 { 198 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock"; 199 compatible = "fixed-clock";
200 #clock-cells = <0>; 200 #clock-cells = <0>;
201 clock-frequency = <133000000>; 201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext4 202 clock-output-names = "clk_ext4";
203 }; 203 };
204 204
205 funnel { 205 funnel {
206 /* 206 /*
207 * non-configurable funnel don 207 * non-configurable funnel don't show up on the AMBA
208 * bus. As such no need to ad 208 * bus. As such no need to add "arm,primecell".
209 */ 209 */
210 compatible = "arm,coresight-st 210 compatible = "arm,coresight-static-funnel";
211 211
212 in-ports { 212 in-ports {
213 #address-cells = <1>; 213 #address-cells = <1>;
214 #size-cells = <0>; 214 #size-cells = <0>;
215 215
216 port@0 { 216 port@0 {
217 reg = <0>; 217 reg = <0>;
218 218
219 ca_funnel_in_p 219 ca_funnel_in_port0: endpoint {
220 remote 220 remote-endpoint = <&etm0_out_port>;
221 }; 221 };
222 }; 222 };
223 223
224 port@1 { 224 port@1 {
225 reg = <1>; 225 reg = <1>;
226 226
227 ca_funnel_in_p 227 ca_funnel_in_port1: endpoint {
228 remote 228 remote-endpoint = <&etm1_out_port>;
229 }; 229 };
230 }; 230 };
231 231
232 port@2 { 232 port@2 {
233 reg = <2>; 233 reg = <2>;
234 234
235 ca_funnel_in_p 235 ca_funnel_in_port2: endpoint {
236 remote 236 remote-endpoint = <&etm2_out_port>;
237 }; 237 };
238 }; 238 };
239 239
240 port@3 { 240 port@3 {
241 reg = <3>; 241 reg = <3>;
242 242
243 ca_fun 243 ca_funnel_in_port3: endpoint {
244 remote 244 remote-endpoint = <&etm3_out_port>;
245 }; 245 };
246 }; 246 };
247 }; 247 };
248 248
249 out-ports { 249 out-ports {
250 port { 250 port {
251 251
252 ca_funnel_out_ 252 ca_funnel_out_port0: endpoint {
253 remote 253 remote-endpoint = <&hugo_funnel_in_port0>;
254 }; 254 };
255 }; 255 };
256 }; 256 };
257 }; 257 };
258 258
259 reserved-memory { 259 reserved-memory {
260 #address-cells = <2>; 260 #address-cells = <2>;
261 #size-cells = <2>; 261 #size-cells = <2>;
262 ranges; 262 ranges;
263 263
264 dsp_reserved: dsp@92400000 { 264 dsp_reserved: dsp@92400000 {
265 reg = <0 0x92400000 0 265 reg = <0 0x92400000 0 0x2000000>;
266 no-map; 266 no-map;
267 status = "disabled"; 267 status = "disabled";
268 }; 268 };
269 }; 269 };
270 270
271 pmu { 271 pmu {
272 compatible = "arm,cortex-a53-p 272 compatible = "arm,cortex-a53-pmu";
273 interrupts = <GIC_PPI 7 273 interrupts = <GIC_PPI 7
274 (GIC_CPU_MASK_SIM 274 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
275 }; 275 };
276 276
277 psci { 277 psci {
278 compatible = "arm,psci-1.0"; 278 compatible = "arm,psci-1.0";
279 method = "smc"; 279 method = "smc";
280 }; 280 };
281 281
282 thermal-zones { 282 thermal-zones {
283 cpu-thermal { 283 cpu-thermal {
284 polling-delay-passive 284 polling-delay-passive = <250>;
285 polling-delay = <2000> 285 polling-delay = <2000>;
286 thermal-sensors = <&tm 286 thermal-sensors = <&tmu 0>;
287 trips { 287 trips {
288 cpu_alert0: tr 288 cpu_alert0: trip0 {
289 temper 289 temperature = <85000>;
290 hyster 290 hysteresis = <2000>;
291 type = 291 type = "passive";
292 }; 292 };
293 293
294 cpu_crit0: tri 294 cpu_crit0: trip1 {
295 temper 295 temperature = <95000>;
296 hyster 296 hysteresis = <2000>;
297 type = 297 type = "critical";
298 }; 298 };
299 }; 299 };
300 300
301 cooling-maps { 301 cooling-maps {
302 map0 { 302 map0 {
303 trip = 303 trip = <&cpu_alert0>;
304 coolin 304 cooling-device =
305 305 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
306 306 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
307 307 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
308 308 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
309 }; 309 };
310 }; 310 };
311 }; 311 };
312 312
313 soc-thermal { 313 soc-thermal {
314 polling-delay-passive 314 polling-delay-passive = <250>;
315 polling-delay = <2000> 315 polling-delay = <2000>;
316 thermal-sensors = <&tm 316 thermal-sensors = <&tmu 1>;
317 trips { 317 trips {
318 soc_alert0: tr 318 soc_alert0: trip0 {
319 temper 319 temperature = <85000>;
320 hyster 320 hysteresis = <2000>;
321 type = 321 type = "passive";
322 }; 322 };
323 323
324 soc_crit0: tri 324 soc_crit0: trip1 {
325 temper 325 temperature = <95000>;
326 hyster 326 hysteresis = <2000>;
327 type = 327 type = "critical";
328 }; 328 };
329 }; 329 };
330 330
331 cooling-maps { 331 cooling-maps {
332 map0 { 332 map0 {
333 trip = 333 trip = <&soc_alert0>;
334 coolin 334 cooling-device =
335 335 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
336 336 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
337 337 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
338 338 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
339 }; 339 };
340 }; 340 };
341 }; 341 };
342 }; 342 };
343 343
344 timer { 344 timer {
345 compatible = "arm,armv8-timer" 345 compatible = "arm,armv8-timer";
346 interrupts = <GIC_PPI 13 (GIC_ 346 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
347 <GIC_PPI 14 (GIC_ 347 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
348 <GIC_PPI 11 (GIC_ 348 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
349 <GIC_PPI 10 (GIC_ 349 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
350 clock-frequency = <8000000>; 350 clock-frequency = <8000000>;
351 arm,no-tick-in-suspend; 351 arm,no-tick-in-suspend;
352 }; 352 };
353 353
354 soc: soc@0 { 354 soc: soc@0 {
355 compatible = "fsl,imx8mp-soc", 355 compatible = "fsl,imx8mp-soc", "simple-bus";
356 #address-cells = <1>; 356 #address-cells = <1>;
357 #size-cells = <1>; 357 #size-cells = <1>;
358 ranges = <0x0 0x0 0x0 0x3e0000 358 ranges = <0x0 0x0 0x0 0x3e000000>;
359 nvmem-cells = <&imx8mp_uid>; 359 nvmem-cells = <&imx8mp_uid>;
360 nvmem-cell-names = "soc_unique 360 nvmem-cell-names = "soc_unique_id";
361 361
362 etm0: etm@28440000 { 362 etm0: etm@28440000 {
363 compatible = "arm,core 363 compatible = "arm,coresight-etm4x", "arm,primecell";
364 reg = <0x28440000 0x10 364 reg = <0x28440000 0x1000>;
365 cpu = <&A53_0>; 365 cpu = <&A53_0>;
366 clocks = <&clk IMX8MP_ 366 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
367 clock-names = "apb_pcl 367 clock-names = "apb_pclk";
368 368
369 out-ports { 369 out-ports {
370 port { 370 port {
371 etm0_o 371 etm0_out_port: endpoint {
372 372 remote-endpoint = <&ca_funnel_in_port0>;
373 }; 373 };
374 }; 374 };
375 }; 375 };
376 }; 376 };
377 377
378 etm1: etm@28540000 { 378 etm1: etm@28540000 {
379 compatible = "arm,core 379 compatible = "arm,coresight-etm4x", "arm,primecell";
380 reg = <0x28540000 0x10 380 reg = <0x28540000 0x1000>;
381 cpu = <&A53_1>; 381 cpu = <&A53_1>;
382 clocks = <&clk IMX8MP_ 382 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
383 clock-names = "apb_pcl 383 clock-names = "apb_pclk";
384 384
385 out-ports { 385 out-ports {
386 port { 386 port {
387 etm1_o 387 etm1_out_port: endpoint {
388 388 remote-endpoint = <&ca_funnel_in_port1>;
389 }; 389 };
390 }; 390 };
391 }; 391 };
392 }; 392 };
393 393
394 etm2: etm@28640000 { 394 etm2: etm@28640000 {
395 compatible = "arm,core 395 compatible = "arm,coresight-etm4x", "arm,primecell";
396 reg = <0x28640000 0x10 396 reg = <0x28640000 0x1000>;
397 cpu = <&A53_2>; 397 cpu = <&A53_2>;
398 clocks = <&clk IMX8MP_ 398 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
399 clock-names = "apb_pcl 399 clock-names = "apb_pclk";
400 400
401 out-ports { 401 out-ports {
402 port { 402 port {
403 etm2_o 403 etm2_out_port: endpoint {
404 404 remote-endpoint = <&ca_funnel_in_port2>;
405 }; 405 };
406 }; 406 };
407 }; 407 };
408 }; 408 };
409 409
410 etm3: etm@28740000 { 410 etm3: etm@28740000 {
411 compatible = "arm,core 411 compatible = "arm,coresight-etm4x", "arm,primecell";
412 reg = <0x28740000 0x10 412 reg = <0x28740000 0x1000>;
413 cpu = <&A53_3>; 413 cpu = <&A53_3>;
414 clocks = <&clk IMX8MP_ 414 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
415 clock-names = "apb_pcl 415 clock-names = "apb_pclk";
416 416
417 out-ports { 417 out-ports {
418 port { 418 port {
419 etm3_o 419 etm3_out_port: endpoint {
420 420 remote-endpoint = <&ca_funnel_in_port3>;
421 }; 421 };
422 }; 422 };
423 }; 423 };
424 }; 424 };
425 425
426 funnel@28c03000 { 426 funnel@28c03000 {
427 compatible = "arm,core 427 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
428 reg = <0x28c03000 0x10 428 reg = <0x28c03000 0x1000>;
429 clocks = <&clk IMX8MP_ 429 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
430 clock-names = "apb_pcl 430 clock-names = "apb_pclk";
431 431
432 in-ports { 432 in-ports {
433 #address-cells 433 #address-cells = <1>;
434 #size-cells = 434 #size-cells = <0>;
435 435
436 port@0 { 436 port@0 {
437 reg = 437 reg = <0>;
438 438
439 hugo_f 439 hugo_funnel_in_port0: endpoint {
440 440 remote-endpoint = <&ca_funnel_out_port0>;
441 }; 441 };
442 }; 442 };
443 443
444 port@1 { 444 port@1 {
445 reg = 445 reg = <1>;
446 446
447 hugo_f 447 hugo_funnel_in_port1: endpoint {
448 /* M7 448 /* M7 input */
449 }; 449 };
450 }; 450 };
451 451
452 port@2 { 452 port@2 {
453 reg = 453 reg = <2>;
454 454
455 hugo_f 455 hugo_funnel_in_port2: endpoint {
456 /* DSP 456 /* DSP input */
457 }; 457 };
458 }; 458 };
459 /* the other i 459 /* the other input ports are not connect to anything */
460 }; 460 };
461 461
462 out-ports { 462 out-ports {
463 port { 463 port {
464 hugo_f 464 hugo_funnel_out_port0: endpoint {
465 465 remote-endpoint = <&etf_in_port>;
466 }; 466 };
467 }; 467 };
468 }; 468 };
469 }; 469 };
470 470
471 etf@28c04000 { 471 etf@28c04000 {
472 compatible = "arm,core 472 compatible = "arm,coresight-tmc", "arm,primecell";
473 reg = <0x28c04000 0x10 473 reg = <0x28c04000 0x1000>;
474 clocks = <&clk IMX8MP_ 474 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
475 clock-names = "apb_pcl 475 clock-names = "apb_pclk";
476 476
477 in-ports { 477 in-ports {
478 port { 478 port {
479 etf_in 479 etf_in_port: endpoint {
480 480 remote-endpoint = <&hugo_funnel_out_port0>;
481 }; 481 };
482 }; 482 };
483 }; 483 };
484 484
485 out-ports { 485 out-ports {
486 port { 486 port {
487 etf_ou 487 etf_out_port: endpoint {
488 488 remote-endpoint = <&etr_in_port>;
489 }; 489 };
490 }; 490 };
491 }; 491 };
492 }; 492 };
493 493
494 etr@28c06000 { 494 etr@28c06000 {
495 compatible = "arm,core 495 compatible = "arm,coresight-tmc", "arm,primecell";
496 reg = <0x28c06000 0x10 496 reg = <0x28c06000 0x1000>;
497 clocks = <&clk IMX8MP_ 497 clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
498 clock-names = "apb_pcl 498 clock-names = "apb_pclk";
499 499
500 in-ports { 500 in-ports {
501 port { 501 port {
502 etr_in 502 etr_in_port: endpoint {
503 503 remote-endpoint = <&etf_out_port>;
504 }; 504 };
505 }; 505 };
506 }; 506 };
507 }; 507 };
508 508
509 aips1: bus@30000000 { 509 aips1: bus@30000000 {
510 compatible = "fsl,aips 510 compatible = "fsl,aips-bus", "simple-bus";
511 reg = <0x30000000 0x40 511 reg = <0x30000000 0x400000>;
512 #address-cells = <1>; 512 #address-cells = <1>;
513 #size-cells = <1>; 513 #size-cells = <1>;
514 ranges; 514 ranges;
515 515
516 gpio1: gpio@30200000 { 516 gpio1: gpio@30200000 {
517 compatible = " 517 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
518 reg = <0x30200 518 reg = <0x30200000 0x10000>;
519 interrupts = < 519 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
520 < 520 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&clk 521 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>;
522 gpio-controlle 522 gpio-controller;
523 #gpio-cells = 523 #gpio-cells = <2>;
524 interrupt-cont 524 interrupt-controller;
525 #interrupt-cel 525 #interrupt-cells = <2>;
526 gpio-ranges = 526 gpio-ranges = <&iomuxc 0 5 30>;
527 }; 527 };
528 528
529 gpio2: gpio@30210000 { 529 gpio2: gpio@30210000 {
530 compatible = " 530 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
531 reg = <0x30210 531 reg = <0x30210000 0x10000>;
532 interrupts = < 532 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
533 < 533 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&clk 534 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>;
535 gpio-controlle 535 gpio-controller;
536 #gpio-cells = 536 #gpio-cells = <2>;
537 interrupt-cont 537 interrupt-controller;
538 #interrupt-cel 538 #interrupt-cells = <2>;
539 gpio-ranges = 539 gpio-ranges = <&iomuxc 0 35 21>;
540 }; 540 };
541 541
542 gpio3: gpio@30220000 { 542 gpio3: gpio@30220000 {
543 compatible = " 543 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
544 reg = <0x30220 544 reg = <0x30220000 0x10000>;
545 interrupts = < 545 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
546 < 546 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&clk 547 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>;
548 gpio-controlle 548 gpio-controller;
549 #gpio-cells = 549 #gpio-cells = <2>;
550 interrupt-cont 550 interrupt-controller;
551 #interrupt-cel 551 #interrupt-cells = <2>;
552 gpio-ranges = 552 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
553 }; 553 };
554 554
555 gpio4: gpio@30230000 { 555 gpio4: gpio@30230000 {
556 compatible = " 556 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
557 reg = <0x30230 557 reg = <0x30230000 0x10000>;
558 interrupts = < 558 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
559 < 559 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
560 clocks = <&clk 560 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>;
561 gpio-controlle 561 gpio-controller;
562 #gpio-cells = 562 #gpio-cells = <2>;
563 interrupt-cont 563 interrupt-controller;
564 #interrupt-cel 564 #interrupt-cells = <2>;
565 gpio-ranges = 565 gpio-ranges = <&iomuxc 0 82 32>;
566 }; 566 };
567 567
568 gpio5: gpio@30240000 { 568 gpio5: gpio@30240000 {
569 compatible = " 569 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
570 reg = <0x30240 570 reg = <0x30240000 0x10000>;
571 interrupts = < 571 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
572 < 572 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
573 clocks = <&clk 573 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>;
574 gpio-controlle 574 gpio-controller;
575 #gpio-cells = 575 #gpio-cells = <2>;
576 interrupt-cont 576 interrupt-controller;
577 #interrupt-cel 577 #interrupt-cells = <2>;
578 gpio-ranges = 578 gpio-ranges = <&iomuxc 0 114 30>;
579 }; 579 };
580 580
581 tmu: tmu@30260000 { 581 tmu: tmu@30260000 {
582 compatible = " 582 compatible = "fsl,imx8mp-tmu";
583 reg = <0x30260 583 reg = <0x30260000 0x10000>;
584 clocks = <&clk 584 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>;
585 nvmem-cells = 585 nvmem-cells = <&tmu_calib>;
586 nvmem-cell-nam 586 nvmem-cell-names = "calib";
587 #thermal-senso 587 #thermal-sensor-cells = <1>;
588 }; 588 };
589 589
590 wdog1: watchdog@302800 590 wdog1: watchdog@30280000 {
591 compatible = " 591 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
592 reg = <0x30280 592 reg = <0x30280000 0x10000>;
593 interrupts = < 593 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&clk 594 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>;
595 status = "disa 595 status = "disabled";
596 }; 596 };
597 597
598 wdog2: watchdog@302900 598 wdog2: watchdog@30290000 {
599 compatible = " 599 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
600 reg = <0x30290 600 reg = <0x30290000 0x10000>;
601 interrupts = < 601 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
602 clocks = <&clk 602 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>;
603 status = "disa 603 status = "disabled";
604 }; 604 };
605 605
606 wdog3: watchdog@302a00 606 wdog3: watchdog@302a0000 {
607 compatible = " 607 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
608 reg = <0x302a0 608 reg = <0x302a0000 0x10000>;
609 interrupts = < 609 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&clk 610 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>;
611 status = "disa 611 status = "disabled";
612 }; 612 };
613 613
614 gpt1: timer@302d0000 { 614 gpt1: timer@302d0000 {
615 compatible = " 615 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
616 reg = <0x302d0 616 reg = <0x302d0000 0x10000>;
617 interrupts = < 617 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&clk 618 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>;
619 clock-names = 619 clock-names = "ipg", "per";
620 }; 620 };
621 621
622 gpt2: timer@302e0000 { 622 gpt2: timer@302e0000 {
623 compatible = " 623 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
624 reg = <0x302e0 624 reg = <0x302e0000 0x10000>;
625 interrupts = < 625 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&clk 626 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>;
627 clock-names = 627 clock-names = "ipg", "per";
628 }; 628 };
629 629
630 gpt3: timer@302f0000 { 630 gpt3: timer@302f0000 {
631 compatible = " 631 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
632 reg = <0x302f0 632 reg = <0x302f0000 0x10000>;
633 interrupts = < 633 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&clk 634 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>;
635 clock-names = 635 clock-names = "ipg", "per";
636 }; 636 };
637 637
638 iomuxc: pinctrl@303300 638 iomuxc: pinctrl@30330000 {
639 compatible = " 639 compatible = "fsl,imx8mp-iomuxc";
640 reg = <0x30330 640 reg = <0x30330000 0x10000>;
641 }; 641 };
642 642
643 gpr: syscon@30340000 { 643 gpr: syscon@30340000 {
644 compatible = " 644 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
645 reg = <0x30340 645 reg = <0x30340000 0x10000>;
646 }; 646 };
647 647
648 ocotp: efuse@30350000 648 ocotp: efuse@30350000 {
649 compatible = " 649 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
650 reg = <0x30350 650 reg = <0x30350000 0x10000>;
651 clocks = <&clk 651 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>;
652 /* For nvmem s 652 /* For nvmem subnodes */
653 #address-cells 653 #address-cells = <1>;
654 #size-cells = 654 #size-cells = <1>;
655 655
656 /* 656 /*
657 * The registe 657 * The register address below maps to the MX8M
658 * Fusemap Des 658 * Fusemap Description Table entries this way.
659 * Assuming 659 * Assuming
660 * reg = <AD 660 * reg = <ADDR SIZE>;
661 * then 661 * then
662 * Fuse Addr 662 * Fuse Address = (ADDR * 4) + 0x400
663 * Note that i 663 * Note that if SIZE is greater than 4, then
664 * each subseq 664 * each subsequent fuse is located at offset
665 * +0x10 in Fu 665 * +0x10 in Fusemap Description Table (e.g.
666 * reg = <0x8 666 * reg = <0x8 0x8> describes fuses 0x420 and
667 * 0x430). 667 * 0x430).
668 */ 668 */
669 imx8mp_uid: un 669 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
670 reg = 670 reg = <0x8 0x8>;
671 }; 671 };
672 672
673 cpu_speed_grad 673 cpu_speed_grade: speed-grade@10 { /* 0x440 */
674 reg = 674 reg = <0x10 4>;
675 }; 675 };
676 676
677 eth_mac1: mac- 677 eth_mac1: mac-address@90 { /* 0x640 */
678 reg = 678 reg = <0x90 6>;
679 }; 679 };
680 680
681 eth_mac2: mac- 681 eth_mac2: mac-address@96 { /* 0x658 */
682 reg = 682 reg = <0x96 6>;
683 }; 683 };
684 684
685 tmu_calib: cal 685 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
686 reg = 686 reg = <0x264 0x10>;
687 }; 687 };
688 }; 688 };
689 689
690 anatop: clock-controll 690 anatop: clock-controller@30360000 {
691 compatible = " 691 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
692 reg = <0x30360 692 reg = <0x30360000 0x10000>;
693 #clock-cells = 693 #clock-cells = <1>;
694 }; 694 };
695 695
696 snvs: snvs@30370000 { 696 snvs: snvs@30370000 {
697 compatible = " 697 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 reg = <0x30370 698 reg = <0x30370000 0x10000>;
699 699
700 snvs_rtc: snvs 700 snvs_rtc: snvs-rtc-lp {
701 compat 701 compatible = "fsl,sec-v4.0-mon-rtc-lp";
702 regmap 702 regmap = <&snvs>;
703 offset 703 offset = <0x34>;
704 interr 704 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
705 705 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
706 clocks 706 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
707 clock- 707 clock-names = "snvs-rtc";
708 }; 708 };
709 709
710 snvs_pwrkey: s 710 snvs_pwrkey: snvs-powerkey {
711 compat 711 compatible = "fsl,sec-v4.0-pwrkey";
712 regmap 712 regmap = <&snvs>;
713 interr 713 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
714 clocks 714 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>;
715 clock- 715 clock-names = "snvs-pwrkey";
716 linux, 716 linux,keycode = <KEY_POWER>;
717 wakeup 717 wakeup-source;
718 status 718 status = "disabled";
719 }; 719 };
720 720
721 snvs_lpgpr: sn 721 snvs_lpgpr: snvs-lpgpr {
722 compat 722 compatible = "fsl,imx8mp-snvs-lpgpr",
723 723 "fsl,imx7d-snvs-lpgpr";
724 }; 724 };
725 }; 725 };
726 726
727 clk: clock-controller@ 727 clk: clock-controller@30380000 {
728 compatible = " 728 compatible = "fsl,imx8mp-ccm";
729 reg = <0x30380 729 reg = <0x30380000 0x10000>;
730 interrupts = < 730 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
731 < 731 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
732 #clock-cells = 732 #clock-cells = <1>;
733 clocks = <&osc 733 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
734 <&clk 734 <&clk_ext3>, <&clk_ext4>;
735 clock-names = 735 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
736 736 "clk_ext3", "clk_ext4";
737 assigned-clock 737 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 738 <&clk IMX8MP_CLK_A53_CORE>,
739 739 <&clk IMX8MP_CLK_NOC>,
740 740 <&clk IMX8MP_CLK_NOC_IO>,
741 741 <&clk IMX8MP_CLK_GIC>;
742 assigned-clock 742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 743 <&clk IMX8MP_ARM_PLL_OUT>,
744 744 <&clk IMX8MP_SYS_PLL2_1000M>,
745 745 <&clk IMX8MP_SYS_PLL1_800M>,
746 746 <&clk IMX8MP_SYS_PLL2_500M>;
747 assigned-clock 747 assigned-clock-rates = <0>, <0>,
748 748 <1000000000>,
749 749 <800000000>,
750 750 <500000000>;
751 }; 751 };
752 752
753 src: reset-controller@ 753 src: reset-controller@30390000 {
754 compatible = " 754 compatible = "fsl,imx8mp-src", "syscon";
755 reg = <0x30390 755 reg = <0x30390000 0x10000>;
756 interrupts = < 756 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
757 #reset-cells = 757 #reset-cells = <1>;
758 }; 758 };
759 759
760 gpc: gpc@303a0000 { 760 gpc: gpc@303a0000 {
761 compatible = " 761 compatible = "fsl,imx8mp-gpc";
762 reg = <0x303a0 762 reg = <0x303a0000 0x1000>;
763 interrupt-pare 763 interrupt-parent = <&gic>;
764 interrupts = < 764 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
765 interrupt-cont 765 interrupt-controller;
766 #interrupt-cel 766 #interrupt-cells = <3>;
767 767
768 pgc { 768 pgc {
769 #addre 769 #address-cells = <1>;
770 #size- 770 #size-cells = <0>;
771 771
772 pgc_mi 772 pgc_mipi_phy1: power-domain@0 {
773 773 #power-domain-cells = <0>;
774 774 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>;
775 }; 775 };
776 776
777 pgc_pc 777 pgc_pcie_phy: power-domain@1 {
778 778 #power-domain-cells = <0>;
779 779 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
780 }; 780 };
781 781
782 pgc_us 782 pgc_usb1_phy: power-domain@2 {
783 783 #power-domain-cells = <0>;
784 784 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
785 }; 785 };
786 786
787 pgc_us 787 pgc_usb2_phy: power-domain@3 {
788 788 #power-domain-cells = <0>;
789 789 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
790 }; 790 };
791 791
792 pgc_ml 792 pgc_mlmix: power-domain@4 {
793 793 #power-domain-cells = <0>;
794 794 reg = <IMX8MP_POWER_DOMAIN_MLMIX>;
795 795 clocks = <&clk IMX8MP_CLK_ML_AXI>,
796 796 <&clk IMX8MP_CLK_ML_AHB>,
797 797 <&clk IMX8MP_CLK_NPU_ROOT>;
798 798 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>,
799 799 <&clk IMX8MP_CLK_ML_AXI>,
800 800 <&clk IMX8MP_CLK_ML_AHB>;
801 801 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
802 802 <&clk IMX8MP_SYS_PLL1_800M>,
803 803 <&clk IMX8MP_SYS_PLL1_800M>;
804 804 assigned-clock-rates = <800000000>,
805 805 <800000000>,
806 806 <300000000>;
807 }; 807 };
808 808
809 pgc_au 809 pgc_audio: power-domain@5 {
810 810 #power-domain-cells = <0>;
811 811 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>;
812 812 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
813 813 <&clk IMX8MP_CLK_AUDIO_AXI>;
814 814 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
815 815 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>;
816 816 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
817 817 <&clk IMX8MP_SYS_PLL1_800M>;
818 818 assigned-clock-rates = <400000000>,
819 819 <600000000>;
820 }; 820 };
821 821
822 pgc_gp 822 pgc_gpu2d: power-domain@6 {
823 823 #power-domain-cells = <0>;
824 824 reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
825 825 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
826 826 power-domains = <&pgc_gpumix>;
827 }; 827 };
828 828
829 pgc_gp 829 pgc_gpumix: power-domain@7 {
830 830 #power-domain-cells = <0>;
831 831 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
832 832 clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
833 833 <&clk IMX8MP_CLK_GPU_AHB>;
834 834 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
835 835 <&clk IMX8MP_CLK_GPU_AHB>;
836 836 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
837 837 <&clk IMX8MP_SYS_PLL1_800M>;
838 838 assigned-clock-rates = <800000000>, <400000000>;
839 }; 839 };
840 840
841 pgc_vp 841 pgc_vpumix: power-domain@8 {
842 842 #power-domain-cells = <0>;
843 843 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>;
844 844 clocks = <&clk IMX8MP_CLK_VPU_ROOT>;
845 }; 845 };
846 846
847 pgc_gp 847 pgc_gpu3d: power-domain@9 {
848 848 #power-domain-cells = <0>;
849 849 reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
850 850 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
851 851 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
852 852 power-domains = <&pgc_gpumix>;
853 }; 853 };
854 854
855 pgc_me 855 pgc_mediamix: power-domain@10 {
856 856 #power-domain-cells = <0>;
857 857 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>;
858 858 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
859 859 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
860 }; 860 };
861 861
862 pgc_vp 862 pgc_vpu_g1: power-domain@11 {
863 863 #power-domain-cells = <0>;
864 864 power-domains = <&pgc_vpumix>;
865 865 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>;
866 866 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
867 }; 867 };
868 868
869 pgc_vp 869 pgc_vpu_g2: power-domain@12 {
870 870 #power-domain-cells = <0>;
871 871 power-domains = <&pgc_vpumix>;
872 872 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>;
873 873 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
874 874
875 }; 875 };
876 876
877 pgc_vp 877 pgc_vpu_vc8000e: power-domain@13 {
878 878 #power-domain-cells = <0>;
879 879 power-domains = <&pgc_vpumix>;
880 880 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>;
881 881 clocks = <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
882 }; 882 };
883 883
884 pgc_hd 884 pgc_hdmimix: power-domain@14 {
885 885 #power-domain-cells = <0>;
886 886 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>;
887 887 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>,
888 888 <&clk IMX8MP_CLK_HDMI_APB>;
889 889 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>,
890 890 <&clk IMX8MP_CLK_HDMI_APB>;
891 891 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>,
892 892 <&clk IMX8MP_SYS_PLL1_133M>;
893 893 assigned-clock-rates = <500000000>, <133000000>;
894 }; 894 };
895 895
896 pgc_hd 896 pgc_hdmi_phy: power-domain@15 {
897 897 #power-domain-cells = <0>;
898 898 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>;
899 }; 899 };
900 900
901 pgc_mi 901 pgc_mipi_phy2: power-domain@16 {
902 902 #power-domain-cells = <0>;
903 903 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>;
904 }; 904 };
905 905
906 pgc_hs 906 pgc_hsiomix: power-domain@17 {
907 907 #power-domain-cells = <0>;
908 908 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
909 909 clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
910 910 <&clk IMX8MP_CLK_HSIO_ROOT>;
911 911 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
912 912 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
913 913 assigned-clock-rates = <500000000>;
914 }; 914 };
915 915
916 pgc_is 916 pgc_ispdwp: power-domain@18 {
917 917 #power-domain-cells = <0>;
918 918 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
919 919 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
920 }; 920 };
921 }; 921 };
922 }; 922 };
923 }; 923 };
924 924
925 aips2: bus@30400000 { 925 aips2: bus@30400000 {
926 compatible = "fsl,aips 926 compatible = "fsl,aips-bus", "simple-bus";
927 reg = <0x30400000 0x40 927 reg = <0x30400000 0x400000>;
928 #address-cells = <1>; 928 #address-cells = <1>;
929 #size-cells = <1>; 929 #size-cells = <1>;
930 ranges; 930 ranges;
931 931
932 pwm1: pwm@30660000 { 932 pwm1: pwm@30660000 {
933 compatible = " 933 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
934 reg = <0x30660 934 reg = <0x30660000 0x10000>;
935 interrupts = < 935 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
936 clocks = <&clk 936 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>,
937 <&clk 937 <&clk IMX8MP_CLK_PWM1_ROOT>;
938 clock-names = 938 clock-names = "ipg", "per";
939 #pwm-cells = < 939 #pwm-cells = <3>;
940 status = "disa 940 status = "disabled";
941 }; 941 };
942 942
943 pwm2: pwm@30670000 { 943 pwm2: pwm@30670000 {
944 compatible = " 944 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
945 reg = <0x30670 945 reg = <0x30670000 0x10000>;
946 interrupts = < 946 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
947 clocks = <&clk 947 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>,
948 <&clk 948 <&clk IMX8MP_CLK_PWM2_ROOT>;
949 clock-names = 949 clock-names = "ipg", "per";
950 #pwm-cells = < 950 #pwm-cells = <3>;
951 status = "disa 951 status = "disabled";
952 }; 952 };
953 953
954 pwm3: pwm@30680000 { 954 pwm3: pwm@30680000 {
955 compatible = " 955 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
956 reg = <0x30680 956 reg = <0x30680000 0x10000>;
957 interrupts = < 957 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&clk 958 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>,
959 <&clk 959 <&clk IMX8MP_CLK_PWM3_ROOT>;
960 clock-names = 960 clock-names = "ipg", "per";
961 #pwm-cells = < 961 #pwm-cells = <3>;
962 status = "disa 962 status = "disabled";
963 }; 963 };
964 964
965 pwm4: pwm@30690000 { 965 pwm4: pwm@30690000 {
966 compatible = " 966 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
967 reg = <0x30690 967 reg = <0x30690000 0x10000>;
968 interrupts = < 968 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
969 clocks = <&clk 969 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>,
970 <&clk 970 <&clk IMX8MP_CLK_PWM4_ROOT>;
971 clock-names = 971 clock-names = "ipg", "per";
972 #pwm-cells = < 972 #pwm-cells = <3>;
973 status = "disa 973 status = "disabled";
974 }; 974 };
975 975
976 system_counter: timer@ 976 system_counter: timer@306a0000 {
977 compatible = " 977 compatible = "nxp,sysctr-timer";
978 reg = <0x306a0 978 reg = <0x306a0000 0x20000>;
979 interrupts = < 979 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&osc 980 clocks = <&osc_24m>;
981 clock-names = 981 clock-names = "per";
982 }; 982 };
983 983
984 gpt6: timer@306e0000 { 984 gpt6: timer@306e0000 {
985 compatible = " 985 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
986 reg = <0x306e0 986 reg = <0x306e0000 0x10000>;
987 interrupts = < 987 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&clk 988 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>;
989 clock-names = 989 clock-names = "ipg", "per";
990 }; 990 };
991 991
992 gpt5: timer@306f0000 { 992 gpt5: timer@306f0000 {
993 compatible = " 993 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
994 reg = <0x306f0 994 reg = <0x306f0000 0x10000>;
995 interrupts = < 995 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
996 clocks = <&clk 996 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>;
997 clock-names = 997 clock-names = "ipg", "per";
998 }; 998 };
999 999
1000 gpt4: timer@30700000 1000 gpt4: timer@30700000 {
1001 compatible = 1001 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
1002 reg = <0x3070 1002 reg = <0x30700000 0x10000>;
1003 interrupts = 1003 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&cl 1004 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>;
1005 clock-names = 1005 clock-names = "ipg", "per";
1006 }; 1006 };
1007 }; 1007 };
1008 1008
1009 aips3: bus@30800000 { 1009 aips3: bus@30800000 {
1010 compatible = "fsl,aip 1010 compatible = "fsl,aips-bus", "simple-bus";
1011 reg = <0x30800000 0x4 1011 reg = <0x30800000 0x400000>;
1012 #address-cells = <1>; 1012 #address-cells = <1>;
1013 #size-cells = <1>; 1013 #size-cells = <1>;
1014 ranges; 1014 ranges;
1015 1015
1016 spba-bus@30800000 { 1016 spba-bus@30800000 {
1017 compatible = 1017 compatible = "fsl,spba-bus", "simple-bus";
1018 reg = <0x3080 1018 reg = <0x30800000 0x100000>;
1019 #address-cell 1019 #address-cells = <1>;
1020 #size-cells = 1020 #size-cells = <1>;
1021 ranges; 1021 ranges;
1022 1022
1023 ecspi1: spi@3 1023 ecspi1: spi@30820000 {
1024 #addr 1024 #address-cells = <1>;
1025 #size 1025 #size-cells = <0>;
1026 compa 1026 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1027 reg = 1027 reg = <0x30820000 0x10000>;
1028 inter 1028 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1029 clock 1029 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>,
1030 1030 <&clk IMX8MP_CLK_ECSPI1_ROOT>;
1031 clock 1031 clock-names = "ipg", "per";
1032 assig 1032 assigned-clock-rates = <80000000>;
1033 assig 1033 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1034 assig 1034 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1035 dmas 1035 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
1036 dma-n 1036 dma-names = "rx", "tx";
1037 statu 1037 status = "disabled";
1038 }; 1038 };
1039 1039
1040 ecspi2: spi@3 1040 ecspi2: spi@30830000 {
1041 #addr 1041 #address-cells = <1>;
1042 #size 1042 #size-cells = <0>;
1043 compa 1043 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1044 reg = 1044 reg = <0x30830000 0x10000>;
1045 inter 1045 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1046 clock 1046 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>,
1047 1047 <&clk IMX8MP_CLK_ECSPI2_ROOT>;
1048 clock 1048 clock-names = "ipg", "per";
1049 assig 1049 assigned-clock-rates = <80000000>;
1050 assig 1050 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1051 assig 1051 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1052 dmas 1052 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
1053 dma-n 1053 dma-names = "rx", "tx";
1054 statu 1054 status = "disabled";
1055 }; 1055 };
1056 1056
1057 ecspi3: spi@3 1057 ecspi3: spi@30840000 {
1058 #addr 1058 #address-cells = <1>;
1059 #size 1059 #size-cells = <0>;
1060 compa 1060 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1061 reg = 1061 reg = <0x30840000 0x10000>;
1062 inter 1062 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1063 clock 1063 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>,
1064 1064 <&clk IMX8MP_CLK_ECSPI3_ROOT>;
1065 clock 1065 clock-names = "ipg", "per";
1066 assig 1066 assigned-clock-rates = <80000000>;
1067 assig 1067 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1068 assig 1068 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1069 dmas 1069 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
1070 dma-n 1070 dma-names = "rx", "tx";
1071 statu 1071 status = "disabled";
1072 }; 1072 };
1073 1073
1074 uart1: serial 1074 uart1: serial@30860000 {
1075 compa 1075 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1076 reg = 1076 reg = <0x30860000 0x10000>;
1077 inter 1077 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1078 clock 1078 clocks = <&clk IMX8MP_CLK_UART1_ROOT>,
1079 1079 <&clk IMX8MP_CLK_UART1_ROOT>;
1080 clock 1080 clock-names = "ipg", "per";
1081 dmas 1081 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
1082 dma-n 1082 dma-names = "rx", "tx";
1083 statu 1083 status = "disabled";
1084 }; 1084 };
1085 1085
1086 uart3: serial 1086 uart3: serial@30880000 {
1087 compa 1087 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1088 reg = 1088 reg = <0x30880000 0x10000>;
1089 inter 1089 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
1090 clock 1090 clocks = <&clk IMX8MP_CLK_UART3_ROOT>,
1091 1091 <&clk IMX8MP_CLK_UART3_ROOT>;
1092 clock 1092 clock-names = "ipg", "per";
1093 dmas 1093 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
1094 dma-n 1094 dma-names = "rx", "tx";
1095 statu 1095 status = "disabled";
1096 }; 1096 };
1097 1097
1098 uart2: serial 1098 uart2: serial@30890000 {
1099 compa 1099 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1100 reg = 1100 reg = <0x30890000 0x10000>;
1101 inter 1101 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
1102 clock 1102 clocks = <&clk IMX8MP_CLK_UART2_ROOT>,
1103 1103 <&clk IMX8MP_CLK_UART2_ROOT>;
1104 clock 1104 clock-names = "ipg", "per";
1105 dmas 1105 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>;
1106 dma-n 1106 dma-names = "rx", "tx";
1107 statu 1107 status = "disabled";
1108 }; 1108 };
1109 1109
1110 flexcan1: can 1110 flexcan1: can@308c0000 {
1111 compa 1111 compatible = "fsl,imx8mp-flexcan";
1112 reg = 1112 reg = <0x308c0000 0x10000>;
1113 inter 1113 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
1114 clock 1114 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1115 1115 <&clk IMX8MP_CLK_CAN1_ROOT>;
1116 clock 1116 clock-names = "ipg", "per";
1117 assig 1117 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1118 assig 1118 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1119 assig 1119 assigned-clock-rates = <40000000>;
1120 fsl,c 1120 fsl,clk-source = /bits/ 8 <0>;
1121 fsl,s 1121 fsl,stop-mode = <&gpr 0x10 4>;
1122 statu 1122 status = "disabled";
1123 }; 1123 };
1124 1124
1125 flexcan2: can 1125 flexcan2: can@308d0000 {
1126 compa 1126 compatible = "fsl,imx8mp-flexcan";
1127 reg = 1127 reg = <0x308d0000 0x10000>;
1128 inter 1128 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
1129 clock 1129 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1130 1130 <&clk IMX8MP_CLK_CAN2_ROOT>;
1131 clock 1131 clock-names = "ipg", "per";
1132 assig 1132 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1133 assig 1133 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1134 assig 1134 assigned-clock-rates = <40000000>;
1135 fsl,c 1135 fsl,clk-source = /bits/ 8 <0>;
1136 fsl,s 1136 fsl,stop-mode = <&gpr 0x10 5>;
1137 statu 1137 status = "disabled";
1138 }; 1138 };
1139 }; 1139 };
1140 1140
1141 crypto: crypto@309000 1141 crypto: crypto@30900000 {
1142 compatible = 1142 compatible = "fsl,sec-v4.0";
1143 #address-cell 1143 #address-cells = <1>;
1144 #size-cells = 1144 #size-cells = <1>;
1145 reg = <0x3090 1145 reg = <0x30900000 0x40000>;
1146 ranges = <0 0 1146 ranges = <0 0x30900000 0x40000>;
1147 interrupts = 1147 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
1148 clocks = <&cl 1148 clocks = <&clk IMX8MP_CLK_AHB>,
1149 <&cl 1149 <&clk IMX8MP_CLK_IPG_ROOT>;
1150 clock-names = 1150 clock-names = "aclk", "ipg";
1151 1151
1152 sec_jr0: jr@1 1152 sec_jr0: jr@1000 {
1153 compa 1153 compatible = "fsl,sec-v4.0-job-ring";
1154 reg = 1154 reg = <0x1000 0x1000>;
1155 inter 1155 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1156 statu 1156 status = "disabled";
1157 }; 1157 };
1158 1158
1159 sec_jr1: jr@2 1159 sec_jr1: jr@2000 {
1160 compa 1160 compatible = "fsl,sec-v4.0-job-ring";
1161 reg = 1161 reg = <0x2000 0x1000>;
1162 inter 1162 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1163 }; 1163 };
1164 1164
1165 sec_jr2: jr@3 1165 sec_jr2: jr@3000 {
1166 compa 1166 compatible = "fsl,sec-v4.0-job-ring";
1167 reg = 1167 reg = <0x3000 0x1000>;
1168 inter 1168 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
1169 }; 1169 };
1170 }; 1170 };
1171 1171
1172 i2c1: i2c@30a20000 { 1172 i2c1: i2c@30a20000 {
1173 compatible = 1173 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1174 #address-cell 1174 #address-cells = <1>;
1175 #size-cells = 1175 #size-cells = <0>;
1176 reg = <0x30a2 1176 reg = <0x30a20000 0x10000>;
1177 interrupts = 1177 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1178 clocks = <&cl 1178 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>;
1179 status = "dis 1179 status = "disabled";
1180 }; 1180 };
1181 1181
1182 i2c2: i2c@30a30000 { 1182 i2c2: i2c@30a30000 {
1183 compatible = 1183 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1184 #address-cell 1184 #address-cells = <1>;
1185 #size-cells = 1185 #size-cells = <0>;
1186 reg = <0x30a3 1186 reg = <0x30a30000 0x10000>;
1187 interrupts = 1187 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1188 clocks = <&cl 1188 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>;
1189 status = "dis 1189 status = "disabled";
1190 }; 1190 };
1191 1191
1192 i2c3: i2c@30a40000 { 1192 i2c3: i2c@30a40000 {
1193 compatible = 1193 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1194 #address-cell 1194 #address-cells = <1>;
1195 #size-cells = 1195 #size-cells = <0>;
1196 reg = <0x30a4 1196 reg = <0x30a40000 0x10000>;
1197 interrupts = 1197 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1198 clocks = <&cl 1198 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>;
1199 status = "dis 1199 status = "disabled";
1200 }; 1200 };
1201 1201
1202 i2c4: i2c@30a50000 { 1202 i2c4: i2c@30a50000 {
1203 compatible = 1203 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1204 #address-cell 1204 #address-cells = <1>;
1205 #size-cells = 1205 #size-cells = <0>;
1206 reg = <0x30a5 1206 reg = <0x30a50000 0x10000>;
1207 interrupts = 1207 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
1208 clocks = <&cl 1208 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>;
1209 status = "dis 1209 status = "disabled";
1210 }; 1210 };
1211 1211
1212 uart4: serial@30a6000 1212 uart4: serial@30a60000 {
1213 compatible = 1213 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1214 reg = <0x30a6 1214 reg = <0x30a60000 0x10000>;
1215 interrupts = 1215 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1216 clocks = <&cl 1216 clocks = <&clk IMX8MP_CLK_UART4_ROOT>,
1217 <&cl 1217 <&clk IMX8MP_CLK_UART4_ROOT>;
1218 clock-names = 1218 clock-names = "ipg", "per";
1219 dmas = <&sdma 1219 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
1220 dma-names = " 1220 dma-names = "rx", "tx";
1221 status = "dis 1221 status = "disabled";
1222 }; 1222 };
1223 1223
1224 mu: mailbox@30aa0000 1224 mu: mailbox@30aa0000 {
1225 compatible = 1225 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1226 reg = <0x30aa 1226 reg = <0x30aa0000 0x10000>;
1227 interrupts = 1227 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1228 clocks = <&cl 1228 clocks = <&clk IMX8MP_CLK_MU_ROOT>;
1229 #mbox-cells = 1229 #mbox-cells = <2>;
1230 }; 1230 };
1231 1231
1232 mu2: mailbox@30e60000 1232 mu2: mailbox@30e60000 {
1233 compatible = 1233 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1234 reg = <0x30e6 1234 reg = <0x30e60000 0x10000>;
1235 interrupts = 1235 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1236 #mbox-cells = 1236 #mbox-cells = <2>;
1237 status = "dis 1237 status = "disabled";
1238 }; 1238 };
1239 1239
1240 i2c5: i2c@30ad0000 { 1240 i2c5: i2c@30ad0000 {
1241 compatible = 1241 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1242 #address-cell 1242 #address-cells = <1>;
1243 #size-cells = 1243 #size-cells = <0>;
1244 reg = <0x30ad 1244 reg = <0x30ad0000 0x10000>;
1245 interrupts = 1245 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1246 clocks = <&cl 1246 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>;
1247 status = "dis 1247 status = "disabled";
1248 }; 1248 };
1249 1249
1250 i2c6: i2c@30ae0000 { 1250 i2c6: i2c@30ae0000 {
1251 compatible = 1251 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1252 #address-cell 1252 #address-cells = <1>;
1253 #size-cells = 1253 #size-cells = <0>;
1254 reg = <0x30ae 1254 reg = <0x30ae0000 0x10000>;
1255 interrupts = 1255 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
1256 clocks = <&cl 1256 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>;
1257 status = "dis 1257 status = "disabled";
1258 }; 1258 };
1259 1259
1260 usdhc1: mmc@30b40000 1260 usdhc1: mmc@30b40000 {
1261 compatible = 1261 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1262 reg = <0x30b4 1262 reg = <0x30b40000 0x10000>;
1263 interrupts = 1263 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
1264 clocks = <&cl 1264 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1265 <&cl 1265 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1266 <&cl 1266 <&clk IMX8MP_CLK_USDHC1_ROOT>;
1267 clock-names = 1267 clock-names = "ipg", "ahb", "per";
1268 fsl,tuning-st 1268 fsl,tuning-start-tap = <20>;
1269 fsl,tuning-st 1269 fsl,tuning-step = <2>;
1270 bus-width = < 1270 bus-width = <4>;
1271 status = "dis 1271 status = "disabled";
1272 }; 1272 };
1273 1273
1274 usdhc2: mmc@30b50000 1274 usdhc2: mmc@30b50000 {
1275 compatible = 1275 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1276 reg = <0x30b5 1276 reg = <0x30b50000 0x10000>;
1277 interrupts = 1277 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&cl 1278 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1279 <&cl 1279 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1280 <&cl 1280 <&clk IMX8MP_CLK_USDHC2_ROOT>;
1281 clock-names = 1281 clock-names = "ipg", "ahb", "per";
1282 fsl,tuning-st 1282 fsl,tuning-start-tap = <20>;
1283 fsl,tuning-st 1283 fsl,tuning-step = <2>;
1284 bus-width = < 1284 bus-width = <4>;
1285 status = "dis 1285 status = "disabled";
1286 }; 1286 };
1287 1287
1288 usdhc3: mmc@30b60000 1288 usdhc3: mmc@30b60000 {
1289 compatible = 1289 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1290 reg = <0x30b6 1290 reg = <0x30b60000 0x10000>;
1291 interrupts = 1291 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1292 clocks = <&cl 1292 clocks = <&clk IMX8MP_CLK_IPG_ROOT>,
1293 <&cl 1293 <&clk IMX8MP_CLK_NAND_USDHC_BUS>,
1294 <&cl 1294 <&clk IMX8MP_CLK_USDHC3_ROOT>;
1295 clock-names = 1295 clock-names = "ipg", "ahb", "per";
1296 fsl,tuning-st 1296 fsl,tuning-start-tap = <20>;
1297 fsl,tuning-st 1297 fsl,tuning-step = <2>;
1298 bus-width = < 1298 bus-width = <4>;
1299 status = "dis 1299 status = "disabled";
1300 }; 1300 };
1301 1301
1302 flexspi: spi@30bb0000 1302 flexspi: spi@30bb0000 {
1303 compatible = 1303 compatible = "nxp,imx8mp-fspi";
1304 reg = <0x30bb 1304 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
1305 reg-names = " 1305 reg-names = "fspi_base", "fspi_mmap";
1306 interrupts = 1306 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&cl 1307 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>,
1308 <&cl 1308 <&clk IMX8MP_CLK_QSPI_ROOT>;
1309 clock-names = 1309 clock-names = "fspi_en", "fspi";
1310 assigned-cloc 1310 assigned-clock-rates = <80000000>;
1311 assigned-cloc 1311 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1312 #address-cell 1312 #address-cells = <1>;
1313 #size-cells = 1313 #size-cells = <0>;
1314 status = "dis 1314 status = "disabled";
1315 }; 1315 };
1316 1316
1317 sdma1: dma-controller 1317 sdma1: dma-controller@30bd0000 {
1318 compatible = 1318 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1319 reg = <0x30bd 1319 reg = <0x30bd0000 0x10000>;
1320 interrupts = 1320 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1321 clocks = <&cl 1321 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>,
1322 <&cl 1322 <&clk IMX8MP_CLK_AHB>;
1323 clock-names = 1323 clock-names = "ipg", "ahb";
1324 #dma-cells = 1324 #dma-cells = <3>;
1325 fsl,sdma-ram- 1325 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1326 }; 1326 };
1327 1327
1328 fec: ethernet@30be000 1328 fec: ethernet@30be0000 {
1329 compatible = 1329 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1330 reg = <0x30be 1330 reg = <0x30be0000 0x10000>;
1331 interrupts = 1331 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
1332 1332 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
1333 1333 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
1334 1334 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1335 clocks = <&cl 1335 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>,
1336 <&cl 1336 <&clk IMX8MP_CLK_SIM_ENET_ROOT>,
1337 <&cl 1337 <&clk IMX8MP_CLK_ENET_TIMER>,
1338 <&cl 1338 <&clk IMX8MP_CLK_ENET_REF>,
1339 <&cl 1339 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1340 clock-names = 1340 clock-names = "ipg", "ahb", "ptp",
1341 1341 "enet_clk_ref", "enet_out";
1342 assigned-cloc 1342 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1343 1343 <&clk IMX8MP_CLK_ENET_TIMER>,
1344 1344 <&clk IMX8MP_CLK_ENET_REF>,
1345 1345 <&clk IMX8MP_CLK_ENET_PHY_REF>;
1346 assigned-cloc 1346 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1347 1347 <&clk IMX8MP_SYS_PLL2_100M>,
1348 1348 <&clk IMX8MP_SYS_PLL2_125M>,
1349 1349 <&clk IMX8MP_SYS_PLL2_50M>;
1350 assigned-cloc 1350 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1351 fsl,num-tx-qu 1351 fsl,num-tx-queues = <3>;
1352 fsl,num-rx-qu 1352 fsl,num-rx-queues = <3>;
1353 nvmem-cells = 1353 nvmem-cells = <ð_mac1>;
1354 nvmem-cell-na 1354 nvmem-cell-names = "mac-address";
1355 fsl,stop-mode 1355 fsl,stop-mode = <&gpr 0x10 3>;
1356 status = "dis 1356 status = "disabled";
1357 }; 1357 };
1358 1358
1359 eqos: ethernet@30bf00 1359 eqos: ethernet@30bf0000 {
1360 compatible = 1360 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1361 reg = <0x30bf 1361 reg = <0x30bf0000 0x10000>;
1362 interrupts = 1362 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1363 1363 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
1364 interrupt-nam 1364 interrupt-names = "macirq", "eth_wake_irq";
1365 clocks = <&cl 1365 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
1366 <&cl 1366 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
1367 <&cl 1367 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1368 <&cl 1368 <&clk IMX8MP_CLK_ENET_QOS>;
1369 clock-names = 1369 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1370 assigned-cloc 1370 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1371 1371 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
1372 1372 <&clk IMX8MP_CLK_ENET_QOS>;
1373 assigned-cloc 1373 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1374 1374 <&clk IMX8MP_SYS_PLL2_100M>,
1375 1375 <&clk IMX8MP_SYS_PLL2_125M>;
1376 assigned-cloc 1376 assigned-clock-rates = <0>, <100000000>, <125000000>;
1377 nvmem-cells = 1377 nvmem-cells = <ð_mac2>;
1378 nvmem-cell-na 1378 nvmem-cell-names = "mac-address";
1379 intf_mode = < 1379 intf_mode = <&gpr 0x4>;
1380 status = "dis 1380 status = "disabled";
1381 }; 1381 };
1382 }; 1382 };
1383 1383
1384 aips5: bus@30c00000 { 1384 aips5: bus@30c00000 {
1385 compatible = "fsl,aip 1385 compatible = "fsl,aips-bus", "simple-bus";
1386 reg = <0x30c00000 0x4 1386 reg = <0x30c00000 0x400000>;
1387 #address-cells = <1>; 1387 #address-cells = <1>;
1388 #size-cells = <1>; 1388 #size-cells = <1>;
1389 ranges; 1389 ranges;
1390 1390
1391 spba-bus@30c00000 { 1391 spba-bus@30c00000 {
1392 compatible = 1392 compatible = "fsl,spba-bus", "simple-bus";
1393 reg = <0x30c0 1393 reg = <0x30c00000 0x100000>;
1394 #address-cell 1394 #address-cells = <1>;
1395 #size-cells = 1395 #size-cells = <1>;
1396 ranges; 1396 ranges;
1397 1397
1398 sai1: sai@30c 1398 sai1: sai@30c10000 {
1399 compa 1399 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1400 reg = 1400 reg = <0x30c10000 0x10000>;
1401 #soun 1401 #sound-dai-cells = <0>;
1402 clock 1402 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>,
1403 1403 <&clk IMX8MP_CLK_DUMMY>,
1404 1404 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>,
1405 1405 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>,
1406 1406 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>;
1407 clock 1407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1408 dmas 1408 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
1409 dma-n 1409 dma-names = "rx", "tx";
1410 inter 1410 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
1411 statu 1411 status = "disabled";
1412 }; 1412 };
1413 1413
1414 sai2: sai@30c 1414 sai2: sai@30c20000 {
1415 compa 1415 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1416 reg = 1416 reg = <0x30c20000 0x10000>;
1417 #soun 1417 #sound-dai-cells = <0>;
1418 clock 1418 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>,
1419 1419 <&clk IMX8MP_CLK_DUMMY>,
1420 1420 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>,
1421 1421 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>,
1422 1422 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>;
1423 clock 1423 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1424 dmas 1424 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
1425 dma-n 1425 dma-names = "rx", "tx";
1426 inter 1426 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1427 statu 1427 status = "disabled";
1428 }; 1428 };
1429 1429
1430 sai3: sai@30c 1430 sai3: sai@30c30000 {
1431 compa 1431 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1432 reg = 1432 reg = <0x30c30000 0x10000>;
1433 #soun 1433 #sound-dai-cells = <0>;
1434 clock 1434 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>,
1435 1435 <&clk IMX8MP_CLK_DUMMY>,
1436 1436 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>,
1437 1437 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>,
1438 1438 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>;
1439 clock 1439 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1440 dmas 1440 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
1441 dma-n 1441 dma-names = "rx", "tx";
1442 inter 1442 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1443 statu 1443 status = "disabled";
1444 }; 1444 };
1445 1445
1446 sai5: sai@30c 1446 sai5: sai@30c50000 {
1447 compa 1447 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1448 reg = 1448 reg = <0x30c50000 0x10000>;
1449 #soun 1449 #sound-dai-cells = <0>;
1450 clock 1450 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>,
1451 1451 <&clk IMX8MP_CLK_DUMMY>,
1452 1452 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>,
1453 1453 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>,
1454 1454 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>;
1455 clock 1455 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1456 dmas 1456 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
1457 dma-n 1457 dma-names = "rx", "tx";
1458 inter 1458 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1459 statu 1459 status = "disabled";
1460 }; 1460 };
1461 1461
1462 sai6: sai@30c 1462 sai6: sai@30c60000 {
1463 compa 1463 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1464 reg = 1464 reg = <0x30c60000 0x10000>;
1465 #soun 1465 #sound-dai-cells = <0>;
1466 clock 1466 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>,
1467 1467 <&clk IMX8MP_CLK_DUMMY>,
1468 1468 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>,
1469 1469 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>,
1470 1470 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>;
1471 clock 1471 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1472 dmas 1472 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
1473 dma-n 1473 dma-names = "rx", "tx";
1474 inter 1474 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1475 statu 1475 status = "disabled";
1476 }; 1476 };
1477 1477
1478 sai7: sai@30c 1478 sai7: sai@30c80000 {
1479 compa 1479 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1480 reg = 1480 reg = <0x30c80000 0x10000>;
1481 #soun 1481 #sound-dai-cells = <0>;
1482 clock 1482 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>,
1483 1483 <&clk IMX8MP_CLK_DUMMY>,
1484 1484 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>,
1485 1485 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>,
1486 1486 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>;
1487 clock 1487 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1488 dmas 1488 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>;
1489 dma-n 1489 dma-names = "rx", "tx";
1490 inter 1490 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
1491 statu 1491 status = "disabled";
1492 }; 1492 };
1493 1493
1494 easrc: easrc@ 1494 easrc: easrc@30c90000 {
1495 compa 1495 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc";
1496 reg = 1496 reg = <0x30c90000 0x10000>;
1497 inter 1497 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1498 clock 1498 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>;
1499 clock 1499 clock-names = "mem";
1500 dmas 1500 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>,
1501 1501 <&sdma2 18 23 0> , <&sdma2 19 23 0>,
1502 1502 <&sdma2 20 23 0> , <&sdma2 21 23 0>,
1503 1503 <&sdma2 22 23 0> , <&sdma2 23 23 0>;
1504 dma-n 1504 dma-names = "ctx0_rx", "ctx0_tx",
1505 1505 "ctx1_rx", "ctx1_tx",
1506 1506 "ctx2_rx", "ctx2_tx",
1507 1507 "ctx3_rx", "ctx3_tx";
1508 firmw 1508 firmware-name = "imx/easrc/easrc-imx8mn.bin";
1509 fsl,a 1509 fsl,asrc-rate = <8000>;
1510 fsl,a 1510 fsl,asrc-format = <2>;
1511 statu 1511 status = "disabled";
1512 }; 1512 };
1513 1513
1514 micfil: audio 1514 micfil: audio-controller@30ca0000 {
1515 compa 1515 compatible = "fsl,imx8mp-micfil";
1516 reg = 1516 reg = <0x30ca0000 0x10000>;
1517 #soun 1517 #sound-dai-cells = <0>;
1518 inter 1518 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1519 1519 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1520 1520 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
1521 1521 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1522 clock 1522 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>,
1523 1523 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>,
1524 1524 <&clk IMX8MP_AUDIO_PLL1_OUT>,
1525 1525 <&clk IMX8MP_AUDIO_PLL2_OUT>,
1526 1526 <&clk IMX8MP_CLK_EXT3>;
1527 clock 1527 clock-names = "ipg_clk", "ipg_clk_app",
1528 1528 "pll8k", "pll11k", "clkext3";
1529 dmas 1529 dmas = <&sdma2 24 25 0x80000000>;
1530 dma-n 1530 dma-names = "rx";
1531 statu 1531 status = "disabled";
1532 }; 1532 };
1533 1533
1534 aud2htx: aud2 1534 aud2htx: aud2htx@30cb0000 {
1535 compa 1535 compatible = "fsl,imx8mp-aud2htx";
1536 reg = 1536 reg = <0x30cb0000 0x10000>;
1537 inter 1537 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
1538 clock 1538 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>;
1539 clock 1539 clock-names = "bus";
1540 dmas 1540 dmas = <&sdma2 26 2 0>;
1541 dma-n 1541 dma-names = "tx";
1542 statu 1542 status = "disabled";
1543 }; 1543 };
1544 1544
1545 xcvr: xcvr@30 1545 xcvr: xcvr@30cc0000 {
1546 compa 1546 compatible = "fsl,imx8mp-xcvr";
1547 reg = 1547 reg = <0x30cc0000 0x800>,
1548 1548 <0x30cc0800 0x400>,
1549 1549 <0x30cc0c00 0x080>,
1550 1550 <0x30cc0e00 0x080>;
1551 reg-n 1551 reg-names = "ram", "regs", "rxfifo",
1552 1552 "txfifo";
1553 inter 1553 interrupts = /* XCVR IRQ 0 */
1554 1554 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
1555 1555 /* XCVR IRQ 1 */
1556 1556 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
1557 1557 /* XCVR PHY - SPDIF wakeup IRQ */
1558 1558 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1559 clock 1559 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>,
1560 1560 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>,
1561 1561 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>,
1562 1562 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>;
1563 clock 1563 clock-names = "ipg", "phy", "spba", "pll_ipg";
1564 dmas 1564 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>;
1565 dma-n 1565 dma-names = "rx", "tx";
1566 reset 1566 resets = <&audio_blk_ctrl 0>;
1567 statu 1567 status = "disabled";
1568 }; 1568 };
1569 }; 1569 };
1570 1570
1571 sdma3: dma-controller 1571 sdma3: dma-controller@30e00000 {
1572 compatible = 1572 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1573 reg = <0x30e0 1573 reg = <0x30e00000 0x10000>;
1574 #dma-cells = 1574 #dma-cells = <3>;
1575 clocks = <&au 1575 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>,
1576 <&cl 1576 <&clk IMX8MP_CLK_AUDIO_ROOT>;
1577 clock-names = 1577 clock-names = "ipg", "ahb";
1578 interrupts = 1578 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1579 fsl,sdma-ram- 1579 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1580 }; 1580 };
1581 1581
1582 sdma2: dma-controller 1582 sdma2: dma-controller@30e10000 {
1583 compatible = 1583 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1584 reg = <0x30e1 1584 reg = <0x30e10000 0x10000>;
1585 #dma-cells = 1585 #dma-cells = <3>;
1586 clocks = <&au 1586 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>,
1587 <&cl 1587 <&clk IMX8MP_CLK_AUDIO_ROOT>;
1588 clock-names = 1588 clock-names = "ipg", "ahb";
1589 interrupts = 1589 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1590 fsl,sdma-ram- 1590 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1591 }; 1591 };
1592 1592
1593 audio_blk_ctrl: clock 1593 audio_blk_ctrl: clock-controller@30e20000 {
1594 compatible = 1594 compatible = "fsl,imx8mp-audio-blk-ctrl";
1595 reg = <0x30e2 1595 reg = <0x30e20000 0x10000>;
1596 #clock-cells 1596 #clock-cells = <1>;
1597 #reset-cells 1597 #reset-cells = <1>;
1598 clocks = <&cl 1598 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
1599 <&cl 1599 <&clk IMX8MP_CLK_SAI1>,
1600 <&cl 1600 <&clk IMX8MP_CLK_SAI2>,
1601 <&cl 1601 <&clk IMX8MP_CLK_SAI3>,
1602 <&cl 1602 <&clk IMX8MP_CLK_SAI5>,
1603 <&cl 1603 <&clk IMX8MP_CLK_SAI6>,
1604 <&cl 1604 <&clk IMX8MP_CLK_SAI7>;
1605 clock-names = 1605 clock-names = "ahb",
1606 1606 "sai1", "sai2", "sai3",
1607 1607 "sai5", "sai6", "sai7";
1608 power-domains 1608 power-domains = <&pgc_audio>;
1609 assigned-cloc 1609 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>,
1610 1610 <&clk IMX8MP_AUDIO_PLL2>;
1611 assigned-cloc 1611 assigned-clock-rates = <393216000>, <361267200>;
1612 }; 1612 };
1613 }; 1613 };
1614 1614
1615 noc: interconnect@32700000 { 1615 noc: interconnect@32700000 {
1616 compatible = "fsl,imx 1616 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1617 reg = <0x32700000 0x1 1617 reg = <0x32700000 0x100000>;
1618 clocks = <&clk IMX8MP 1618 clocks = <&clk IMX8MP_CLK_NOC>;
1619 #interconnect-cells = 1619 #interconnect-cells = <1>;
1620 operating-points-v2 = 1620 operating-points-v2 = <&noc_opp_table>;
1621 1621
1622 noc_opp_table: opp-ta 1622 noc_opp_table: opp-table {
1623 compatible = 1623 compatible = "operating-points-v2";
1624 1624
1625 opp-200000000 1625 opp-200000000 {
1626 opp-h 1626 opp-hz = /bits/ 64 <200000000>;
1627 }; 1627 };
1628 1628
1629 opp-100000000 1629 opp-1000000000 {
1630 opp-h 1630 opp-hz = /bits/ 64 <1000000000>;
1631 }; 1631 };
1632 }; 1632 };
1633 }; 1633 };
1634 1634
1635 aips4: bus@32c00000 { 1635 aips4: bus@32c00000 {
1636 compatible = "fsl,aip 1636 compatible = "fsl,aips-bus", "simple-bus";
1637 reg = <0x32c00000 0x4 1637 reg = <0x32c00000 0x400000>;
1638 #address-cells = <1>; 1638 #address-cells = <1>;
1639 #size-cells = <1>; 1639 #size-cells = <1>;
1640 ranges; 1640 ranges;
1641 1641
1642 isi_0: isi@32e00000 { 1642 isi_0: isi@32e00000 {
1643 compatible = 1643 compatible = "fsl,imx8mp-isi";
1644 reg = <0x32e0 1644 reg = <0x32e00000 0x4000>;
1645 interrupts = 1645 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1646 1646 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1647 clocks = <&cl 1647 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1648 <&cl 1648 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1649 clock-names = 1649 clock-names = "axi", "apb";
1650 fsl,blk-ctrl 1650 fsl,blk-ctrl = <&media_blk_ctrl>;
1651 power-domains 1651 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1652 status = "dis 1652 status = "disabled";
1653 1653
1654 ports { 1654 ports {
1655 #addr 1655 #address-cells = <1>;
1656 #size 1656 #size-cells = <0>;
1657 1657
1658 port@ 1658 port@0 {
1659 1659 reg = <0>;
1660 1660
1661 1661 isi_in_0: endpoint {
1662 1662 remote-endpoint = <&mipi_csi_0_out>;
1663 1663 };
1664 }; 1664 };
1665 1665
1666 port@ 1666 port@1 {
1667 1667 reg = <1>;
1668 1668
1669 1669 isi_in_1: endpoint {
1670 1670 remote-endpoint = <&mipi_csi_1_out>;
1671 1671 };
1672 }; 1672 };
1673 }; 1673 };
1674 }; 1674 };
1675 1675
1676 isp_0: isp@32e10000 { 1676 isp_0: isp@32e10000 {
1677 compatible = 1677 compatible = "fsl,imx8mp-isp";
1678 reg = <0x32e1 1678 reg = <0x32e10000 0x10000>;
1679 interrupts = 1679 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1680 clocks = <&cl 1680 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1681 <&cl 1681 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1682 <&cl 1682 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1683 clock-names = 1683 clock-names = "isp", "aclk", "hclk";
1684 power-domains 1684 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1685 fsl,blk-ctrl 1685 fsl,blk-ctrl = <&media_blk_ctrl 0>;
1686 status = "dis 1686 status = "disabled";
1687 1687
1688 ports { 1688 ports {
1689 #addr 1689 #address-cells = <1>;
1690 #size 1690 #size-cells = <0>;
1691 1691
1692 port@ 1692 port@1 {
1693 1693 reg = <1>;
1694 }; 1694 };
1695 }; 1695 };
1696 }; 1696 };
1697 1697
1698 isp_1: isp@32e20000 { 1698 isp_1: isp@32e20000 {
1699 compatible = 1699 compatible = "fsl,imx8mp-isp";
1700 reg = <0x32e2 1700 reg = <0x32e20000 0x10000>;
1701 interrupts = 1701 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1702 clocks = <&cl 1702 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1703 <&cl 1703 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1704 <&cl 1704 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1705 clock-names = 1705 clock-names = "isp", "aclk", "hclk";
1706 power-domains 1706 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>;
1707 fsl,blk-ctrl 1707 fsl,blk-ctrl = <&media_blk_ctrl 1>;
1708 status = "dis 1708 status = "disabled";
1709 1709
1710 ports { 1710 ports {
1711 #addr 1711 #address-cells = <1>;
1712 #size 1712 #size-cells = <0>;
1713 1713
1714 port@ 1714 port@1 {
1715 1715 reg = <1>;
1716 }; 1716 };
1717 }; 1717 };
1718 }; 1718 };
1719 1719
1720 dewarp: dwe@32e30000 1720 dewarp: dwe@32e30000 {
1721 compatible = 1721 compatible = "nxp,imx8mp-dw100";
1722 reg = <0x32e3 1722 reg = <0x32e30000 0x10000>;
1723 interrupts = 1723 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
1724 clocks = <&cl 1724 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1725 <&cl 1725 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
1726 clock-names = 1726 clock-names = "axi", "ahb";
1727 power-domains 1727 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1728 }; 1728 };
1729 1729
1730 mipi_csi_0: csi@32e40 1730 mipi_csi_0: csi@32e40000 {
1731 compatible = 1731 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1732 reg = <0x32e4 1732 reg = <0x32e40000 0x10000>;
1733 interrupts = 1733 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1734 clock-frequen 1734 clock-frequency = <250000000>;
1735 clocks = <&cl 1735 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1736 <&cl 1736 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1737 <&cl 1737 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1738 <&cl 1738 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1739 clock-names = 1739 clock-names = "pclk", "wrap", "phy", "axi";
1740 assigned-cloc 1740 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>,
1741 1741 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1742 assigned-cloc 1742 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1743 1743 <&clk IMX8MP_CLK_24M>;
1744 power-domains 1744 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1745 status = "dis 1745 status = "disabled";
1746 1746
1747 ports { 1747 ports {
1748 #addr 1748 #address-cells = <1>;
1749 #size 1749 #size-cells = <0>;
1750 1750
1751 port@ 1751 port@0 {
1752 1752 reg = <0>;
1753 }; 1753 };
1754 1754
1755 port@ 1755 port@1 {
1756 1756 reg = <1>;
1757 1757
1758 1758 mipi_csi_0_out: endpoint {
1759 1759 remote-endpoint = <&isi_in_0>;
1760 1760 };
1761 }; 1761 };
1762 }; 1762 };
1763 }; 1763 };
1764 1764
1765 mipi_csi_1: csi@32e50 1765 mipi_csi_1: csi@32e50000 {
1766 compatible = 1766 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1767 reg = <0x32e5 1767 reg = <0x32e50000 0x10000>;
1768 interrupts = 1768 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1769 clock-frequen 1769 clock-frequency = <250000000>;
1770 clocks = <&cl 1770 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1771 <&cl 1771 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1772 <&cl 1772 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>,
1773 <&cl 1773 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1774 clock-names = 1774 clock-names = "pclk", "wrap", "phy", "axi";
1775 assigned-cloc 1775 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>,
1776 1776 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1777 assigned-cloc 1777 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>,
1778 1778 <&clk IMX8MP_CLK_24M>;
1779 power-domains 1779 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1780 status = "dis 1780 status = "disabled";
1781 1781
1782 ports { 1782 ports {
1783 #addr 1783 #address-cells = <1>;
1784 #size 1784 #size-cells = <0>;
1785 1785
1786 port@ 1786 port@0 {
1787 1787 reg = <0>;
1788 }; 1788 };
1789 1789
1790 port@ 1790 port@1 {
1791 1791 reg = <1>;
1792 1792
1793 1793 mipi_csi_1_out: endpoint {
1794 1794 remote-endpoint = <&isi_in_1>;
1795 1795 };
1796 }; 1796 };
1797 }; 1797 };
1798 }; 1798 };
1799 1799
1800 mipi_dsi: dsi@32e6000 1800 mipi_dsi: dsi@32e60000 {
1801 compatible = 1801 compatible = "fsl,imx8mp-mipi-dsim";
1802 reg = <0x32e6 1802 reg = <0x32e60000 0x400>;
1803 clocks = <&cl 1803 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1804 <&cl 1804 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1805 clock-names = 1805 clock-names = "bus_clk", "sclk_mipi";
1806 assigned-cloc 1806 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1807 1807 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>;
1808 assigned-cloc 1808 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1809 1809 <&clk IMX8MP_CLK_24M>;
1810 assigned-cloc 1810 assigned-clock-rates = <200000000>, <24000000>;
1811 samsung,pll-c 1811 samsung,pll-clock-frequency = <24000000>;
1812 interrupts = 1812 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1813 power-domains 1813 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1814 status = "dis 1814 status = "disabled";
1815 1815
1816 ports { 1816 ports {
1817 #addr 1817 #address-cells = <1>;
1818 #size 1818 #size-cells = <0>;
1819 1819
1820 port@ 1820 port@0 {
1821 1821 reg = <0>;
1822 1822
1823 1823 dsim_from_lcdif1: endpoint {
1824 1824 remote-endpoint = <&lcdif1_to_dsim>;
1825 1825 };
1826 }; 1826 };
1827 1827
1828 port@ 1828 port@1 {
1829 1829 reg = <1>;
1830 1830
1831 1831 mipi_dsi_out: endpoint {
1832 1832 };
1833 }; 1833 };
1834 }; 1834 };
1835 }; 1835 };
1836 1836
1837 lcdif1: display-contr 1837 lcdif1: display-controller@32e80000 {
1838 compatible = 1838 compatible = "fsl,imx8mp-lcdif";
1839 reg = <0x32e8 1839 reg = <0x32e80000 0x10000>;
1840 clocks = <&cl 1840 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1841 <&cl 1841 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1842 <&cl 1842 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1843 clock-names = 1843 clock-names = "pix", "axi", "disp_axi";
1844 interrupts = 1844 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1845 power-domains 1845 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1846 status = "dis 1846 status = "disabled";
1847 1847
1848 port { 1848 port {
1849 lcdif 1849 lcdif1_to_dsim: endpoint {
1850 1850 remote-endpoint = <&dsim_from_lcdif1>;
1851 }; 1851 };
1852 }; 1852 };
1853 }; 1853 };
1854 1854
1855 lcdif2: display-contr 1855 lcdif2: display-controller@32e90000 {
1856 compatible = 1856 compatible = "fsl,imx8mp-lcdif";
1857 reg = <0x32e9 1857 reg = <0x32e90000 0x10000>;
1858 interrupts = 1858 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1859 clocks = <&cl 1859 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1860 <&cl 1860 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1861 <&cl 1861 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>;
1862 clock-names = 1862 clock-names = "pix", "axi", "disp_axi";
1863 power-domains 1863 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1864 status = "dis 1864 status = "disabled";
1865 1865
1866 port { 1866 port {
1867 lcdif 1867 lcdif2_to_ldb: endpoint {
1868 1868 remote-endpoint = <&ldb_from_lcdif2>;
1869 }; 1869 };
1870 }; 1870 };
1871 }; 1871 };
1872 1872
1873 media_blk_ctrl: blk-c 1873 media_blk_ctrl: blk-ctrl@32ec0000 {
1874 compatible = 1874 compatible = "fsl,imx8mp-media-blk-ctrl",
1875 1875 "syscon";
1876 reg = <0x32ec 1876 reg = <0x32ec0000 0x10000>;
1877 #address-cell 1877 #address-cells = <1>;
1878 #size-cells = 1878 #size-cells = <1>;
1879 power-domains 1879 power-domains = <&pgc_mediamix>,
1880 1880 <&pgc_mipi_phy1>,
1881 1881 <&pgc_mipi_phy1>,
1882 1882 <&pgc_mediamix>,
1883 1883 <&pgc_mediamix>,
1884 1884 <&pgc_mipi_phy2>,
1885 1885 <&pgc_mediamix>,
1886 1886 <&pgc_ispdwp>,
1887 1887 <&pgc_ispdwp>,
1888 1888 <&pgc_mipi_phy2>;
1889 power-domain- 1889 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1890 1890 "lcdif1", "isi", "mipi-csi2",
1891 1891 "lcdif2", "isp", "dwe",
1892 1892 "mipi-dsi2";
1893 interconnects 1893 interconnects =
1894 <&noc 1894 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>,
1895 <&noc 1895 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>,
1896 <&noc 1896 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>,
1897 <&noc 1897 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>,
1898 <&noc 1898 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>,
1899 <&noc 1899 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>,
1900 <&noc 1900 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>,
1901 <&noc 1901 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>;
1902 interconnect- 1902 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1903 1903 "isi1", "isi2", "isp0", "isp1",
1904 1904 "dwe";
1905 clocks = <&cl 1905 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>,
1906 <&cl 1906 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
1907 <&cl 1907 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>,
1908 <&cl 1908 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>,
1909 <&cl 1909 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>,
1910 <&cl 1910 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>,
1911 <&cl 1911 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>,
1912 <&cl 1912 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>;
1913 clock-names = 1913 clock-names = "apb", "axi", "cam1", "cam2",
1914 1914 "disp1", "disp2", "isp", "phy";
1915 1915
1916 /* 1916 /*
1917 * The ISP ma 1917 * The ISP maximum frequency is 400MHz in normal mode
1918 * and 500MHz 1918 * and 500MHz in overdrive mode. The 400MHz operating
1919 * point hasn 1919 * point hasn't been successfully tested yet, so set
1920 * IMX8MP_CLK 1920 * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being.
1921 */ 1921 */
1922 assigned-cloc 1922 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1923 1923 <&clk IMX8MP_CLK_MEDIA_APB>,
1924 1924 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>,
1925 1925 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>,
1926 1926 <&clk IMX8MP_CLK_MEDIA_ISP>,
1927 1927 <&clk IMX8MP_VIDEO_PLL1>;
1928 assigned-cloc 1928 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1929 1929 <&clk IMX8MP_SYS_PLL1_800M>,
1930 1930 <&clk IMX8MP_VIDEO_PLL1_OUT>,
1931 1931 <&clk IMX8MP_VIDEO_PLL1_OUT>,
1932 1932 <&clk IMX8MP_SYS_PLL2_500M>;
1933 assigned-cloc 1933 assigned-clock-rates = <500000000>, <200000000>,
1934 1934 <0>, <0>, <500000000>,
1935 1935 <1039500000>;
1936 #power-domain 1936 #power-domain-cells = <1>;
1937 1937
1938 lvds_bridge: 1938 lvds_bridge: bridge@5c {
1939 compa 1939 compatible = "fsl,imx8mp-ldb";
1940 reg = 1940 reg = <0x5c 0x4>, <0x128 0x4>;
1941 reg-n 1941 reg-names = "ldb", "lvds";
1942 clock 1942 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>;
1943 clock 1943 clock-names = "ldb";
1944 assig 1944 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1945 assig 1945 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1946 statu 1946 status = "disabled";
1947 1947
1948 ports 1948 ports {
1949 1949 #address-cells = <1>;
1950 1950 #size-cells = <0>;
1951 1951
1952 1952 port@0 {
1953 1953 reg = <0>;
1954 1954
1955 1955 ldb_from_lcdif2: endpoint {
1956 1956 remote-endpoint = <&lcdif2_to_ldb>;
1957 1957 };
1958 1958 };
1959 1959
1960 1960 port@1 {
1961 1961 reg = <1>;
1962 1962
1963 1963 ldb_lvds_ch0: endpoint {
1964 1964 };
1965 1965 };
1966 1966
1967 1967 port@2 {
1968 1968 reg = <2>;
1969 1969
1970 1970 ldb_lvds_ch1: endpoint {
1971 1971 };
1972 1972 };
1973 }; 1973 };
1974 }; 1974 };
1975 }; 1975 };
1976 1976
1977 pcie_phy: pcie-phy@32 1977 pcie_phy: pcie-phy@32f00000 {
1978 compatible = 1978 compatible = "fsl,imx8mp-pcie-phy";
1979 reg = <0x32f0 1979 reg = <0x32f00000 0x10000>;
1980 resets = <&sr 1980 resets = <&src IMX8MP_RESET_PCIEPHY>,
1981 <&sr 1981 <&src IMX8MP_RESET_PCIEPHY_PERST>;
1982 reset-names = 1982 reset-names = "pciephy", "perst";
1983 power-domains 1983 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1984 #phy-cells = 1984 #phy-cells = <0>;
1985 status = "dis 1985 status = "disabled";
1986 }; 1986 };
1987 1987
1988 hsio_blk_ctrl: blk-ct 1988 hsio_blk_ctrl: blk-ctrl@32f10000 {
1989 compatible = 1989 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1990 reg = <0x32f1 1990 reg = <0x32f10000 0x24>;
1991 clocks = <&cl 1991 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
1992 <&cl 1992 <&clk IMX8MP_CLK_PCIE_ROOT>;
1993 clock-names = 1993 clock-names = "usb", "pcie";
1994 power-domains 1994 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1995 1995 <&pgc_usb1_phy>, <&pgc_usb2_phy>,
1996 1996 <&pgc_hsiomix>, <&pgc_pcie_phy>;
1997 power-domain- 1997 power-domain-names = "bus", "usb", "usb-phy1",
1998 1998 "usb-phy2", "pcie", "pcie-phy";
1999 interconnects 1999 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>,
2000 2000 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>,
2001 2001 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>,
2002 2002 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>;
2003 interconnect- 2003 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
2004 #power-domain 2004 #power-domain-cells = <1>;
2005 #clock-cells 2005 #clock-cells = <0>;
2006 }; 2006 };
2007 2007
2008 hdmi_blk_ctrl: blk-ct 2008 hdmi_blk_ctrl: blk-ctrl@32fc0000 {
2009 compatible = 2009 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon";
2010 reg = <0x32fc 2010 reg = <0x32fc0000 0x1000>;
2011 clocks = <&cl 2011 clocks = <&clk IMX8MP_CLK_HDMI_APB>,
2012 <&cl 2012 <&clk IMX8MP_CLK_HDMI_ROOT>,
2013 <&cl 2013 <&clk IMX8MP_CLK_HDMI_REF_266M>,
2014 <&cl 2014 <&clk IMX8MP_CLK_HDMI_24M>,
2015 <&cl 2015 <&clk IMX8MP_CLK_HDMI_FDCC_TST>;
2016 clock-names = 2016 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc";
2017 power-domains 2017 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>,
2018 2018 <&pgc_hdmimix>, <&pgc_hdmimix>,
2019 2019 <&pgc_hdmimix>, <&pgc_hdmimix>,
2020 2020 <&pgc_hdmimix>, <&pgc_hdmi_phy>,
2021 2021 <&pgc_hdmimix>, <&pgc_hdmimix>;
2022 power-domain- 2022 power-domain-names = "bus", "irqsteer", "lcdif",
2023 2023 "pai", "pvi", "trng",
2024 2024 "hdmi-tx", "hdmi-tx-phy",
2025 2025 "hdcp", "hrv";
2026 #power-domain 2026 #power-domain-cells = <1>;
2027 }; 2027 };
2028 2028
2029 irqsteer_hdmi: interr 2029 irqsteer_hdmi: interrupt-controller@32fc2000 {
2030 compatible = 2030 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer";
2031 reg = <0x32fc 2031 reg = <0x32fc2000 0x1000>;
2032 interrupts = 2032 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
2033 interrupt-con 2033 interrupt-controller;
2034 #interrupt-ce 2034 #interrupt-cells = <1>;
2035 fsl,channel = 2035 fsl,channel = <1>;
2036 fsl,num-irqs 2036 fsl,num-irqs = <64>;
2037 clocks = <&cl 2037 clocks = <&clk IMX8MP_CLK_HDMI_APB>;
2038 clock-names = 2038 clock-names = "ipg";
2039 power-domains 2039 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>;
2040 }; 2040 };
2041 2041
2042 hdmi_pvi: display-bri 2042 hdmi_pvi: display-bridge@32fc4000 {
2043 compatible = 2043 compatible = "fsl,imx8mp-hdmi-pvi";
2044 reg = <0x32fc 2044 reg = <0x32fc4000 0x1000>;
2045 interrupt-par 2045 interrupt-parent = <&irqsteer_hdmi>;
2046 interrupts = 2046 interrupts = <12>;
2047 power-domains 2047 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>;
2048 status = "dis 2048 status = "disabled";
2049 2049
2050 ports { 2050 ports {
2051 #addr 2051 #address-cells = <1>;
2052 #size 2052 #size-cells = <0>;
2053 2053
2054 port@ 2054 port@0 {
2055 2055 reg = <0>;
2056 2056 pvi_from_lcdif3: endpoint {
2057 2057 remote-endpoint = <&lcdif3_to_pvi>;
2058 2058 };
2059 }; 2059 };
2060 2060
2061 port@ 2061 port@1 {
2062 2062 reg = <1>;
2063 2063 pvi_to_hdmi_tx: endpoint {
2064 2064 remote-endpoint = <&hdmi_tx_from_pvi>;
2065 2065 };
2066 }; 2066 };
2067 }; 2067 };
2068 }; 2068 };
2069 2069
2070 lcdif3: display-contr 2070 lcdif3: display-controller@32fc6000 {
2071 compatible = 2071 compatible = "fsl,imx8mp-lcdif";
2072 reg = <0x32fc 2072 reg = <0x32fc6000 0x1000>;
2073 interrupt-par 2073 interrupt-parent = <&irqsteer_hdmi>;
2074 interrupts = 2074 interrupts = <8>;
2075 clocks = <&hd 2075 clocks = <&hdmi_tx_phy>,
2076 <&cl 2076 <&clk IMX8MP_CLK_HDMI_APB>,
2077 <&cl 2077 <&clk IMX8MP_CLK_HDMI_ROOT>;
2078 clock-names = 2078 clock-names = "pix", "axi", "disp_axi";
2079 power-domains 2079 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>;
2080 status = "dis 2080 status = "disabled";
2081 2081
2082 port { 2082 port {
2083 lcdif 2083 lcdif3_to_pvi: endpoint {
2084 2084 remote-endpoint = <&pvi_from_lcdif3>;
2085 }; 2085 };
2086 }; 2086 };
2087 }; 2087 };
2088 2088
2089 hdmi_tx: hdmi@32fd800 2089 hdmi_tx: hdmi@32fd8000 {
2090 compatible = 2090 compatible = "fsl,imx8mp-hdmi-tx";
2091 reg = <0x32fd 2091 reg = <0x32fd8000 0x7eff>;
2092 interrupt-par 2092 interrupt-parent = <&irqsteer_hdmi>;
2093 interrupts = 2093 interrupts = <0>;
2094 clocks = <&cl 2094 clocks = <&clk IMX8MP_CLK_HDMI_APB>,
2095 <&cl 2095 <&clk IMX8MP_CLK_HDMI_REF_266M>,
2096 <&cl 2096 <&clk IMX8MP_CLK_32K>,
2097 <&hd 2097 <&hdmi_tx_phy>;
2098 clock-names = 2098 clock-names = "iahb", "isfr", "cec", "pix";
2099 assigned-cloc 2099 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>;
2100 assigned-cloc 2100 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>;
2101 power-domains 2101 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>;
2102 reg-io-width 2102 reg-io-width = <1>;
2103 status = "dis 2103 status = "disabled";
2104 2104
2105 ports { 2105 ports {
2106 #addr 2106 #address-cells = <1>;
2107 #size 2107 #size-cells = <0>;
2108 2108
2109 port@ 2109 port@0 {
2110 2110 reg = <0>;
2111 2111
2112 2112 hdmi_tx_from_pvi: endpoint {
2113 2113 remote-endpoint = <&pvi_to_hdmi_tx>;
2114 2114 };
2115 }; 2115 };
2116 2116
2117 port@ 2117 port@1 {
2118 2118 reg = <1>;
2119 2119 /* Point endpoint to the HDMI connector */
2120 }; 2120 };
2121 }; 2121 };
2122 }; 2122 };
2123 2123
2124 hdmi_tx_phy: phy@32fd 2124 hdmi_tx_phy: phy@32fdff00 {
2125 compatible = 2125 compatible = "fsl,imx8mp-hdmi-phy";
2126 reg = <0x32fd 2126 reg = <0x32fdff00 0x100>;
2127 clocks = <&cl 2127 clocks = <&clk IMX8MP_CLK_HDMI_APB>,
2128 <&cl 2128 <&clk IMX8MP_CLK_HDMI_24M>;
2129 clock-names = 2129 clock-names = "apb", "ref";
2130 assigned-cloc 2130 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>;
2131 assigned-cloc 2131 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2132 power-domains 2132 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>;
2133 #clock-cells 2133 #clock-cells = <0>;
2134 #phy-cells = 2134 #phy-cells = <0>;
2135 status = "dis 2135 status = "disabled";
2136 }; 2136 };
2137 }; 2137 };
2138 2138
2139 pcie: pcie@33800000 { 2139 pcie: pcie@33800000 {
2140 compatible = "fsl,imx 2140 compatible = "fsl,imx8mp-pcie";
2141 reg = <0x33800000 0x4 2141 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
2142 reg-names = "dbi", "c 2142 reg-names = "dbi", "config";
2143 clocks = <&clk IMX8MP 2143 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2144 <&clk IMX8MP 2144 <&clk IMX8MP_CLK_HSIO_AXI>,
2145 <&clk IMX8MP 2145 <&clk IMX8MP_CLK_PCIE_ROOT>;
2146 clock-names = "pcie", 2146 clock-names = "pcie", "pcie_bus", "pcie_aux";
2147 assigned-clocks = <&c 2147 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2148 assigned-clock-rates 2148 assigned-clock-rates = <10000000>;
2149 assigned-clock-parent 2149 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2150 #address-cells = <3>; 2150 #address-cells = <3>;
2151 #size-cells = <2>; 2151 #size-cells = <2>;
2152 device_type = "pci"; 2152 device_type = "pci";
2153 bus-range = <0x00 0xf 2153 bus-range = <0x00 0xff>;
2154 ranges = <0x81000000 2154 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */
2155 <0x82000000 2155 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
2156 num-lanes = <1>; 2156 num-lanes = <1>;
2157 num-viewport = <4>; 2157 num-viewport = <4>;
2158 interrupts = <GIC_SPI 2158 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
2159 interrupt-names = "ms 2159 interrupt-names = "msi";
2160 #interrupt-cells = <1 2160 #interrupt-cells = <1>;
2161 interrupt-map-mask = 2161 interrupt-map-mask = <0 0 0 0x7>;
2162 interrupt-map = <0 0 2162 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2163 <0 0 2163 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2164 <0 0 2164 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2165 <0 0 2165 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
2166 fsl,max-link-speed = 2166 fsl,max-link-speed = <3>;
2167 linux,pci-domain = <0 2167 linux,pci-domain = <0>;
2168 power-domains = <&hsi 2168 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2169 resets = <&src IMX8MP 2169 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
2170 <&src IMX8MP 2170 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
2171 reset-names = "apps", 2171 reset-names = "apps", "turnoff";
2172 phys = <&pcie_phy>; 2172 phys = <&pcie_phy>;
2173 phy-names = "pcie-phy 2173 phy-names = "pcie-phy";
2174 status = "disabled"; 2174 status = "disabled";
2175 }; 2175 };
2176 2176
2177 pcie_ep: pcie-ep@33800000 { 2177 pcie_ep: pcie-ep@33800000 {
2178 compatible = "fsl,imx 2178 compatible = "fsl,imx8mp-pcie-ep";
2179 reg = <0x33800000 0x0 2179 reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
2180 reg-names = "dbi", "a 2180 reg-names = "dbi", "addr_space";
2181 clocks = <&clk IMX8MP 2181 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2182 <&clk IMX8MP 2182 <&clk IMX8MP_CLK_HSIO_AXI>,
2183 <&clk IMX8MP 2183 <&clk IMX8MP_CLK_PCIE_ROOT>;
2184 clock-names = "pcie", 2184 clock-names = "pcie", "pcie_bus", "pcie_aux";
2185 assigned-clocks = <&c 2185 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
2186 assigned-clock-rates 2186 assigned-clock-rates = <10000000>;
2187 assigned-clock-parent 2187 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
2188 num-lanes = <1>; 2188 num-lanes = <1>;
2189 interrupts = <GIC_SPI 2189 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
2190 interrupt-names = "dm 2190 interrupt-names = "dma";
2191 fsl,max-link-speed = 2191 fsl,max-link-speed = <3>;
2192 power-domains = <&hsi 2192 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
2193 resets = <&src IMX8MP 2193 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
2194 <&src IMX8MP 2194 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
2195 reset-names = "apps", 2195 reset-names = "apps", "turnoff";
2196 phys = <&pcie_phy>; 2196 phys = <&pcie_phy>;
2197 phy-names = "pcie-phy 2197 phy-names = "pcie-phy";
2198 num-ib-windows = <4>; 2198 num-ib-windows = <4>;
2199 num-ob-windows = <4>; 2199 num-ob-windows = <4>;
2200 status = "disabled"; 2200 status = "disabled";
2201 }; 2201 };
2202 2202
2203 gpu3d: gpu@38000000 { 2203 gpu3d: gpu@38000000 {
2204 compatible = "vivante 2204 compatible = "vivante,gc";
2205 reg = <0x38000000 0x8 2205 reg = <0x38000000 0x8000>;
2206 interrupts = <GIC_SPI 2206 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
2207 clocks = <&clk IMX8MP 2207 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
2208 <&clk IMX8MP 2208 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
2209 <&clk IMX8MP 2209 <&clk IMX8MP_CLK_GPU_ROOT>,
2210 <&clk IMX8MP 2210 <&clk IMX8MP_CLK_GPU_AHB>;
2211 clock-names = "core", 2211 clock-names = "core", "shader", "bus", "reg";
2212 assigned-clocks = <&c 2212 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
2213 <&c 2213 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
2214 assigned-clock-parent 2214 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
2215 2215 <&clk IMX8MP_SYS_PLL1_800M>;
2216 assigned-clock-rates 2216 assigned-clock-rates = <800000000>, <800000000>;
2217 power-domains = <&pgc 2217 power-domains = <&pgc_gpu3d>;
2218 }; 2218 };
2219 2219
2220 gpu2d: gpu@38008000 { 2220 gpu2d: gpu@38008000 {
2221 compatible = "vivante 2221 compatible = "vivante,gc";
2222 reg = <0x38008000 0x8 2222 reg = <0x38008000 0x8000>;
2223 interrupts = <GIC_SPI 2223 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
2224 clocks = <&clk IMX8MP 2224 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
2225 <&clk IMX8MP 2225 <&clk IMX8MP_CLK_GPU_ROOT>,
2226 <&clk IMX8MP 2226 <&clk IMX8MP_CLK_GPU_AHB>;
2227 clock-names = "core", 2227 clock-names = "core", "bus", "reg";
2228 assigned-clocks = <&c 2228 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
2229 assigned-clock-parent 2229 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
2230 assigned-clock-rates 2230 assigned-clock-rates = <800000000>;
2231 power-domains = <&pgc 2231 power-domains = <&pgc_gpu2d>;
2232 }; 2232 };
2233 2233
2234 vpu_g1: video-codec@38300000 2234 vpu_g1: video-codec@38300000 {
2235 compatible = "nxp,imx 2235 compatible = "nxp,imx8mm-vpu-g1";
2236 reg = <0x38300000 0x1 2236 reg = <0x38300000 0x10000>;
2237 interrupts = <GIC_SPI 2237 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2238 clocks = <&clk IMX8MP 2238 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>;
2239 assigned-clocks = <&c 2239 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
2240 assigned-clock-parent 2240 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2241 assigned-clock-rates 2241 assigned-clock-rates = <600000000>;
2242 power-domains = <&vpu 2242 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
2243 }; 2243 };
2244 2244
2245 vpu_g2: video-codec@38310000 2245 vpu_g2: video-codec@38310000 {
2246 compatible = "nxp,imx 2246 compatible = "nxp,imx8mq-vpu-g2";
2247 reg = <0x38310000 0x1 2247 reg = <0x38310000 0x10000>;
2248 interrupts = <GIC_SPI 2248 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
2249 clocks = <&clk IMX8MP 2249 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>;
2250 assigned-clocks = <&c 2250 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
2251 assigned-clock-parent 2251 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
2252 assigned-clock-rates 2252 assigned-clock-rates = <500000000>;
2253 power-domains = <&vpu 2253 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
2254 }; 2254 };
2255 2255
2256 vpumix_blk_ctrl: blk-ctrl@383 2256 vpumix_blk_ctrl: blk-ctrl@38330000 {
2257 compatible = "fsl,imx 2257 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
2258 reg = <0x38330000 0x1 2258 reg = <0x38330000 0x100>;
2259 #power-domain-cells = 2259 #power-domain-cells = <1>;
2260 power-domains = <&pgc 2260 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
2261 <&pgc 2261 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>;
2262 power-domain-names = 2262 power-domain-names = "bus", "g1", "g2", "vc8000e";
2263 clocks = <&clk IMX8MP 2263 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>,
2264 <&clk IMX8MP 2264 <&clk IMX8MP_CLK_VPU_G2_ROOT>,
2265 <&clk IMX8MP 2265 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>;
2266 clock-names = "g1", " 2266 clock-names = "g1", "g2", "vc8000e";
2267 assigned-clocks = <&c 2267 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
2268 assigned-clock-parent 2268 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
2269 assigned-clock-rates 2269 assigned-clock-rates = <600000000>, <600000000>;
2270 interconnects = <&noc 2270 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>,
2271 <&noc 2271 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>,
2272 <&noc 2272 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>;
2273 interconnect-names = 2273 interconnect-names = "g1", "g2", "vc8000e";
2274 }; 2274 };
2275 2275
2276 npu: npu@38500000 { 2276 npu: npu@38500000 {
2277 compatible = "vivante 2277 compatible = "vivante,gc";
2278 reg = <0x38500000 0x2 2278 reg = <0x38500000 0x200000>;
2279 interrupts = <GIC_SPI 2279 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
2280 clocks = <&clk IMX8MP 2280 clocks = <&clk IMX8MP_CLK_NPU_ROOT>,
2281 <&clk IMX8MP 2281 <&clk IMX8MP_CLK_NPU_ROOT>,
2282 <&clk IMX8MP 2282 <&clk IMX8MP_CLK_ML_AXI>,
2283 <&clk IMX8MP 2283 <&clk IMX8MP_CLK_ML_AHB>;
2284 clock-names = "core", 2284 clock-names = "core", "shader", "bus", "reg";
2285 power-domains = <&pgc 2285 power-domains = <&pgc_mlmix>;
2286 }; 2286 };
2287 2287
2288 gic: interrupt-controller@388 2288 gic: interrupt-controller@38800000 {
2289 compatible = "arm,gic 2289 compatible = "arm,gic-v3";
2290 reg = <0x38800000 0x1 2290 reg = <0x38800000 0x10000>,
2291 <0x38880000 0xc 2291 <0x38880000 0xc0000>;
2292 #interrupt-cells = <3 2292 #interrupt-cells = <3>;
2293 interrupt-controller; 2293 interrupt-controller;
2294 interrupts = <GIC_PPI 2294 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
2295 interrupt-parent = <& 2295 interrupt-parent = <&gic>;
2296 }; 2296 };
2297 2297
2298 edacmc: memory-controller@3d4 2298 edacmc: memory-controller@3d400000 {
2299 compatible = "snps,dd 2299 compatible = "snps,ddrc-3.80a";
2300 reg = <0x3d400000 0x4 2300 reg = <0x3d400000 0x400000>;
2301 interrupts = <GIC_SPI 2301 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
2302 }; 2302 };
2303 2303
2304 ddr-pmu@3d800000 { 2304 ddr-pmu@3d800000 {
2305 compatible = "fsl,imx 2305 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
2306 reg = <0x3d800000 0x4 2306 reg = <0x3d800000 0x400000>;
2307 interrupts = <GIC_SPI 2307 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
2308 }; 2308 };
2309 2309
2310 usb3_phy0: usb-phy@381f0040 { 2310 usb3_phy0: usb-phy@381f0040 {
2311 compatible = "fsl,imx 2311 compatible = "fsl,imx8mp-usb-phy";
2312 reg = <0x381f0040 0x4 2312 reg = <0x381f0040 0x40>;
2313 clocks = <&clk IMX8MP 2313 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2314 clock-names = "phy"; 2314 clock-names = "phy";
2315 assigned-clocks = <&c 2315 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2316 assigned-clock-parent 2316 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2317 power-domains = <&hsi 2317 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2318 #phy-cells = <0>; 2318 #phy-cells = <0>;
2319 status = "disabled"; 2319 status = "disabled";
2320 }; 2320 };
2321 2321
2322 usb3_0: usb@32f10100 { 2322 usb3_0: usb@32f10100 {
2323 compatible = "fsl,imx 2323 compatible = "fsl,imx8mp-dwc3";
2324 reg = <0x32f10100 0x8 2324 reg = <0x32f10100 0x8>,
2325 <0x381f0000 0x2 2325 <0x381f0000 0x20>;
2326 clocks = <&clk IMX8MP 2326 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2327 <&clk IMX8MP 2327 <&clk IMX8MP_CLK_USB_SUSP>;
2328 clock-names = "hsio", 2328 clock-names = "hsio", "suspend";
2329 interrupts = <GIC_SPI 2329 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
2330 power-domains = <&hsi 2330 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2331 #address-cells = <1>; 2331 #address-cells = <1>;
2332 #size-cells = <1>; 2332 #size-cells = <1>;
2333 dma-ranges = <0x40000 2333 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2334 ranges; 2334 ranges;
2335 status = "disabled"; 2335 status = "disabled";
2336 2336
2337 usb_dwc3_0: usb@38100 2337 usb_dwc3_0: usb@38100000 {
2338 compatible = 2338 compatible = "snps,dwc3";
2339 reg = <0x3810 2339 reg = <0x38100000 0x10000>;
2340 clocks = <&cl 2340 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2341 <&cl 2341 <&clk IMX8MP_CLK_USB_CORE_REF>,
2342 <&cl 2342 <&clk IMX8MP_CLK_USB_SUSP>;
2343 clock-names = 2343 clock-names = "bus_early", "ref", "suspend";
2344 interrupts = 2344 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
2345 phys = <&usb3 2345 phys = <&usb3_phy0>, <&usb3_phy0>;
2346 phy-names = " 2346 phy-names = "usb2-phy", "usb3-phy";
2347 snps,gfladj-r 2347 snps,gfladj-refclk-lpm-sel-quirk;
2348 snps,parkmode 2348 snps,parkmode-disable-ss-quirk;
2349 }; 2349 };
2350 2350
2351 }; 2351 };
2352 2352
2353 usb3_phy1: usb-phy@382f0040 { 2353 usb3_phy1: usb-phy@382f0040 {
2354 compatible = "fsl,imx 2354 compatible = "fsl,imx8mp-usb-phy";
2355 reg = <0x382f0040 0x4 2355 reg = <0x382f0040 0x40>;
2356 clocks = <&clk IMX8MP 2356 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>;
2357 clock-names = "phy"; 2357 clock-names = "phy";
2358 assigned-clocks = <&c 2358 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2359 assigned-clock-parent 2359 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2360 power-domains = <&hsi 2360 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2361 #phy-cells = <0>; 2361 #phy-cells = <0>;
2362 status = "disabled"; 2362 status = "disabled";
2363 }; 2363 };
2364 2364
2365 usb3_1: usb@32f10108 { 2365 usb3_1: usb@32f10108 {
2366 compatible = "fsl,imx 2366 compatible = "fsl,imx8mp-dwc3";
2367 reg = <0x32f10108 0x8 2367 reg = <0x32f10108 0x8>,
2368 <0x382f0000 0x2 2368 <0x382f0000 0x20>;
2369 clocks = <&clk IMX8MP 2369 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
2370 <&clk IMX8MP 2370 <&clk IMX8MP_CLK_USB_SUSP>;
2371 clock-names = "hsio", 2371 clock-names = "hsio", "suspend";
2372 interrupts = <GIC_SPI 2372 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
2373 power-domains = <&hsi 2373 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2374 #address-cells = <1>; 2374 #address-cells = <1>;
2375 #size-cells = <1>; 2375 #size-cells = <1>;
2376 dma-ranges = <0x40000 2376 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2377 ranges; 2377 ranges;
2378 status = "disabled"; 2378 status = "disabled";
2379 2379
2380 usb_dwc3_1: usb@38200 2380 usb_dwc3_1: usb@38200000 {
2381 compatible = 2381 compatible = "snps,dwc3";
2382 reg = <0x3820 2382 reg = <0x38200000 0x10000>;
2383 clocks = <&cl 2383 clocks = <&clk IMX8MP_CLK_USB_ROOT>,
2384 <&cl 2384 <&clk IMX8MP_CLK_USB_CORE_REF>,
2385 <&cl 2385 <&clk IMX8MP_CLK_USB_SUSP>;
2386 clock-names = 2386 clock-names = "bus_early", "ref", "suspend";
2387 interrupts = 2387 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
2388 phys = <&usb3 2388 phys = <&usb3_phy1>, <&usb3_phy1>;
2389 phy-names = " 2389 phy-names = "usb2-phy", "usb3-phy";
2390 snps,gfladj-r 2390 snps,gfladj-refclk-lpm-sel-quirk;
2391 snps,parkmode 2391 snps,parkmode-disable-ss-quirk;
2392 }; 2392 };
2393 }; 2393 };
2394 2394
2395 dsp: dsp@3b6e8000 { 2395 dsp: dsp@3b6e8000 {
2396 compatible = "fsl,imx 2396 compatible = "fsl,imx8mp-dsp";
2397 reg = <0x3b6e8000 0x8 2397 reg = <0x3b6e8000 0x88000>;
2398 mbox-names = "txdb0", 2398 mbox-names = "txdb0", "txdb1",
2399 "rxdb0", "rxd 2399 "rxdb0", "rxdb1";
2400 mboxes = <&mu2 2 0>, 2400 mboxes = <&mu2 2 0>, <&mu2 2 1>,
2401 <&mu2 3 0>, < 2401 <&mu2 3 0>, <&mu2 3 1>;
2402 memory-region = <&dsp 2402 memory-region = <&dsp_reserved>;
2403 status = "disabled"; 2403 status = "disabled";
2404 }; 2404 };
2405 }; 2405 };
2406 }; 2406 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.