1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas < 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "imx8mq.dtsi" 9 #include "imx8mq.dtsi"
10 10
11 / { 11 / {
12 model = "NXP i.MX8MQ EVK"; 12 model = "NXP i.MX8MQ EVK";
13 compatible = "fsl,imx8mq-evk", "fsl,im 13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14 14
15 chosen { 15 chosen {
16 stdout-path = &uart1; 16 stdout-path = &uart1;
17 }; 17 };
18 18
19 memory@40000000 { 19 memory@40000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 21 reg = <0x00000000 0x40000000 0 0xc0000000>;
22 }; 22 };
23 23
24 pcie0_refclk: pcie0-refclk { <<
25 compatible = "fixed-clock"; <<
26 #clock-cells = <0>; <<
27 clock-frequency = <100000000>; <<
28 }; <<
29 <<
30 reg_pcie1: regulator-pcie { <<
31 compatible = "regulator-fixed" <<
32 pinctrl-names = "default"; <<
33 pinctrl-0 = <&pinctrl_pcie1_re <<
34 regulator-name = "MPCIE_3V3"; <<
35 regulator-min-microvolt = <330 <<
36 regulator-max-microvolt = <330 <<
37 gpio = <&gpio5 10 GPIO_ACTIVE_ <<
38 enable-active-high; <<
39 }; <<
40 <<
41 reg_usdhc2_vmmc: regulator-vsd-3v3 { 24 reg_usdhc2_vmmc: regulator-vsd-3v3 {
42 pinctrl-names = "default"; 25 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_reg_usdh 26 pinctrl-0 = <&pinctrl_reg_usdhc2>;
44 compatible = "regulator-fixed" 27 compatible = "regulator-fixed";
45 regulator-name = "VSD_3V3"; 28 regulator-name = "VSD_3V3";
46 regulator-min-microvolt = <330 29 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <330 30 regulator-max-microvolt = <3300000>;
48 gpio = <&gpio2 19 GPIO_ACTIVE_ 31 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49 off-on-delay-us = <20000>; <<
50 enable-active-high; 32 enable-active-high;
51 }; 33 };
52 <<
53 buck2_reg: regulator-buck2 { <<
54 pinctrl-names = "default"; <<
55 pinctrl-0 = <&pinctrl_buck2>; <<
56 compatible = "regulator-gpio"; <<
57 regulator-name = "vdd_arm"; <<
58 regulator-min-microvolt = <900 <<
59 regulator-max-microvolt = <100 <<
60 gpios = <&gpio1 13 GPIO_ACTIVE <<
61 states = <1000000 0x0 <<
62 900000 0x1>; <<
63 regulator-boot-on; <<
64 regulator-always-on; <<
65 }; <<
66 <<
67 ir-receiver { <<
68 compatible = "gpio-ir-receiver <<
69 gpios = <&gpio1 12 GPIO_ACTIVE <<
70 pinctrl-names = "default"; <<
71 pinctrl-0 = <&pinctrl_ir>; <<
72 linux,autosuspend-period = <12 <<
73 }; <<
74 <<
75 audio_codec_bt_sco: audio-codec-bt-sco <<
76 compatible = "linux,bt-sco"; <<
77 #sound-dai-cells = <1>; <<
78 }; <<
79 <<
80 wm8524: audio-codec { <<
81 #sound-dai-cells = <0>; <<
82 compatible = "wlf,wm8524"; <<
83 wlf,mute-gpios = <&gpio1 8 GPI <<
84 }; <<
85 <<
86 sound-bt-sco { <<
87 compatible = "simple-audio-car <<
88 simple-audio-card,name = "bt-s <<
89 simple-audio-card,format = "ds <<
90 simple-audio-card,bitclock-inv <<
91 simple-audio-card,frame-master <<
92 simple-audio-card,bitclock-mas <<
93 <<
94 btcpu: simple-audio-card,cpu { <<
95 sound-dai = <&sai3>; <<
96 dai-tdm-slot-num = <2> <<
97 dai-tdm-slot-width = < <<
98 }; <<
99 <<
100 simple-audio-card,codec { <<
101 sound-dai = <&audio_co <<
102 }; <<
103 }; <<
104 <<
105 sound-wm8524 { <<
106 compatible = "simple-audio-car <<
107 simple-audio-card,name = "wm85 <<
108 simple-audio-card,format = "i2 <<
109 simple-audio-card,frame-master <<
110 simple-audio-card,bitclock-mas <<
111 simple-audio-card,widgets = <<
112 "Line", "Left Line Out <<
113 "Line", "Right Line Ou <<
114 simple-audio-card,routing = <<
115 "Left Line Out Jack", <<
116 "Right Line Out Jack", <<
117 <<
118 cpudai: simple-audio-card,cpu <<
119 sound-dai = <&sai2>; <<
120 }; <<
121 <<
122 link_codec: simple-audio-card, <<
123 sound-dai = <&wm8524>; <<
124 clocks = <&clk IMX8MQ_ <<
125 }; <<
126 }; <<
127 <<
128 spdif_out: spdif-out { <<
129 compatible = "linux,spdif-dit" <<
130 #sound-dai-cells = <0>; <<
131 }; <<
132 <<
133 spdif_in: spdif-in { <<
134 compatible = "linux,spdif-dir" <<
135 #sound-dai-cells = <0>; <<
136 }; <<
137 <<
138 sound-spdif { <<
139 compatible = "fsl,imx-audio-sp <<
140 model = "imx-spdif"; <<
141 audio-cpu = <&spdif1>; <<
142 audio-codec = <&spdif_out>, <& <<
143 }; <<
144 <<
145 hdmi_arc_in: hdmi-arc-in { <<
146 compatible = "linux,spdif-dir" <<
147 #sound-dai-cells = <0>; <<
148 }; <<
149 <<
150 sound-hdmi-arc { <<
151 compatible = "fsl,imx-audio-sp <<
152 model = "imx-hdmi-arc"; <<
153 audio-cpu = <&spdif2>; <<
154 audio-codec = <&hdmi_arc_in>; <<
155 }; <<
156 }; <<
157 <<
158 &A53_0 { <<
159 cpu-supply = <&buck2_reg>; <<
160 }; <<
161 <<
162 &A53_1 { <<
163 cpu-supply = <&buck2_reg>; <<
164 }; <<
165 <<
166 &A53_2 { <<
167 cpu-supply = <&buck2_reg>; <<
168 }; <<
169 <<
170 &A53_3 { <<
171 cpu-supply = <&buck2_reg>; <<
172 }; <<
173 <<
174 &ddrc { <<
175 operating-points-v2 = <&ddrc_opp_table <<
176 status = "okay"; <<
177 <<
178 ddrc_opp_table: opp-table { <<
179 compatible = "operating-points <<
180 <<
181 opp-25000000 { <<
182 opp-hz = /bits/ 64 <25 <<
183 }; <<
184 <<
185 opp-100000000 { <<
186 opp-hz = /bits/ 64 <10 <<
187 }; <<
188 <<
189 /* <<
190 * On imx8mq B0 PLL can't be b <<
191 */ <<
192 opp-166000000 { <<
193 opp-hz = /bits/ 64 <16 <<
194 }; <<
195 <<
196 opp-800000000 { <<
197 opp-hz = /bits/ 64 <80 <<
198 }; <<
199 }; <<
200 }; <<
201 <<
202 &dphy { <<
203 status = "okay"; <<
204 }; 34 };
205 35
206 &fec1 { 36 &fec1 {
207 pinctrl-names = "default"; 37 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_fec1>; 38 pinctrl-0 = <&pinctrl_fec1>;
209 phy-mode = "rgmii-id"; 39 phy-mode = "rgmii-id";
210 phy-handle = <ðphy0>; 40 phy-handle = <ðphy0>;
211 fsl,magic-packet; 41 fsl,magic-packet;
212 status = "okay"; 42 status = "okay";
213 43
214 mdio { 44 mdio {
215 #address-cells = <1>; 45 #address-cells = <1>;
216 #size-cells = <0>; 46 #size-cells = <0>;
217 47
218 ethphy0: ethernet-phy@0 { 48 ethphy0: ethernet-phy@0 {
219 compatible = "ethernet 49 compatible = "ethernet-phy-ieee802.3-c22";
220 reg = <0>; 50 reg = <0>;
221 reset-gpios = <&gpio1 <<
222 reset-assert-us = <100 <<
223 qca,disable-smarteee; <<
224 vddio-supply = <&vddh> <<
225 <<
226 vddh: vddh-regulator { <<
227 }; <<
228 }; 51 };
229 }; 52 };
230 }; 53 };
231 54
232 &gpio5 { <<
233 pinctrl-names = "default"; <<
234 pinctrl-0 = <&pinctrl_wifi_reset>; <<
235 <<
236 wl-reg-on-hog { <<
237 gpio-hog; <<
238 gpios = <29 GPIO_ACTIVE_HIGH>; <<
239 output-high; <<
240 }; <<
241 }; <<
242 <<
243 &i2c1 { 55 &i2c1 {
244 clock-frequency = <100000>; 56 clock-frequency = <100000>;
245 pinctrl-names = "default"; 57 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c1>; 58 pinctrl-0 = <&pinctrl_i2c1>;
247 status = "okay"; 59 status = "okay";
248 60
249 pmic@8 { 61 pmic@8 {
250 compatible = "fsl,pfuze100"; 62 compatible = "fsl,pfuze100";
251 reg = <0x8>; 63 reg = <0x8>;
252 64
253 regulators { 65 regulators {
254 sw1a_reg: sw1ab { 66 sw1a_reg: sw1ab {
255 regulator-min- 67 regulator-min-microvolt = <825000>;
256 regulator-max- 68 regulator-max-microvolt = <1100000>;
257 }; 69 };
258 70
259 sw1c_reg: sw1c { 71 sw1c_reg: sw1c {
260 regulator-min- 72 regulator-min-microvolt = <825000>;
261 regulator-max- 73 regulator-max-microvolt = <1100000>;
262 }; 74 };
263 75
264 sw2_reg: sw2 { 76 sw2_reg: sw2 {
265 regulator-min- 77 regulator-min-microvolt = <1100000>;
266 regulator-max- 78 regulator-max-microvolt = <1100000>;
267 regulator-alwa 79 regulator-always-on;
268 }; 80 };
269 81
270 sw3a_reg: sw3ab { 82 sw3a_reg: sw3ab {
271 regulator-min- 83 regulator-min-microvolt = <825000>;
272 regulator-max- 84 regulator-max-microvolt = <1100000>;
273 regulator-alwa 85 regulator-always-on;
274 }; 86 };
275 87
276 sw4_reg: sw4 { 88 sw4_reg: sw4 {
277 regulator-min- 89 regulator-min-microvolt = <1800000>;
278 regulator-max- 90 regulator-max-microvolt = <1800000>;
279 regulator-alwa 91 regulator-always-on;
280 }; 92 };
281 93
282 swbst_reg: swbst { 94 swbst_reg: swbst {
283 regulator-min- 95 regulator-min-microvolt = <5000000>;
284 regulator-max- 96 regulator-max-microvolt = <5150000>;
285 }; 97 };
286 98
287 snvs_reg: vsnvs { 99 snvs_reg: vsnvs {
288 regulator-min- 100 regulator-min-microvolt = <1000000>;
289 regulator-max- 101 regulator-max-microvolt = <3000000>;
290 regulator-alwa 102 regulator-always-on;
291 }; 103 };
292 104
293 vref_reg: vrefddr { 105 vref_reg: vrefddr {
294 regulator-alwa 106 regulator-always-on;
295 }; 107 };
296 108
297 vgen1_reg: vgen1 { 109 vgen1_reg: vgen1 {
298 regulator-min- 110 regulator-min-microvolt = <800000>;
299 regulator-max- 111 regulator-max-microvolt = <1550000>;
300 }; 112 };
301 113
302 vgen2_reg: vgen2 { 114 vgen2_reg: vgen2 {
303 regulator-min- 115 regulator-min-microvolt = <850000>;
304 regulator-max- 116 regulator-max-microvolt = <975000>;
305 regulator-alwa 117 regulator-always-on;
306 }; 118 };
307 119
308 vgen3_reg: vgen3 { 120 vgen3_reg: vgen3 {
309 regulator-min- 121 regulator-min-microvolt = <1675000>;
310 regulator-max- 122 regulator-max-microvolt = <1975000>;
311 regulator-alwa 123 regulator-always-on;
312 }; 124 };
313 125
314 vgen4_reg: vgen4 { 126 vgen4_reg: vgen4 {
315 regulator-min- 127 regulator-min-microvolt = <1625000>;
316 regulator-max- 128 regulator-max-microvolt = <1875000>;
317 regulator-alwa 129 regulator-always-on;
318 }; 130 };
319 131
320 vgen5_reg: vgen5 { 132 vgen5_reg: vgen5 {
321 regulator-min- 133 regulator-min-microvolt = <3075000>;
322 regulator-max- 134 regulator-max-microvolt = <3625000>;
323 regulator-alwa 135 regulator-always-on;
324 }; 136 };
325 137
326 vgen6_reg: vgen6 { 138 vgen6_reg: vgen6 {
327 regulator-min- 139 regulator-min-microvolt = <1800000>;
328 regulator-max- 140 regulator-max-microvolt = <3300000>;
329 }; 141 };
330 }; 142 };
331 }; 143 };
332 }; 144 };
333 145
334 &lcdif { !! 146 &uart1 {
335 status = "okay"; <<
336 }; <<
337 <<
338 &mipi_dsi { <<
339 #address-cells = <1>; <<
340 #size-cells = <0>; <<
341 status = "okay"; <<
342 <<
343 panel@0 { <<
344 pinctrl-0 = <&pinctrl_mipi_dsi <<
345 pinctrl-names = "default"; <<
346 compatible = "raydium,rm67191" <<
347 reg = <0>; <<
348 reset-gpios = <&gpio5 6 GPIO_A <<
349 dsi-lanes = <4>; <<
350 <<
351 port { <<
352 panel_in: endpoint { <<
353 remote-endpoin <<
354 }; <<
355 }; <<
356 }; <<
357 <<
358 ports { <<
359 port@1 { <<
360 reg = <1>; <<
361 mipi_dsi_out: endpoint <<
362 remote-endpoin <<
363 }; <<
364 }; <<
365 }; <<
366 }; <<
367 <<
368 &pcie0 { <<
369 pinctrl-names = "default"; 147 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_pcie0>; !! 148 pinctrl-0 = <&pinctrl_uart1>;
371 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LO <<
372 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, <<
373 <&pcie0_refclk>, <<
374 <&clk IMX8MQ_CLK_PCIE1_PHY>, <<
375 <&clk IMX8MQ_CLK_PCIE1_AUX>; <<
376 vph-supply = <&vgen5_reg>; <<
377 status = "okay"; 149 status = "okay";
378 }; 150 };
379 151
380 &pcie1 { !! 152 &usb3_phy1 {
381 pinctrl-names = "default"; <<
382 pinctrl-0 = <&pinctrl_pcie1>; <<
383 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LO <<
384 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <<
385 <&pcie0_refclk>, <<
386 <&clk IMX8MQ_CLK_PCIE2_PHY>, <<
387 <&clk IMX8MQ_CLK_PCIE2_AUX>; <<
388 vpcie-supply = <®_pcie1>; <<
389 vph-supply = <&vgen5_reg>; <<
390 status = "okay"; 153 status = "okay";
391 }; 154 };
392 155
393 &pgc_gpu { !! 156 &usb_dwc3_1 {
394 power-supply = <&sw1a_reg>; !! 157 dr_mode = "host";
395 }; !! 158 status = "okay";
396 <<
397 &pgc_vpu { <<
398 power-supply = <&sw1c_reg>; <<
399 }; 159 };
400 160
401 &qspi0 { 161 &qspi0 {
402 pinctrl-names = "default"; 162 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_qspi>; 163 pinctrl-0 = <&pinctrl_qspi>;
404 status = "okay"; 164 status = "okay";
405 165
406 n25q256a: flash@0 { 166 n25q256a: flash@0 {
407 reg = <0>; 167 reg = <0>;
408 #address-cells = <1>; 168 #address-cells = <1>;
409 #size-cells = <1>; 169 #size-cells = <1>;
410 compatible = "micron,n25q256a" 170 compatible = "micron,n25q256a", "jedec,spi-nor";
411 spi-max-frequency = <29000000> 171 spi-max-frequency = <29000000>;
412 spi-tx-bus-width = <1>; <<
413 spi-rx-bus-width = <4>; <<
414 }; 172 };
415 }; 173 };
416 174
417 &sai2 { <<
418 pinctrl-names = "default"; <<
419 pinctrl-0 = <&pinctrl_sai2>; <<
420 assigned-clocks = <&clk IMX8MQ_AUDIO_P <<
421 assigned-clock-parents = <&clk IMX8MQ_ <<
422 assigned-clock-rates = <0>, <24576000> <<
423 status = "okay"; <<
424 }; <<
425 <<
426 &sai3 { <<
427 #sound-dai-cells = <0>; <<
428 pinctrl-names = "default"; <<
429 pinctrl-0 = <&pinctrl_sai3>; <<
430 assigned-clocks = <&clk IMX8MQ_CLK_SAI <<
431 assigned-clock-parents = <&clk IMX8MQ_ <<
432 assigned-clock-rates = <24576000>; <<
433 status = "okay"; <<
434 }; <<
435 <<
436 &snvs_pwrkey { <<
437 status = "okay"; <<
438 }; <<
439 <<
440 &spdif1 { <<
441 pinctrl-names = "default"; <<
442 pinctrl-0 = <&pinctrl_spdif1>; <<
443 assigned-clocks = <&clk IMX8MQ_CLK_SPD <<
444 assigned-clock-parents = <&clk IMX8MQ_ <<
445 assigned-clock-rates = <24576000>; <<
446 status = "okay"; <<
447 }; <<
448 <<
449 &spdif2 { <<
450 assigned-clocks = <&clk IMX8MQ_CLK_SPD <<
451 assigned-clock-parents = <&clk IMX8MQ_ <<
452 assigned-clock-rates = <24576000>; <<
453 status = "okay"; <<
454 }; <<
455 <<
456 &uart1 { <<
457 pinctrl-names = "default"; <<
458 pinctrl-0 = <&pinctrl_uart1>; <<
459 status = "okay"; <<
460 }; <<
461 <<
462 &usb3_phy1 { <<
463 status = "okay"; <<
464 }; <<
465 <<
466 &usb_dwc3_1 { <<
467 dr_mode = "host"; <<
468 status = "okay"; <<
469 }; <<
470 <<
471 &usdhc1 { 175 &usdhc1 {
472 assigned-clocks = <&clk IMX8MQ_CLK_USD <<
473 assigned-clock-rates = <400000000>; <<
474 pinctrl-names = "default", "state_100m 176 pinctrl-names = "default", "state_100mhz", "state_200mhz";
475 pinctrl-0 = <&pinctrl_usdhc1>; 177 pinctrl-0 = <&pinctrl_usdhc1>;
476 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 178 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
477 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 179 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
478 vqmmc-supply = <&sw4_reg>; 180 vqmmc-supply = <&sw4_reg>;
479 bus-width = <8>; 181 bus-width = <8>;
480 non-removable; 182 non-removable;
481 no-sd; 183 no-sd;
482 no-sdio; 184 no-sdio;
483 status = "okay"; 185 status = "okay";
484 }; 186 };
485 187
486 &usdhc2 { 188 &usdhc2 {
487 assigned-clocks = <&clk IMX8MQ_CLK_USD <<
488 assigned-clock-rates = <200000000>; <<
489 pinctrl-names = "default", "state_100m 189 pinctrl-names = "default", "state_100mhz", "state_200mhz";
490 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct !! 190 pinctrl-0 = <&pinctrl_usdhc2>;
491 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, !! 191 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
492 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, !! 192 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
493 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 193 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
494 vmmc-supply = <®_usdhc2_vmmc>; 194 vmmc-supply = <®_usdhc2_vmmc>;
495 status = "okay"; 195 status = "okay";
496 }; 196 };
497 197
498 &wdog1 { 198 &wdog1 {
499 pinctrl-names = "default"; 199 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_wdog>; 200 pinctrl-0 = <&pinctrl_wdog>;
501 fsl,ext-reset-output; 201 fsl,ext-reset-output;
502 status = "okay"; 202 status = "okay";
503 }; 203 };
504 204
505 &iomuxc { 205 &iomuxc {
506 pinctrl_buck2: vddarmgrp { <<
507 fsl,pins = < <<
508 MX8MQ_IOMUXC_GPIO1_IO1 <<
509 >; <<
510 }; <<
511 <<
512 pinctrl_fec1: fec1grp { 206 pinctrl_fec1: fec1grp {
513 fsl,pins = < 207 fsl,pins = <
514 MX8MQ_IOMUXC_ENET_MDC_ 208 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
515 MX8MQ_IOMUXC_ENET_MDIO 209 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
516 MX8MQ_IOMUXC_ENET_TD3_ 210 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
517 MX8MQ_IOMUXC_ENET_TD2_ 211 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
518 MX8MQ_IOMUXC_ENET_TD1_ 212 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
519 MX8MQ_IOMUXC_ENET_TD0_ 213 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
520 MX8MQ_IOMUXC_ENET_RD3_ 214 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
521 MX8MQ_IOMUXC_ENET_RD2_ 215 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
522 MX8MQ_IOMUXC_ENET_RD1_ 216 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
523 MX8MQ_IOMUXC_ENET_RD0_ 217 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
524 MX8MQ_IOMUXC_ENET_TXC_ 218 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
525 MX8MQ_IOMUXC_ENET_RXC_ 219 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
526 MX8MQ_IOMUXC_ENET_RX_C 220 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
527 MX8MQ_IOMUXC_ENET_TX_C 221 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
528 MX8MQ_IOMUXC_GPIO1_IO0 222 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
529 >; 223 >;
530 }; 224 };
531 225
532 pinctrl_i2c1: i2c1grp { 226 pinctrl_i2c1: i2c1grp {
533 fsl,pins = < 227 fsl,pins = <
534 MX8MQ_IOMUXC_I2C1_SCL_ 228 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
535 MX8MQ_IOMUXC_I2C1_SDA_ 229 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
536 >; 230 >;
537 }; 231 };
538 232
539 pinctrl_ir: irgrp { <<
540 fsl,pins = < <<
541 MX8MQ_IOMUXC_GPIO1_IO1 <<
542 >; <<
543 }; <<
544 <<
545 pinctrl_mipi_dsi: mipidsigrp { <<
546 fsl,pins = < <<
547 MX8MQ_IOMUXC_ECSPI1_SC <<
548 >; <<
549 }; <<
550 <<
551 pinctrl_pcie0: pcie0grp { <<
552 fsl,pins = < <<
553 MX8MQ_IOMUXC_I2C4_SCL_ <<
554 MX8MQ_IOMUXC_UART4_RXD <<
555 >; <<
556 }; <<
557 <<
558 pinctrl_pcie1: pcie1grp { <<
559 fsl,pins = < <<
560 MX8MQ_IOMUXC_I2C4_SDA_ <<
561 MX8MQ_IOMUXC_ECSPI2_MI <<
562 >; <<
563 }; <<
564 <<
565 pinctrl_pcie1_reg: pcie1reggrp { <<
566 fsl,pins = < <<
567 MX8MQ_IOMUXC_ECSPI2_SC <<
568 >; <<
569 }; <<
570 <<
571 pinctrl_qspi: qspigrp { 233 pinctrl_qspi: qspigrp {
572 fsl,pins = < 234 fsl,pins = <
573 MX8MQ_IOMUXC_NAND_ALE_ 235 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
574 MX8MQ_IOMUXC_NAND_CE0_ 236 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
575 MX8MQ_IOMUXC_NAND_DATA 237 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
576 MX8MQ_IOMUXC_NAND_DATA 238 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
577 MX8MQ_IOMUXC_NAND_DATA 239 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
578 MX8MQ_IOMUXC_NAND_DATA 240 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
579 >; <<
580 }; <<
581 <<
582 pinctrl_reg_usdhc2: regusdhc2gpiogrp { <<
583 fsl,pins = < <<
584 MX8MQ_IOMUXC_SD2_RESET <<
585 >; <<
586 }; <<
587 <<
588 pinctrl_sai2: sai2grp { <<
589 fsl,pins = < <<
590 MX8MQ_IOMUXC_SAI2_TXFS <<
591 MX8MQ_IOMUXC_SAI2_TXC_ <<
592 MX8MQ_IOMUXC_SAI2_MCLK <<
593 MX8MQ_IOMUXC_SAI2_TXD0 <<
594 MX8MQ_IOMUXC_GPIO1_IO0 <<
595 >; <<
596 }; <<
597 241
598 pinctrl_sai3: sai3grp { <<
599 fsl,pins = < <<
600 MX8MQ_IOMUXC_SAI3_TXFS <<
601 MX8MQ_IOMUXC_SAI3_TXC_ <<
602 MX8MQ_IOMUXC_SAI3_TXD_ <<
603 MX8MQ_IOMUXC_SAI3_RXD_ <<
604 >; 242 >;
605 }; 243 };
606 244
607 pinctrl_spdif1: spdif1grp { !! 245 pinctrl_reg_usdhc2: regusdhc2grpgpio {
608 fsl,pins = < 246 fsl,pins = <
609 MX8MQ_IOMUXC_SPDIF_TX_ !! 247 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
610 MX8MQ_IOMUXC_SPDIF_RX_ <<
611 >; 248 >;
612 }; 249 };
613 250
614 pinctrl_uart1: uart1grp { 251 pinctrl_uart1: uart1grp {
615 fsl,pins = < 252 fsl,pins = <
616 MX8MQ_IOMUXC_UART1_RXD 253 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
617 MX8MQ_IOMUXC_UART1_TXD 254 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
618 >; 255 >;
619 }; 256 };
620 257
621 pinctrl_usdhc1: usdhc1grp { 258 pinctrl_usdhc1: usdhc1grp {
622 fsl,pins = < 259 fsl,pins = <
623 MX8MQ_IOMUXC_SD1_CLK_U 260 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
624 MX8MQ_IOMUXC_SD1_CMD_U 261 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
625 MX8MQ_IOMUXC_SD1_DATA0 262 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
626 MX8MQ_IOMUXC_SD1_DATA1 263 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
627 MX8MQ_IOMUXC_SD1_DATA2 264 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
628 MX8MQ_IOMUXC_SD1_DATA3 265 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
629 MX8MQ_IOMUXC_SD1_DATA4 266 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
630 MX8MQ_IOMUXC_SD1_DATA5 267 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
631 MX8MQ_IOMUXC_SD1_DATA6 268 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
632 MX8MQ_IOMUXC_SD1_DATA7 269 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
633 MX8MQ_IOMUXC_SD1_STROB 270 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
634 MX8MQ_IOMUXC_SD1_RESET 271 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
635 >; 272 >;
636 }; 273 };
637 274
638 pinctrl_usdhc1_100mhz: usdhc1-100grp { 275 pinctrl_usdhc1_100mhz: usdhc1-100grp {
639 fsl,pins = < 276 fsl,pins = <
640 MX8MQ_IOMUXC_SD1_CLK_U 277 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
641 MX8MQ_IOMUXC_SD1_CMD_U 278 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
642 MX8MQ_IOMUXC_SD1_DATA0 279 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
643 MX8MQ_IOMUXC_SD1_DATA1 280 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
644 MX8MQ_IOMUXC_SD1_DATA2 281 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
645 MX8MQ_IOMUXC_SD1_DATA3 282 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
646 MX8MQ_IOMUXC_SD1_DATA4 283 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
647 MX8MQ_IOMUXC_SD1_DATA5 284 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
648 MX8MQ_IOMUXC_SD1_DATA6 285 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
649 MX8MQ_IOMUXC_SD1_DATA7 286 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
650 MX8MQ_IOMUXC_SD1_STROB 287 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
651 MX8MQ_IOMUXC_SD1_RESET 288 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
652 >; 289 >;
653 }; 290 };
654 291
655 pinctrl_usdhc1_200mhz: usdhc1-200grp { 292 pinctrl_usdhc1_200mhz: usdhc1-200grp {
656 fsl,pins = < 293 fsl,pins = <
657 MX8MQ_IOMUXC_SD1_CLK_U 294 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
658 MX8MQ_IOMUXC_SD1_CMD_U 295 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
659 MX8MQ_IOMUXC_SD1_DATA0 296 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
660 MX8MQ_IOMUXC_SD1_DATA1 297 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
661 MX8MQ_IOMUXC_SD1_DATA2 298 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
662 MX8MQ_IOMUXC_SD1_DATA3 299 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
663 MX8MQ_IOMUXC_SD1_DATA4 300 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
664 MX8MQ_IOMUXC_SD1_DATA5 301 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
665 MX8MQ_IOMUXC_SD1_DATA6 302 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
666 MX8MQ_IOMUXC_SD1_DATA7 303 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
667 MX8MQ_IOMUXC_SD1_STROB 304 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
668 MX8MQ_IOMUXC_SD1_RESET 305 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
669 >; 306 >;
670 }; 307 };
671 308
672 pinctrl_usdhc2_gpio: usdhc2gpiogrp { <<
673 fsl,pins = < <<
674 MX8MQ_IOMUXC_SD2_CD_B_ <<
675 >; <<
676 }; <<
677 <<
678 pinctrl_usdhc2: usdhc2grp { 309 pinctrl_usdhc2: usdhc2grp {
679 fsl,pins = < 310 fsl,pins = <
680 MX8MQ_IOMUXC_SD2_CLK_U 311 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
681 MX8MQ_IOMUXC_SD2_CMD_U 312 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
682 MX8MQ_IOMUXC_SD2_DATA0 313 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
683 MX8MQ_IOMUXC_SD2_DATA1 314 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
684 MX8MQ_IOMUXC_SD2_DATA2 315 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
685 MX8MQ_IOMUXC_SD2_DATA3 316 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
686 MX8MQ_IOMUXC_GPIO1_IO0 317 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
687 >; 318 >;
688 }; 319 };
689 320
690 pinctrl_usdhc2_100mhz: usdhc2-100grp { 321 pinctrl_usdhc2_100mhz: usdhc2-100grp {
691 fsl,pins = < 322 fsl,pins = <
692 MX8MQ_IOMUXC_SD2_CLK_U 323 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
693 MX8MQ_IOMUXC_SD2_CMD_U 324 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
694 MX8MQ_IOMUXC_SD2_DATA0 325 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
695 MX8MQ_IOMUXC_SD2_DATA1 326 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
696 MX8MQ_IOMUXC_SD2_DATA2 327 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
697 MX8MQ_IOMUXC_SD2_DATA3 328 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
698 MX8MQ_IOMUXC_GPIO1_IO0 329 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
699 >; 330 >;
700 }; 331 };
701 332
702 pinctrl_usdhc2_200mhz: usdhc2-200grp { 333 pinctrl_usdhc2_200mhz: usdhc2-200grp {
703 fsl,pins = < 334 fsl,pins = <
704 MX8MQ_IOMUXC_SD2_CLK_U 335 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
705 MX8MQ_IOMUXC_SD2_CMD_U 336 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
706 MX8MQ_IOMUXC_SD2_DATA0 337 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
707 MX8MQ_IOMUXC_SD2_DATA1 338 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
708 MX8MQ_IOMUXC_SD2_DATA2 339 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
709 MX8MQ_IOMUXC_SD2_DATA3 340 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
710 MX8MQ_IOMUXC_GPIO1_IO0 341 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
711 >; 342 >;
712 }; 343 };
713 344
714 pinctrl_wdog: wdog1grp { 345 pinctrl_wdog: wdog1grp {
715 fsl,pins = < 346 fsl,pins = <
716 MX8MQ_IOMUXC_GPIO1_IO0 347 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
717 >; <<
718 }; <<
719 <<
720 pinctrl_wifi_reset: wifiresetgrp { <<
721 fsl,pins = < <<
722 MX8MQ_IOMUXC_UART4_TXD <<
723 >; 348 >;
724 }; 349 };
725 }; 350 };
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