1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas < 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "imx8mq.dtsi" 9 #include "imx8mq.dtsi"
10 10
11 / { 11 / {
12 model = "NXP i.MX8MQ EVK"; 12 model = "NXP i.MX8MQ EVK";
13 compatible = "fsl,imx8mq-evk", "fsl,im 13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14 14
15 chosen { 15 chosen {
16 stdout-path = &uart1; 16 stdout-path = &uart1;
17 }; 17 };
18 18
19 memory@40000000 { 19 memory@40000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 21 reg = <0x00000000 0x40000000 0 0xc0000000>;
22 }; 22 };
23 23
24 pcie0_refclk: pcie0-refclk { 24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock"; 25 compatible = "fixed-clock";
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 clock-frequency = <100000000>; 27 clock-frequency = <100000000>;
28 }; 28 };
29 29
30 reg_pcie1: regulator-pcie { <<
31 compatible = "regulator-fixed" <<
32 pinctrl-names = "default"; <<
33 pinctrl-0 = <&pinctrl_pcie1_re <<
34 regulator-name = "MPCIE_3V3"; <<
35 regulator-min-microvolt = <330 <<
36 regulator-max-microvolt = <330 <<
37 gpio = <&gpio5 10 GPIO_ACTIVE_ <<
38 enable-active-high; <<
39 }; <<
40 <<
41 reg_usdhc2_vmmc: regulator-vsd-3v3 { 30 reg_usdhc2_vmmc: regulator-vsd-3v3 {
42 pinctrl-names = "default"; 31 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_reg_usdh 32 pinctrl-0 = <&pinctrl_reg_usdhc2>;
44 compatible = "regulator-fixed" 33 compatible = "regulator-fixed";
45 regulator-name = "VSD_3V3"; 34 regulator-name = "VSD_3V3";
46 regulator-min-microvolt = <330 35 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <330 36 regulator-max-microvolt = <3300000>;
48 gpio = <&gpio2 19 GPIO_ACTIVE_ 37 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49 off-on-delay-us = <20000>; <<
50 enable-active-high; 38 enable-active-high;
51 }; 39 };
52 40
53 buck2_reg: regulator-buck2 { 41 buck2_reg: regulator-buck2 {
54 pinctrl-names = "default"; 42 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_buck2>; 43 pinctrl-0 = <&pinctrl_buck2>;
56 compatible = "regulator-gpio"; 44 compatible = "regulator-gpio";
57 regulator-name = "vdd_arm"; 45 regulator-name = "vdd_arm";
58 regulator-min-microvolt = <900 46 regulator-min-microvolt = <900000>;
59 regulator-max-microvolt = <100 47 regulator-max-microvolt = <1000000>;
60 gpios = <&gpio1 13 GPIO_ACTIVE 48 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
61 states = <1000000 0x0 49 states = <1000000 0x0
62 900000 0x1>; 50 900000 0x1>;
63 regulator-boot-on; 51 regulator-boot-on;
64 regulator-always-on; 52 regulator-always-on;
65 }; 53 };
66 54
67 ir-receiver { 55 ir-receiver {
68 compatible = "gpio-ir-receiver 56 compatible = "gpio-ir-receiver";
69 gpios = <&gpio1 12 GPIO_ACTIVE 57 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
70 pinctrl-names = "default"; 58 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_ir>; 59 pinctrl-0 = <&pinctrl_ir>;
72 linux,autosuspend-period = <12 60 linux,autosuspend-period = <125>;
73 }; 61 };
74 62
75 audio_codec_bt_sco: audio-codec-bt-sco <<
76 compatible = "linux,bt-sco"; <<
77 #sound-dai-cells = <1>; <<
78 }; <<
79 <<
80 wm8524: audio-codec { 63 wm8524: audio-codec {
81 #sound-dai-cells = <0>; 64 #sound-dai-cells = <0>;
82 compatible = "wlf,wm8524"; 65 compatible = "wlf,wm8524";
83 wlf,mute-gpios = <&gpio1 8 GPI 66 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
84 }; 67 };
85 68
86 sound-bt-sco { <<
87 compatible = "simple-audio-car <<
88 simple-audio-card,name = "bt-s <<
89 simple-audio-card,format = "ds <<
90 simple-audio-card,bitclock-inv <<
91 simple-audio-card,frame-master <<
92 simple-audio-card,bitclock-mas <<
93 <<
94 btcpu: simple-audio-card,cpu { <<
95 sound-dai = <&sai3>; <<
96 dai-tdm-slot-num = <2> <<
97 dai-tdm-slot-width = < <<
98 }; <<
99 <<
100 simple-audio-card,codec { <<
101 sound-dai = <&audio_co <<
102 }; <<
103 }; <<
104 <<
105 sound-wm8524 { 69 sound-wm8524 {
106 compatible = "simple-audio-car 70 compatible = "simple-audio-card";
107 simple-audio-card,name = "wm85 71 simple-audio-card,name = "wm8524-audio";
108 simple-audio-card,format = "i2 72 simple-audio-card,format = "i2s";
109 simple-audio-card,frame-master 73 simple-audio-card,frame-master = <&cpudai>;
110 simple-audio-card,bitclock-mas 74 simple-audio-card,bitclock-master = <&cpudai>;
111 simple-audio-card,widgets = 75 simple-audio-card,widgets =
112 "Line", "Left Line Out 76 "Line", "Left Line Out Jack",
113 "Line", "Right Line Ou 77 "Line", "Right Line Out Jack";
114 simple-audio-card,routing = 78 simple-audio-card,routing =
115 "Left Line Out Jack", 79 "Left Line Out Jack", "LINEVOUTL",
116 "Right Line Out Jack", 80 "Right Line Out Jack", "LINEVOUTR";
117 81
118 cpudai: simple-audio-card,cpu 82 cpudai: simple-audio-card,cpu {
119 sound-dai = <&sai2>; 83 sound-dai = <&sai2>;
120 }; 84 };
121 85
122 link_codec: simple-audio-card, 86 link_codec: simple-audio-card,codec {
123 sound-dai = <&wm8524>; 87 sound-dai = <&wm8524>;
124 clocks = <&clk IMX8MQ_ 88 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
125 }; 89 };
126 }; 90 };
127 91
128 spdif_out: spdif-out { <<
129 compatible = "linux,spdif-dit" <<
130 #sound-dai-cells = <0>; <<
131 }; <<
132 <<
133 spdif_in: spdif-in { <<
134 compatible = "linux,spdif-dir" <<
135 #sound-dai-cells = <0>; <<
136 }; <<
137 <<
138 sound-spdif { 92 sound-spdif {
139 compatible = "fsl,imx-audio-sp 93 compatible = "fsl,imx-audio-spdif";
140 model = "imx-spdif"; 94 model = "imx-spdif";
141 audio-cpu = <&spdif1>; !! 95 spdif-controller = <&spdif1>;
142 audio-codec = <&spdif_out>, <& !! 96 spdif-out;
143 }; !! 97 spdif-in;
144 <<
145 hdmi_arc_in: hdmi-arc-in { <<
146 compatible = "linux,spdif-dir" <<
147 #sound-dai-cells = <0>; <<
148 }; 98 };
149 99
150 sound-hdmi-arc { 100 sound-hdmi-arc {
151 compatible = "fsl,imx-audio-sp 101 compatible = "fsl,imx-audio-spdif";
152 model = "imx-hdmi-arc"; 102 model = "imx-hdmi-arc";
153 audio-cpu = <&spdif2>; !! 103 spdif-controller = <&spdif2>;
154 audio-codec = <&hdmi_arc_in>; !! 104 spdif-in;
155 }; 105 };
156 }; 106 };
157 107
158 &A53_0 { 108 &A53_0 {
159 cpu-supply = <&buck2_reg>; 109 cpu-supply = <&buck2_reg>;
160 }; 110 };
161 111
162 &A53_1 { 112 &A53_1 {
163 cpu-supply = <&buck2_reg>; 113 cpu-supply = <&buck2_reg>;
164 }; 114 };
165 115
166 &A53_2 { 116 &A53_2 {
167 cpu-supply = <&buck2_reg>; 117 cpu-supply = <&buck2_reg>;
168 }; 118 };
169 119
170 &A53_3 { 120 &A53_3 {
171 cpu-supply = <&buck2_reg>; 121 cpu-supply = <&buck2_reg>;
172 }; 122 };
173 123
174 &ddrc { 124 &ddrc {
175 operating-points-v2 = <&ddrc_opp_table 125 operating-points-v2 = <&ddrc_opp_table>;
176 status = "okay"; <<
177 126
178 ddrc_opp_table: opp-table { 127 ddrc_opp_table: opp-table {
179 compatible = "operating-points 128 compatible = "operating-points-v2";
180 129
181 opp-25000000 { !! 130 opp-25M {
182 opp-hz = /bits/ 64 <25 131 opp-hz = /bits/ 64 <25000000>;
183 }; 132 };
184 133
185 opp-100000000 { !! 134 opp-100M {
186 opp-hz = /bits/ 64 <10 135 opp-hz = /bits/ 64 <100000000>;
187 }; 136 };
188 137
189 /* 138 /*
190 * On imx8mq B0 PLL can't be b 139 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
191 */ 140 */
192 opp-166000000 { !! 141 opp-166M {
193 opp-hz = /bits/ 64 <16 142 opp-hz = /bits/ 64 <166935483>;
194 }; 143 };
195 144
196 opp-800000000 { !! 145 opp-800M {
197 opp-hz = /bits/ 64 <80 146 opp-hz = /bits/ 64 <800000000>;
198 }; 147 };
199 }; 148 };
200 }; 149 };
201 150
202 &dphy { 151 &dphy {
203 status = "okay"; 152 status = "okay";
204 }; 153 };
205 154
206 &fec1 { 155 &fec1 {
207 pinctrl-names = "default"; 156 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_fec1>; 157 pinctrl-0 = <&pinctrl_fec1>;
209 phy-mode = "rgmii-id"; 158 phy-mode = "rgmii-id";
210 phy-handle = <ðphy0>; 159 phy-handle = <ðphy0>;
211 fsl,magic-packet; 160 fsl,magic-packet;
212 status = "okay"; 161 status = "okay";
213 162
214 mdio { 163 mdio {
215 #address-cells = <1>; 164 #address-cells = <1>;
216 #size-cells = <0>; 165 #size-cells = <0>;
217 166
218 ethphy0: ethernet-phy@0 { 167 ethphy0: ethernet-phy@0 {
219 compatible = "ethernet 168 compatible = "ethernet-phy-ieee802.3-c22";
220 reg = <0>; 169 reg = <0>;
221 reset-gpios = <&gpio1 170 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
222 reset-assert-us = <100 171 reset-assert-us = <10000>;
223 qca,disable-smarteee; <<
224 vddio-supply = <&vddh> <<
225 <<
226 vddh: vddh-regulator { <<
227 }; <<
228 }; 172 };
229 }; 173 };
230 }; 174 };
231 175
232 &gpio5 { 176 &gpio5 {
233 pinctrl-names = "default"; 177 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_wifi_reset>; 178 pinctrl-0 = <&pinctrl_wifi_reset>;
235 179
236 wl-reg-on-hog { 180 wl-reg-on-hog {
237 gpio-hog; 181 gpio-hog;
238 gpios = <29 GPIO_ACTIVE_HIGH>; 182 gpios = <29 GPIO_ACTIVE_HIGH>;
239 output-high; 183 output-high;
240 }; 184 };
241 }; 185 };
242 186
243 &i2c1 { 187 &i2c1 {
244 clock-frequency = <100000>; 188 clock-frequency = <100000>;
245 pinctrl-names = "default"; 189 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c1>; 190 pinctrl-0 = <&pinctrl_i2c1>;
247 status = "okay"; 191 status = "okay";
248 192
249 pmic@8 { 193 pmic@8 {
250 compatible = "fsl,pfuze100"; 194 compatible = "fsl,pfuze100";
251 reg = <0x8>; 195 reg = <0x8>;
252 196
253 regulators { 197 regulators {
254 sw1a_reg: sw1ab { 198 sw1a_reg: sw1ab {
255 regulator-min- 199 regulator-min-microvolt = <825000>;
256 regulator-max- 200 regulator-max-microvolt = <1100000>;
257 }; 201 };
258 202
259 sw1c_reg: sw1c { 203 sw1c_reg: sw1c {
260 regulator-min- 204 regulator-min-microvolt = <825000>;
261 regulator-max- 205 regulator-max-microvolt = <1100000>;
262 }; 206 };
263 207
264 sw2_reg: sw2 { 208 sw2_reg: sw2 {
265 regulator-min- 209 regulator-min-microvolt = <1100000>;
266 regulator-max- 210 regulator-max-microvolt = <1100000>;
267 regulator-alwa 211 regulator-always-on;
268 }; 212 };
269 213
270 sw3a_reg: sw3ab { 214 sw3a_reg: sw3ab {
271 regulator-min- 215 regulator-min-microvolt = <825000>;
272 regulator-max- 216 regulator-max-microvolt = <1100000>;
273 regulator-alwa 217 regulator-always-on;
274 }; 218 };
275 219
276 sw4_reg: sw4 { 220 sw4_reg: sw4 {
277 regulator-min- 221 regulator-min-microvolt = <1800000>;
278 regulator-max- 222 regulator-max-microvolt = <1800000>;
279 regulator-alwa 223 regulator-always-on;
280 }; 224 };
281 225
282 swbst_reg: swbst { 226 swbst_reg: swbst {
283 regulator-min- 227 regulator-min-microvolt = <5000000>;
284 regulator-max- 228 regulator-max-microvolt = <5150000>;
285 }; 229 };
286 230
287 snvs_reg: vsnvs { 231 snvs_reg: vsnvs {
288 regulator-min- 232 regulator-min-microvolt = <1000000>;
289 regulator-max- 233 regulator-max-microvolt = <3000000>;
290 regulator-alwa 234 regulator-always-on;
291 }; 235 };
292 236
293 vref_reg: vrefddr { 237 vref_reg: vrefddr {
294 regulator-alwa 238 regulator-always-on;
295 }; 239 };
296 240
297 vgen1_reg: vgen1 { 241 vgen1_reg: vgen1 {
298 regulator-min- 242 regulator-min-microvolt = <800000>;
299 regulator-max- 243 regulator-max-microvolt = <1550000>;
300 }; 244 };
301 245
302 vgen2_reg: vgen2 { 246 vgen2_reg: vgen2 {
303 regulator-min- 247 regulator-min-microvolt = <850000>;
304 regulator-max- 248 regulator-max-microvolt = <975000>;
305 regulator-alwa 249 regulator-always-on;
306 }; 250 };
307 251
308 vgen3_reg: vgen3 { 252 vgen3_reg: vgen3 {
309 regulator-min- 253 regulator-min-microvolt = <1675000>;
310 regulator-max- 254 regulator-max-microvolt = <1975000>;
311 regulator-alwa 255 regulator-always-on;
312 }; 256 };
313 257
314 vgen4_reg: vgen4 { 258 vgen4_reg: vgen4 {
315 regulator-min- 259 regulator-min-microvolt = <1625000>;
316 regulator-max- 260 regulator-max-microvolt = <1875000>;
317 regulator-alwa 261 regulator-always-on;
318 }; 262 };
319 263
320 vgen5_reg: vgen5 { 264 vgen5_reg: vgen5 {
321 regulator-min- 265 regulator-min-microvolt = <3075000>;
322 regulator-max- 266 regulator-max-microvolt = <3625000>;
323 regulator-alwa 267 regulator-always-on;
324 }; 268 };
325 269
326 vgen6_reg: vgen6 { 270 vgen6_reg: vgen6 {
327 regulator-min- 271 regulator-min-microvolt = <1800000>;
328 regulator-max- 272 regulator-max-microvolt = <3300000>;
329 }; 273 };
330 }; 274 };
331 }; 275 };
332 }; 276 };
333 277
334 &lcdif { 278 &lcdif {
335 status = "okay"; 279 status = "okay";
336 }; 280 };
337 281
338 &mipi_dsi { 282 &mipi_dsi {
339 #address-cells = <1>; 283 #address-cells = <1>;
340 #size-cells = <0>; 284 #size-cells = <0>;
341 status = "okay"; 285 status = "okay";
342 286
343 panel@0 { 287 panel@0 {
344 pinctrl-0 = <&pinctrl_mipi_dsi 288 pinctrl-0 = <&pinctrl_mipi_dsi>;
345 pinctrl-names = "default"; 289 pinctrl-names = "default";
346 compatible = "raydium,rm67191" 290 compatible = "raydium,rm67191";
347 reg = <0>; 291 reg = <0>;
348 reset-gpios = <&gpio5 6 GPIO_A 292 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
349 dsi-lanes = <4>; 293 dsi-lanes = <4>;
350 294
351 port { 295 port {
352 panel_in: endpoint { 296 panel_in: endpoint {
353 remote-endpoin 297 remote-endpoint = <&mipi_dsi_out>;
354 }; 298 };
355 }; 299 };
356 }; 300 };
357 301
358 ports { 302 ports {
359 port@1 { 303 port@1 {
360 reg = <1>; 304 reg = <1>;
361 mipi_dsi_out: endpoint 305 mipi_dsi_out: endpoint {
362 remote-endpoin 306 remote-endpoint = <&panel_in>;
363 }; 307 };
364 }; 308 };
365 }; 309 };
366 }; 310 };
367 311
368 &pcie0 { 312 &pcie0 {
369 pinctrl-names = "default"; 313 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_pcie0>; 314 pinctrl-0 = <&pinctrl_pcie0>;
371 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LO 315 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
372 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 316 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
373 <&pcie0_refclk>, !! 317 <&clk IMX8MQ_CLK_PCIE1_AUX>,
374 <&clk IMX8MQ_CLK_PCIE1_PHY>, 318 <&clk IMX8MQ_CLK_PCIE1_PHY>,
375 <&clk IMX8MQ_CLK_PCIE1_AUX>; !! 319 <&pcie0_refclk>;
376 vph-supply = <&vgen5_reg>; !! 320 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
377 status = "okay"; <<
378 }; <<
379 <<
380 &pcie1 { <<
381 pinctrl-names = "default"; <<
382 pinctrl-0 = <&pinctrl_pcie1>; <<
383 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LO <<
384 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, <<
385 <&pcie0_refclk>, <<
386 <&clk IMX8MQ_CLK_PCIE2_PHY>, <<
387 <&clk IMX8MQ_CLK_PCIE2_AUX>; <<
388 vpcie-supply = <®_pcie1>; <<
389 vph-supply = <&vgen5_reg>; <<
390 status = "okay"; 321 status = "okay";
391 }; 322 };
392 323
393 &pgc_gpu { 324 &pgc_gpu {
394 power-supply = <&sw1a_reg>; 325 power-supply = <&sw1a_reg>;
395 }; 326 };
396 327
397 &pgc_vpu { <<
398 power-supply = <&sw1c_reg>; <<
399 }; <<
400 <<
401 &qspi0 { 328 &qspi0 {
402 pinctrl-names = "default"; 329 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_qspi>; 330 pinctrl-0 = <&pinctrl_qspi>;
404 status = "okay"; 331 status = "okay";
405 332
406 n25q256a: flash@0 { 333 n25q256a: flash@0 {
407 reg = <0>; 334 reg = <0>;
408 #address-cells = <1>; 335 #address-cells = <1>;
409 #size-cells = <1>; 336 #size-cells = <1>;
410 compatible = "micron,n25q256a" 337 compatible = "micron,n25q256a", "jedec,spi-nor";
411 spi-max-frequency = <29000000> 338 spi-max-frequency = <29000000>;
412 spi-tx-bus-width = <1>; <<
413 spi-rx-bus-width = <4>; <<
414 }; 339 };
415 }; 340 };
416 341
417 &sai2 { 342 &sai2 {
418 pinctrl-names = "default"; 343 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_sai2>; 344 pinctrl-0 = <&pinctrl_sai2>;
420 assigned-clocks = <&clk IMX8MQ_AUDIO_P 345 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
421 assigned-clock-parents = <&clk IMX8MQ_ 346 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
422 assigned-clock-rates = <0>, <24576000> 347 assigned-clock-rates = <0>, <24576000>;
423 status = "okay"; 348 status = "okay";
424 }; 349 };
425 350
426 &sai3 { <<
427 #sound-dai-cells = <0>; <<
428 pinctrl-names = "default"; <<
429 pinctrl-0 = <&pinctrl_sai3>; <<
430 assigned-clocks = <&clk IMX8MQ_CLK_SAI <<
431 assigned-clock-parents = <&clk IMX8MQ_ <<
432 assigned-clock-rates = <24576000>; <<
433 status = "okay"; <<
434 }; <<
435 <<
436 &snvs_pwrkey { 351 &snvs_pwrkey {
437 status = "okay"; 352 status = "okay";
438 }; 353 };
439 354
440 &spdif1 { 355 &spdif1 {
441 pinctrl-names = "default"; 356 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_spdif1>; 357 pinctrl-0 = <&pinctrl_spdif1>;
443 assigned-clocks = <&clk IMX8MQ_CLK_SPD 358 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
444 assigned-clock-parents = <&clk IMX8MQ_ 359 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
445 assigned-clock-rates = <24576000>; 360 assigned-clock-rates = <24576000>;
446 status = "okay"; 361 status = "okay";
447 }; 362 };
448 363
449 &spdif2 { 364 &spdif2 {
450 assigned-clocks = <&clk IMX8MQ_CLK_SPD 365 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
451 assigned-clock-parents = <&clk IMX8MQ_ 366 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
452 assigned-clock-rates = <24576000>; 367 assigned-clock-rates = <24576000>;
453 status = "okay"; 368 status = "okay";
454 }; 369 };
455 370
456 &uart1 { 371 &uart1 {
457 pinctrl-names = "default"; 372 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_uart1>; 373 pinctrl-0 = <&pinctrl_uart1>;
459 status = "okay"; 374 status = "okay";
460 }; 375 };
461 376
462 &usb3_phy1 { 377 &usb3_phy1 {
463 status = "okay"; 378 status = "okay";
464 }; 379 };
465 380
466 &usb_dwc3_1 { 381 &usb_dwc3_1 {
467 dr_mode = "host"; 382 dr_mode = "host";
468 status = "okay"; 383 status = "okay";
469 }; 384 };
470 385
471 &usdhc1 { 386 &usdhc1 {
472 assigned-clocks = <&clk IMX8MQ_CLK_USD 387 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
473 assigned-clock-rates = <400000000>; 388 assigned-clock-rates = <400000000>;
474 pinctrl-names = "default", "state_100m 389 pinctrl-names = "default", "state_100mhz", "state_200mhz";
475 pinctrl-0 = <&pinctrl_usdhc1>; 390 pinctrl-0 = <&pinctrl_usdhc1>;
476 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 391 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
477 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 392 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
478 vqmmc-supply = <&sw4_reg>; 393 vqmmc-supply = <&sw4_reg>;
479 bus-width = <8>; 394 bus-width = <8>;
480 non-removable; 395 non-removable;
481 no-sd; 396 no-sd;
482 no-sdio; 397 no-sdio;
483 status = "okay"; 398 status = "okay";
484 }; 399 };
485 400
486 &usdhc2 { 401 &usdhc2 {
487 assigned-clocks = <&clk IMX8MQ_CLK_USD 402 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
488 assigned-clock-rates = <200000000>; 403 assigned-clock-rates = <200000000>;
489 pinctrl-names = "default", "state_100m 404 pinctrl-names = "default", "state_100mhz", "state_200mhz";
490 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct !! 405 pinctrl-0 = <&pinctrl_usdhc2>;
491 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, !! 406 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
492 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, !! 407 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
493 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 408 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
494 vmmc-supply = <®_usdhc2_vmmc>; 409 vmmc-supply = <®_usdhc2_vmmc>;
495 status = "okay"; 410 status = "okay";
496 }; 411 };
497 412
498 &wdog1 { 413 &wdog1 {
499 pinctrl-names = "default"; 414 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_wdog>; 415 pinctrl-0 = <&pinctrl_wdog>;
501 fsl,ext-reset-output; 416 fsl,ext-reset-output;
502 status = "okay"; 417 status = "okay";
503 }; 418 };
504 419
505 &iomuxc { 420 &iomuxc {
506 pinctrl_buck2: vddarmgrp { 421 pinctrl_buck2: vddarmgrp {
507 fsl,pins = < 422 fsl,pins = <
508 MX8MQ_IOMUXC_GPIO1_IO1 423 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
509 >; 424 >;
>> 425
510 }; 426 };
511 427
512 pinctrl_fec1: fec1grp { 428 pinctrl_fec1: fec1grp {
513 fsl,pins = < 429 fsl,pins = <
514 MX8MQ_IOMUXC_ENET_MDC_ 430 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
515 MX8MQ_IOMUXC_ENET_MDIO 431 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
516 MX8MQ_IOMUXC_ENET_TD3_ 432 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
517 MX8MQ_IOMUXC_ENET_TD2_ 433 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
518 MX8MQ_IOMUXC_ENET_TD1_ 434 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
519 MX8MQ_IOMUXC_ENET_TD0_ 435 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
520 MX8MQ_IOMUXC_ENET_RD3_ 436 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
521 MX8MQ_IOMUXC_ENET_RD2_ 437 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
522 MX8MQ_IOMUXC_ENET_RD1_ 438 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
523 MX8MQ_IOMUXC_ENET_RD0_ 439 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
524 MX8MQ_IOMUXC_ENET_TXC_ 440 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
525 MX8MQ_IOMUXC_ENET_RXC_ 441 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
526 MX8MQ_IOMUXC_ENET_RX_C 442 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
527 MX8MQ_IOMUXC_ENET_TX_C 443 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
528 MX8MQ_IOMUXC_GPIO1_IO0 444 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
529 >; 445 >;
530 }; 446 };
531 447
532 pinctrl_i2c1: i2c1grp { 448 pinctrl_i2c1: i2c1grp {
533 fsl,pins = < 449 fsl,pins = <
534 MX8MQ_IOMUXC_I2C1_SCL_ 450 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
535 MX8MQ_IOMUXC_I2C1_SDA_ 451 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
536 >; 452 >;
537 }; 453 };
538 454
539 pinctrl_ir: irgrp { 455 pinctrl_ir: irgrp {
540 fsl,pins = < 456 fsl,pins = <
541 MX8MQ_IOMUXC_GPIO1_IO1 457 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
542 >; 458 >;
543 }; 459 };
544 460
545 pinctrl_mipi_dsi: mipidsigrp { 461 pinctrl_mipi_dsi: mipidsigrp {
546 fsl,pins = < 462 fsl,pins = <
547 MX8MQ_IOMUXC_ECSPI1_SC 463 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
548 >; 464 >;
549 }; 465 };
550 466
551 pinctrl_pcie0: pcie0grp { 467 pinctrl_pcie0: pcie0grp {
552 fsl,pins = < 468 fsl,pins = <
553 MX8MQ_IOMUXC_I2C4_SCL_ 469 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
554 MX8MQ_IOMUXC_UART4_RXD 470 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
555 >; 471 >;
556 }; 472 };
557 473
558 pinctrl_pcie1: pcie1grp { <<
559 fsl,pins = < <<
560 MX8MQ_IOMUXC_I2C4_SDA_ <<
561 MX8MQ_IOMUXC_ECSPI2_MI <<
562 >; <<
563 }; <<
564 <<
565 pinctrl_pcie1_reg: pcie1reggrp { <<
566 fsl,pins = < <<
567 MX8MQ_IOMUXC_ECSPI2_SC <<
568 >; <<
569 }; <<
570 <<
571 pinctrl_qspi: qspigrp { 474 pinctrl_qspi: qspigrp {
572 fsl,pins = < 475 fsl,pins = <
573 MX8MQ_IOMUXC_NAND_ALE_ 476 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
574 MX8MQ_IOMUXC_NAND_CE0_ 477 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
575 MX8MQ_IOMUXC_NAND_DATA 478 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
576 MX8MQ_IOMUXC_NAND_DATA 479 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
577 MX8MQ_IOMUXC_NAND_DATA 480 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
578 MX8MQ_IOMUXC_NAND_DATA 481 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
>> 482
579 >; 483 >;
580 }; 484 };
581 485
582 pinctrl_reg_usdhc2: regusdhc2gpiogrp { 486 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
583 fsl,pins = < 487 fsl,pins = <
584 MX8MQ_IOMUXC_SD2_RESET 488 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
585 >; 489 >;
586 }; 490 };
587 491
588 pinctrl_sai2: sai2grp { 492 pinctrl_sai2: sai2grp {
589 fsl,pins = < 493 fsl,pins = <
590 MX8MQ_IOMUXC_SAI2_TXFS 494 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
591 MX8MQ_IOMUXC_SAI2_TXC_ 495 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
592 MX8MQ_IOMUXC_SAI2_MCLK 496 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
593 MX8MQ_IOMUXC_SAI2_TXD0 497 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
594 MX8MQ_IOMUXC_GPIO1_IO0 498 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
595 >; 499 >;
596 }; 500 };
597 501
598 pinctrl_sai3: sai3grp { <<
599 fsl,pins = < <<
600 MX8MQ_IOMUXC_SAI3_TXFS <<
601 MX8MQ_IOMUXC_SAI3_TXC_ <<
602 MX8MQ_IOMUXC_SAI3_TXD_ <<
603 MX8MQ_IOMUXC_SAI3_RXD_ <<
604 >; <<
605 }; <<
606 <<
607 pinctrl_spdif1: spdif1grp { 502 pinctrl_spdif1: spdif1grp {
608 fsl,pins = < 503 fsl,pins = <
609 MX8MQ_IOMUXC_SPDIF_TX_ 504 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
610 MX8MQ_IOMUXC_SPDIF_RX_ 505 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
611 >; 506 >;
612 }; 507 };
613 508
614 pinctrl_uart1: uart1grp { 509 pinctrl_uart1: uart1grp {
615 fsl,pins = < 510 fsl,pins = <
616 MX8MQ_IOMUXC_UART1_RXD 511 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
617 MX8MQ_IOMUXC_UART1_TXD 512 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
618 >; 513 >;
619 }; 514 };
620 515
621 pinctrl_usdhc1: usdhc1grp { 516 pinctrl_usdhc1: usdhc1grp {
622 fsl,pins = < 517 fsl,pins = <
623 MX8MQ_IOMUXC_SD1_CLK_U 518 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
624 MX8MQ_IOMUXC_SD1_CMD_U 519 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
625 MX8MQ_IOMUXC_SD1_DATA0 520 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
626 MX8MQ_IOMUXC_SD1_DATA1 521 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
627 MX8MQ_IOMUXC_SD1_DATA2 522 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
628 MX8MQ_IOMUXC_SD1_DATA3 523 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
629 MX8MQ_IOMUXC_SD1_DATA4 524 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
630 MX8MQ_IOMUXC_SD1_DATA5 525 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
631 MX8MQ_IOMUXC_SD1_DATA6 526 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
632 MX8MQ_IOMUXC_SD1_DATA7 527 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
633 MX8MQ_IOMUXC_SD1_STROB 528 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
634 MX8MQ_IOMUXC_SD1_RESET 529 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
635 >; 530 >;
636 }; 531 };
637 532
638 pinctrl_usdhc1_100mhz: usdhc1-100grp { 533 pinctrl_usdhc1_100mhz: usdhc1-100grp {
639 fsl,pins = < 534 fsl,pins = <
640 MX8MQ_IOMUXC_SD1_CLK_U 535 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
641 MX8MQ_IOMUXC_SD1_CMD_U 536 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
642 MX8MQ_IOMUXC_SD1_DATA0 537 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
643 MX8MQ_IOMUXC_SD1_DATA1 538 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
644 MX8MQ_IOMUXC_SD1_DATA2 539 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
645 MX8MQ_IOMUXC_SD1_DATA3 540 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
646 MX8MQ_IOMUXC_SD1_DATA4 541 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
647 MX8MQ_IOMUXC_SD1_DATA5 542 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
648 MX8MQ_IOMUXC_SD1_DATA6 543 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
649 MX8MQ_IOMUXC_SD1_DATA7 544 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
650 MX8MQ_IOMUXC_SD1_STROB 545 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
651 MX8MQ_IOMUXC_SD1_RESET 546 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
652 >; 547 >;
653 }; 548 };
654 549
655 pinctrl_usdhc1_200mhz: usdhc1-200grp { 550 pinctrl_usdhc1_200mhz: usdhc1-200grp {
656 fsl,pins = < 551 fsl,pins = <
657 MX8MQ_IOMUXC_SD1_CLK_U 552 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
658 MX8MQ_IOMUXC_SD1_CMD_U 553 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
659 MX8MQ_IOMUXC_SD1_DATA0 554 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
660 MX8MQ_IOMUXC_SD1_DATA1 555 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
661 MX8MQ_IOMUXC_SD1_DATA2 556 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
662 MX8MQ_IOMUXC_SD1_DATA3 557 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
663 MX8MQ_IOMUXC_SD1_DATA4 558 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
664 MX8MQ_IOMUXC_SD1_DATA5 559 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
665 MX8MQ_IOMUXC_SD1_DATA6 560 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
666 MX8MQ_IOMUXC_SD1_DATA7 561 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
667 MX8MQ_IOMUXC_SD1_STROB 562 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
668 MX8MQ_IOMUXC_SD1_RESET 563 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
669 >; <<
670 }; <<
671 <<
672 pinctrl_usdhc2_gpio: usdhc2gpiogrp { <<
673 fsl,pins = < <<
674 MX8MQ_IOMUXC_SD2_CD_B_ <<
675 >; 564 >;
676 }; 565 };
677 566
678 pinctrl_usdhc2: usdhc2grp { 567 pinctrl_usdhc2: usdhc2grp {
679 fsl,pins = < 568 fsl,pins = <
680 MX8MQ_IOMUXC_SD2_CLK_U 569 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
681 MX8MQ_IOMUXC_SD2_CMD_U 570 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
682 MX8MQ_IOMUXC_SD2_DATA0 571 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
683 MX8MQ_IOMUXC_SD2_DATA1 572 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
684 MX8MQ_IOMUXC_SD2_DATA2 573 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
685 MX8MQ_IOMUXC_SD2_DATA3 574 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
686 MX8MQ_IOMUXC_GPIO1_IO0 575 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
687 >; 576 >;
688 }; 577 };
689 578
690 pinctrl_usdhc2_100mhz: usdhc2-100grp { 579 pinctrl_usdhc2_100mhz: usdhc2-100grp {
691 fsl,pins = < 580 fsl,pins = <
692 MX8MQ_IOMUXC_SD2_CLK_U 581 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
693 MX8MQ_IOMUXC_SD2_CMD_U 582 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
694 MX8MQ_IOMUXC_SD2_DATA0 583 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
695 MX8MQ_IOMUXC_SD2_DATA1 584 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
696 MX8MQ_IOMUXC_SD2_DATA2 585 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
697 MX8MQ_IOMUXC_SD2_DATA3 586 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
698 MX8MQ_IOMUXC_GPIO1_IO0 587 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
699 >; 588 >;
700 }; 589 };
701 590
702 pinctrl_usdhc2_200mhz: usdhc2-200grp { 591 pinctrl_usdhc2_200mhz: usdhc2-200grp {
703 fsl,pins = < 592 fsl,pins = <
704 MX8MQ_IOMUXC_SD2_CLK_U 593 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
705 MX8MQ_IOMUXC_SD2_CMD_U 594 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
706 MX8MQ_IOMUXC_SD2_DATA0 595 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
707 MX8MQ_IOMUXC_SD2_DATA1 596 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
708 MX8MQ_IOMUXC_SD2_DATA2 597 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
709 MX8MQ_IOMUXC_SD2_DATA3 598 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
710 MX8MQ_IOMUXC_GPIO1_IO0 599 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
711 >; 600 >;
712 }; 601 };
713 602
714 pinctrl_wdog: wdog1grp { 603 pinctrl_wdog: wdog1grp {
715 fsl,pins = < 604 fsl,pins = <
716 MX8MQ_IOMUXC_GPIO1_IO0 605 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
717 >; 606 >;
718 }; 607 };
719 608
720 pinctrl_wifi_reset: wifiresetgrp { 609 pinctrl_wifi_reset: wifiresetgrp {
721 fsl,pins = < 610 fsl,pins = <
722 MX8MQ_IOMUXC_UART4_TXD 611 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
723 >; 612 >;
724 }; 613 };
725 }; 614 };
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