1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright 2017 NXP 3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas < 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */ 5 */
6 6
7 /dts-v1/; 7 /dts-v1/;
8 8
9 #include "imx8mq.dtsi" 9 #include "imx8mq.dtsi"
10 10
11 / { 11 / {
12 model = "NXP i.MX8MQ EVK"; 12 model = "NXP i.MX8MQ EVK";
13 compatible = "fsl,imx8mq-evk", "fsl,im 13 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
14 14
15 chosen { 15 chosen {
16 stdout-path = &uart1; 16 stdout-path = &uart1;
17 }; 17 };
18 18
19 memory@40000000 { 19 memory@40000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 21 reg = <0x00000000 0x40000000 0 0xc0000000>;
22 }; 22 };
23 23
24 pcie0_refclk: pcie0-refclk { 24 pcie0_refclk: pcie0-refclk {
25 compatible = "fixed-clock"; 25 compatible = "fixed-clock";
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 clock-frequency = <100000000>; 27 clock-frequency = <100000000>;
28 }; 28 };
29 29
30 reg_pcie1: regulator-pcie { 30 reg_pcie1: regulator-pcie {
31 compatible = "regulator-fixed" 31 compatible = "regulator-fixed";
32 pinctrl-names = "default"; 32 pinctrl-names = "default";
33 pinctrl-0 = <&pinctrl_pcie1_re 33 pinctrl-0 = <&pinctrl_pcie1_reg>;
34 regulator-name = "MPCIE_3V3"; 34 regulator-name = "MPCIE_3V3";
35 regulator-min-microvolt = <330 35 regulator-min-microvolt = <3300000>;
36 regulator-max-microvolt = <330 36 regulator-max-microvolt = <3300000>;
37 gpio = <&gpio5 10 GPIO_ACTIVE_ 37 gpio = <&gpio5 10 GPIO_ACTIVE_HIGH>;
38 enable-active-high; 38 enable-active-high;
39 }; 39 };
40 40
41 reg_usdhc2_vmmc: regulator-vsd-3v3 { 41 reg_usdhc2_vmmc: regulator-vsd-3v3 {
42 pinctrl-names = "default"; 42 pinctrl-names = "default";
43 pinctrl-0 = <&pinctrl_reg_usdh 43 pinctrl-0 = <&pinctrl_reg_usdhc2>;
44 compatible = "regulator-fixed" 44 compatible = "regulator-fixed";
45 regulator-name = "VSD_3V3"; 45 regulator-name = "VSD_3V3";
46 regulator-min-microvolt = <330 46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <330 47 regulator-max-microvolt = <3300000>;
48 gpio = <&gpio2 19 GPIO_ACTIVE_ 48 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
49 off-on-delay-us = <20000>; 49 off-on-delay-us = <20000>;
50 enable-active-high; 50 enable-active-high;
51 }; 51 };
52 52
53 buck2_reg: regulator-buck2 { 53 buck2_reg: regulator-buck2 {
54 pinctrl-names = "default"; 54 pinctrl-names = "default";
55 pinctrl-0 = <&pinctrl_buck2>; 55 pinctrl-0 = <&pinctrl_buck2>;
56 compatible = "regulator-gpio"; 56 compatible = "regulator-gpio";
57 regulator-name = "vdd_arm"; 57 regulator-name = "vdd_arm";
58 regulator-min-microvolt = <900 58 regulator-min-microvolt = <900000>;
59 regulator-max-microvolt = <100 59 regulator-max-microvolt = <1000000>;
60 gpios = <&gpio1 13 GPIO_ACTIVE 60 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
61 states = <1000000 0x0 61 states = <1000000 0x0
62 900000 0x1>; 62 900000 0x1>;
63 regulator-boot-on; 63 regulator-boot-on;
64 regulator-always-on; 64 regulator-always-on;
65 }; 65 };
66 66
67 ir-receiver { 67 ir-receiver {
68 compatible = "gpio-ir-receiver 68 compatible = "gpio-ir-receiver";
69 gpios = <&gpio1 12 GPIO_ACTIVE 69 gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
70 pinctrl-names = "default"; 70 pinctrl-names = "default";
71 pinctrl-0 = <&pinctrl_ir>; 71 pinctrl-0 = <&pinctrl_ir>;
72 linux,autosuspend-period = <12 72 linux,autosuspend-period = <125>;
73 }; 73 };
74 74
75 audio_codec_bt_sco: audio-codec-bt-sco 75 audio_codec_bt_sco: audio-codec-bt-sco {
76 compatible = "linux,bt-sco"; 76 compatible = "linux,bt-sco";
77 #sound-dai-cells = <1>; 77 #sound-dai-cells = <1>;
78 }; 78 };
79 79
80 wm8524: audio-codec { 80 wm8524: audio-codec {
81 #sound-dai-cells = <0>; 81 #sound-dai-cells = <0>;
82 compatible = "wlf,wm8524"; 82 compatible = "wlf,wm8524";
83 wlf,mute-gpios = <&gpio1 8 GPI 83 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
84 }; 84 };
85 85
86 sound-bt-sco { 86 sound-bt-sco {
87 compatible = "simple-audio-car 87 compatible = "simple-audio-card";
88 simple-audio-card,name = "bt-s 88 simple-audio-card,name = "bt-sco-audio";
89 simple-audio-card,format = "ds 89 simple-audio-card,format = "dsp_a";
90 simple-audio-card,bitclock-inv 90 simple-audio-card,bitclock-inversion;
91 simple-audio-card,frame-master 91 simple-audio-card,frame-master = <&btcpu>;
92 simple-audio-card,bitclock-mas 92 simple-audio-card,bitclock-master = <&btcpu>;
93 93
94 btcpu: simple-audio-card,cpu { 94 btcpu: simple-audio-card,cpu {
95 sound-dai = <&sai3>; 95 sound-dai = <&sai3>;
96 dai-tdm-slot-num = <2> 96 dai-tdm-slot-num = <2>;
97 dai-tdm-slot-width = < 97 dai-tdm-slot-width = <16>;
98 }; 98 };
99 99
100 simple-audio-card,codec { 100 simple-audio-card,codec {
101 sound-dai = <&audio_co 101 sound-dai = <&audio_codec_bt_sco 1>;
102 }; 102 };
103 }; 103 };
104 104
105 sound-wm8524 { 105 sound-wm8524 {
106 compatible = "simple-audio-car 106 compatible = "simple-audio-card";
107 simple-audio-card,name = "wm85 107 simple-audio-card,name = "wm8524-audio";
108 simple-audio-card,format = "i2 108 simple-audio-card,format = "i2s";
109 simple-audio-card,frame-master 109 simple-audio-card,frame-master = <&cpudai>;
110 simple-audio-card,bitclock-mas 110 simple-audio-card,bitclock-master = <&cpudai>;
111 simple-audio-card,widgets = 111 simple-audio-card,widgets =
112 "Line", "Left Line Out 112 "Line", "Left Line Out Jack",
113 "Line", "Right Line Ou 113 "Line", "Right Line Out Jack";
114 simple-audio-card,routing = 114 simple-audio-card,routing =
115 "Left Line Out Jack", 115 "Left Line Out Jack", "LINEVOUTL",
116 "Right Line Out Jack", 116 "Right Line Out Jack", "LINEVOUTR";
117 117
118 cpudai: simple-audio-card,cpu 118 cpudai: simple-audio-card,cpu {
119 sound-dai = <&sai2>; 119 sound-dai = <&sai2>;
120 }; 120 };
121 121
122 link_codec: simple-audio-card, 122 link_codec: simple-audio-card,codec {
123 sound-dai = <&wm8524>; 123 sound-dai = <&wm8524>;
124 clocks = <&clk IMX8MQ_ 124 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
125 }; 125 };
126 }; 126 };
127 127
128 spdif_out: spdif-out { <<
129 compatible = "linux,spdif-dit" <<
130 #sound-dai-cells = <0>; <<
131 }; <<
132 <<
133 spdif_in: spdif-in { <<
134 compatible = "linux,spdif-dir" <<
135 #sound-dai-cells = <0>; <<
136 }; <<
137 <<
138 sound-spdif { 128 sound-spdif {
139 compatible = "fsl,imx-audio-sp 129 compatible = "fsl,imx-audio-spdif";
140 model = "imx-spdif"; 130 model = "imx-spdif";
141 audio-cpu = <&spdif1>; !! 131 spdif-controller = <&spdif1>;
142 audio-codec = <&spdif_out>, <& !! 132 spdif-out;
143 }; !! 133 spdif-in;
144 <<
145 hdmi_arc_in: hdmi-arc-in { <<
146 compatible = "linux,spdif-dir" <<
147 #sound-dai-cells = <0>; <<
148 }; 134 };
149 135
150 sound-hdmi-arc { 136 sound-hdmi-arc {
151 compatible = "fsl,imx-audio-sp 137 compatible = "fsl,imx-audio-spdif";
152 model = "imx-hdmi-arc"; 138 model = "imx-hdmi-arc";
153 audio-cpu = <&spdif2>; !! 139 spdif-controller = <&spdif2>;
154 audio-codec = <&hdmi_arc_in>; !! 140 spdif-in;
155 }; 141 };
156 }; 142 };
157 143
158 &A53_0 { 144 &A53_0 {
159 cpu-supply = <&buck2_reg>; 145 cpu-supply = <&buck2_reg>;
160 }; 146 };
161 147
162 &A53_1 { 148 &A53_1 {
163 cpu-supply = <&buck2_reg>; 149 cpu-supply = <&buck2_reg>;
164 }; 150 };
165 151
166 &A53_2 { 152 &A53_2 {
167 cpu-supply = <&buck2_reg>; 153 cpu-supply = <&buck2_reg>;
168 }; 154 };
169 155
170 &A53_3 { 156 &A53_3 {
171 cpu-supply = <&buck2_reg>; 157 cpu-supply = <&buck2_reg>;
172 }; 158 };
173 159
174 &ddrc { 160 &ddrc {
175 operating-points-v2 = <&ddrc_opp_table 161 operating-points-v2 = <&ddrc_opp_table>;
176 status = "okay"; 162 status = "okay";
177 163
178 ddrc_opp_table: opp-table { 164 ddrc_opp_table: opp-table {
179 compatible = "operating-points 165 compatible = "operating-points-v2";
180 166
181 opp-25000000 { 167 opp-25000000 {
182 opp-hz = /bits/ 64 <25 168 opp-hz = /bits/ 64 <25000000>;
183 }; 169 };
184 170
185 opp-100000000 { 171 opp-100000000 {
186 opp-hz = /bits/ 64 <10 172 opp-hz = /bits/ 64 <100000000>;
187 }; 173 };
188 174
189 /* 175 /*
190 * On imx8mq B0 PLL can't be b 176 * On imx8mq B0 PLL can't be bypassed so low bus is 166M
191 */ 177 */
192 opp-166000000 { 178 opp-166000000 {
193 opp-hz = /bits/ 64 <16 179 opp-hz = /bits/ 64 <166935483>;
194 }; 180 };
195 181
196 opp-800000000 { 182 opp-800000000 {
197 opp-hz = /bits/ 64 <80 183 opp-hz = /bits/ 64 <800000000>;
198 }; 184 };
199 }; 185 };
200 }; 186 };
201 187
202 &dphy { 188 &dphy {
203 status = "okay"; 189 status = "okay";
204 }; 190 };
205 191
206 &fec1 { 192 &fec1 {
207 pinctrl-names = "default"; 193 pinctrl-names = "default";
208 pinctrl-0 = <&pinctrl_fec1>; 194 pinctrl-0 = <&pinctrl_fec1>;
209 phy-mode = "rgmii-id"; 195 phy-mode = "rgmii-id";
210 phy-handle = <ðphy0>; 196 phy-handle = <ðphy0>;
211 fsl,magic-packet; 197 fsl,magic-packet;
212 status = "okay"; 198 status = "okay";
213 199
214 mdio { 200 mdio {
215 #address-cells = <1>; 201 #address-cells = <1>;
216 #size-cells = <0>; 202 #size-cells = <0>;
217 203
218 ethphy0: ethernet-phy@0 { 204 ethphy0: ethernet-phy@0 {
219 compatible = "ethernet 205 compatible = "ethernet-phy-ieee802.3-c22";
220 reg = <0>; 206 reg = <0>;
221 reset-gpios = <&gpio1 207 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
222 reset-assert-us = <100 208 reset-assert-us = <10000>;
223 qca,disable-smarteee; 209 qca,disable-smarteee;
224 vddio-supply = <&vddh> 210 vddio-supply = <&vddh>;
225 211
226 vddh: vddh-regulator { 212 vddh: vddh-regulator {
227 }; 213 };
228 }; 214 };
229 }; 215 };
230 }; 216 };
231 217
232 &gpio5 { 218 &gpio5 {
233 pinctrl-names = "default"; 219 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_wifi_reset>; 220 pinctrl-0 = <&pinctrl_wifi_reset>;
235 221
236 wl-reg-on-hog { 222 wl-reg-on-hog {
237 gpio-hog; 223 gpio-hog;
238 gpios = <29 GPIO_ACTIVE_HIGH>; 224 gpios = <29 GPIO_ACTIVE_HIGH>;
239 output-high; 225 output-high;
240 }; 226 };
241 }; 227 };
242 228
243 &i2c1 { 229 &i2c1 {
244 clock-frequency = <100000>; 230 clock-frequency = <100000>;
245 pinctrl-names = "default"; 231 pinctrl-names = "default";
246 pinctrl-0 = <&pinctrl_i2c1>; 232 pinctrl-0 = <&pinctrl_i2c1>;
247 status = "okay"; 233 status = "okay";
248 234
249 pmic@8 { 235 pmic@8 {
250 compatible = "fsl,pfuze100"; 236 compatible = "fsl,pfuze100";
251 reg = <0x8>; 237 reg = <0x8>;
252 238
253 regulators { 239 regulators {
254 sw1a_reg: sw1ab { 240 sw1a_reg: sw1ab {
255 regulator-min- 241 regulator-min-microvolt = <825000>;
256 regulator-max- 242 regulator-max-microvolt = <1100000>;
257 }; 243 };
258 244
259 sw1c_reg: sw1c { 245 sw1c_reg: sw1c {
260 regulator-min- 246 regulator-min-microvolt = <825000>;
261 regulator-max- 247 regulator-max-microvolt = <1100000>;
262 }; 248 };
263 249
264 sw2_reg: sw2 { 250 sw2_reg: sw2 {
265 regulator-min- 251 regulator-min-microvolt = <1100000>;
266 regulator-max- 252 regulator-max-microvolt = <1100000>;
267 regulator-alwa 253 regulator-always-on;
268 }; 254 };
269 255
270 sw3a_reg: sw3ab { 256 sw3a_reg: sw3ab {
271 regulator-min- 257 regulator-min-microvolt = <825000>;
272 regulator-max- 258 regulator-max-microvolt = <1100000>;
273 regulator-alwa 259 regulator-always-on;
274 }; 260 };
275 261
276 sw4_reg: sw4 { 262 sw4_reg: sw4 {
277 regulator-min- 263 regulator-min-microvolt = <1800000>;
278 regulator-max- 264 regulator-max-microvolt = <1800000>;
279 regulator-alwa 265 regulator-always-on;
280 }; 266 };
281 267
282 swbst_reg: swbst { 268 swbst_reg: swbst {
283 regulator-min- 269 regulator-min-microvolt = <5000000>;
284 regulator-max- 270 regulator-max-microvolt = <5150000>;
285 }; 271 };
286 272
287 snvs_reg: vsnvs { 273 snvs_reg: vsnvs {
288 regulator-min- 274 regulator-min-microvolt = <1000000>;
289 regulator-max- 275 regulator-max-microvolt = <3000000>;
290 regulator-alwa 276 regulator-always-on;
291 }; 277 };
292 278
293 vref_reg: vrefddr { 279 vref_reg: vrefddr {
294 regulator-alwa 280 regulator-always-on;
295 }; 281 };
296 282
297 vgen1_reg: vgen1 { 283 vgen1_reg: vgen1 {
298 regulator-min- 284 regulator-min-microvolt = <800000>;
299 regulator-max- 285 regulator-max-microvolt = <1550000>;
300 }; 286 };
301 287
302 vgen2_reg: vgen2 { 288 vgen2_reg: vgen2 {
303 regulator-min- 289 regulator-min-microvolt = <850000>;
304 regulator-max- 290 regulator-max-microvolt = <975000>;
305 regulator-alwa 291 regulator-always-on;
306 }; 292 };
307 293
308 vgen3_reg: vgen3 { 294 vgen3_reg: vgen3 {
309 regulator-min- 295 regulator-min-microvolt = <1675000>;
310 regulator-max- 296 regulator-max-microvolt = <1975000>;
311 regulator-alwa 297 regulator-always-on;
312 }; 298 };
313 299
314 vgen4_reg: vgen4 { 300 vgen4_reg: vgen4 {
315 regulator-min- 301 regulator-min-microvolt = <1625000>;
316 regulator-max- 302 regulator-max-microvolt = <1875000>;
317 regulator-alwa 303 regulator-always-on;
318 }; 304 };
319 305
320 vgen5_reg: vgen5 { 306 vgen5_reg: vgen5 {
321 regulator-min- 307 regulator-min-microvolt = <3075000>;
322 regulator-max- 308 regulator-max-microvolt = <3625000>;
323 regulator-alwa 309 regulator-always-on;
324 }; 310 };
325 311
326 vgen6_reg: vgen6 { 312 vgen6_reg: vgen6 {
327 regulator-min- 313 regulator-min-microvolt = <1800000>;
328 regulator-max- 314 regulator-max-microvolt = <3300000>;
329 }; 315 };
330 }; 316 };
331 }; 317 };
332 }; 318 };
333 319
334 &lcdif { 320 &lcdif {
335 status = "okay"; 321 status = "okay";
336 }; 322 };
337 323
338 &mipi_dsi { 324 &mipi_dsi {
339 #address-cells = <1>; 325 #address-cells = <1>;
340 #size-cells = <0>; 326 #size-cells = <0>;
341 status = "okay"; 327 status = "okay";
342 328
343 panel@0 { 329 panel@0 {
344 pinctrl-0 = <&pinctrl_mipi_dsi 330 pinctrl-0 = <&pinctrl_mipi_dsi>;
345 pinctrl-names = "default"; 331 pinctrl-names = "default";
346 compatible = "raydium,rm67191" 332 compatible = "raydium,rm67191";
347 reg = <0>; 333 reg = <0>;
348 reset-gpios = <&gpio5 6 GPIO_A 334 reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
349 dsi-lanes = <4>; 335 dsi-lanes = <4>;
350 336
351 port { 337 port {
352 panel_in: endpoint { 338 panel_in: endpoint {
353 remote-endpoin 339 remote-endpoint = <&mipi_dsi_out>;
354 }; 340 };
355 }; 341 };
356 }; 342 };
357 343
358 ports { 344 ports {
359 port@1 { 345 port@1 {
360 reg = <1>; 346 reg = <1>;
361 mipi_dsi_out: endpoint 347 mipi_dsi_out: endpoint {
362 remote-endpoin 348 remote-endpoint = <&panel_in>;
363 }; 349 };
364 }; 350 };
365 }; 351 };
366 }; 352 };
367 353
368 &pcie0 { 354 &pcie0 {
369 pinctrl-names = "default"; 355 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_pcie0>; 356 pinctrl-0 = <&pinctrl_pcie0>;
371 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LO 357 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
372 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 358 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
373 <&pcie0_refclk>, 359 <&pcie0_refclk>,
374 <&clk IMX8MQ_CLK_PCIE1_PHY>, 360 <&clk IMX8MQ_CLK_PCIE1_PHY>,
375 <&clk IMX8MQ_CLK_PCIE1_AUX>; 361 <&clk IMX8MQ_CLK_PCIE1_AUX>;
376 vph-supply = <&vgen5_reg>; 362 vph-supply = <&vgen5_reg>;
377 status = "okay"; 363 status = "okay";
378 }; 364 };
379 365
380 &pcie1 { 366 &pcie1 {
381 pinctrl-names = "default"; 367 pinctrl-names = "default";
382 pinctrl-0 = <&pinctrl_pcie1>; 368 pinctrl-0 = <&pinctrl_pcie1>;
383 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LO 369 reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>;
384 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 370 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
385 <&pcie0_refclk>, 371 <&pcie0_refclk>,
386 <&clk IMX8MQ_CLK_PCIE2_PHY>, 372 <&clk IMX8MQ_CLK_PCIE2_PHY>,
387 <&clk IMX8MQ_CLK_PCIE2_AUX>; 373 <&clk IMX8MQ_CLK_PCIE2_AUX>;
388 vpcie-supply = <®_pcie1>; 374 vpcie-supply = <®_pcie1>;
389 vph-supply = <&vgen5_reg>; 375 vph-supply = <&vgen5_reg>;
390 status = "okay"; 376 status = "okay";
391 }; 377 };
392 378
393 &pgc_gpu { 379 &pgc_gpu {
394 power-supply = <&sw1a_reg>; 380 power-supply = <&sw1a_reg>;
395 }; 381 };
396 382
397 &pgc_vpu { 383 &pgc_vpu {
398 power-supply = <&sw1c_reg>; 384 power-supply = <&sw1c_reg>;
399 }; 385 };
400 386
401 &qspi0 { 387 &qspi0 {
402 pinctrl-names = "default"; 388 pinctrl-names = "default";
403 pinctrl-0 = <&pinctrl_qspi>; 389 pinctrl-0 = <&pinctrl_qspi>;
404 status = "okay"; 390 status = "okay";
405 391
406 n25q256a: flash@0 { 392 n25q256a: flash@0 {
407 reg = <0>; 393 reg = <0>;
408 #address-cells = <1>; 394 #address-cells = <1>;
409 #size-cells = <1>; 395 #size-cells = <1>;
410 compatible = "micron,n25q256a" 396 compatible = "micron,n25q256a", "jedec,spi-nor";
411 spi-max-frequency = <29000000> 397 spi-max-frequency = <29000000>;
412 spi-tx-bus-width = <1>; 398 spi-tx-bus-width = <1>;
413 spi-rx-bus-width = <4>; 399 spi-rx-bus-width = <4>;
414 }; 400 };
415 }; 401 };
416 402
417 &sai2 { 403 &sai2 {
418 pinctrl-names = "default"; 404 pinctrl-names = "default";
419 pinctrl-0 = <&pinctrl_sai2>; 405 pinctrl-0 = <&pinctrl_sai2>;
420 assigned-clocks = <&clk IMX8MQ_AUDIO_P 406 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
421 assigned-clock-parents = <&clk IMX8MQ_ 407 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
422 assigned-clock-rates = <0>, <24576000> 408 assigned-clock-rates = <0>, <24576000>;
423 status = "okay"; 409 status = "okay";
424 }; 410 };
425 411
426 &sai3 { 412 &sai3 {
427 #sound-dai-cells = <0>; 413 #sound-dai-cells = <0>;
428 pinctrl-names = "default"; 414 pinctrl-names = "default";
429 pinctrl-0 = <&pinctrl_sai3>; 415 pinctrl-0 = <&pinctrl_sai3>;
430 assigned-clocks = <&clk IMX8MQ_CLK_SAI 416 assigned-clocks = <&clk IMX8MQ_CLK_SAI3>;
431 assigned-clock-parents = <&clk IMX8MQ_ 417 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
432 assigned-clock-rates = <24576000>; 418 assigned-clock-rates = <24576000>;
433 status = "okay"; 419 status = "okay";
434 }; 420 };
435 421
436 &snvs_pwrkey { 422 &snvs_pwrkey {
437 status = "okay"; 423 status = "okay";
438 }; 424 };
439 425
440 &spdif1 { 426 &spdif1 {
441 pinctrl-names = "default"; 427 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_spdif1>; 428 pinctrl-0 = <&pinctrl_spdif1>;
443 assigned-clocks = <&clk IMX8MQ_CLK_SPD 429 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>;
444 assigned-clock-parents = <&clk IMX8MQ_ 430 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
445 assigned-clock-rates = <24576000>; 431 assigned-clock-rates = <24576000>;
446 status = "okay"; 432 status = "okay";
447 }; 433 };
448 434
449 &spdif2 { 435 &spdif2 {
450 assigned-clocks = <&clk IMX8MQ_CLK_SPD 436 assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>;
451 assigned-clock-parents = <&clk IMX8MQ_ 437 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>;
452 assigned-clock-rates = <24576000>; 438 assigned-clock-rates = <24576000>;
453 status = "okay"; 439 status = "okay";
454 }; 440 };
455 441
456 &uart1 { 442 &uart1 {
457 pinctrl-names = "default"; 443 pinctrl-names = "default";
458 pinctrl-0 = <&pinctrl_uart1>; 444 pinctrl-0 = <&pinctrl_uart1>;
459 status = "okay"; 445 status = "okay";
460 }; 446 };
461 447
462 &usb3_phy1 { 448 &usb3_phy1 {
463 status = "okay"; 449 status = "okay";
464 }; 450 };
465 451
466 &usb_dwc3_1 { 452 &usb_dwc3_1 {
467 dr_mode = "host"; 453 dr_mode = "host";
468 status = "okay"; 454 status = "okay";
469 }; 455 };
470 456
471 &usdhc1 { 457 &usdhc1 {
472 assigned-clocks = <&clk IMX8MQ_CLK_USD 458 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
473 assigned-clock-rates = <400000000>; 459 assigned-clock-rates = <400000000>;
474 pinctrl-names = "default", "state_100m 460 pinctrl-names = "default", "state_100mhz", "state_200mhz";
475 pinctrl-0 = <&pinctrl_usdhc1>; 461 pinctrl-0 = <&pinctrl_usdhc1>;
476 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 462 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
477 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 463 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
478 vqmmc-supply = <&sw4_reg>; 464 vqmmc-supply = <&sw4_reg>;
479 bus-width = <8>; 465 bus-width = <8>;
480 non-removable; 466 non-removable;
481 no-sd; 467 no-sd;
482 no-sdio; 468 no-sdio;
483 status = "okay"; 469 status = "okay";
484 }; 470 };
485 471
486 &usdhc2 { 472 &usdhc2 {
487 assigned-clocks = <&clk IMX8MQ_CLK_USD 473 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
488 assigned-clock-rates = <200000000>; 474 assigned-clock-rates = <200000000>;
489 pinctrl-names = "default", "state_100m 475 pinctrl-names = "default", "state_100mhz", "state_200mhz";
490 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 476 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
491 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 477 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
492 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 478 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
493 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 479 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
494 vmmc-supply = <®_usdhc2_vmmc>; 480 vmmc-supply = <®_usdhc2_vmmc>;
495 status = "okay"; 481 status = "okay";
496 }; 482 };
497 483
498 &wdog1 { 484 &wdog1 {
499 pinctrl-names = "default"; 485 pinctrl-names = "default";
500 pinctrl-0 = <&pinctrl_wdog>; 486 pinctrl-0 = <&pinctrl_wdog>;
501 fsl,ext-reset-output; 487 fsl,ext-reset-output;
502 status = "okay"; 488 status = "okay";
503 }; 489 };
504 490
505 &iomuxc { 491 &iomuxc {
506 pinctrl_buck2: vddarmgrp { 492 pinctrl_buck2: vddarmgrp {
507 fsl,pins = < 493 fsl,pins = <
508 MX8MQ_IOMUXC_GPIO1_IO1 494 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
509 >; 495 >;
510 }; 496 };
511 497
512 pinctrl_fec1: fec1grp { 498 pinctrl_fec1: fec1grp {
513 fsl,pins = < 499 fsl,pins = <
514 MX8MQ_IOMUXC_ENET_MDC_ 500 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
515 MX8MQ_IOMUXC_ENET_MDIO 501 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
516 MX8MQ_IOMUXC_ENET_TD3_ 502 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
517 MX8MQ_IOMUXC_ENET_TD2_ 503 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
518 MX8MQ_IOMUXC_ENET_TD1_ 504 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
519 MX8MQ_IOMUXC_ENET_TD0_ 505 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
520 MX8MQ_IOMUXC_ENET_RD3_ 506 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
521 MX8MQ_IOMUXC_ENET_RD2_ 507 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
522 MX8MQ_IOMUXC_ENET_RD1_ 508 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
523 MX8MQ_IOMUXC_ENET_RD0_ 509 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
524 MX8MQ_IOMUXC_ENET_TXC_ 510 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
525 MX8MQ_IOMUXC_ENET_RXC_ 511 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
526 MX8MQ_IOMUXC_ENET_RX_C 512 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
527 MX8MQ_IOMUXC_ENET_TX_C 513 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
528 MX8MQ_IOMUXC_GPIO1_IO0 514 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
529 >; 515 >;
530 }; 516 };
531 517
532 pinctrl_i2c1: i2c1grp { 518 pinctrl_i2c1: i2c1grp {
533 fsl,pins = < 519 fsl,pins = <
534 MX8MQ_IOMUXC_I2C1_SCL_ 520 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
535 MX8MQ_IOMUXC_I2C1_SDA_ 521 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
536 >; 522 >;
537 }; 523 };
538 524
539 pinctrl_ir: irgrp { 525 pinctrl_ir: irgrp {
540 fsl,pins = < 526 fsl,pins = <
541 MX8MQ_IOMUXC_GPIO1_IO1 527 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f
542 >; 528 >;
543 }; 529 };
544 530
545 pinctrl_mipi_dsi: mipidsigrp { 531 pinctrl_mipi_dsi: mipidsigrp {
546 fsl,pins = < 532 fsl,pins = <
547 MX8MQ_IOMUXC_ECSPI1_SC 533 MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6 0x16
548 >; 534 >;
549 }; 535 };
550 536
551 pinctrl_pcie0: pcie0grp { 537 pinctrl_pcie0: pcie0grp {
552 fsl,pins = < 538 fsl,pins = <
553 MX8MQ_IOMUXC_I2C4_SCL_ 539 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
554 MX8MQ_IOMUXC_UART4_RXD 540 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
555 >; 541 >;
556 }; 542 };
557 543
558 pinctrl_pcie1: pcie1grp { 544 pinctrl_pcie1: pcie1grp {
559 fsl,pins = < 545 fsl,pins = <
560 MX8MQ_IOMUXC_I2C4_SDA_ 546 MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76
561 MX8MQ_IOMUXC_ECSPI2_MI 547 MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16
562 >; 548 >;
563 }; 549 };
564 550
565 pinctrl_pcie1_reg: pcie1reggrp { 551 pinctrl_pcie1_reg: pcie1reggrp {
566 fsl,pins = < 552 fsl,pins = <
567 MX8MQ_IOMUXC_ECSPI2_SC 553 MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16
568 >; 554 >;
569 }; 555 };
570 556
571 pinctrl_qspi: qspigrp { 557 pinctrl_qspi: qspigrp {
572 fsl,pins = < 558 fsl,pins = <
573 MX8MQ_IOMUXC_NAND_ALE_ 559 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
574 MX8MQ_IOMUXC_NAND_CE0_ 560 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
575 MX8MQ_IOMUXC_NAND_DATA 561 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
576 MX8MQ_IOMUXC_NAND_DATA 562 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
577 MX8MQ_IOMUXC_NAND_DATA 563 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
578 MX8MQ_IOMUXC_NAND_DATA 564 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
579 >; 565 >;
580 }; 566 };
581 567
582 pinctrl_reg_usdhc2: regusdhc2gpiogrp { 568 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
583 fsl,pins = < 569 fsl,pins = <
584 MX8MQ_IOMUXC_SD2_RESET 570 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
585 >; 571 >;
586 }; 572 };
587 573
588 pinctrl_sai2: sai2grp { 574 pinctrl_sai2: sai2grp {
589 fsl,pins = < 575 fsl,pins = <
590 MX8MQ_IOMUXC_SAI2_TXFS 576 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
591 MX8MQ_IOMUXC_SAI2_TXC_ 577 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
592 MX8MQ_IOMUXC_SAI2_MCLK 578 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
593 MX8MQ_IOMUXC_SAI2_TXD0 579 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
594 MX8MQ_IOMUXC_GPIO1_IO0 580 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
595 >; 581 >;
596 }; 582 };
597 583
598 pinctrl_sai3: sai3grp { 584 pinctrl_sai3: sai3grp {
599 fsl,pins = < 585 fsl,pins = <
600 MX8MQ_IOMUXC_SAI3_TXFS 586 MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
601 MX8MQ_IOMUXC_SAI3_TXC_ 587 MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
602 MX8MQ_IOMUXC_SAI3_TXD_ 588 MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
603 MX8MQ_IOMUXC_SAI3_RXD_ 589 MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0 0xd6
604 >; 590 >;
605 }; 591 };
606 592
607 pinctrl_spdif1: spdif1grp { 593 pinctrl_spdif1: spdif1grp {
608 fsl,pins = < 594 fsl,pins = <
609 MX8MQ_IOMUXC_SPDIF_TX_ 595 MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
610 MX8MQ_IOMUXC_SPDIF_RX_ 596 MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
611 >; 597 >;
612 }; 598 };
613 599
614 pinctrl_uart1: uart1grp { 600 pinctrl_uart1: uart1grp {
615 fsl,pins = < 601 fsl,pins = <
616 MX8MQ_IOMUXC_UART1_RXD 602 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
617 MX8MQ_IOMUXC_UART1_TXD 603 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
618 >; 604 >;
619 }; 605 };
620 606
621 pinctrl_usdhc1: usdhc1grp { 607 pinctrl_usdhc1: usdhc1grp {
622 fsl,pins = < 608 fsl,pins = <
623 MX8MQ_IOMUXC_SD1_CLK_U 609 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
624 MX8MQ_IOMUXC_SD1_CMD_U 610 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
625 MX8MQ_IOMUXC_SD1_DATA0 611 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
626 MX8MQ_IOMUXC_SD1_DATA1 612 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
627 MX8MQ_IOMUXC_SD1_DATA2 613 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
628 MX8MQ_IOMUXC_SD1_DATA3 614 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
629 MX8MQ_IOMUXC_SD1_DATA4 615 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
630 MX8MQ_IOMUXC_SD1_DATA5 616 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
631 MX8MQ_IOMUXC_SD1_DATA6 617 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
632 MX8MQ_IOMUXC_SD1_DATA7 618 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
633 MX8MQ_IOMUXC_SD1_STROB 619 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
634 MX8MQ_IOMUXC_SD1_RESET 620 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
635 >; 621 >;
636 }; 622 };
637 623
638 pinctrl_usdhc1_100mhz: usdhc1-100grp { 624 pinctrl_usdhc1_100mhz: usdhc1-100grp {
639 fsl,pins = < 625 fsl,pins = <
640 MX8MQ_IOMUXC_SD1_CLK_U 626 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
641 MX8MQ_IOMUXC_SD1_CMD_U 627 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
642 MX8MQ_IOMUXC_SD1_DATA0 628 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
643 MX8MQ_IOMUXC_SD1_DATA1 629 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
644 MX8MQ_IOMUXC_SD1_DATA2 630 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
645 MX8MQ_IOMUXC_SD1_DATA3 631 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
646 MX8MQ_IOMUXC_SD1_DATA4 632 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
647 MX8MQ_IOMUXC_SD1_DATA5 633 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
648 MX8MQ_IOMUXC_SD1_DATA6 634 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
649 MX8MQ_IOMUXC_SD1_DATA7 635 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
650 MX8MQ_IOMUXC_SD1_STROB 636 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
651 MX8MQ_IOMUXC_SD1_RESET 637 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
652 >; 638 >;
653 }; 639 };
654 640
655 pinctrl_usdhc1_200mhz: usdhc1-200grp { 641 pinctrl_usdhc1_200mhz: usdhc1-200grp {
656 fsl,pins = < 642 fsl,pins = <
657 MX8MQ_IOMUXC_SD1_CLK_U 643 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
658 MX8MQ_IOMUXC_SD1_CMD_U 644 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
659 MX8MQ_IOMUXC_SD1_DATA0 645 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
660 MX8MQ_IOMUXC_SD1_DATA1 646 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
661 MX8MQ_IOMUXC_SD1_DATA2 647 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
662 MX8MQ_IOMUXC_SD1_DATA3 648 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
663 MX8MQ_IOMUXC_SD1_DATA4 649 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
664 MX8MQ_IOMUXC_SD1_DATA5 650 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
665 MX8MQ_IOMUXC_SD1_DATA6 651 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
666 MX8MQ_IOMUXC_SD1_DATA7 652 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
667 MX8MQ_IOMUXC_SD1_STROB 653 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
668 MX8MQ_IOMUXC_SD1_RESET 654 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
669 >; 655 >;
670 }; 656 };
671 657
672 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 658 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
673 fsl,pins = < 659 fsl,pins = <
674 MX8MQ_IOMUXC_SD2_CD_B_ 660 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
675 >; 661 >;
676 }; 662 };
677 663
678 pinctrl_usdhc2: usdhc2grp { 664 pinctrl_usdhc2: usdhc2grp {
679 fsl,pins = < 665 fsl,pins = <
680 MX8MQ_IOMUXC_SD2_CLK_U 666 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
681 MX8MQ_IOMUXC_SD2_CMD_U 667 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
682 MX8MQ_IOMUXC_SD2_DATA0 668 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
683 MX8MQ_IOMUXC_SD2_DATA1 669 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
684 MX8MQ_IOMUXC_SD2_DATA2 670 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
685 MX8MQ_IOMUXC_SD2_DATA3 671 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
686 MX8MQ_IOMUXC_GPIO1_IO0 672 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
687 >; 673 >;
688 }; 674 };
689 675
690 pinctrl_usdhc2_100mhz: usdhc2-100grp { 676 pinctrl_usdhc2_100mhz: usdhc2-100grp {
691 fsl,pins = < 677 fsl,pins = <
692 MX8MQ_IOMUXC_SD2_CLK_U 678 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
693 MX8MQ_IOMUXC_SD2_CMD_U 679 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
694 MX8MQ_IOMUXC_SD2_DATA0 680 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
695 MX8MQ_IOMUXC_SD2_DATA1 681 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
696 MX8MQ_IOMUXC_SD2_DATA2 682 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
697 MX8MQ_IOMUXC_SD2_DATA3 683 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
698 MX8MQ_IOMUXC_GPIO1_IO0 684 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
699 >; 685 >;
700 }; 686 };
701 687
702 pinctrl_usdhc2_200mhz: usdhc2-200grp { 688 pinctrl_usdhc2_200mhz: usdhc2-200grp {
703 fsl,pins = < 689 fsl,pins = <
704 MX8MQ_IOMUXC_SD2_CLK_U 690 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
705 MX8MQ_IOMUXC_SD2_CMD_U 691 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
706 MX8MQ_IOMUXC_SD2_DATA0 692 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
707 MX8MQ_IOMUXC_SD2_DATA1 693 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
708 MX8MQ_IOMUXC_SD2_DATA2 694 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
709 MX8MQ_IOMUXC_SD2_DATA3 695 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
710 MX8MQ_IOMUXC_GPIO1_IO0 696 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
711 >; 697 >;
712 }; 698 };
713 699
714 pinctrl_wdog: wdog1grp { 700 pinctrl_wdog: wdog1grp {
715 fsl,pins = < 701 fsl,pins = <
716 MX8MQ_IOMUXC_GPIO1_IO0 702 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
717 >; 703 >;
718 }; 704 };
719 705
720 pinctrl_wifi_reset: wifiresetgrp { 706 pinctrl_wifi_reset: wifiresetgrp {
721 fsl,pins = < 707 fsl,pins = <
722 MX8MQ_IOMUXC_UART4_TXD 708 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
723 >; 709 >;
724 }; 710 };
725 }; 711 };
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.