1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Device Tree File for the Kontron pitx-imx8m
4 *
5 * Copyright (C) 2021 Heiko Thiery <heiko.thier
6 */
7
8 /dts-v1/;
9
10 #include "imx8mq.dtsi"
11 #include <dt-bindings/net/ti-dp83867.h>
12
13 / {
14 model = "Kontron pITX-imx8m";
15 compatible = "kontron,pitx-imx8m", "fs
16
17 aliases {
18 i2c0 = &i2c1;
19 i2c1 = &i2c2;
20 i2c2 = &i2c3;
21 mmc0 = &usdhc1;
22 mmc1 = &usdhc2;
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 spi0 = &qspi0;
27 spi1 = &ecspi2;
28 };
29
30 chosen {
31 stdout-path = "serial2:115200n
32 };
33
34 pcie0_refclk: pcie0-clock {
35 compatible = "fixed-clock";
36 #clock-cells = <0>;
37 clock-frequency = <100000000>;
38 };
39
40 pcie1_refclk: pcie1-clock {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <100000000>;
44 };
45
46 reg_usdhc2_vmmc: regulator-usdhc2-vmmc
47 compatible = "regulator-fixed"
48 pinctrl-names = "default";
49 pinctrl-0 = <&pinctrl_reg_usdh
50 regulator-name = "V_3V3_SD";
51 regulator-min-microvolt = <330
52 regulator-max-microvolt = <330
53 gpio = <&gpio2 19 GPIO_ACTIVE_
54 off-on-delay-us = <20000>;
55 enable-active-high;
56 };
57 };
58
59 &ecspi2 {
60 #address-cells = <1>;
61 #size-cells = <0>;
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_
64 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>
65 status = "okay";
66
67 tpm@0 {
68 compatible = "infineon,slb9670
69 reg = <0>;
70 spi-max-frequency = <43000000>
71 };
72 };
73
74 &fec1 {
75 pinctrl-names = "default";
76 pinctrl-0 = <&pinctrl_fec1>;
77 phy-mode = "rgmii-id";
78 phy-handle = <ðphy0>;
79 fsl,magic-packet;
80 status = "okay";
81
82 mdio {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 ethphy0: ethernet-phy@0 {
87 compatible = "ethernet
88 reg = <0>;
89 ti,rx-internal-delay =
90 ti,tx-internal-delay =
91 ti,fifo-depth = <DP838
92 reset-gpios = <&gpio1
93 reset-assert-us = <10>
94 reset-deassert-us = <2
95 };
96 };
97 };
98
99 &i2c1 {
100 clock-frequency = <400000>;
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_i2c1>;
103 status = "okay";
104
105 pmic@8 {
106 compatible = "fsl,pfuze100";
107 fsl,pfuze-support-disable-sw;
108 reg = <0x8>;
109
110 regulators {
111 sw1a_reg: sw1ab {
112 regulator-name
113 regulator-min-
114 regulator-max-
115 };
116
117 sw1c_reg: sw1c {
118 regulator-name
119 regulator-min-
120 regulator-max-
121 };
122
123 sw2_reg: sw2 {
124 regulator-name
125 regulator-min-
126 regulator-max-
127 regulator-alwa
128 };
129
130 sw3a_reg: sw3ab {
131 regulator-name
132 regulator-min-
133 regulator-max-
134 regulator-alwa
135 };
136
137 sw4_reg: sw4 {
138 regulator-name
139 regulator-min-
140 regulator-max-
141 regulator-alwa
142 };
143
144 swbst_reg: swbst {
145 regulator-name
146 regulator-min-
147 regulator-max-
148 };
149
150 snvs_reg: vsnvs {
151 regulator-name
152 regulator-min-
153 regulator-max-
154 regulator-alwa
155 };
156
157 vref_reg: vrefddr {
158 regulator-name
159 regulator-alwa
160 };
161
162 vgen1_reg: vgen1 {
163 regulator-name
164 regulator-min-
165 regulator-max-
166 };
167
168 vgen2_reg: vgen2 {
169 regulator-name
170 regulator-min-
171 regulator-max-
172 regulator-alwa
173 };
174
175 vgen3_reg: vgen3 {
176 regulator-name
177 regulator-min-
178 regulator-max-
179 regulator-alwa
180 };
181
182 vgen4_reg: vgen4 {
183 regulator-name
184 regulator-min-
185 regulator-max-
186 regulator-alwa
187 };
188
189 vgen5_reg: vgen5 {
190 regulator-name
191 regulator-min-
192 regulator-max-
193 regulator-alwa
194 };
195
196 vgen6_reg: vgen6 {
197 regulator-name
198 regulator-min-
199 regulator-max-
200 regulator-alwa
201 };
202 };
203 };
204
205 fan-controller@1b {
206 compatible = "maxim,max6650";
207 reg = <0x1b>;
208 maxim,fan-microvolt = <5000000
209 };
210
211 rtc@32 {
212 compatible = "microcrystal,rv8
213 reg = <0x32>;
214 };
215
216 sensor@4b {
217 compatible = "national,lm75b";
218 reg = <0x4b>;
219 };
220
221 eeprom@51 {
222 compatible = "atmel,24c32";
223 reg = <0x51>;
224 pagesize = <32>;
225 };
226 };
227
228 &i2c2 {
229 clock-frequency = <100000>;
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_i2c2>;
232 status = "okay";
233 };
234
235 &i2c3 {
236 clock-frequency = <100000>;
237 pinctrl-names = "default";
238 pinctrl-0 = <&pinctrl_i2c3>;
239 status = "okay";
240 };
241
242 /* M.2 B-key slot */
243 &pcie0 {
244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_pcie0>;
246 reset-gpio = <&gpio1 9 GPIO_ACTIVE_LOW
247 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
248 <&pcie0_refclk>,
249 <&clk IMX8MQ_CLK_PCIE1_PHY>,
250 <&clk IMX8MQ_CLK_PCIE1_AUX>;
251 status = "okay";
252 };
253
254 /* Intel Ethernet Controller I210/I211 */
255 &pcie1 {
256 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
257 <&pcie1_refclk>,
258 <&clk IMX8MQ_CLK_PCIE2_PHY>,
259 <&clk IMX8MQ_CLK_PCIE2_AUX>;
260 fsl,max-link-speed = <1>;
261 status = "okay";
262 };
263
264 &pgc_gpu {
265 power-supply = <&sw1a_reg>;
266 };
267
268 &pgc_vpu {
269 power-supply = <&sw1c_reg>;
270 };
271
272 &qspi0 {
273 pinctrl-names = "default";
274 pinctrl-0 = <&pinctrl_qspi>;
275 status = "okay";
276
277 flash@0 {
278 compatible = "jedec,spi-nor";
279 #address-cells = <1>;
280 #size-cells = <1>;
281 reg = <0>;
282 spi-tx-bus-width = <1>;
283 spi-rx-bus-width = <4>;
284 m25p,fast-read;
285 spi-max-frequency = <50000000>
286 };
287 };
288
289 &snvs_pwrkey {
290 status = "okay";
291 };
292
293 &uart1 {
294 pinctrl-names = "default";
295 pinctrl-0 = <&pinctrl_uart1>;
296 assigned-clocks = <&clk IMX8MQ_CLK_UAR
297 assigned-clock-parents = <&clk IMX8MQ_
298 status = "okay";
299 };
300
301 &uart2 {
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_uart2>;
304 assigned-clocks = <&clk IMX8MQ_CLK_UAR
305 assigned-clock-parents = <&clk IMX8MQ_
306 status = "okay";
307 };
308
309 &uart3 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_uart3>;
312 uart-has-rtscts;
313 assigned-clocks = <&clk IMX8MQ_CLK_UAR
314 assigned-clock-parents = <&clk IMX8MQ_
315 status = "okay";
316 };
317
318 &usb3_phy0 {
319 status = "okay";
320 };
321
322 &usb3_phy1 {
323 status = "okay";
324 };
325
326 &usb_dwc3_0 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&pinctrl_usb0>;
329 dr_mode = "otg";
330 hnp-disable;
331 srp-disable;
332 adp-disable;
333 maximum-speed = "high-speed";
334 status = "okay";
335 };
336
337 &usb_dwc3_1 {
338 dr_mode = "host";
339 status = "okay";
340 };
341
342 &usdhc1 {
343 assigned-clocks = <&clk IMX8MQ_CLK_USD
344 assigned-clock-rates = <400000000>;
345 pinctrl-names = "default", "state_100m
346 pinctrl-0 = <&pinctrl_usdhc1>;
347 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
348 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
349 vqmmc-supply = <&sw4_reg>;
350 bus-width = <8>;
351 non-removable;
352 no-sd;
353 no-sdio;
354 status = "okay";
355 };
356
357 &usdhc2 {
358 assigned-clocks = <&clk IMX8MQ_CLK_USD
359 assigned-clock-rates = <200000000>;
360 pinctrl-names = "default", "state_100m
361 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
362 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
363 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
364 bus-width = <4>;
365 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
366 wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH
367 vmmc-supply = <®_usdhc2_vmmc>;
368 status = "okay";
369 };
370
371 &wdog1 {
372 pinctrl-names = "default";
373 pinctrl-0 = <&pinctrl_wdog>;
374 fsl,ext-reset-output;
375 status = "okay";
376 };
377
378 &iomuxc {
379 pinctrl-names = "default";
380 pinctrl-0 = <&pinctrl_hog>;
381
382 pinctrl_hog: hoggrp {
383 fsl,pins = <
384 MX8MQ_IOMUXC_NAND_CE1_
385 MX8MQ_IOMUXC_NAND_CE3_
386 >;
387 };
388
389 pinctrl_gpio: gpiogrp {
390 fsl,pins = <
391 MX8MQ_IOMUXC_NAND_CLE_
392 MX8MQ_IOMUXC_NAND_RE_B
393 MX8MQ_IOMUXC_NAND_WE_B
394 MX8MQ_IOMUXC_NAND_WP_B
395 MX8MQ_IOMUXC_NAND_READ
396 MX8MQ_IOMUXC_NAND_DATA
397 MX8MQ_IOMUXC_NAND_DATA
398 MX8MQ_IOMUXC_NAND_DATA
399 >;
400 };
401
402 pinctrl_pcie0: pcie0grp {
403 fsl,pins = <
404 MX8MQ_IOMUXC_GPIO1_IO0
405 MX8MQ_IOMUXC_UART4_TXD
406 >;
407 };
408
409 pinctrl_reg_usdhc2: regusdhc2gpiogrp {
410 fsl,pins = <
411 MX8MQ_IOMUXC_SD2_RESET
412 >;
413 };
414
415 pinctrl_fec1: fec1grp {
416 fsl,pins = <
417 MX8MQ_IOMUXC_ENET_MDC_
418 MX8MQ_IOMUXC_ENET_MDIO
419 MX8MQ_IOMUXC_ENET_TD3_
420 MX8MQ_IOMUXC_ENET_TD2_
421 MX8MQ_IOMUXC_ENET_TD1_
422 MX8MQ_IOMUXC_ENET_TD0_
423 MX8MQ_IOMUXC_ENET_RD3_
424 MX8MQ_IOMUXC_ENET_RD2_
425 MX8MQ_IOMUXC_ENET_RD1_
426 MX8MQ_IOMUXC_ENET_RD0_
427 MX8MQ_IOMUXC_ENET_TXC_
428 MX8MQ_IOMUXC_ENET_RXC_
429 MX8MQ_IOMUXC_ENET_RX_C
430 MX8MQ_IOMUXC_ENET_TX_C
431 MX8MQ_IOMUXC_GPIO1_IO1
432 MX8MQ_IOMUXC_GPIO1_IO1
433 >;
434 };
435
436 pinctrl_i2c1: i2c1grp {
437 fsl,pins = <
438 MX8MQ_IOMUXC_I2C1_SCL_
439 MX8MQ_IOMUXC_I2C1_SDA_
440 >;
441 };
442
443 pinctrl_i2c2: i2c2grp {
444 fsl,pins = <
445 MX8MQ_IOMUXC_I2C2_SCL_
446 MX8MQ_IOMUXC_I2C2_SDA_
447 >;
448 };
449
450 pinctrl_i2c3: i2c3grp {
451 fsl,pins = <
452 MX8MQ_IOMUXC_I2C3_SCL_
453 MX8MQ_IOMUXC_I2C3_SDA_
454 >;
455 };
456
457 pinctrl_qspi: qspigrp {
458 fsl,pins = <
459 MX8MQ_IOMUXC_NAND_ALE_
460 MX8MQ_IOMUXC_NAND_CE0_
461 MX8MQ_IOMUXC_NAND_DATA
462 MX8MQ_IOMUXC_NAND_DATA
463 MX8MQ_IOMUXC_NAND_DATA
464 MX8MQ_IOMUXC_NAND_DATA
465 >;
466 };
467
468 pinctrl_ecspi2: ecspi2grp {
469 fsl,pins = <
470 MX8MQ_IOMUXC_ECSPI2_MO
471 MX8MQ_IOMUXC_ECSPI2_MI
472 MX8MQ_IOMUXC_ECSPI2_SC
473 >;
474 };
475
476 pinctrl_ecspi2_cs: ecspi2csgrp {
477 fsl,pins = <
478 MX8MQ_IOMUXC_ECSPI2_SS
479 >;
480 };
481
482 pinctrl_uart1: uart1grp {
483 fsl,pins = <
484 MX8MQ_IOMUXC_UART1_TXD
485 MX8MQ_IOMUXC_UART1_RXD
486 >;
487 };
488
489 pinctrl_uart2: uart2grp {
490 fsl,pins = <
491 MX8MQ_IOMUXC_UART2_TXD
492 MX8MQ_IOMUXC_UART2_RXD
493 >;
494 };
495
496 pinctrl_uart3: uart3grp {
497 fsl,pins = <
498 MX8MQ_IOMUXC_UART3_TXD
499 MX8MQ_IOMUXC_UART3_RXD
500 MX8MQ_IOMUXC_ECSPI1_SS
501 MX8MQ_IOMUXC_ECSPI1_MI
502 >;
503 };
504
505 pinctrl_usdhc1: usdhc1grp {
506 fsl,pins = <
507 MX8MQ_IOMUXC_SD1_CLK_U
508 MX8MQ_IOMUXC_SD1_CMD_U
509 MX8MQ_IOMUXC_SD1_DATA0
510 MX8MQ_IOMUXC_SD1_DATA1
511 MX8MQ_IOMUXC_SD1_DATA2
512 MX8MQ_IOMUXC_SD1_DATA3
513 MX8MQ_IOMUXC_SD1_DATA4
514 MX8MQ_IOMUXC_SD1_DATA5
515 MX8MQ_IOMUXC_SD1_DATA6
516 MX8MQ_IOMUXC_SD1_DATA7
517 MX8MQ_IOMUXC_SD1_STROB
518 MX8MQ_IOMUXC_SD1_RESET
519 >;
520 };
521
522 pinctrl_usdhc1_100mhz: usdhc1-100grp {
523 fsl,pins = <
524 MX8MQ_IOMUXC_SD1_CLK_U
525 MX8MQ_IOMUXC_SD1_CMD_U
526 MX8MQ_IOMUXC_SD1_DATA0
527 MX8MQ_IOMUXC_SD1_DATA1
528 MX8MQ_IOMUXC_SD1_DATA2
529 MX8MQ_IOMUXC_SD1_DATA3
530 MX8MQ_IOMUXC_SD1_DATA4
531 MX8MQ_IOMUXC_SD1_DATA5
532 MX8MQ_IOMUXC_SD1_DATA6
533 MX8MQ_IOMUXC_SD1_DATA7
534 MX8MQ_IOMUXC_SD1_STROB
535 MX8MQ_IOMUXC_SD1_RESET
536 >;
537 };
538
539 pinctrl_usdhc1_200mhz: usdhc1-200grp {
540 fsl,pins = <
541 MX8MQ_IOMUXC_SD1_CLK_U
542 MX8MQ_IOMUXC_SD1_CMD_U
543 MX8MQ_IOMUXC_SD1_DATA0
544 MX8MQ_IOMUXC_SD1_DATA1
545 MX8MQ_IOMUXC_SD1_DATA2
546 MX8MQ_IOMUXC_SD1_DATA3
547 MX8MQ_IOMUXC_SD1_DATA4
548 MX8MQ_IOMUXC_SD1_DATA5
549 MX8MQ_IOMUXC_SD1_DATA6
550 MX8MQ_IOMUXC_SD1_DATA7
551 MX8MQ_IOMUXC_SD1_STROB
552 MX8MQ_IOMUXC_SD1_RESET
553 >;
554 };
555
556 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
557 fsl,pins = <
558 MX8MQ_IOMUXC_SD2_CD_B_
559 MX8MQ_IOMUXC_SD2_WP_GP
560 >;
561 };
562
563 pinctrl_usdhc2: usdhc2grp {
564 fsl,pins = <
565 MX8MQ_IOMUXC_SD2_CLK_U
566 MX8MQ_IOMUXC_SD2_CMD_U
567 MX8MQ_IOMUXC_SD2_DATA0
568 MX8MQ_IOMUXC_SD2_DATA1
569 MX8MQ_IOMUXC_SD2_DATA2
570 MX8MQ_IOMUXC_SD2_DATA3
571 MX8MQ_IOMUXC_GPIO1_IO0
572 >;
573 };
574
575 pinctrl_usdhc2_100mhz: usdhc2-100grp {
576 fsl,pins = <
577 MX8MQ_IOMUXC_SD2_CLK_U
578 MX8MQ_IOMUXC_SD2_CMD_U
579 MX8MQ_IOMUXC_SD2_DATA0
580 MX8MQ_IOMUXC_SD2_DATA1
581 MX8MQ_IOMUXC_SD2_DATA2
582 MX8MQ_IOMUXC_SD2_DATA3
583 MX8MQ_IOMUXC_GPIO1_IO0
584 >;
585 };
586
587 pinctrl_usdhc2_200mhz: usdhc2-200grp {
588 fsl,pins = <
589 MX8MQ_IOMUXC_SD2_CLK_U
590 MX8MQ_IOMUXC_SD2_CMD_U
591 MX8MQ_IOMUXC_SD2_DATA0
592 MX8MQ_IOMUXC_SD2_DATA1
593 MX8MQ_IOMUXC_SD2_DATA2
594 MX8MQ_IOMUXC_SD2_DATA3
595 MX8MQ_IOMUXC_GPIO1_IO0
596 >;
597 };
598
599 pinctrl_usb0: usb0grp {
600 fsl,pins = <
601 MX8MQ_IOMUXC_GPIO1_IO1
602 MX8MQ_IOMUXC_GPIO1_IO1
603 >;
604 };
605
606 pinctrl_wdog: wdoggrp {
607 fsl,pins = <
608 MX8MQ_IOMUXC_GPIO1_IO0
609 >;
610 };
611 };
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