1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2018 Boundary Devices
4 * Copyright 2021 Lucas Stach <dev@lynxeye.de>
5 */
6
7 #include "imx8mq.dtsi"
8
9 / {
10 model = "Boundary Devices i.MX8MQ Nitr
11 compatible = "boundary,imx8mq-nitrogen
12
13 chosen {
14 stdout-path = &uart1;
15 };
16
17 reg_1p8v: regulator-fixed-1v8 {
18 compatible = "regulator-fixed"
19 regulator-name = "1P8V";
20 regulator-min-microvolt = <180
21 regulator-max-microvolt = <180
22 };
23
24 reg_snvs: regulator-fixed-snvs {
25 compatible = "regulator-fixed"
26 regulator-name = "VDD_SNVS";
27 regulator-min-microvolt = <330
28 regulator-max-microvolt = <330
29 };
30 };
31
32 &{/opp-table/opp-800000000} {
33 opp-microvolt = <1000000>;
34 };
35
36 &{/opp-table/opp-1000000000} {
37 opp-microvolt = <1000000>;
38 };
39
40 &A53_0 {
41 cpu-supply = <®_arm_dram>;
42 };
43
44 &A53_1 {
45 cpu-supply = <®_arm_dram>;
46 };
47
48 &A53_2 {
49 cpu-supply = <®_arm_dram>;
50 };
51
52 &A53_3 {
53 cpu-supply = <®_arm_dram>;
54 };
55
56 &fec1 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_fec1>;
59 phy-mode = "rgmii-id";
60 phy-handle = <ðphy0>;
61 fsl,magic-packet;
62
63 mdio {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 ethphy0: ethernet-phy@4 {
68 compatible = "ethernet
69 reg = <4>;
70 interrupt-parent = <&g
71 interrupts = <11 IRQ_T
72 reset-gpios = <&gpio1
73 reset-assert-us = <100
74 reset-deassert-us = <3
75 };
76 };
77 };
78
79 &i2c1 {
80 clock-frequency = <400000>;
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_i2c1>;
83 status = "okay";
84
85 i2c-mux@70 {
86 compatible = "nxp,pca9546";
87 pinctrl-names = "default";
88 pinctrl-0 = <&pinctrl_i2c1_pca
89 reg = <0x70>;
90 reset-gpios = <&gpio1 8 GPIO_A
91 #address-cells = <1>;
92 #size-cells = <0>;
93
94 i2c1a: i2c@0 {
95 reg = <0>;
96 #address-cells = <1>;
97 #size-cells = <0>;
98
99 reg_arm_dram: regulato
100 compatible = "
101 reg = <0x60>;
102 regulator-name
103 regulator-min-
104 regulator-max-
105 regulator-alwa
106 };
107 };
108
109 i2c1b: i2c@1 {
110 reg = <1>;
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 reg_dram_1p1v: regulat
115 compatible = "
116 reg = <0x60>;
117 regulator-name
118 regulator-min-
119 regulator-max-
120 regulator-alwa
121 };
122 };
123
124 i2c1c: i2c@2 {
125 reg = <2>;
126 #address-cells = <1>;
127 #size-cells = <0>;
128
129 reg_soc_gpu_vpu: regul
130 compatible = "
131 reg = <0x60>;
132 regulator-name
133 regulator-min-
134 regulator-max-
135 regulator-alwa
136 };
137 };
138
139 i2c1d: i2c@3 {
140 reg = <3>;
141 #address-cells = <1>;
142 #size-cells = <0>;
143 };
144 };
145 };
146
147 &pgc_gpu {
148 power-supply = <®_soc_gpu_vpu>;
149 };
150
151 &pgc_vpu {
152 power-supply = <®_soc_gpu_vpu>;
153 };
154
155 &uart1 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&pinctrl_uart1>;
158 status = "okay";
159 };
160
161 &usdhc1 {
162 assigned-clocks = <&clk IMX8MQ_CLK_USD
163 assigned-clock-rates = <400000000>;
164 pinctrl-names = "default", "state_100m
165 pinctrl-0 = <&pinctrl_usdhc1>;
166 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
167 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
168 vqmmc-supply = <®_1p8v>;
169 vmmc-supply = <®_snvs>;
170 bus-width = <8>;
171 non-removable;
172 no-mmc-hs400;
173 no-sdio;
174 no-sd;
175 status = "okay";
176 };
177
178 &wdog1 {
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_wdog>;
181 fsl,ext-reset-output;
182 status = "okay";
183 };
184
185 &iomuxc {
186 pinctrl_fec1: fec1grp {
187 fsl,pins = <
188 MX8MQ_IOMUXC_ENET_MDC_
189 MX8MQ_IOMUXC_ENET_MDIO
190 MX8MQ_IOMUXC_ENET_TX_C
191 MX8MQ_IOMUXC_ENET_TXC_
192 MX8MQ_IOMUXC_ENET_TD0_
193 MX8MQ_IOMUXC_ENET_TD1_
194 MX8MQ_IOMUXC_ENET_TD2_
195 MX8MQ_IOMUXC_ENET_TD3_
196 MX8MQ_IOMUXC_ENET_RX_C
197 MX8MQ_IOMUXC_ENET_RXC_
198 MX8MQ_IOMUXC_ENET_RD0_
199 MX8MQ_IOMUXC_ENET_RD1_
200 MX8MQ_IOMUXC_ENET_RD2_
201 MX8MQ_IOMUXC_ENET_RD3_
202 MX8MQ_IOMUXC_GPIO1_IO0
203 MX8MQ_IOMUXC_GPIO1_IO1
204 >;
205 };
206
207 pinctrl_i2c1: i2c1grp {
208 fsl,pins = <
209 MX8MQ_IOMUXC_I2C1_SCL_
210 MX8MQ_IOMUXC_I2C1_SDA_
211 >;
212 };
213
214 pinctrl_i2c1_pca9546: i2c1-pca9546grp
215 fsl,pins = <
216 MX8MQ_IOMUXC_GPIO1_IO0
217 >;
218 };
219
220 pinctrl_uart1: uart1grp {
221 fsl,pins = <
222 MX8MQ_IOMUXC_UART1_RXD
223 MX8MQ_IOMUXC_UART1_TXD
224 >;
225 };
226
227 pinctrl_usdhc1: usdhc1grp {
228 fsl,pins = <
229 MX8MQ_IOMUXC_SD1_CLK_U
230 MX8MQ_IOMUXC_SD1_CMD_U
231 MX8MQ_IOMUXC_SD1_DATA0
232 MX8MQ_IOMUXC_SD1_DATA1
233 MX8MQ_IOMUXC_SD1_DATA2
234 MX8MQ_IOMUXC_SD1_DATA3
235 MX8MQ_IOMUXC_SD1_DATA4
236 MX8MQ_IOMUXC_SD1_DATA5
237 MX8MQ_IOMUXC_SD1_DATA6
238 MX8MQ_IOMUXC_SD1_DATA7
239 MX8MQ_IOMUXC_SD1_RESET
240 >;
241 };
242
243 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
244 fsl,pins = <
245 MX8MQ_IOMUXC_SD1_CLK_U
246 MX8MQ_IOMUXC_SD1_CMD_U
247 MX8MQ_IOMUXC_SD1_DATA0
248 MX8MQ_IOMUXC_SD1_DATA1
249 MX8MQ_IOMUXC_SD1_DATA2
250 MX8MQ_IOMUXC_SD1_DATA3
251 MX8MQ_IOMUXC_SD1_DATA4
252 MX8MQ_IOMUXC_SD1_DATA5
253 MX8MQ_IOMUXC_SD1_DATA6
254 MX8MQ_IOMUXC_SD1_DATA7
255 >;
256 };
257
258 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
259 fsl,pins = <
260 MX8MQ_IOMUXC_SD1_CLK_U
261 MX8MQ_IOMUXC_SD1_CMD_U
262 MX8MQ_IOMUXC_SD1_DATA0
263 MX8MQ_IOMUXC_SD1_DATA1
264 MX8MQ_IOMUXC_SD1_DATA2
265 MX8MQ_IOMUXC_SD1_DATA3
266 MX8MQ_IOMUXC_SD1_DATA4
267 MX8MQ_IOMUXC_SD1_DATA5
268 MX8MQ_IOMUXC_SD1_DATA6
269 MX8MQ_IOMUXC_SD1_DATA7
270 >;
271 };
272
273 pinctrl_wdog: wdoggrp {
274 fsl,pins = <
275 MX8MQ_IOMUXC_GPIO1_IO0
276 >;
277 };
278 };
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