1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright 2018 Boundary Devices
4 */
5
6 /dts-v1/;
7
8 #include <dt-bindings/input/input.h>
9 #include "imx8mq.dtsi"
10
11 / {
12 model = "Boundary Devices i.MX8MQ Nitr
13 compatible = "boundary,imx8mq-nitrogen
14
15 chosen {
16 stdout-path = "serial0:115200n
17 };
18
19 memory@40000000 {
20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0
22 };
23
24 gpio-keys {
25 compatible = "gpio-keys";
26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_key
28
29 button-power {
30 label = "Power Button"
31 gpios = <&gpio1 7 GPIO
32 linux,code = <KEY_POWE
33 wakeup-source;
34 };
35 };
36
37 hdmi-connector {
38 compatible = "hdmi-connector";
39 ddc-i2c-bus = <&ddc_i2c_bus>;
40 label = "hdmi";
41 type = "a";
42
43 port {
44 hdmi_connector_in: end
45 remote-endpoin
46 };
47 };
48 };
49
50 reg_usb_otg_vbus: regulator-usb-otg-vb
51 compatible = "regulator-fixed"
52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_reg_usbo
54 regulator-name = "usb_otg_vbus
55 regulator-min-microvolt = <500
56 regulator-max-microvolt = <500
57 gpio = <&gpio1 12 GPIO_ACTIVE_
58 enable-active-high;
59 };
60
61 reg_vref_0v9: regulator-vref-0v9 {
62 compatible = "regulator-fixed"
63 regulator-name = "vref-0v9";
64 regulator-min-microvolt = <900
65 regulator-max-microvolt = <900
66 };
67
68 reg_vref_1v8: regulator-vref-1v8 {
69 compatible = "regulator-fixed"
70 regulator-name = "vref-1v8";
71 regulator-min-microvolt = <180
72 regulator-max-microvolt = <180
73 };
74
75 reg_vref_2v5: regulator-vref-2v5 {
76 compatible = "regulator-fixed"
77 regulator-name = "vref-2v5";
78 regulator-min-microvolt = <250
79 regulator-max-microvolt = <250
80 };
81
82 reg_vref_3v3: regulator-vref-3v3 {
83 compatible = "regulator-fixed"
84 regulator-name = "vref-3v3";
85 regulator-min-microvolt = <330
86 regulator-max-microvolt = <330
87 };
88
89 reg_vref_5v: regulator-vref-5v {
90 compatible = "regulator-fixed"
91 regulator-name = "vref-5v";
92 regulator-min-microvolt = <500
93 regulator-max-microvolt = <500
94 };
95 };
96
97 &dphy {
98 status = "okay";
99 };
100
101 &fec1 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_fec1>;
104 phy-mode = "rgmii-id";
105 phy-handle = <ðphy0>;
106 fsl,magic-packet;
107 status = "okay";
108
109 mdio {
110 #address-cells = <1>;
111 #size-cells = <0>;
112
113 ethphy0: ethernet-phy@4 {
114 compatible = "ethernet
115 reg = <4>;
116 interrupts-extended =
117 };
118 };
119 };
120
121 /* Release reset of the USB Host HUB */
122 &gpio1 {
123 usb-host-reset-hog {
124 gpio-hog;
125 gpios = <14 GPIO_ACTIVE_HIGH>;
126 output-high;
127 };
128 };
129
130 &i2c1 {
131 clock-frequency = <400000>;
132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_i2c1>;
134 status = "okay";
135
136 i2c-mux@70 {
137 compatible = "nxp,pca9546";
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c1_pca
140 reg = <0x70>;
141 reset-gpios = <&gpio1 8 GPIO_A
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 i2c1a: i2c@0 {
146 reg = <0>;
147 #address-cells = <1>;
148 #size-cells = <0>;
149
150 reg_arm_dram: regulato
151 compatible = "
152 pinctrl-names
153 pinctrl-0 = <&
154 reg = <0x60>;
155 regulator-min-
156 regulator-max-
157 regulator-alwa
158 vsel-gpios = <
159 };
160 };
161
162 i2c1b: i2c@1 {
163 reg = <1>;
164 #address-cells = <1>;
165 #size-cells = <0>;
166
167 reg_dram_1p1v: regulat
168 compatible = "
169 pinctrl-names
170 pinctrl-0 = <&
171 reg = <0x60>;
172 regulator-min-
173 regulator-max-
174 regulator-alwa
175 vsel-gpios = <
176 };
177 };
178
179 i2c1c: i2c@2 {
180 reg = <2>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 reg_soc_gpu_vpu: regul
185 compatible = "
186 pinctrl-names
187 pinctrl-0 = <&
188 reg = <0x60>;
189 regulator-min-
190 regulator-max-
191 regulator-alwa
192 vsel-gpios = <
193 };
194 };
195
196 i2c1d: i2c@3 {
197 reg = <3>;
198 #address-cells = <1>;
199 #size-cells = <0>;
200
201 rtc@68 {
202 compatible = "
203 pinctrl-names
204 pinctrl-0 = <&
205 reg = <0x68>;
206 interrupts-ext
207 wakeup-source;
208 };
209 };
210 };
211 };
212
213 &i2c4 {
214 clock-frequency = <100000>;
215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_i2c4>;
217 status = "okay";
218
219 pca9546: i2c-mux@70 {
220 compatible = "nxp,pca9546";
221 reg = <0x70>;
222 #address-cells = <1>;
223 #size-cells = <0>;
224
225 i2c@0 {
226 reg = <0>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229 clock-frequency = <100
230
231 hdmi-bridge@48 {
232 compatible = "
233 reg = <0x48> ;
234 reset-gpios =
235
236 ports {
237 #addre
238 #size-
239
240 port@0
241
242
243
244
245
246
247 };
248
249 port@1
250
251
252
253
254
255 };
256 };
257 };
258 };
259
260 ddc_i2c_bus: i2c@1 {
261 reg = <1>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264 clock-frequency = <100
265 };
266
267 i2c@3 {
268 reg = <3>;
269 #address-cells = <1>;
270 #size-cells = <0>;
271 clock-frequency = <100
272
273 max7323: gpio-expander
274 compatible = "
275 pinctrl-names
276 pinctrl-0 = <&
277 gpio-controlle
278 reg = <0x68>;
279 #gpio-cells =
280 };
281 };
282 };
283 };
284
285 &lcdif {
286 status = "okay";
287 };
288
289 &mipi_dsi {
290 #address-cells = <1>;
291 #size-cells = <0>;
292 status = "okay";
293
294 ports {
295 port@1 {
296 reg = <1>;
297
298 mipi_dsi_out: endpoint
299 remote-endpoin
300 };
301 };
302 };
303 };
304
305 &uart1 { /* console */
306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_uart1>;
308 assigned-clocks = <&clk IMX8MQ_CLK_UAR
309 assigned-clock-parents = <&clk IMX8MQ_
310 status = "okay";
311 };
312
313 &uart2 {
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_uart2>;
316 assigned-clocks = <&clk IMX8MQ_CLK_UAR
317 assigned-clock-parents = <&clk IMX8MQ_
318 status = "okay";
319 };
320
321 &usb_dwc3_0 {
322 dr_mode = "otg";
323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_usb3_0>;
325 status = "okay";
326 };
327
328 &usb3_phy0 {
329 vbus-supply = <®_usb_otg_vbus>;
330 status = "okay";
331 };
332
333 &usb_dwc3_1 {
334 dr_mode = "host";
335 status = "okay";
336 };
337
338 &usb3_phy1 {
339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_usb3_1>;
341 status = "okay";
342 };
343
344 &usdhc1 {
345 assigned-clocks = <&clk IMX8MQ_CLK_USD
346 assigned-clock-rates = <400000000>;
347 bus-width = <8>;
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_usdhc1>;
350 non-removable;
351 vmmc-supply = <®_vref_1v8>;
352 status = "okay";
353 };
354
355 &wdog1 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_wdog>;
358 fsl,ext-reset-output;
359 status = "okay";
360 };
361
362 &iomuxc {
363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_hog>;
365
366 pinctrl_hog: hoggrp {
367 fsl,pins = <
368 /* J17 connector, odd
369 MX8MQ_IOMUXC_SAI1_RXFS
370 MX8MQ_IOMUXC_SAI1_RXC_
371 MX8MQ_IOMUXC_SAI1_RXD1
372 MX8MQ_IOMUXC_SAI1_RXD2
373 MX8MQ_IOMUXC_SAI1_RXD3
374 MX8MQ_IOMUXC_SAI1_RXD4
375 MX8MQ_IOMUXC_SAI1_RXD5
376 MX8MQ_IOMUXC_SAI1_RXD6
377 MX8MQ_IOMUXC_SAI1_RXD7
378 MX8MQ_IOMUXC_SAI1_TXD1
379 MX8MQ_IOMUXC_SAI1_TXD2
380 MX8MQ_IOMUXC_SAI1_TXD3
381 MX8MQ_IOMUXC_SAI1_TXD4
382 MX8MQ_IOMUXC_SAI1_TXD5
383 MX8MQ_IOMUXC_SAI1_TXD6
384 MX8MQ_IOMUXC_SAI1_TXD7
385
386 /* J17 connector, even
387 MX8MQ_IOMUXC_SAI3_RXFS
388 MX8MQ_IOMUXC_SAI3_RXC_
389 MX8MQ_IOMUXC_GPIO1_IO1
390 MX8MQ_IOMUXC_GPIO1_IO0
391 MX8MQ_IOMUXC_GPIO1_IO0
392
393 /* J18 connector, odd
394 MX8MQ_IOMUXC_NAND_CE3_
395 MX8MQ_IOMUXC_NAND_CLE_
396 MX8MQ_IOMUXC_NAND_READ
397 MX8MQ_IOMUXC_NAND_DATA
398 MX8MQ_IOMUXC_NAND_WP_B
399 MX8MQ_IOMUXC_NAND_DQS_
400
401 /* J18 connector, even
402 MX8MQ_IOMUXC_NAND_ALE_
403 MX8MQ_IOMUXC_NAND_CE0_
404 MX8MQ_IOMUXC_NAND_DATA
405 MX8MQ_IOMUXC_NAND_DATA
406 MX8MQ_IOMUXC_NAND_DATA
407 MX8MQ_IOMUXC_NAND_DATA
408 MX8MQ_IOMUXC_NAND_DATA
409
410 /* J13 Pin 2, WL_WAKE
411 MX8MQ_IOMUXC_SAI5_RXD2
412 /* J13 Pin 4, WL_IRQ,
413 MX8MQ_IOMUXC_SAI5_RXD0
414 /* J13 pin 9, unused *
415 MX8MQ_IOMUXC_SD2_CD_B_
416 /* J13 Pin 41, BT_CLK_
417 MX8MQ_IOMUXC_SAI5_RXD1
418 /* J13 Pin 42, BT_HOST
419 MX8MQ_IOMUXC_SAI5_MCLK
420
421 /* Clock for both CSI1
422 MX8MQ_IOMUXC_GPIO1_IO1
423 /* test points */
424 MX8MQ_IOMUXC_GPIO1_IO0
425 >;
426 };
427
428 pinctrl_fec1: fec1grp {
429 fsl,pins = <
430 MX8MQ_IOMUXC_ENET_MDC_
431 MX8MQ_IOMUXC_ENET_MDIO
432 MX8MQ_IOMUXC_ENET_TX_C
433 MX8MQ_IOMUXC_ENET_TXC_
434 MX8MQ_IOMUXC_ENET_TD0_
435 MX8MQ_IOMUXC_ENET_TD1_
436 MX8MQ_IOMUXC_ENET_TD2_
437 MX8MQ_IOMUXC_ENET_TD3_
438 MX8MQ_IOMUXC_ENET_RX_C
439 MX8MQ_IOMUXC_ENET_RXC_
440 MX8MQ_IOMUXC_ENET_RD0_
441 MX8MQ_IOMUXC_ENET_RD1_
442 MX8MQ_IOMUXC_ENET_RD2_
443 MX8MQ_IOMUXC_ENET_RD3_
444 MX8MQ_IOMUXC_GPIO1_IO0
445 MX8MQ_IOMUXC_GPIO1_IO1
446 >;
447 };
448
449 pinctrl_gpio_keys: gpio-keysgrp {
450 fsl,pins = <
451 MX8MQ_IOMUXC_GPIO1_IO0
452 >;
453 };
454
455
456 pinctrl_i2c1: i2c1grp {
457 fsl,pins = <
458 MX8MQ_IOMUXC_I2C1_SCL_
459 MX8MQ_IOMUXC_I2C1_SDA_
460 >;
461 };
462
463 pinctrl_i2c1_pca9546: i2c1-pca9546grp
464 fsl,pins = <
465 MX8MQ_IOMUXC_GPIO1_IO0
466 >;
467 };
468
469 pinctrl_i2c1d_rv4162: i2c1d-rv4162grp
470 fsl,pins = <
471 MX8MQ_IOMUXC_GPIO1_IO0
472 >;
473 };
474
475 pinctrl_i2c4: i2c4grp {
476 fsl,pins = <
477 MX8MQ_IOMUXC_I2C4_SCL_
478 MX8MQ_IOMUXC_I2C4_SDA_
479 >;
480 };
481
482 pinctrl_max7323: max7323grp {
483 fsl,pins = <
484 MX8MQ_IOMUXC_NAND_RE_B
485 >;
486 };
487
488 pinctrl_reg_arm_dram: reg-arm-dramgrp
489 fsl,pins = <
490 MX8MQ_IOMUXC_SAI5_RXD3
491 >;
492 };
493
494 pinctrl_reg_dram_1p1v: reg-dram-1p1vgr
495 fsl,pins = <
496 MX8MQ_IOMUXC_SD1_STROB
497 >;
498 };
499
500 pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-v
501 fsl,pins = <
502 MX8MQ_IOMUXC_SD2_WP_GP
503 >;
504 };
505
506 pinctrl_reg_usbotg_vbus: reg-usbotg-vb
507 fsl,pins = <
508 MX8MQ_IOMUXC_GPIO1_IO1
509 >;
510 };
511
512 pinctrl_uart1: uart1grp {
513 fsl,pins = <
514 MX8MQ_IOMUXC_UART1_RXD
515 MX8MQ_IOMUXC_UART1_TXD
516 >;
517 };
518
519 pinctrl_uart2: uart2grp {
520 fsl,pins = <
521 MX8MQ_IOMUXC_UART2_RXD
522 MX8MQ_IOMUXC_UART2_TXD
523 >;
524 };
525
526 pinctrl_usb3_0: usb3-0grp {
527 fsl,pins = <
528 MX8MQ_IOMUXC_GPIO1_IO1
529 >;
530 };
531
532 pinctrl_usb3_1: usb3-1grp {
533 fsl,pins = <
534 MX8MQ_IOMUXC_GPIO1_IO1
535 >;
536 };
537
538 pinctrl_usdhc1: usdhc1grp {
539 fsl,pins = <
540 MX8MQ_IOMUXC_SD1_CLK_U
541 MX8MQ_IOMUXC_SD1_CMD_U
542 MX8MQ_IOMUXC_SD1_DATA0
543 MX8MQ_IOMUXC_SD1_DATA1
544 MX8MQ_IOMUXC_SD1_DATA2
545 MX8MQ_IOMUXC_SD1_DATA3
546 MX8MQ_IOMUXC_SD1_DATA4
547 MX8MQ_IOMUXC_SD1_DATA5
548 MX8MQ_IOMUXC_SD1_DATA6
549 MX8MQ_IOMUXC_SD1_DATA7
550 MX8MQ_IOMUXC_SD1_RESET
551 >;
552 };
553
554 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
555 fsl,pins = <
556 MX8MQ_IOMUXC_SD1_CLK_U
557 MX8MQ_IOMUXC_SD1_CMD_U
558 MX8MQ_IOMUXC_SD1_DATA0
559 MX8MQ_IOMUXC_SD1_DATA1
560 MX8MQ_IOMUXC_SD1_DATA2
561 MX8MQ_IOMUXC_SD1_DATA3
562 MX8MQ_IOMUXC_SD1_DATA4
563 MX8MQ_IOMUXC_SD1_DATA5
564 MX8MQ_IOMUXC_SD1_DATA6
565 MX8MQ_IOMUXC_SD1_DATA7
566 >;
567 };
568
569 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
570 fsl,pins = <
571 MX8MQ_IOMUXC_SD1_CLK_U
572 MX8MQ_IOMUXC_SD1_CMD_U
573 MX8MQ_IOMUXC_SD1_DATA0
574 MX8MQ_IOMUXC_SD1_DATA1
575 MX8MQ_IOMUXC_SD1_DATA2
576 MX8MQ_IOMUXC_SD1_DATA3
577 MX8MQ_IOMUXC_SD1_DATA4
578 MX8MQ_IOMUXC_SD1_DATA5
579 MX8MQ_IOMUXC_SD1_DATA6
580 MX8MQ_IOMUXC_SD1_DATA7
581 >;
582 };
583
584 pinctrl_wdog: wdoggrp {
585 fsl,pins = <
586 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_
587 >;
588 };
589 };
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