1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2018 Boundary Devices 3 * Copyright 2018 Boundary Devices
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 #include "imx8mq.dtsi" 9 #include "imx8mq.dtsi"
10 10
11 / { 11 / {
12 model = "Boundary Devices i.MX8MQ Nitr 12 model = "Boundary Devices i.MX8MQ Nitrogen8M";
13 compatible = "boundary,imx8mq-nitrogen 13 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
14 14
15 chosen { 15 chosen {
16 stdout-path = "serial0:115200n 16 stdout-path = "serial0:115200n8";
17 }; 17 };
18 18
19 memory@40000000 { 19 memory@40000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 21 reg = <0x00000000 0x40000000 0 0x80000000>;
22 }; 22 };
23 23
24 gpio-keys { 24 gpio-keys {
25 compatible = "gpio-keys"; 25 compatible = "gpio-keys";
26 pinctrl-names = "default"; 26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_key 27 pinctrl-0 = <&pinctrl_gpio_keys>;
28 28
29 button-power { !! 29 power {
30 label = "Power Button" 30 label = "Power Button";
31 gpios = <&gpio1 7 GPIO 31 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
32 linux,code = <KEY_POWE 32 linux,code = <KEY_POWER>;
33 wakeup-source; 33 wakeup-source;
34 }; 34 };
35 }; 35 };
36 36
37 hdmi-connector { <<
38 compatible = "hdmi-connector"; <<
39 ddc-i2c-bus = <&ddc_i2c_bus>; <<
40 label = "hdmi"; <<
41 type = "a"; <<
42 <<
43 port { <<
44 hdmi_connector_in: end <<
45 remote-endpoin <<
46 }; <<
47 }; <<
48 }; <<
49 <<
50 reg_usb_otg_vbus: regulator-usb-otg-vb <<
51 compatible = "regulator-fixed" <<
52 pinctrl-names = "default"; <<
53 pinctrl-0 = <&pinctrl_reg_usbo <<
54 regulator-name = "usb_otg_vbus <<
55 regulator-min-microvolt = <500 <<
56 regulator-max-microvolt = <500 <<
57 gpio = <&gpio1 12 GPIO_ACTIVE_ <<
58 enable-active-high; <<
59 }; <<
60 <<
61 reg_vref_0v9: regulator-vref-0v9 { 37 reg_vref_0v9: regulator-vref-0v9 {
62 compatible = "regulator-fixed" 38 compatible = "regulator-fixed";
63 regulator-name = "vref-0v9"; 39 regulator-name = "vref-0v9";
64 regulator-min-microvolt = <900 40 regulator-min-microvolt = <900000>;
65 regulator-max-microvolt = <900 41 regulator-max-microvolt = <900000>;
66 }; 42 };
67 43
68 reg_vref_1v8: regulator-vref-1v8 { 44 reg_vref_1v8: regulator-vref-1v8 {
69 compatible = "regulator-fixed" 45 compatible = "regulator-fixed";
70 regulator-name = "vref-1v8"; 46 regulator-name = "vref-1v8";
71 regulator-min-microvolt = <180 47 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <180 48 regulator-max-microvolt = <1800000>;
73 }; 49 };
74 50
75 reg_vref_2v5: regulator-vref-2v5 { 51 reg_vref_2v5: regulator-vref-2v5 {
76 compatible = "regulator-fixed" 52 compatible = "regulator-fixed";
77 regulator-name = "vref-2v5"; 53 regulator-name = "vref-2v5";
78 regulator-min-microvolt = <250 54 regulator-min-microvolt = <2500000>;
79 regulator-max-microvolt = <250 55 regulator-max-microvolt = <2500000>;
80 }; 56 };
81 57
82 reg_vref_3v3: regulator-vref-3v3 { 58 reg_vref_3v3: regulator-vref-3v3 {
83 compatible = "regulator-fixed" 59 compatible = "regulator-fixed";
84 regulator-name = "vref-3v3"; 60 regulator-name = "vref-3v3";
85 regulator-min-microvolt = <330 61 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <330 62 regulator-max-microvolt = <3300000>;
87 }; 63 };
88 64
89 reg_vref_5v: regulator-vref-5v { 65 reg_vref_5v: regulator-vref-5v {
90 compatible = "regulator-fixed" 66 compatible = "regulator-fixed";
91 regulator-name = "vref-5v"; 67 regulator-name = "vref-5v";
92 regulator-min-microvolt = <500 68 regulator-min-microvolt = <5000000>;
93 regulator-max-microvolt = <500 69 regulator-max-microvolt = <5000000>;
94 }; 70 };
95 }; 71 };
96 72
97 &dphy { <<
98 status = "okay"; <<
99 }; <<
100 73
101 &fec1 { 74 &fec1 {
102 pinctrl-names = "default"; 75 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_fec1>; 76 pinctrl-0 = <&pinctrl_fec1>;
104 phy-mode = "rgmii-id"; 77 phy-mode = "rgmii-id";
105 phy-handle = <ðphy0>; 78 phy-handle = <ðphy0>;
106 fsl,magic-packet; 79 fsl,magic-packet;
107 status = "okay"; 80 status = "okay";
108 81
109 mdio { 82 mdio {
110 #address-cells = <1>; 83 #address-cells = <1>;
111 #size-cells = <0>; 84 #size-cells = <0>;
112 85
113 ethphy0: ethernet-phy@4 { 86 ethphy0: ethernet-phy@4 {
114 compatible = "ethernet 87 compatible = "ethernet-phy-ieee802.3-c22";
115 reg = <4>; 88 reg = <4>;
116 interrupts-extended = 89 interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
117 }; 90 };
118 }; 91 };
119 }; 92 };
120 93
121 /* Release reset of the USB Host HUB */ <<
122 &gpio1 { <<
123 usb-host-reset-hog { <<
124 gpio-hog; <<
125 gpios = <14 GPIO_ACTIVE_HIGH>; <<
126 output-high; <<
127 }; <<
128 }; <<
129 <<
130 &i2c1 { 94 &i2c1 {
131 clock-frequency = <400000>; 95 clock-frequency = <400000>;
132 pinctrl-names = "default"; 96 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_i2c1>; 97 pinctrl-0 = <&pinctrl_i2c1>;
134 status = "okay"; 98 status = "okay";
135 99
136 i2c-mux@70 { !! 100 i2cmux@70 {
137 compatible = "nxp,pca9546"; 101 compatible = "nxp,pca9546";
138 pinctrl-names = "default"; 102 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c1_pca 103 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
140 reg = <0x70>; 104 reg = <0x70>;
141 reset-gpios = <&gpio1 8 GPIO_A 105 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
142 #address-cells = <1>; 106 #address-cells = <1>;
143 #size-cells = <0>; 107 #size-cells = <0>;
144 108
145 i2c1a: i2c@0 { !! 109 i2c1a: i2c1@0 {
146 reg = <0>; 110 reg = <0>;
147 #address-cells = <1>; 111 #address-cells = <1>;
148 #size-cells = <0>; 112 #size-cells = <0>;
149 113
150 reg_arm_dram: regulato 114 reg_arm_dram: regulator@60 {
151 compatible = " 115 compatible = "fcs,fan53555";
152 pinctrl-names 116 pinctrl-names = "default";
153 pinctrl-0 = <& 117 pinctrl-0 = <&pinctrl_reg_arm_dram>;
154 reg = <0x60>; 118 reg = <0x60>;
155 regulator-min- !! 119 regulator-min-microvolt = <900000>;
156 regulator-max- 120 regulator-max-microvolt = <1000000>;
157 regulator-alwa 121 regulator-always-on;
158 vsel-gpios = < 122 vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
159 }; 123 };
160 }; 124 };
161 125
162 i2c1b: i2c@1 { !! 126 i2c1b: i2c1@1 {
163 reg = <1>; 127 reg = <1>;
164 #address-cells = <1>; 128 #address-cells = <1>;
165 #size-cells = <0>; 129 #size-cells = <0>;
166 130
167 reg_dram_1p1v: regulat 131 reg_dram_1p1v: regulator@60 {
168 compatible = " 132 compatible = "fcs,fan53555";
169 pinctrl-names 133 pinctrl-names = "default";
170 pinctrl-0 = <& 134 pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
171 reg = <0x60>; 135 reg = <0x60>;
172 regulator-min- 136 regulator-min-microvolt = <1100000>;
173 regulator-max- 137 regulator-max-microvolt = <1100000>;
174 regulator-alwa 138 regulator-always-on;
175 vsel-gpios = < 139 vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
176 }; 140 };
177 }; 141 };
178 142
179 i2c1c: i2c@2 { !! 143 i2c1c: i2c1@2 {
180 reg = <2>; 144 reg = <2>;
181 #address-cells = <1>; 145 #address-cells = <1>;
182 #size-cells = <0>; 146 #size-cells = <0>;
183 147
184 reg_soc_gpu_vpu: regul 148 reg_soc_gpu_vpu: regulator@60 {
185 compatible = " 149 compatible = "fcs,fan53555";
186 pinctrl-names 150 pinctrl-names = "default";
187 pinctrl-0 = <& 151 pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
188 reg = <0x60>; 152 reg = <0x60>;
189 regulator-min- !! 153 regulator-min-microvolt = <900000>;
190 regulator-max- 154 regulator-max-microvolt = <1000000>;
191 regulator-alwa 155 regulator-always-on;
192 vsel-gpios = < 156 vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
193 }; 157 };
194 }; 158 };
195 159
196 i2c1d: i2c@3 { !! 160 i2c1d: i2c1@3 {
197 reg = <3>; 161 reg = <3>;
198 #address-cells = <1>; 162 #address-cells = <1>;
199 #size-cells = <0>; 163 #size-cells = <0>;
200 164
201 rtc@68 { 165 rtc@68 {
202 compatible = " 166 compatible = "microcrystal,rv4162";
203 pinctrl-names 167 pinctrl-names = "default";
204 pinctrl-0 = <& 168 pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
205 reg = <0x68>; 169 reg = <0x68>;
206 interrupts-ext 170 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
207 wakeup-source; 171 wakeup-source;
208 }; 172 };
209 }; 173 };
210 }; 174 };
211 }; 175 };
212 176
213 &i2c4 { <<
214 clock-frequency = <100000>; <<
215 pinctrl-names = "default"; <<
216 pinctrl-0 = <&pinctrl_i2c4>; <<
217 status = "okay"; <<
218 <<
219 pca9546: i2c-mux@70 { <<
220 compatible = "nxp,pca9546"; <<
221 reg = <0x70>; <<
222 #address-cells = <1>; <<
223 #size-cells = <0>; <<
224 <<
225 i2c@0 { <<
226 reg = <0>; <<
227 #address-cells = <1>; <<
228 #size-cells = <0>; <<
229 clock-frequency = <100 <<
230 <<
231 hdmi-bridge@48 { <<
232 compatible = " <<
233 reg = <0x48> ; <<
234 reset-gpios = <<
235 <<
236 ports { <<
237 #addre <<
238 #size- <<
239 <<
240 port@0 <<
241 <<
242 <<
243 <<
244 <<
245 <<
246 <<
247 }; <<
248 <<
249 port@1 <<
250 <<
251 <<
252 <<
253 <<
254 <<
255 }; <<
256 }; <<
257 }; <<
258 }; <<
259 <<
260 ddc_i2c_bus: i2c@1 { <<
261 reg = <1>; <<
262 #address-cells = <1>; <<
263 #size-cells = <0>; <<
264 clock-frequency = <100 <<
265 }; <<
266 <<
267 i2c@3 { <<
268 reg = <3>; <<
269 #address-cells = <1>; <<
270 #size-cells = <0>; <<
271 clock-frequency = <100 <<
272 <<
273 max7323: gpio-expander <<
274 compatible = " <<
275 pinctrl-names <<
276 pinctrl-0 = <& <<
277 gpio-controlle <<
278 reg = <0x68>; <<
279 #gpio-cells = <<
280 }; <<
281 }; <<
282 }; <<
283 }; <<
284 <<
285 &lcdif { <<
286 status = "okay"; <<
287 }; <<
288 <<
289 &mipi_dsi { <<
290 #address-cells = <1>; <<
291 #size-cells = <0>; <<
292 status = "okay"; <<
293 <<
294 ports { <<
295 port@1 { <<
296 reg = <1>; <<
297 <<
298 mipi_dsi_out: endpoint <<
299 remote-endpoin <<
300 }; <<
301 }; <<
302 }; <<
303 }; <<
304 <<
305 &uart1 { /* console */ 177 &uart1 { /* console */
306 pinctrl-names = "default"; 178 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_uart1>; 179 pinctrl-0 = <&pinctrl_uart1>;
308 assigned-clocks = <&clk IMX8MQ_CLK_UAR 180 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
309 assigned-clock-parents = <&clk IMX8MQ_ 181 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
310 status = "okay"; 182 status = "okay";
311 }; 183 };
312 184
313 &uart2 { 185 &uart2 {
314 pinctrl-names = "default"; 186 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_uart2>; 187 pinctrl-0 = <&pinctrl_uart2>;
316 assigned-clocks = <&clk IMX8MQ_CLK_UAR 188 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
317 assigned-clock-parents = <&clk IMX8MQ_ 189 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
318 status = "okay"; 190 status = "okay";
319 }; 191 };
320 192
321 &usb_dwc3_0 { <<
322 dr_mode = "otg"; <<
323 pinctrl-names = "default"; <<
324 pinctrl-0 = <&pinctrl_usb3_0>; <<
325 status = "okay"; <<
326 }; <<
327 <<
328 &usb3_phy0 { <<
329 vbus-supply = <®_usb_otg_vbus>; <<
330 status = "okay"; <<
331 }; <<
332 <<
333 &usb_dwc3_1 { <<
334 dr_mode = "host"; <<
335 status = "okay"; <<
336 }; <<
337 <<
338 &usb3_phy1 { <<
339 pinctrl-names = "default"; <<
340 pinctrl-0 = <&pinctrl_usb3_1>; <<
341 status = "okay"; <<
342 }; <<
343 <<
344 &usdhc1 { 193 &usdhc1 {
345 assigned-clocks = <&clk IMX8MQ_CLK_USD 194 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
346 assigned-clock-rates = <400000000>; 195 assigned-clock-rates = <400000000>;
347 bus-width = <8>; 196 bus-width = <8>;
348 pinctrl-names = "default"; 197 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_usdhc1>; 198 pinctrl-0 = <&pinctrl_usdhc1>;
350 non-removable; 199 non-removable;
351 vmmc-supply = <®_vref_1v8>; 200 vmmc-supply = <®_vref_1v8>;
352 status = "okay"; 201 status = "okay";
353 }; 202 };
354 203
355 &wdog1 { 204 &wdog1 {
356 pinctrl-names = "default"; 205 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_wdog>; 206 pinctrl-0 = <&pinctrl_wdog>;
358 fsl,ext-reset-output; 207 fsl,ext-reset-output;
359 status = "okay"; 208 status = "okay";
360 }; 209 };
361 210
362 &iomuxc { 211 &iomuxc {
363 pinctrl-names = "default"; 212 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_hog>; 213 pinctrl-0 = <&pinctrl_hog>;
365 214
366 pinctrl_hog: hoggrp { 215 pinctrl_hog: hoggrp {
367 fsl,pins = < 216 fsl,pins = <
368 /* J17 connector, odd 217 /* J17 connector, odd */
369 MX8MQ_IOMUXC_SAI1_RXFS 218 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
370 MX8MQ_IOMUXC_SAI1_RXC_ 219 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
371 MX8MQ_IOMUXC_SAI1_RXD1 220 MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
372 MX8MQ_IOMUXC_SAI1_RXD2 221 MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
373 MX8MQ_IOMUXC_SAI1_RXD3 222 MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
374 MX8MQ_IOMUXC_SAI1_RXD4 223 MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
375 MX8MQ_IOMUXC_SAI1_RXD5 224 MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
376 MX8MQ_IOMUXC_SAI1_RXD6 225 MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
377 MX8MQ_IOMUXC_SAI1_RXD7 226 MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
378 MX8MQ_IOMUXC_SAI1_TXD1 227 MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
379 MX8MQ_IOMUXC_SAI1_TXD2 228 MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
380 MX8MQ_IOMUXC_SAI1_TXD3 229 MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
381 MX8MQ_IOMUXC_SAI1_TXD4 230 MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
382 MX8MQ_IOMUXC_SAI1_TXD5 231 MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
383 MX8MQ_IOMUXC_SAI1_TXD6 232 MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
384 MX8MQ_IOMUXC_SAI1_TXD7 233 MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
385 234
386 /* J17 connector, even 235 /* J17 connector, even */
387 MX8MQ_IOMUXC_SAI3_RXFS 236 MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
388 MX8MQ_IOMUXC_SAI3_RXC_ 237 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
389 MX8MQ_IOMUXC_GPIO1_IO1 238 MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
390 MX8MQ_IOMUXC_GPIO1_IO0 239 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
391 MX8MQ_IOMUXC_GPIO1_IO0 240 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
392 241
393 /* J18 connector, odd 242 /* J18 connector, odd */
394 MX8MQ_IOMUXC_NAND_CE3_ 243 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
395 MX8MQ_IOMUXC_NAND_CLE_ 244 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
396 MX8MQ_IOMUXC_NAND_READ 245 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
397 MX8MQ_IOMUXC_NAND_DATA 246 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
398 MX8MQ_IOMUXC_NAND_WP_B 247 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
399 MX8MQ_IOMUXC_NAND_DQS_ 248 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
400 249
401 /* J18 connector, even 250 /* J18 connector, even */
402 MX8MQ_IOMUXC_NAND_ALE_ 251 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
403 MX8MQ_IOMUXC_NAND_CE0_ 252 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
404 MX8MQ_IOMUXC_NAND_DATA 253 MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
405 MX8MQ_IOMUXC_NAND_DATA 254 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
406 MX8MQ_IOMUXC_NAND_DATA 255 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
407 MX8MQ_IOMUXC_NAND_DATA 256 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
408 MX8MQ_IOMUXC_NAND_DATA 257 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
409 258
410 /* J13 Pin 2, WL_WAKE 259 /* J13 Pin 2, WL_WAKE */
411 MX8MQ_IOMUXC_SAI5_RXD2 260 MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
412 /* J13 Pin 4, WL_IRQ, 261 /* J13 Pin 4, WL_IRQ, not needed for Silex */
413 MX8MQ_IOMUXC_SAI5_RXD0 262 MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
414 /* J13 pin 9, unused * 263 /* J13 pin 9, unused */
415 MX8MQ_IOMUXC_SD2_CD_B_ 264 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
416 /* J13 Pin 41, BT_CLK_ 265 /* J13 Pin 41, BT_CLK_REQ */
417 MX8MQ_IOMUXC_SAI5_RXD1 266 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
418 /* J13 Pin 42, BT_HOST 267 /* J13 Pin 42, BT_HOST_WAKE */
419 MX8MQ_IOMUXC_SAI5_MCLK 268 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
420 269
421 /* Clock for both CSI1 270 /* Clock for both CSI1 and CSI2 */
422 MX8MQ_IOMUXC_GPIO1_IO1 271 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
423 /* test points */ 272 /* test points */
424 MX8MQ_IOMUXC_GPIO1_IO0 273 MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
425 >; 274 >;
426 }; 275 };
427 276
428 pinctrl_fec1: fec1grp { 277 pinctrl_fec1: fec1grp {
429 fsl,pins = < 278 fsl,pins = <
430 MX8MQ_IOMUXC_ENET_MDC_ 279 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
431 MX8MQ_IOMUXC_ENET_MDIO 280 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
432 MX8MQ_IOMUXC_ENET_TX_C 281 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
433 MX8MQ_IOMUXC_ENET_TXC_ 282 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
434 MX8MQ_IOMUXC_ENET_TD0_ 283 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
435 MX8MQ_IOMUXC_ENET_TD1_ 284 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
436 MX8MQ_IOMUXC_ENET_TD2_ 285 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
437 MX8MQ_IOMUXC_ENET_TD3_ 286 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
438 MX8MQ_IOMUXC_ENET_RX_C 287 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
439 MX8MQ_IOMUXC_ENET_RXC_ 288 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
440 MX8MQ_IOMUXC_ENET_RD0_ 289 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
441 MX8MQ_IOMUXC_ENET_RD1_ 290 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
442 MX8MQ_IOMUXC_ENET_RD2_ 291 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
443 MX8MQ_IOMUXC_ENET_RD3_ 292 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
444 MX8MQ_IOMUXC_GPIO1_IO0 293 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
445 MX8MQ_IOMUXC_GPIO1_IO1 294 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
446 >; 295 >;
447 }; 296 };
448 297
449 pinctrl_gpio_keys: gpio-keysgrp { 298 pinctrl_gpio_keys: gpio-keysgrp {
450 fsl,pins = < 299 fsl,pins = <
451 MX8MQ_IOMUXC_GPIO1_IO0 300 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
452 >; 301 >;
453 }; 302 };
454 303
455 304
456 pinctrl_i2c1: i2c1grp { 305 pinctrl_i2c1: i2c1grp {
457 fsl,pins = < 306 fsl,pins = <
458 MX8MQ_IOMUXC_I2C1_SCL_ 307 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
459 MX8MQ_IOMUXC_I2C1_SDA_ 308 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
460 >; 309 >;
461 }; 310 };
462 311
463 pinctrl_i2c1_pca9546: i2c1-pca9546grp 312 pinctrl_i2c1_pca9546: i2c1-pca9546grp {
464 fsl,pins = < 313 fsl,pins = <
465 MX8MQ_IOMUXC_GPIO1_IO0 314 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
466 >; 315 >;
467 }; 316 };
468 317
469 pinctrl_i2c1d_rv4162: i2c1d-rv4162grp 318 pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
470 fsl,pins = < 319 fsl,pins = <
471 MX8MQ_IOMUXC_GPIO1_IO0 320 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
472 >; 321 >;
473 }; 322 };
474 323
475 pinctrl_i2c4: i2c4grp { <<
476 fsl,pins = < <<
477 MX8MQ_IOMUXC_I2C4_SCL_ <<
478 MX8MQ_IOMUXC_I2C4_SDA_ <<
479 >; <<
480 }; <<
481 <<
482 pinctrl_max7323: max7323grp { <<
483 fsl,pins = < <<
484 MX8MQ_IOMUXC_NAND_RE_B <<
485 >; <<
486 }; <<
487 <<
488 pinctrl_reg_arm_dram: reg-arm-dramgrp 324 pinctrl_reg_arm_dram: reg-arm-dramgrp {
489 fsl,pins = < 325 fsl,pins = <
490 MX8MQ_IOMUXC_SAI5_RXD3 326 MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
491 >; 327 >;
492 }; 328 };
493 329
494 pinctrl_reg_dram_1p1v: reg-dram-1p1vgr 330 pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
495 fsl,pins = < 331 fsl,pins = <
496 MX8MQ_IOMUXC_SD1_STROB 332 MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
497 >; 333 >;
498 }; 334 };
499 335
500 pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-v 336 pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
501 fsl,pins = < 337 fsl,pins = <
502 MX8MQ_IOMUXC_SD2_WP_GP 338 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
503 >; 339 >;
504 }; 340 };
505 341
506 pinctrl_reg_usbotg_vbus: reg-usbotg-vb <<
507 fsl,pins = < <<
508 MX8MQ_IOMUXC_GPIO1_IO1 <<
509 >; <<
510 }; <<
511 <<
512 pinctrl_uart1: uart1grp { 342 pinctrl_uart1: uart1grp {
513 fsl,pins = < 343 fsl,pins = <
514 MX8MQ_IOMUXC_UART1_RXD 344 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
515 MX8MQ_IOMUXC_UART1_TXD 345 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
516 >; 346 >;
517 }; 347 };
518 348
519 pinctrl_uart2: uart2grp { 349 pinctrl_uart2: uart2grp {
520 fsl,pins = < 350 fsl,pins = <
521 MX8MQ_IOMUXC_UART2_RXD 351 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
522 MX8MQ_IOMUXC_UART2_TXD 352 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
523 >; <<
524 }; <<
525 <<
526 pinctrl_usb3_0: usb3-0grp { <<
527 fsl,pins = < <<
528 MX8MQ_IOMUXC_GPIO1_IO1 <<
529 >; <<
530 }; <<
531 <<
532 pinctrl_usb3_1: usb3-1grp { <<
533 fsl,pins = < <<
534 MX8MQ_IOMUXC_GPIO1_IO1 <<
535 >; 353 >;
536 }; 354 };
537 355
538 pinctrl_usdhc1: usdhc1grp { 356 pinctrl_usdhc1: usdhc1grp {
539 fsl,pins = < 357 fsl,pins = <
540 MX8MQ_IOMUXC_SD1_CLK_U 358 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
541 MX8MQ_IOMUXC_SD1_CMD_U 359 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
542 MX8MQ_IOMUXC_SD1_DATA0 360 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
543 MX8MQ_IOMUXC_SD1_DATA1 361 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
544 MX8MQ_IOMUXC_SD1_DATA2 362 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
545 MX8MQ_IOMUXC_SD1_DATA3 363 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
546 MX8MQ_IOMUXC_SD1_DATA4 364 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
547 MX8MQ_IOMUXC_SD1_DATA5 365 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
548 MX8MQ_IOMUXC_SD1_DATA6 366 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
549 MX8MQ_IOMUXC_SD1_DATA7 367 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
550 MX8MQ_IOMUXC_SD1_RESET 368 MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
551 >; 369 >;
552 }; 370 };
553 371
554 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 372 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
555 fsl,pins = < 373 fsl,pins = <
556 MX8MQ_IOMUXC_SD1_CLK_U 374 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
557 MX8MQ_IOMUXC_SD1_CMD_U 375 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
558 MX8MQ_IOMUXC_SD1_DATA0 376 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
559 MX8MQ_IOMUXC_SD1_DATA1 377 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
560 MX8MQ_IOMUXC_SD1_DATA2 378 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
561 MX8MQ_IOMUXC_SD1_DATA3 379 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
562 MX8MQ_IOMUXC_SD1_DATA4 380 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
563 MX8MQ_IOMUXC_SD1_DATA5 381 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
564 MX8MQ_IOMUXC_SD1_DATA6 382 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
565 MX8MQ_IOMUXC_SD1_DATA7 383 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
566 >; 384 >;
567 }; 385 };
568 386
569 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 387 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
570 fsl,pins = < 388 fsl,pins = <
571 MX8MQ_IOMUXC_SD1_CLK_U 389 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
572 MX8MQ_IOMUXC_SD1_CMD_U 390 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
573 MX8MQ_IOMUXC_SD1_DATA0 391 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
574 MX8MQ_IOMUXC_SD1_DATA1 392 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
575 MX8MQ_IOMUXC_SD1_DATA2 393 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
576 MX8MQ_IOMUXC_SD1_DATA3 394 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
577 MX8MQ_IOMUXC_SD1_DATA4 395 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
578 MX8MQ_IOMUXC_SD1_DATA5 396 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
579 MX8MQ_IOMUXC_SD1_DATA6 397 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
580 MX8MQ_IOMUXC_SD1_DATA7 398 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
581 >; 399 >;
582 }; 400 };
583 401
584 pinctrl_wdog: wdoggrp { 402 pinctrl_wdog: wdoggrp {
585 fsl,pins = < 403 fsl,pins = <
586 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_ 404 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
587 >; 405 >;
588 }; 406 };
589 }; 407 };
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