1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /* 2 /*
3 * Copyright 2018 Boundary Devices 3 * Copyright 2018 Boundary Devices
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include <dt-bindings/input/input.h> 8 #include <dt-bindings/input/input.h>
9 #include "imx8mq.dtsi" 9 #include "imx8mq.dtsi"
10 10
11 / { 11 / {
12 model = "Boundary Devices i.MX8MQ Nitr 12 model = "Boundary Devices i.MX8MQ Nitrogen8M";
13 compatible = "boundary,imx8mq-nitrogen 13 compatible = "boundary,imx8mq-nitrogen8m", "fsl,imx8mq";
14 14
15 chosen { 15 chosen {
16 stdout-path = "serial0:115200n 16 stdout-path = "serial0:115200n8";
17 }; 17 };
18 18
19 memory@40000000 { 19 memory@40000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 21 reg = <0x00000000 0x40000000 0 0x80000000>;
22 }; 22 };
23 23
24 gpio-keys { 24 gpio-keys {
25 compatible = "gpio-keys"; 25 compatible = "gpio-keys";
26 pinctrl-names = "default"; 26 pinctrl-names = "default";
27 pinctrl-0 = <&pinctrl_gpio_key 27 pinctrl-0 = <&pinctrl_gpio_keys>;
28 28
29 button-power { 29 button-power {
30 label = "Power Button" 30 label = "Power Button";
31 gpios = <&gpio1 7 GPIO 31 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
32 linux,code = <KEY_POWE 32 linux,code = <KEY_POWER>;
33 wakeup-source; 33 wakeup-source;
34 }; 34 };
35 }; 35 };
36 36
37 hdmi-connector { 37 hdmi-connector {
38 compatible = "hdmi-connector"; 38 compatible = "hdmi-connector";
39 ddc-i2c-bus = <&ddc_i2c_bus>; 39 ddc-i2c-bus = <&ddc_i2c_bus>;
40 label = "hdmi"; 40 label = "hdmi";
41 type = "a"; 41 type = "a";
42 42
43 port { 43 port {
44 hdmi_connector_in: end 44 hdmi_connector_in: endpoint {
45 remote-endpoin 45 remote-endpoint = <<8912_out>;
46 }; 46 };
47 }; 47 };
48 }; 48 };
49 49
50 reg_usb_otg_vbus: regulator-usb-otg-vb 50 reg_usb_otg_vbus: regulator-usb-otg-vbus {
51 compatible = "regulator-fixed" 51 compatible = "regulator-fixed";
52 pinctrl-names = "default"; 52 pinctrl-names = "default";
53 pinctrl-0 = <&pinctrl_reg_usbo 53 pinctrl-0 = <&pinctrl_reg_usbotg_vbus>;
54 regulator-name = "usb_otg_vbus 54 regulator-name = "usb_otg_vbus";
55 regulator-min-microvolt = <500 55 regulator-min-microvolt = <5000000>;
56 regulator-max-microvolt = <500 56 regulator-max-microvolt = <5000000>;
57 gpio = <&gpio1 12 GPIO_ACTIVE_ 57 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
58 enable-active-high; 58 enable-active-high;
59 }; 59 };
60 60
61 reg_vref_0v9: regulator-vref-0v9 { 61 reg_vref_0v9: regulator-vref-0v9 {
62 compatible = "regulator-fixed" 62 compatible = "regulator-fixed";
63 regulator-name = "vref-0v9"; 63 regulator-name = "vref-0v9";
64 regulator-min-microvolt = <900 64 regulator-min-microvolt = <900000>;
65 regulator-max-microvolt = <900 65 regulator-max-microvolt = <900000>;
66 }; 66 };
67 67
68 reg_vref_1v8: regulator-vref-1v8 { 68 reg_vref_1v8: regulator-vref-1v8 {
69 compatible = "regulator-fixed" 69 compatible = "regulator-fixed";
70 regulator-name = "vref-1v8"; 70 regulator-name = "vref-1v8";
71 regulator-min-microvolt = <180 71 regulator-min-microvolt = <1800000>;
72 regulator-max-microvolt = <180 72 regulator-max-microvolt = <1800000>;
73 }; 73 };
74 74
75 reg_vref_2v5: regulator-vref-2v5 { 75 reg_vref_2v5: regulator-vref-2v5 {
76 compatible = "regulator-fixed" 76 compatible = "regulator-fixed";
77 regulator-name = "vref-2v5"; 77 regulator-name = "vref-2v5";
78 regulator-min-microvolt = <250 78 regulator-min-microvolt = <2500000>;
79 regulator-max-microvolt = <250 79 regulator-max-microvolt = <2500000>;
80 }; 80 };
81 81
82 reg_vref_3v3: regulator-vref-3v3 { 82 reg_vref_3v3: regulator-vref-3v3 {
83 compatible = "regulator-fixed" 83 compatible = "regulator-fixed";
84 regulator-name = "vref-3v3"; 84 regulator-name = "vref-3v3";
85 regulator-min-microvolt = <330 85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <330 86 regulator-max-microvolt = <3300000>;
87 }; 87 };
88 88
89 reg_vref_5v: regulator-vref-5v { 89 reg_vref_5v: regulator-vref-5v {
90 compatible = "regulator-fixed" 90 compatible = "regulator-fixed";
91 regulator-name = "vref-5v"; 91 regulator-name = "vref-5v";
92 regulator-min-microvolt = <500 92 regulator-min-microvolt = <5000000>;
93 regulator-max-microvolt = <500 93 regulator-max-microvolt = <5000000>;
94 }; 94 };
95 }; 95 };
96 96
97 &dphy { 97 &dphy {
98 status = "okay"; 98 status = "okay";
99 }; 99 };
100 100
101 &fec1 { 101 &fec1 {
102 pinctrl-names = "default"; 102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_fec1>; 103 pinctrl-0 = <&pinctrl_fec1>;
104 phy-mode = "rgmii-id"; 104 phy-mode = "rgmii-id";
105 phy-handle = <ðphy0>; 105 phy-handle = <ðphy0>;
106 fsl,magic-packet; 106 fsl,magic-packet;
107 status = "okay"; 107 status = "okay";
108 108
109 mdio { 109 mdio {
110 #address-cells = <1>; 110 #address-cells = <1>;
111 #size-cells = <0>; 111 #size-cells = <0>;
112 112
113 ethphy0: ethernet-phy@4 { 113 ethphy0: ethernet-phy@4 {
114 compatible = "ethernet 114 compatible = "ethernet-phy-ieee802.3-c22";
115 reg = <4>; 115 reg = <4>;
116 interrupts-extended = 116 interrupts-extended = <&gpio1 11 IRQ_TYPE_LEVEL_LOW>;
117 }; 117 };
118 }; 118 };
119 }; 119 };
120 120
121 /* Release reset of the USB Host HUB */ 121 /* Release reset of the USB Host HUB */
122 &gpio1 { 122 &gpio1 {
123 usb-host-reset-hog { 123 usb-host-reset-hog {
124 gpio-hog; 124 gpio-hog;
125 gpios = <14 GPIO_ACTIVE_HIGH>; 125 gpios = <14 GPIO_ACTIVE_HIGH>;
126 output-high; 126 output-high;
127 }; 127 };
128 }; 128 };
129 129
130 &i2c1 { 130 &i2c1 {
131 clock-frequency = <400000>; 131 clock-frequency = <400000>;
132 pinctrl-names = "default"; 132 pinctrl-names = "default";
133 pinctrl-0 = <&pinctrl_i2c1>; 133 pinctrl-0 = <&pinctrl_i2c1>;
134 status = "okay"; 134 status = "okay";
135 135
136 i2c-mux@70 { 136 i2c-mux@70 {
137 compatible = "nxp,pca9546"; 137 compatible = "nxp,pca9546";
138 pinctrl-names = "default"; 138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c1_pca 139 pinctrl-0 = <&pinctrl_i2c1_pca9546>;
140 reg = <0x70>; 140 reg = <0x70>;
141 reset-gpios = <&gpio1 8 GPIO_A 141 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
142 #address-cells = <1>; 142 #address-cells = <1>;
143 #size-cells = <0>; 143 #size-cells = <0>;
144 144
145 i2c1a: i2c@0 { 145 i2c1a: i2c@0 {
146 reg = <0>; 146 reg = <0>;
147 #address-cells = <1>; 147 #address-cells = <1>;
148 #size-cells = <0>; 148 #size-cells = <0>;
149 149
150 reg_arm_dram: regulato 150 reg_arm_dram: regulator@60 {
151 compatible = " 151 compatible = "fcs,fan53555";
152 pinctrl-names 152 pinctrl-names = "default";
153 pinctrl-0 = <& 153 pinctrl-0 = <&pinctrl_reg_arm_dram>;
154 reg = <0x60>; 154 reg = <0x60>;
155 regulator-min- 155 regulator-min-microvolt = <900000>;
156 regulator-max- 156 regulator-max-microvolt = <1000000>;
157 regulator-alwa 157 regulator-always-on;
158 vsel-gpios = < 158 vsel-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
159 }; 159 };
160 }; 160 };
161 161
162 i2c1b: i2c@1 { 162 i2c1b: i2c@1 {
163 reg = <1>; 163 reg = <1>;
164 #address-cells = <1>; 164 #address-cells = <1>;
165 #size-cells = <0>; 165 #size-cells = <0>;
166 166
167 reg_dram_1p1v: regulat 167 reg_dram_1p1v: regulator@60 {
168 compatible = " 168 compatible = "fcs,fan53555";
169 pinctrl-names 169 pinctrl-names = "default";
170 pinctrl-0 = <& 170 pinctrl-0 = <&pinctrl_reg_dram_1p1v>;
171 reg = <0x60>; 171 reg = <0x60>;
172 regulator-min- 172 regulator-min-microvolt = <1100000>;
173 regulator-max- 173 regulator-max-microvolt = <1100000>;
174 regulator-alwa 174 regulator-always-on;
175 vsel-gpios = < 175 vsel-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>;
176 }; 176 };
177 }; 177 };
178 178
179 i2c1c: i2c@2 { 179 i2c1c: i2c@2 {
180 reg = <2>; 180 reg = <2>;
181 #address-cells = <1>; 181 #address-cells = <1>;
182 #size-cells = <0>; 182 #size-cells = <0>;
183 183
184 reg_soc_gpu_vpu: regul 184 reg_soc_gpu_vpu: regulator@60 {
185 compatible = " 185 compatible = "fcs,fan53555";
186 pinctrl-names 186 pinctrl-names = "default";
187 pinctrl-0 = <& 187 pinctrl-0 = <&pinctrl_reg_soc_gpu_vpu>;
188 reg = <0x60>; 188 reg = <0x60>;
189 regulator-min- 189 regulator-min-microvolt = <900000>;
190 regulator-max- 190 regulator-max-microvolt = <1000000>;
191 regulator-alwa 191 regulator-always-on;
192 vsel-gpios = < 192 vsel-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>;
193 }; 193 };
194 }; 194 };
195 195
196 i2c1d: i2c@3 { 196 i2c1d: i2c@3 {
197 reg = <3>; 197 reg = <3>;
198 #address-cells = <1>; 198 #address-cells = <1>;
199 #size-cells = <0>; 199 #size-cells = <0>;
200 200
201 rtc@68 { 201 rtc@68 {
202 compatible = " 202 compatible = "microcrystal,rv4162";
203 pinctrl-names 203 pinctrl-names = "default";
204 pinctrl-0 = <& 204 pinctrl-0 = <&pinctrl_i2c1d_rv4162>;
205 reg = <0x68>; 205 reg = <0x68>;
206 interrupts-ext 206 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_LOW>;
207 wakeup-source; 207 wakeup-source;
208 }; 208 };
209 }; 209 };
210 }; 210 };
211 }; 211 };
212 212
213 &i2c4 { 213 &i2c4 {
214 clock-frequency = <100000>; 214 clock-frequency = <100000>;
215 pinctrl-names = "default"; 215 pinctrl-names = "default";
216 pinctrl-0 = <&pinctrl_i2c4>; 216 pinctrl-0 = <&pinctrl_i2c4>;
217 status = "okay"; 217 status = "okay";
218 218
219 pca9546: i2c-mux@70 { 219 pca9546: i2c-mux@70 {
220 compatible = "nxp,pca9546"; 220 compatible = "nxp,pca9546";
221 reg = <0x70>; 221 reg = <0x70>;
222 #address-cells = <1>; 222 #address-cells = <1>;
223 #size-cells = <0>; 223 #size-cells = <0>;
224 224
225 i2c@0 { 225 i2c@0 {
226 reg = <0>; 226 reg = <0>;
227 #address-cells = <1>; 227 #address-cells = <1>;
228 #size-cells = <0>; 228 #size-cells = <0>;
229 clock-frequency = <100 229 clock-frequency = <100000>;
230 230
231 hdmi-bridge@48 { 231 hdmi-bridge@48 {
232 compatible = " 232 compatible = "lontium,lt8912b";
233 reg = <0x48> ; 233 reg = <0x48> ;
234 reset-gpios = 234 reset-gpios = <&max7323 0 GPIO_ACTIVE_LOW>;
235 235
236 ports { 236 ports {
237 #addre 237 #address-cells = <1>;
238 #size- 238 #size-cells = <0>;
239 239
240 port@0 240 port@0 {
241 241 reg = <0>;
242 242
243 243 hdmi_out_in: endpoint {
244 244 data-lanes = <1 2 3 4>;
245 245 remote-endpoint = <&mipi_dsi_out>;
246 246 };
247 }; 247 };
248 248
249 port@1 249 port@1 {
250 250 reg = <1>;
251 251
252 252 lt8912_out: endpoint {
253 253 remote-endpoint = <&hdmi_connector_in>;
254 254 };
255 }; 255 };
256 }; 256 };
257 }; 257 };
258 }; 258 };
259 259
260 ddc_i2c_bus: i2c@1 { 260 ddc_i2c_bus: i2c@1 {
261 reg = <1>; 261 reg = <1>;
262 #address-cells = <1>; 262 #address-cells = <1>;
263 #size-cells = <0>; 263 #size-cells = <0>;
264 clock-frequency = <100 264 clock-frequency = <100000>;
265 }; 265 };
266 266
267 i2c@3 { 267 i2c@3 {
268 reg = <3>; 268 reg = <3>;
269 #address-cells = <1>; 269 #address-cells = <1>;
270 #size-cells = <0>; 270 #size-cells = <0>;
271 clock-frequency = <100 271 clock-frequency = <100000>;
272 272
273 max7323: gpio-expander 273 max7323: gpio-expander@68 {
274 compatible = " 274 compatible = "maxim,max7323";
275 pinctrl-names 275 pinctrl-names = "default";
276 pinctrl-0 = <& 276 pinctrl-0 = <&pinctrl_max7323>;
277 gpio-controlle 277 gpio-controller;
278 reg = <0x68>; 278 reg = <0x68>;
279 #gpio-cells = 279 #gpio-cells = <2>;
280 }; 280 };
281 }; 281 };
282 }; 282 };
283 }; 283 };
284 284
285 &lcdif { 285 &lcdif {
286 status = "okay"; 286 status = "okay";
287 }; 287 };
288 288
289 &mipi_dsi { 289 &mipi_dsi {
290 #address-cells = <1>; 290 #address-cells = <1>;
291 #size-cells = <0>; 291 #size-cells = <0>;
292 status = "okay"; 292 status = "okay";
293 293
294 ports { 294 ports {
295 port@1 { 295 port@1 {
296 reg = <1>; 296 reg = <1>;
297 297
298 mipi_dsi_out: endpoint 298 mipi_dsi_out: endpoint {
299 remote-endpoin 299 remote-endpoint = <&hdmi_out_in>;
300 }; 300 };
301 }; 301 };
302 }; 302 };
303 }; 303 };
304 304
305 &uart1 { /* console */ 305 &uart1 { /* console */
306 pinctrl-names = "default"; 306 pinctrl-names = "default";
307 pinctrl-0 = <&pinctrl_uart1>; 307 pinctrl-0 = <&pinctrl_uart1>;
308 assigned-clocks = <&clk IMX8MQ_CLK_UAR 308 assigned-clocks = <&clk IMX8MQ_CLK_UART1>;
309 assigned-clock-parents = <&clk IMX8MQ_ 309 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
310 status = "okay"; 310 status = "okay";
311 }; 311 };
312 312
313 &uart2 { 313 &uart2 {
314 pinctrl-names = "default"; 314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_uart2>; 315 pinctrl-0 = <&pinctrl_uart2>;
316 assigned-clocks = <&clk IMX8MQ_CLK_UAR 316 assigned-clocks = <&clk IMX8MQ_CLK_UART2>;
317 assigned-clock-parents = <&clk IMX8MQ_ 317 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
318 status = "okay"; 318 status = "okay";
319 }; 319 };
320 320
321 &usb_dwc3_0 { 321 &usb_dwc3_0 {
322 dr_mode = "otg"; 322 dr_mode = "otg";
323 pinctrl-names = "default"; 323 pinctrl-names = "default";
324 pinctrl-0 = <&pinctrl_usb3_0>; 324 pinctrl-0 = <&pinctrl_usb3_0>;
325 status = "okay"; 325 status = "okay";
326 }; 326 };
327 327
328 &usb3_phy0 { 328 &usb3_phy0 {
329 vbus-supply = <®_usb_otg_vbus>; 329 vbus-supply = <®_usb_otg_vbus>;
330 status = "okay"; 330 status = "okay";
331 }; 331 };
332 332
333 &usb_dwc3_1 { 333 &usb_dwc3_1 {
334 dr_mode = "host"; 334 dr_mode = "host";
335 status = "okay"; 335 status = "okay";
336 }; 336 };
337 337
338 &usb3_phy1 { 338 &usb3_phy1 {
339 pinctrl-names = "default"; 339 pinctrl-names = "default";
340 pinctrl-0 = <&pinctrl_usb3_1>; 340 pinctrl-0 = <&pinctrl_usb3_1>;
341 status = "okay"; 341 status = "okay";
342 }; 342 };
343 343
344 &usdhc1 { 344 &usdhc1 {
345 assigned-clocks = <&clk IMX8MQ_CLK_USD 345 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
346 assigned-clock-rates = <400000000>; 346 assigned-clock-rates = <400000000>;
347 bus-width = <8>; 347 bus-width = <8>;
348 pinctrl-names = "default"; 348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_usdhc1>; 349 pinctrl-0 = <&pinctrl_usdhc1>;
350 non-removable; 350 non-removable;
351 vmmc-supply = <®_vref_1v8>; 351 vmmc-supply = <®_vref_1v8>;
352 status = "okay"; 352 status = "okay";
353 }; 353 };
354 354
355 &wdog1 { 355 &wdog1 {
356 pinctrl-names = "default"; 356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_wdog>; 357 pinctrl-0 = <&pinctrl_wdog>;
358 fsl,ext-reset-output; 358 fsl,ext-reset-output;
359 status = "okay"; 359 status = "okay";
360 }; 360 };
361 361
362 &iomuxc { 362 &iomuxc {
363 pinctrl-names = "default"; 363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_hog>; 364 pinctrl-0 = <&pinctrl_hog>;
365 365
366 pinctrl_hog: hoggrp { 366 pinctrl_hog: hoggrp {
367 fsl,pins = < 367 fsl,pins = <
368 /* J17 connector, odd 368 /* J17 connector, odd */
369 MX8MQ_IOMUXC_SAI1_RXFS 369 MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0 0x19 /* Pin 19 */
370 MX8MQ_IOMUXC_SAI1_RXC_ 370 MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1 0x19 /* Pin 21 */
371 MX8MQ_IOMUXC_SAI1_RXD1 371 MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x19 /* Pin 23 */
372 MX8MQ_IOMUXC_SAI1_RXD2 372 MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x19 /* Pin 25 */
373 MX8MQ_IOMUXC_SAI1_RXD3 373 MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x19 /* Pin 27 */
374 MX8MQ_IOMUXC_SAI1_RXD4 374 MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6 0x19 /* Pin 29 */
375 MX8MQ_IOMUXC_SAI1_RXD5 375 MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x19 /* Pin 31 */
376 MX8MQ_IOMUXC_SAI1_RXD6 376 MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8 0x19 /* Pin 33 */
377 MX8MQ_IOMUXC_SAI1_RXD7 377 MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9 0x19 /* Pin 35 */
378 MX8MQ_IOMUXC_SAI1_TXD1 378 MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13 0x19 /* Pin 39 */
379 MX8MQ_IOMUXC_SAI1_TXD2 379 MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14 0x19 /* Pin 41 */
380 MX8MQ_IOMUXC_SAI1_TXD3 380 MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15 0x19 /* Pin 43 */
381 MX8MQ_IOMUXC_SAI1_TXD4 381 MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16 0x19 /* Pin 45 */
382 MX8MQ_IOMUXC_SAI1_TXD5 382 MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17 0x19 /* Pin 47 */
383 MX8MQ_IOMUXC_SAI1_TXD6 383 MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18 0x19 /* Pin 49 */
384 MX8MQ_IOMUXC_SAI1_TXD7 384 MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19 0x19 /* Pin 51 */
385 385
386 /* J17 connector, even 386 /* J17 connector, even */
387 MX8MQ_IOMUXC_SAI3_RXFS 387 MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x19 /* Pin 44 */
388 MX8MQ_IOMUXC_SAI3_RXC_ 388 MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 /* Pin 48 */
389 MX8MQ_IOMUXC_GPIO1_IO1 389 MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x19 /* Pin 50 */
390 MX8MQ_IOMUXC_GPIO1_IO0 390 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 /* Pin 54 */
391 MX8MQ_IOMUXC_GPIO1_IO0 391 MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 /* Pin 56 */
392 392
393 /* J18 connector, odd 393 /* J18 connector, odd */
394 MX8MQ_IOMUXC_NAND_CE3_ 394 MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 /* Pin 41 */
395 MX8MQ_IOMUXC_NAND_CLE_ 395 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 /* Pin 43 */
396 MX8MQ_IOMUXC_NAND_READ 396 MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 /* Pin 45 */
397 MX8MQ_IOMUXC_NAND_DATA 397 MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11 0x19 /* Pin 47 */
398 MX8MQ_IOMUXC_NAND_WP_B 398 MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 /* Pin 49 */
399 MX8MQ_IOMUXC_NAND_DQS_ 399 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* Pin 53 */
400 400
401 /* J18 connector, even 401 /* J18 connector, even */
402 MX8MQ_IOMUXC_NAND_ALE_ 402 MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0 0x19 /* Pin 32 */
403 MX8MQ_IOMUXC_NAND_CE0_ 403 MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x19 /* Pin 36 */
404 MX8MQ_IOMUXC_NAND_DATA 404 MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6 0x19 /* Pin 38 */
405 MX8MQ_IOMUXC_NAND_DATA 405 MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7 0x19 /* Pin 40 */
406 MX8MQ_IOMUXC_NAND_DATA 406 MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8 0x19 /* Pin 42 */
407 MX8MQ_IOMUXC_NAND_DATA 407 MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9 0x19 /* Pin 44 */
408 MX8MQ_IOMUXC_NAND_DATA 408 MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10 0x19 /* Pin 46 */
409 409
410 /* J13 Pin 2, WL_WAKE 410 /* J13 Pin 2, WL_WAKE */
411 MX8MQ_IOMUXC_SAI5_RXD2 411 MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xd6
412 /* J13 Pin 4, WL_IRQ, 412 /* J13 Pin 4, WL_IRQ, not needed for Silex */
413 MX8MQ_IOMUXC_SAI5_RXD0 413 MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21 0xd6
414 /* J13 pin 9, unused * 414 /* J13 pin 9, unused */
415 MX8MQ_IOMUXC_SD2_CD_B_ 415 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x19
416 /* J13 Pin 41, BT_CLK_ 416 /* J13 Pin 41, BT_CLK_REQ */
417 MX8MQ_IOMUXC_SAI5_RXD1 417 MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22 0xd6
418 /* J13 Pin 42, BT_HOST 418 /* J13 Pin 42, BT_HOST_WAKE */
419 MX8MQ_IOMUXC_SAI5_MCLK 419 MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25 0xd6
420 420
421 /* Clock for both CSI1 421 /* Clock for both CSI1 and CSI2 */
422 MX8MQ_IOMUXC_GPIO1_IO1 422 MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x07
423 /* test points */ 423 /* test points */
424 MX8MQ_IOMUXC_GPIO1_IO0 424 MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4 0xc1 /* TP87 */
425 >; 425 >;
426 }; 426 };
427 427
428 pinctrl_fec1: fec1grp { 428 pinctrl_fec1: fec1grp {
429 fsl,pins = < 429 fsl,pins = <
430 MX8MQ_IOMUXC_ENET_MDC_ 430 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
431 MX8MQ_IOMUXC_ENET_MDIO 431 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
432 MX8MQ_IOMUXC_ENET_TX_C 432 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
433 MX8MQ_IOMUXC_ENET_TXC_ 433 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
434 MX8MQ_IOMUXC_ENET_TD0_ 434 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
435 MX8MQ_IOMUXC_ENET_TD1_ 435 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
436 MX8MQ_IOMUXC_ENET_TD2_ 436 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
437 MX8MQ_IOMUXC_ENET_TD3_ 437 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
438 MX8MQ_IOMUXC_ENET_RX_C 438 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
439 MX8MQ_IOMUXC_ENET_RXC_ 439 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
440 MX8MQ_IOMUXC_ENET_RD0_ 440 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
441 MX8MQ_IOMUXC_ENET_RD1_ 441 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
442 MX8MQ_IOMUXC_ENET_RD2_ 442 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
443 MX8MQ_IOMUXC_ENET_RD3_ 443 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
444 MX8MQ_IOMUXC_GPIO1_IO0 444 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
445 MX8MQ_IOMUXC_GPIO1_IO1 445 MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59
446 >; 446 >;
447 }; 447 };
448 448
449 pinctrl_gpio_keys: gpio-keysgrp { 449 pinctrl_gpio_keys: gpio-keysgrp {
450 fsl,pins = < 450 fsl,pins = <
451 MX8MQ_IOMUXC_GPIO1_IO0 451 MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x19
452 >; 452 >;
453 }; 453 };
454 454
455 455
456 pinctrl_i2c1: i2c1grp { 456 pinctrl_i2c1: i2c1grp {
457 fsl,pins = < 457 fsl,pins = <
458 MX8MQ_IOMUXC_I2C1_SCL_ 458 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
459 MX8MQ_IOMUXC_I2C1_SDA_ 459 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
460 >; 460 >;
461 }; 461 };
462 462
463 pinctrl_i2c1_pca9546: i2c1-pca9546grp 463 pinctrl_i2c1_pca9546: i2c1-pca9546grp {
464 fsl,pins = < 464 fsl,pins = <
465 MX8MQ_IOMUXC_GPIO1_IO0 465 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49
466 >; 466 >;
467 }; 467 };
468 468
469 pinctrl_i2c1d_rv4162: i2c1d-rv4162grp 469 pinctrl_i2c1d_rv4162: i2c1d-rv4162grp {
470 fsl,pins = < 470 fsl,pins = <
471 MX8MQ_IOMUXC_GPIO1_IO0 471 MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x49
472 >; 472 >;
473 }; 473 };
474 474
475 pinctrl_i2c4: i2c4grp { 475 pinctrl_i2c4: i2c4grp {
476 fsl,pins = < 476 fsl,pins = <
477 MX8MQ_IOMUXC_I2C4_SCL_ 477 MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL 0x4000007f
478 MX8MQ_IOMUXC_I2C4_SDA_ 478 MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA 0x4000007f
479 >; 479 >;
480 }; 480 };
481 481
482 pinctrl_max7323: max7323grp { 482 pinctrl_max7323: max7323grp {
483 fsl,pins = < 483 fsl,pins = <
484 MX8MQ_IOMUXC_NAND_RE_B 484 MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x19
485 >; 485 >;
486 }; 486 };
487 487
488 pinctrl_reg_arm_dram: reg-arm-dramgrp 488 pinctrl_reg_arm_dram: reg-arm-dramgrp {
489 fsl,pins = < 489 fsl,pins = <
490 MX8MQ_IOMUXC_SAI5_RXD3 490 MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24 0x16
491 >; 491 >;
492 }; 492 };
493 493
494 pinctrl_reg_dram_1p1v: reg-dram-1p1vgr 494 pinctrl_reg_dram_1p1v: reg-dram-1p1vgrp {
495 fsl,pins = < 495 fsl,pins = <
496 MX8MQ_IOMUXC_SD1_STROB 496 MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11 0x16
497 >; 497 >;
498 }; 498 };
499 499
500 pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-v 500 pinctrl_reg_soc_gpu_vpu: reg-soc-gpu-vpugrp {
501 fsl,pins = < 501 fsl,pins = <
502 MX8MQ_IOMUXC_SD2_WP_GP 502 MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x16
503 >; 503 >;
504 }; 504 };
505 505
506 pinctrl_reg_usbotg_vbus: reg-usbotg-vb 506 pinctrl_reg_usbotg_vbus: reg-usbotg-vbusgrp {
507 fsl,pins = < 507 fsl,pins = <
508 MX8MQ_IOMUXC_GPIO1_IO1 508 MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x16
509 >; 509 >;
510 }; 510 };
511 511
512 pinctrl_uart1: uart1grp { 512 pinctrl_uart1: uart1grp {
513 fsl,pins = < 513 fsl,pins = <
514 MX8MQ_IOMUXC_UART1_RXD 514 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45
515 MX8MQ_IOMUXC_UART1_TXD 515 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45
516 >; 516 >;
517 }; 517 };
518 518
519 pinctrl_uart2: uart2grp { 519 pinctrl_uart2: uart2grp {
520 fsl,pins = < 520 fsl,pins = <
521 MX8MQ_IOMUXC_UART2_RXD 521 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45
522 MX8MQ_IOMUXC_UART2_TXD 522 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45
523 >; 523 >;
524 }; 524 };
525 525
526 pinctrl_usb3_0: usb3-0grp { 526 pinctrl_usb3_0: usb3-0grp {
527 fsl,pins = < 527 fsl,pins = <
528 MX8MQ_IOMUXC_GPIO1_IO1 528 MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x16
529 >; 529 >;
530 }; 530 };
531 531
532 pinctrl_usb3_1: usb3-1grp { 532 pinctrl_usb3_1: usb3-1grp {
533 fsl,pins = < 533 fsl,pins = <
534 MX8MQ_IOMUXC_GPIO1_IO1 534 MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x16
535 >; 535 >;
536 }; 536 };
537 537
538 pinctrl_usdhc1: usdhc1grp { 538 pinctrl_usdhc1: usdhc1grp {
539 fsl,pins = < 539 fsl,pins = <
540 MX8MQ_IOMUXC_SD1_CLK_U 540 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
541 MX8MQ_IOMUXC_SD1_CMD_U 541 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
542 MX8MQ_IOMUXC_SD1_DATA0 542 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
543 MX8MQ_IOMUXC_SD1_DATA1 543 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
544 MX8MQ_IOMUXC_SD1_DATA2 544 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
545 MX8MQ_IOMUXC_SD1_DATA3 545 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
546 MX8MQ_IOMUXC_SD1_DATA4 546 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
547 MX8MQ_IOMUXC_SD1_DATA5 547 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
548 MX8MQ_IOMUXC_SD1_DATA6 548 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
549 MX8MQ_IOMUXC_SD1_DATA7 549 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
550 MX8MQ_IOMUXC_SD1_RESET 550 MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
551 >; 551 >;
552 }; 552 };
553 553
554 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 554 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
555 fsl,pins = < 555 fsl,pins = <
556 MX8MQ_IOMUXC_SD1_CLK_U 556 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
557 MX8MQ_IOMUXC_SD1_CMD_U 557 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
558 MX8MQ_IOMUXC_SD1_DATA0 558 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
559 MX8MQ_IOMUXC_SD1_DATA1 559 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
560 MX8MQ_IOMUXC_SD1_DATA2 560 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
561 MX8MQ_IOMUXC_SD1_DATA3 561 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
562 MX8MQ_IOMUXC_SD1_DATA4 562 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
563 MX8MQ_IOMUXC_SD1_DATA5 563 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
564 MX8MQ_IOMUXC_SD1_DATA6 564 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
565 MX8MQ_IOMUXC_SD1_DATA7 565 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
566 >; 566 >;
567 }; 567 };
568 568
569 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 569 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
570 fsl,pins = < 570 fsl,pins = <
571 MX8MQ_IOMUXC_SD1_CLK_U 571 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
572 MX8MQ_IOMUXC_SD1_CMD_U 572 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
573 MX8MQ_IOMUXC_SD1_DATA0 573 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
574 MX8MQ_IOMUXC_SD1_DATA1 574 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
575 MX8MQ_IOMUXC_SD1_DATA2 575 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
576 MX8MQ_IOMUXC_SD1_DATA3 576 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
577 MX8MQ_IOMUXC_SD1_DATA4 577 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
578 MX8MQ_IOMUXC_SD1_DATA5 578 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
579 MX8MQ_IOMUXC_SD1_DATA6 579 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
580 MX8MQ_IOMUXC_SD1_DATA7 580 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
581 >; 581 >;
582 }; 582 };
583 583
584 pinctrl_wdog: wdoggrp { 584 pinctrl_wdog: wdoggrp {
585 fsl,pins = < 585 fsl,pins = <
586 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_ 586 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
587 >; 587 >;
588 }; 588 };
589 }; 589 };
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