1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright 2017-2019 NXP 3 * Copyright 2017-2019 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8mq.dtsi" 8 #include "imx8mq.dtsi"
9 #include <dt-bindings/interrupt-controller/irq <<
10 9
11 / { 10 / {
12 model = "Google i.MX8MQ Phanbell"; 11 model = "Google i.MX8MQ Phanbell";
13 compatible = "google,imx8mq-phanbell", 12 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
14 13
15 chosen { 14 chosen {
16 stdout-path = &uart1; 15 stdout-path = &uart1;
17 }; 16 };
18 17
19 memory@40000000 { 18 memory@40000000 {
20 device_type = "memory"; 19 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 20 reg = <0x00000000 0x40000000 0 0x40000000>;
22 }; 21 };
23 22
24 pmic_osc: clock-pmic { 23 pmic_osc: clock-pmic {
25 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
26 #clock-cells = <0>; 25 #clock-cells = <0>;
27 clock-frequency = <32768>; 26 clock-frequency = <32768>;
28 clock-output-names = "pmic_osc 27 clock-output-names = "pmic_osc";
29 }; 28 };
30 29
31 reg_usdhc2_vmmc: regulator-usdhc2-vmmc 30 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
32 compatible = "regulator-fixed" 31 compatible = "regulator-fixed";
33 regulator-name = "VSD_3V3"; 32 regulator-name = "VSD_3V3";
34 regulator-min-microvolt = <330 33 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <330 34 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio2 19 GPIO_ACTIVE_ 35 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
37 enable-active-high; 36 enable-active-high;
38 }; 37 };
39 <<
40 fan: gpio-fan { <<
41 compatible = "gpio-fan"; <<
42 gpio-fan,speed-map = <0 0>, <8 <<
43 gpios = <&gpio3 5 GPIO_ACTIVE_ <<
44 #cooling-cells = <2>; <<
45 pinctrl-names = "default"; <<
46 pinctrl-0 = <&pinctrl_gpio_fan <<
47 status = "okay"; <<
48 }; <<
49 }; 38 };
50 39
51 &A53_0 { 40 &A53_0 {
52 cpu-supply = <&buck2>; 41 cpu-supply = <&buck2>;
53 }; 42 };
54 43
55 &A53_1 { 44 &A53_1 {
56 cpu-supply = <&buck2>; 45 cpu-supply = <&buck2>;
57 }; 46 };
58 47
59 &A53_2 { 48 &A53_2 {
60 cpu-supply = <&buck2>; 49 cpu-supply = <&buck2>;
61 }; 50 };
62 51
63 &A53_3 { 52 &A53_3 {
64 cpu-supply = <&buck2>; 53 cpu-supply = <&buck2>;
65 }; 54 };
66 55
67 &cpu_thermal { <<
68 trips { <<
69 cpu_alert0: trip0 { <<
70 temperature = <75000>; <<
71 hysteresis = <2000>; <<
72 type = "passive"; <<
73 }; <<
74 <<
75 cpu_alert1: trip1 { <<
76 temperature = <80000>; <<
77 hysteresis = <2000>; <<
78 type = "passive"; <<
79 }; <<
80 <<
81 cpu_crit0: trip3 { <<
82 temperature = <90000>; <<
83 hysteresis = <2000>; <<
84 type = "critical"; <<
85 }; <<
86 <<
87 fan_toggle0: trip4 { <<
88 temperature = <65000>; <<
89 hysteresis = <10000>; <<
90 type = "active"; <<
91 }; <<
92 }; <<
93 <<
94 cooling-maps { <<
95 map0 { <<
96 trip = <&cpu_alert0>; <<
97 cooling-device = <<
98 <&A53_0 0 1>; /* Exclu <<
99 }; <<
100 <<
101 map1 { <<
102 trip = <&cpu_alert1>; <<
103 cooling-device = <<
104 <&A53_0 0 2>; /* Exclu <<
105 }; <<
106 <<
107 map4 { <<
108 trip = <&fan_toggle0>; <<
109 cooling-device = <&fan <<
110 }; <<
111 }; <<
112 }; <<
113 <<
114 &i2c1 { 56 &i2c1 {
115 clock-frequency = <400000>; 57 clock-frequency = <400000>;
116 pinctrl-names = "default"; 58 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c1>; 59 pinctrl-0 = <&pinctrl_i2c1>;
118 status = "okay"; 60 status = "okay";
119 61
120 pmic: pmic@4b { 62 pmic: pmic@4b {
121 compatible = "rohm,bd71837"; 63 compatible = "rohm,bd71837";
122 reg = <0x4b>; 64 reg = <0x4b>;
123 pinctrl-names = "default"; 65 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_pmic>; 66 pinctrl-0 = <&pinctrl_pmic>;
125 #clock-cells = <0>; 67 #clock-cells = <0>;
126 clocks = <&pmic_osc>; 68 clocks = <&pmic_osc>;
127 clock-output-names = "pmic_clk 69 clock-output-names = "pmic_clk";
128 interrupt-parent = <&gpio1>; 70 interrupt-parent = <&gpio1>;
129 interrupts = <3 IRQ_TYPE_LEVEL !! 71 interrupts = <3 GPIO_ACTIVE_LOW>;
130 72
131 regulators { 73 regulators {
132 buck1: BUCK1 { 74 buck1: BUCK1 {
133 regulator-name 75 regulator-name = "buck1";
134 regulator-min- 76 regulator-min-microvolt = <700000>;
135 regulator-max- 77 regulator-max-microvolt = <1300000>;
136 regulator-boot 78 regulator-boot-on;
137 regulator-alwa 79 regulator-always-on;
138 regulator-ramp 80 regulator-ramp-delay = <1250>;
139 rohm,dvs-run-v 81 rohm,dvs-run-voltage = <900000>;
140 rohm,dvs-idle- 82 rohm,dvs-idle-voltage = <900000>;
141 rohm,dvs-suspe 83 rohm,dvs-suspend-voltage = <800000>;
142 }; 84 };
143 85
144 buck2: BUCK2 { 86 buck2: BUCK2 {
145 regulator-name 87 regulator-name = "buck2";
146 regulator-min- 88 regulator-min-microvolt = <850000>;
147 regulator-max- 89 regulator-max-microvolt = <1000000>;
148 regulator-boot 90 regulator-boot-on;
149 regulator-alwa 91 regulator-always-on;
150 rohm,dvs-run-v 92 rohm,dvs-run-voltage = <1000000>;
151 rohm,dvs-idle- 93 rohm,dvs-idle-voltage = <900000>;
152 }; 94 };
153 95
154 buck3: BUCK3 { 96 buck3: BUCK3 {
155 regulator-name 97 regulator-name = "buck3";
156 regulator-min- 98 regulator-min-microvolt = <700000>;
157 regulator-max- 99 regulator-max-microvolt = <1300000>;
158 regulator-boot 100 regulator-boot-on;
159 rohm,dvs-run-v 101 rohm,dvs-run-voltage = <900000>;
160 }; 102 };
161 103
162 buck4: BUCK4 { 104 buck4: BUCK4 {
163 regulator-name 105 regulator-name = "buck4";
164 regulator-min- 106 regulator-min-microvolt = <700000>;
165 regulator-max- 107 regulator-max-microvolt = <1300000>;
166 regulator-boot 108 regulator-boot-on;
167 regulator-alwa 109 regulator-always-on;
168 rohm,dvs-run-v 110 rohm,dvs-run-voltage = <900000>;
169 }; 111 };
170 112
171 buck5: BUCK5 { 113 buck5: BUCK5 {
172 regulator-name 114 regulator-name = "buck5";
173 regulator-min- 115 regulator-min-microvolt = <700000>;
174 regulator-max- 116 regulator-max-microvolt = <1350000>;
175 regulator-boot 117 regulator-boot-on;
176 regulator-alwa 118 regulator-always-on;
177 }; 119 };
178 120
179 buck6: BUCK6 { 121 buck6: BUCK6 {
180 regulator-name 122 regulator-name = "buck6";
181 regulator-min- 123 regulator-min-microvolt = <3000000>;
182 regulator-max- 124 regulator-max-microvolt = <3300000>;
183 regulator-boot 125 regulator-boot-on;
184 regulator-alwa 126 regulator-always-on;
185 }; 127 };
186 128
187 buck7: BUCK7 { 129 buck7: BUCK7 {
188 regulator-name 130 regulator-name = "buck7";
189 regulator-min- 131 regulator-min-microvolt = <1605000>;
190 regulator-max- 132 regulator-max-microvolt = <1995000>;
191 regulator-boot 133 regulator-boot-on;
192 regulator-alwa 134 regulator-always-on;
193 }; 135 };
194 136
195 buck8: BUCK8 { 137 buck8: BUCK8 {
196 regulator-name 138 regulator-name = "buck8";
197 regulator-min- 139 regulator-min-microvolt = <800000>;
198 regulator-max- 140 regulator-max-microvolt = <1400000>;
199 regulator-boot 141 regulator-boot-on;
200 regulator-alwa 142 regulator-always-on;
201 }; 143 };
202 144
203 ldo1: LDO1 { 145 ldo1: LDO1 {
204 regulator-name 146 regulator-name = "ldo1";
205 regulator-min- 147 regulator-min-microvolt = <3000000>;
206 regulator-max- 148 regulator-max-microvolt = <3300000>;
207 regulator-boot 149 regulator-boot-on;
208 regulator-alwa 150 regulator-always-on;
209 }; 151 };
210 152
211 ldo2: LDO2 { 153 ldo2: LDO2 {
212 regulator-name 154 regulator-name = "ldo2";
213 regulator-min- 155 regulator-min-microvolt = <900000>;
214 regulator-max- 156 regulator-max-microvolt = <900000>;
215 regulator-boot 157 regulator-boot-on;
216 regulator-alwa 158 regulator-always-on;
217 }; 159 };
218 160
219 ldo3: LDO3 { 161 ldo3: LDO3 {
220 regulator-name 162 regulator-name = "ldo3";
221 regulator-min- 163 regulator-min-microvolt = <1800000>;
222 regulator-max- 164 regulator-max-microvolt = <3300000>;
223 regulator-boot 165 regulator-boot-on;
224 regulator-alwa 166 regulator-always-on;
225 }; 167 };
226 168
227 ldo4: LDO4 { 169 ldo4: LDO4 {
228 regulator-name 170 regulator-name = "ldo4";
229 regulator-min- 171 regulator-min-microvolt = <900000>;
230 regulator-max- 172 regulator-max-microvolt = <1800000>;
231 regulator-boot 173 regulator-boot-on;
232 regulator-alwa 174 regulator-always-on;
233 }; 175 };
234 176
235 ldo5: LDO5 { 177 ldo5: LDO5 {
236 regulator-name 178 regulator-name = "ldo5";
237 regulator-min- 179 regulator-min-microvolt = <1800000>;
238 regulator-max- 180 regulator-max-microvolt = <3300000>;
239 regulator-boot 181 regulator-boot-on;
240 regulator-alwa 182 regulator-always-on;
241 }; 183 };
242 184
243 ldo6: LDO6 { 185 ldo6: LDO6 {
244 regulator-name 186 regulator-name = "ldo6";
245 regulator-min- 187 regulator-min-microvolt = <900000>;
246 regulator-max- 188 regulator-max-microvolt = <1800000>;
247 regulator-boot 189 regulator-boot-on;
248 regulator-alwa 190 regulator-always-on;
249 }; 191 };
250 192
251 ldo7: LDO7 { 193 ldo7: LDO7 {
252 regulator-name 194 regulator-name = "ldo7";
253 regulator-min- 195 regulator-min-microvolt = <1800000>;
254 regulator-max- 196 regulator-max-microvolt = <3300000>;
255 regulator-boot 197 regulator-boot-on;
256 regulator-alwa 198 regulator-always-on;
257 }; 199 };
258 }; 200 };
259 }; 201 };
260 }; 202 };
261 203
262 &fec1 { <<
263 pinctrl-names = "default"; <<
264 pinctrl-0 = <&pinctrl_fec1>; <<
265 phy-mode = "rgmii-id"; <<
266 phy-handle = <ðphy0>; <<
267 fsl,magic-packet; <<
268 status = "okay"; <<
269 <<
270 mdio { <<
271 #address-cells = <1>; <<
272 #size-cells = <0>; <<
273 ethphy0: ethernet-phy@0 { <<
274 compatible = "ethernet <<
275 reg = <0>; <<
276 reset-gpios = <&gpio1 <<
277 reset-assert-us = <100 <<
278 reset-deassert-us = <5 <<
279 }; <<
280 }; <<
281 }; <<
282 <<
283 &uart1 { 204 &uart1 {
284 pinctrl-names = "default"; 205 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart1>; 206 pinctrl-0 = <&pinctrl_uart1>;
286 status = "okay"; 207 status = "okay";
287 }; 208 };
288 209
289 &usdhc1 { 210 &usdhc1 {
290 pinctrl-names = "default", "state_100m 211 pinctrl-names = "default", "state_100mhz", "state_200mhz";
291 pinctrl-0 = <&pinctrl_usdhc1>; 212 pinctrl-0 = <&pinctrl_usdhc1>;
292 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 213 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
293 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 214 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
294 bus-width = <8>; 215 bus-width = <8>;
295 non-removable; 216 non-removable;
296 status = "okay"; 217 status = "okay";
297 }; 218 };
298 219
299 &usdhc2 { 220 &usdhc2 {
300 pinctrl-names = "default", "state_100m 221 pinctrl-names = "default", "state_100mhz", "state_200mhz";
301 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 222 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
302 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 223 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
303 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 224 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
304 bus-width = <4>; 225 bus-width = <4>;
305 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 226 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
306 vmmc-supply = <®_usdhc2_vmmc>; 227 vmmc-supply = <®_usdhc2_vmmc>;
307 status = "okay"; 228 status = "okay";
308 }; 229 };
309 230
310 &usb3_phy0 { 231 &usb3_phy0 {
311 status = "okay"; 232 status = "okay";
312 }; 233 };
313 234
314 &usb_dwc3_0 { 235 &usb_dwc3_0 {
315 dr_mode = "otg"; 236 dr_mode = "otg";
316 status = "okay"; 237 status = "okay";
317 }; 238 };
318 239
319 &usb3_phy1 { 240 &usb3_phy1 {
320 status = "okay"; 241 status = "okay";
321 }; 242 };
322 243
323 &usb_dwc3_1 { 244 &usb_dwc3_1 {
324 dr_mode = "host"; 245 dr_mode = "host";
325 status = "okay"; 246 status = "okay";
326 }; 247 };
327 248
328 &wdog1 { 249 &wdog1 {
329 pinctrl-names = "default"; 250 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_wdog>; 251 pinctrl-0 = <&pinctrl_wdog>;
331 fsl,ext-reset-output; 252 fsl,ext-reset-output;
332 status = "okay"; 253 status = "okay";
333 }; 254 };
334 255
335 &iomuxc { 256 &iomuxc {
336 pinctrl_fec1: fec1grp { <<
337 fsl,pins = < <<
338 MX8MQ_IOMUXC_ENET_MDC_ <<
339 MX8MQ_IOMUXC_ENET_MDIO <<
340 MX8MQ_IOMUXC_ENET_TD3_ <<
341 MX8MQ_IOMUXC_ENET_TD2_ <<
342 MX8MQ_IOMUXC_ENET_TD1_ <<
343 MX8MQ_IOMUXC_ENET_TD0_ <<
344 MX8MQ_IOMUXC_ENET_RD3_ <<
345 MX8MQ_IOMUXC_ENET_RD2_ <<
346 MX8MQ_IOMUXC_ENET_RD1_ <<
347 MX8MQ_IOMUXC_ENET_RD0_ <<
348 MX8MQ_IOMUXC_ENET_TXC_ <<
349 MX8MQ_IOMUXC_ENET_RXC_ <<
350 MX8MQ_IOMUXC_ENET_RX_C <<
351 MX8MQ_IOMUXC_ENET_TX_C <<
352 MX8MQ_IOMUXC_GPIO1_IO0 <<
353 >; <<
354 }; <<
355 <<
356 pinctrl_gpio_fan: gpiofangrp { <<
357 fsl,pins = < <<
358 MX8MQ_IOMUXC_NAND_CLE_ <<
359 >; <<
360 }; <<
361 <<
362 pinctrl_i2c1: i2c1grp { 257 pinctrl_i2c1: i2c1grp {
363 fsl,pins = < 258 fsl,pins = <
364 MX8MQ_IOMUXC_I2C1_SCL_ 259 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
365 MX8MQ_IOMUXC_I2C1_SDA_ 260 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
366 >; 261 >;
367 }; 262 };
368 263
369 pinctrl_pmic: pmicirqgrp { !! 264 pinctrl_pmic: pmicirq {
370 fsl,pins = < 265 fsl,pins = <
371 MX8MQ_IOMUXC_GPIO1_IO0 266 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
372 >; 267 >;
373 }; 268 };
374 269
375 pinctrl_uart1: uart1grp { 270 pinctrl_uart1: uart1grp {
376 fsl,pins = < 271 fsl,pins = <
377 MX8MQ_IOMUXC_UART1_RXD 272 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
378 MX8MQ_IOMUXC_UART1_TXD 273 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
379 >; 274 >;
380 }; 275 };
381 276
382 pinctrl_usdhc1: usdhc1grp { 277 pinctrl_usdhc1: usdhc1grp {
383 fsl,pins = < 278 fsl,pins = <
384 MX8MQ_IOMUXC_SD1_CLK_U 279 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
385 MX8MQ_IOMUXC_SD1_CMD_U 280 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
386 MX8MQ_IOMUXC_SD1_DATA0 281 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
387 MX8MQ_IOMUXC_SD1_DATA1 282 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
388 MX8MQ_IOMUXC_SD1_DATA2 283 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
389 MX8MQ_IOMUXC_SD1_DATA3 284 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
390 MX8MQ_IOMUXC_SD1_DATA4 285 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
391 MX8MQ_IOMUXC_SD1_DATA5 286 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
392 MX8MQ_IOMUXC_SD1_DATA6 287 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
393 MX8MQ_IOMUXC_SD1_DATA7 288 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
394 MX8MQ_IOMUXC_SD1_STROB 289 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
395 MX8MQ_IOMUXC_SD1_RESET 290 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
396 >; 291 >;
397 }; 292 };
398 293
399 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr !! 294 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
400 fsl,pins = < 295 fsl,pins = <
401 MX8MQ_IOMUXC_SD1_CLK_U 296 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
402 MX8MQ_IOMUXC_SD1_CMD_U 297 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
403 MX8MQ_IOMUXC_SD1_DATA0 298 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
404 MX8MQ_IOMUXC_SD1_DATA1 299 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
405 MX8MQ_IOMUXC_SD1_DATA2 300 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
406 MX8MQ_IOMUXC_SD1_DATA3 301 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
407 MX8MQ_IOMUXC_SD1_DATA4 302 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
408 MX8MQ_IOMUXC_SD1_DATA5 303 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
409 MX8MQ_IOMUXC_SD1_DATA6 304 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
410 MX8MQ_IOMUXC_SD1_DATA7 305 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
411 MX8MQ_IOMUXC_SD1_STROB 306 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
412 MX8MQ_IOMUXC_SD1_RESET 307 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
413 >; 308 >;
414 }; 309 };
415 310
416 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr !! 311 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
417 fsl,pins = < 312 fsl,pins = <
418 MX8MQ_IOMUXC_SD1_CLK_U 313 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
419 MX8MQ_IOMUXC_SD1_CMD_U 314 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
420 MX8MQ_IOMUXC_SD1_DATA0 315 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
421 MX8MQ_IOMUXC_SD1_DATA1 316 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
422 MX8MQ_IOMUXC_SD1_DATA2 317 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
423 MX8MQ_IOMUXC_SD1_DATA3 318 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
424 MX8MQ_IOMUXC_SD1_DATA4 319 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
425 MX8MQ_IOMUXC_SD1_DATA5 320 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
426 MX8MQ_IOMUXC_SD1_DATA6 321 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
427 MX8MQ_IOMUXC_SD1_DATA7 322 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
428 MX8MQ_IOMUXC_SD1_STROB 323 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
429 MX8MQ_IOMUXC_SD1_RESET 324 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
430 >; 325 >;
431 }; 326 };
432 327
433 pinctrl_usdhc2_gpio: usdhc2gpiogrp { !! 328 pinctrl_usdhc2_gpio: usdhc2grpgpio {
434 fsl,pins = < 329 fsl,pins = <
435 MX8MQ_IOMUXC_SD2_CD_B_ 330 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
436 MX8MQ_IOMUXC_SD2_RESET 331 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
437 >; 332 >;
438 }; 333 };
439 334
440 pinctrl_usdhc2: usdhc2grp { 335 pinctrl_usdhc2: usdhc2grp {
441 fsl,pins = < 336 fsl,pins = <
442 MX8MQ_IOMUXC_SD2_CLK_U 337 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
443 MX8MQ_IOMUXC_SD2_CMD_U 338 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
444 MX8MQ_IOMUXC_SD2_DATA0 339 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
445 MX8MQ_IOMUXC_SD2_DATA1 340 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
446 MX8MQ_IOMUXC_SD2_DATA2 341 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
447 MX8MQ_IOMUXC_SD2_DATA3 342 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
448 MX8MQ_IOMUXC_GPIO1_IO0 343 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
449 >; 344 >;
450 }; 345 };
451 346
452 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr !! 347 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
453 fsl,pins = < 348 fsl,pins = <
454 MX8MQ_IOMUXC_SD2_CLK_U 349 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
455 MX8MQ_IOMUXC_SD2_CMD_U 350 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
456 MX8MQ_IOMUXC_SD2_DATA0 351 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
457 MX8MQ_IOMUXC_SD2_DATA1 352 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
458 MX8MQ_IOMUXC_SD2_DATA2 353 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
459 MX8MQ_IOMUXC_SD2_DATA3 354 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
460 MX8MQ_IOMUXC_GPIO1_IO0 355 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
461 >; 356 >;
462 }; 357 };
463 358
464 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr !! 359 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
465 fsl,pins = < 360 fsl,pins = <
466 MX8MQ_IOMUXC_SD2_CLK_U 361 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
467 MX8MQ_IOMUXC_SD2_CMD_U 362 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
468 MX8MQ_IOMUXC_SD2_DATA0 363 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
469 MX8MQ_IOMUXC_SD2_DATA1 364 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
470 MX8MQ_IOMUXC_SD2_DATA2 365 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
471 MX8MQ_IOMUXC_SD2_DATA3 366 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
472 MX8MQ_IOMUXC_GPIO1_IO0 367 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
473 >; 368 >;
474 }; 369 };
475 370
476 pinctrl_wdog: wdoggrp { 371 pinctrl_wdog: wdoggrp {
477 fsl,pins = < 372 fsl,pins = <
478 MX8MQ_IOMUXC_GPIO1_IO0 373 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
479 >; 374 >;
480 }; 375 };
481 }; 376 };
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