1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright 2017-2019 NXP 3 * Copyright 2017-2019 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8mq.dtsi" 8 #include "imx8mq.dtsi"
9 #include <dt-bindings/interrupt-controller/irq <<
10 9
11 / { 10 / {
12 model = "Google i.MX8MQ Phanbell"; 11 model = "Google i.MX8MQ Phanbell";
13 compatible = "google,imx8mq-phanbell", 12 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
14 13
15 chosen { 14 chosen {
16 stdout-path = &uart1; 15 stdout-path = &uart1;
17 }; 16 };
18 17
19 memory@40000000 { 18 memory@40000000 {
20 device_type = "memory"; 19 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 20 reg = <0x00000000 0x40000000 0 0x40000000>;
22 }; 21 };
23 22
24 pmic_osc: clock-pmic { 23 pmic_osc: clock-pmic {
25 compatible = "fixed-clock"; 24 compatible = "fixed-clock";
26 #clock-cells = <0>; 25 #clock-cells = <0>;
27 clock-frequency = <32768>; 26 clock-frequency = <32768>;
28 clock-output-names = "pmic_osc 27 clock-output-names = "pmic_osc";
29 }; 28 };
30 29
31 reg_usdhc2_vmmc: regulator-usdhc2-vmmc 30 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
32 compatible = "regulator-fixed" 31 compatible = "regulator-fixed";
33 regulator-name = "VSD_3V3"; 32 regulator-name = "VSD_3V3";
34 regulator-min-microvolt = <330 33 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <330 34 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio2 19 GPIO_ACTIVE_ 35 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
37 enable-active-high; 36 enable-active-high;
38 }; 37 };
39 38
40 fan: gpio-fan { 39 fan: gpio-fan {
41 compatible = "gpio-fan"; 40 compatible = "gpio-fan";
42 gpio-fan,speed-map = <0 0>, <8 !! 41 gpio-fan,speed-map = <0 0 8600 1>;
43 gpios = <&gpio3 5 GPIO_ACTIVE_ 42 gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
44 #cooling-cells = <2>; 43 #cooling-cells = <2>;
45 pinctrl-names = "default"; 44 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_gpio_fan 45 pinctrl-0 = <&pinctrl_gpio_fan>;
47 status = "okay"; 46 status = "okay";
48 }; 47 };
49 }; 48 };
50 49
51 &A53_0 { 50 &A53_0 {
52 cpu-supply = <&buck2>; 51 cpu-supply = <&buck2>;
53 }; 52 };
54 53
55 &A53_1 { 54 &A53_1 {
56 cpu-supply = <&buck2>; 55 cpu-supply = <&buck2>;
57 }; 56 };
58 57
59 &A53_2 { 58 &A53_2 {
60 cpu-supply = <&buck2>; 59 cpu-supply = <&buck2>;
61 }; 60 };
62 61
63 &A53_3 { 62 &A53_3 {
64 cpu-supply = <&buck2>; 63 cpu-supply = <&buck2>;
65 }; 64 };
66 65
67 &cpu_thermal { 66 &cpu_thermal {
68 trips { 67 trips {
69 cpu_alert0: trip0 { 68 cpu_alert0: trip0 {
70 temperature = <75000>; 69 temperature = <75000>;
71 hysteresis = <2000>; 70 hysteresis = <2000>;
72 type = "passive"; 71 type = "passive";
73 }; 72 };
74 73
75 cpu_alert1: trip1 { 74 cpu_alert1: trip1 {
76 temperature = <80000>; 75 temperature = <80000>;
77 hysteresis = <2000>; 76 hysteresis = <2000>;
78 type = "passive"; 77 type = "passive";
79 }; 78 };
80 79
81 cpu_crit0: trip3 { 80 cpu_crit0: trip3 {
82 temperature = <90000>; 81 temperature = <90000>;
83 hysteresis = <2000>; 82 hysteresis = <2000>;
84 type = "critical"; 83 type = "critical";
85 }; 84 };
86 85
87 fan_toggle0: trip4 { 86 fan_toggle0: trip4 {
88 temperature = <65000>; 87 temperature = <65000>;
89 hysteresis = <10000>; 88 hysteresis = <10000>;
90 type = "active"; 89 type = "active";
91 }; 90 };
92 }; 91 };
93 92
94 cooling-maps { 93 cooling-maps {
95 map0 { 94 map0 {
96 trip = <&cpu_alert0>; 95 trip = <&cpu_alert0>;
97 cooling-device = 96 cooling-device =
98 <&A53_0 0 1>; /* Exclu 97 <&A53_0 0 1>; /* Exclude highest OPP */
99 }; 98 };
100 99
101 map1 { 100 map1 {
102 trip = <&cpu_alert1>; 101 trip = <&cpu_alert1>;
103 cooling-device = 102 cooling-device =
104 <&A53_0 0 2>; /* Exclu 103 <&A53_0 0 2>; /* Exclude two highest OPPs */
105 }; 104 };
106 105
107 map4 { 106 map4 {
108 trip = <&fan_toggle0>; 107 trip = <&fan_toggle0>;
109 cooling-device = <&fan 108 cooling-device = <&fan 0 1>;
110 }; 109 };
111 }; 110 };
112 }; 111 };
113 112
114 &i2c1 { 113 &i2c1 {
115 clock-frequency = <400000>; 114 clock-frequency = <400000>;
116 pinctrl-names = "default"; 115 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c1>; 116 pinctrl-0 = <&pinctrl_i2c1>;
118 status = "okay"; 117 status = "okay";
119 118
120 pmic: pmic@4b { 119 pmic: pmic@4b {
121 compatible = "rohm,bd71837"; 120 compatible = "rohm,bd71837";
122 reg = <0x4b>; 121 reg = <0x4b>;
123 pinctrl-names = "default"; 122 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_pmic>; 123 pinctrl-0 = <&pinctrl_pmic>;
125 #clock-cells = <0>; 124 #clock-cells = <0>;
126 clocks = <&pmic_osc>; 125 clocks = <&pmic_osc>;
127 clock-output-names = "pmic_clk 126 clock-output-names = "pmic_clk";
128 interrupt-parent = <&gpio1>; 127 interrupt-parent = <&gpio1>;
129 interrupts = <3 IRQ_TYPE_LEVEL !! 128 interrupts = <3 GPIO_ACTIVE_LOW>;
130 129
131 regulators { 130 regulators {
132 buck1: BUCK1 { 131 buck1: BUCK1 {
133 regulator-name 132 regulator-name = "buck1";
134 regulator-min- 133 regulator-min-microvolt = <700000>;
135 regulator-max- 134 regulator-max-microvolt = <1300000>;
136 regulator-boot 135 regulator-boot-on;
137 regulator-alwa 136 regulator-always-on;
138 regulator-ramp 137 regulator-ramp-delay = <1250>;
139 rohm,dvs-run-v 138 rohm,dvs-run-voltage = <900000>;
140 rohm,dvs-idle- 139 rohm,dvs-idle-voltage = <900000>;
141 rohm,dvs-suspe 140 rohm,dvs-suspend-voltage = <800000>;
142 }; 141 };
143 142
144 buck2: BUCK2 { 143 buck2: BUCK2 {
145 regulator-name 144 regulator-name = "buck2";
146 regulator-min- 145 regulator-min-microvolt = <850000>;
147 regulator-max- 146 regulator-max-microvolt = <1000000>;
148 regulator-boot 147 regulator-boot-on;
149 regulator-alwa 148 regulator-always-on;
150 rohm,dvs-run-v 149 rohm,dvs-run-voltage = <1000000>;
151 rohm,dvs-idle- 150 rohm,dvs-idle-voltage = <900000>;
152 }; 151 };
153 152
154 buck3: BUCK3 { 153 buck3: BUCK3 {
155 regulator-name 154 regulator-name = "buck3";
156 regulator-min- 155 regulator-min-microvolt = <700000>;
157 regulator-max- 156 regulator-max-microvolt = <1300000>;
158 regulator-boot 157 regulator-boot-on;
159 rohm,dvs-run-v 158 rohm,dvs-run-voltage = <900000>;
160 }; 159 };
161 160
162 buck4: BUCK4 { 161 buck4: BUCK4 {
163 regulator-name 162 regulator-name = "buck4";
164 regulator-min- 163 regulator-min-microvolt = <700000>;
165 regulator-max- 164 regulator-max-microvolt = <1300000>;
166 regulator-boot 165 regulator-boot-on;
167 regulator-alwa 166 regulator-always-on;
168 rohm,dvs-run-v 167 rohm,dvs-run-voltage = <900000>;
169 }; 168 };
170 169
171 buck5: BUCK5 { 170 buck5: BUCK5 {
172 regulator-name 171 regulator-name = "buck5";
173 regulator-min- 172 regulator-min-microvolt = <700000>;
174 regulator-max- 173 regulator-max-microvolt = <1350000>;
175 regulator-boot 174 regulator-boot-on;
176 regulator-alwa 175 regulator-always-on;
177 }; 176 };
178 177
179 buck6: BUCK6 { 178 buck6: BUCK6 {
180 regulator-name 179 regulator-name = "buck6";
181 regulator-min- 180 regulator-min-microvolt = <3000000>;
182 regulator-max- 181 regulator-max-microvolt = <3300000>;
183 regulator-boot 182 regulator-boot-on;
184 regulator-alwa 183 regulator-always-on;
185 }; 184 };
186 185
187 buck7: BUCK7 { 186 buck7: BUCK7 {
188 regulator-name 187 regulator-name = "buck7";
189 regulator-min- 188 regulator-min-microvolt = <1605000>;
190 regulator-max- 189 regulator-max-microvolt = <1995000>;
191 regulator-boot 190 regulator-boot-on;
192 regulator-alwa 191 regulator-always-on;
193 }; 192 };
194 193
195 buck8: BUCK8 { 194 buck8: BUCK8 {
196 regulator-name 195 regulator-name = "buck8";
197 regulator-min- 196 regulator-min-microvolt = <800000>;
198 regulator-max- 197 regulator-max-microvolt = <1400000>;
199 regulator-boot 198 regulator-boot-on;
200 regulator-alwa 199 regulator-always-on;
201 }; 200 };
202 201
203 ldo1: LDO1 { 202 ldo1: LDO1 {
204 regulator-name 203 regulator-name = "ldo1";
205 regulator-min- 204 regulator-min-microvolt = <3000000>;
206 regulator-max- 205 regulator-max-microvolt = <3300000>;
207 regulator-boot 206 regulator-boot-on;
208 regulator-alwa 207 regulator-always-on;
209 }; 208 };
210 209
211 ldo2: LDO2 { 210 ldo2: LDO2 {
212 regulator-name 211 regulator-name = "ldo2";
213 regulator-min- 212 regulator-min-microvolt = <900000>;
214 regulator-max- 213 regulator-max-microvolt = <900000>;
215 regulator-boot 214 regulator-boot-on;
216 regulator-alwa 215 regulator-always-on;
217 }; 216 };
218 217
219 ldo3: LDO3 { 218 ldo3: LDO3 {
220 regulator-name 219 regulator-name = "ldo3";
221 regulator-min- 220 regulator-min-microvolt = <1800000>;
222 regulator-max- 221 regulator-max-microvolt = <3300000>;
223 regulator-boot 222 regulator-boot-on;
224 regulator-alwa 223 regulator-always-on;
225 }; 224 };
226 225
227 ldo4: LDO4 { 226 ldo4: LDO4 {
228 regulator-name 227 regulator-name = "ldo4";
229 regulator-min- 228 regulator-min-microvolt = <900000>;
230 regulator-max- 229 regulator-max-microvolt = <1800000>;
231 regulator-boot 230 regulator-boot-on;
232 regulator-alwa 231 regulator-always-on;
233 }; 232 };
234 233
235 ldo5: LDO5 { 234 ldo5: LDO5 {
236 regulator-name 235 regulator-name = "ldo5";
237 regulator-min- 236 regulator-min-microvolt = <1800000>;
238 regulator-max- 237 regulator-max-microvolt = <3300000>;
239 regulator-boot 238 regulator-boot-on;
240 regulator-alwa 239 regulator-always-on;
241 }; 240 };
242 241
243 ldo6: LDO6 { 242 ldo6: LDO6 {
244 regulator-name 243 regulator-name = "ldo6";
245 regulator-min- 244 regulator-min-microvolt = <900000>;
246 regulator-max- 245 regulator-max-microvolt = <1800000>;
247 regulator-boot 246 regulator-boot-on;
248 regulator-alwa 247 regulator-always-on;
249 }; 248 };
250 249
251 ldo7: LDO7 { 250 ldo7: LDO7 {
252 regulator-name 251 regulator-name = "ldo7";
253 regulator-min- 252 regulator-min-microvolt = <1800000>;
254 regulator-max- 253 regulator-max-microvolt = <3300000>;
255 regulator-boot 254 regulator-boot-on;
256 regulator-alwa 255 regulator-always-on;
257 }; 256 };
258 }; 257 };
259 }; 258 };
260 }; 259 };
261 260
262 &fec1 { 261 &fec1 {
263 pinctrl-names = "default"; 262 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_fec1>; 263 pinctrl-0 = <&pinctrl_fec1>;
265 phy-mode = "rgmii-id"; 264 phy-mode = "rgmii-id";
>> 265 phy-reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
>> 266 phy-reset-duration = <10>;
>> 267 phy-reset-post-delay = <50>;
266 phy-handle = <ðphy0>; 268 phy-handle = <ðphy0>;
267 fsl,magic-packet; 269 fsl,magic-packet;
268 status = "okay"; 270 status = "okay";
269 271
270 mdio { 272 mdio {
271 #address-cells = <1>; 273 #address-cells = <1>;
272 #size-cells = <0>; 274 #size-cells = <0>;
273 ethphy0: ethernet-phy@0 { 275 ethphy0: ethernet-phy@0 {
274 compatible = "ethernet 276 compatible = "ethernet-phy-ieee802.3-c22";
275 reg = <0>; 277 reg = <0>;
276 reset-gpios = <&gpio1 <<
277 reset-assert-us = <100 <<
278 reset-deassert-us = <5 <<
279 }; 278 };
280 }; 279 };
281 }; 280 };
282 281
283 &uart1 { 282 &uart1 {
284 pinctrl-names = "default"; 283 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart1>; 284 pinctrl-0 = <&pinctrl_uart1>;
286 status = "okay"; 285 status = "okay";
287 }; 286 };
288 287
289 &usdhc1 { 288 &usdhc1 {
290 pinctrl-names = "default", "state_100m 289 pinctrl-names = "default", "state_100mhz", "state_200mhz";
291 pinctrl-0 = <&pinctrl_usdhc1>; 290 pinctrl-0 = <&pinctrl_usdhc1>;
292 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 291 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
293 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 292 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
294 bus-width = <8>; 293 bus-width = <8>;
295 non-removable; 294 non-removable;
296 status = "okay"; 295 status = "okay";
297 }; 296 };
298 297
299 &usdhc2 { 298 &usdhc2 {
300 pinctrl-names = "default", "state_100m 299 pinctrl-names = "default", "state_100mhz", "state_200mhz";
301 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 300 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
302 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 301 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
303 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 302 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
304 bus-width = <4>; 303 bus-width = <4>;
305 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 304 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
306 vmmc-supply = <®_usdhc2_vmmc>; 305 vmmc-supply = <®_usdhc2_vmmc>;
307 status = "okay"; 306 status = "okay";
308 }; 307 };
309 308
310 &usb3_phy0 { 309 &usb3_phy0 {
311 status = "okay"; 310 status = "okay";
312 }; 311 };
313 312
314 &usb_dwc3_0 { 313 &usb_dwc3_0 {
315 dr_mode = "otg"; 314 dr_mode = "otg";
316 status = "okay"; 315 status = "okay";
317 }; 316 };
318 317
319 &usb3_phy1 { 318 &usb3_phy1 {
320 status = "okay"; 319 status = "okay";
321 }; 320 };
322 321
323 &usb_dwc3_1 { 322 &usb_dwc3_1 {
324 dr_mode = "host"; 323 dr_mode = "host";
325 status = "okay"; 324 status = "okay";
326 }; 325 };
327 326
328 &wdog1 { 327 &wdog1 {
329 pinctrl-names = "default"; 328 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_wdog>; 329 pinctrl-0 = <&pinctrl_wdog>;
331 fsl,ext-reset-output; 330 fsl,ext-reset-output;
332 status = "okay"; 331 status = "okay";
333 }; 332 };
334 333
335 &iomuxc { 334 &iomuxc {
336 pinctrl_fec1: fec1grp { 335 pinctrl_fec1: fec1grp {
337 fsl,pins = < 336 fsl,pins = <
338 MX8MQ_IOMUXC_ENET_MDC_ 337 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
339 MX8MQ_IOMUXC_ENET_MDIO 338 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
340 MX8MQ_IOMUXC_ENET_TD3_ 339 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
341 MX8MQ_IOMUXC_ENET_TD2_ 340 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
342 MX8MQ_IOMUXC_ENET_TD1_ 341 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
343 MX8MQ_IOMUXC_ENET_TD0_ 342 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
344 MX8MQ_IOMUXC_ENET_RD3_ 343 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
345 MX8MQ_IOMUXC_ENET_RD2_ 344 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
346 MX8MQ_IOMUXC_ENET_RD1_ 345 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
347 MX8MQ_IOMUXC_ENET_RD0_ 346 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
348 MX8MQ_IOMUXC_ENET_TXC_ 347 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
349 MX8MQ_IOMUXC_ENET_RXC_ 348 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
350 MX8MQ_IOMUXC_ENET_RX_C 349 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
351 MX8MQ_IOMUXC_ENET_TX_C 350 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
352 MX8MQ_IOMUXC_GPIO1_IO0 351 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
353 >; 352 >;
354 }; 353 };
355 354
356 pinctrl_gpio_fan: gpiofangrp { 355 pinctrl_gpio_fan: gpiofangrp {
357 fsl,pins = < 356 fsl,pins = <
358 MX8MQ_IOMUXC_NAND_CLE_ 357 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
359 >; 358 >;
360 }; 359 };
361 360
362 pinctrl_i2c1: i2c1grp { 361 pinctrl_i2c1: i2c1grp {
363 fsl,pins = < 362 fsl,pins = <
364 MX8MQ_IOMUXC_I2C1_SCL_ 363 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
365 MX8MQ_IOMUXC_I2C1_SDA_ 364 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
366 >; 365 >;
367 }; 366 };
368 367
369 pinctrl_pmic: pmicirqgrp { !! 368 pinctrl_pmic: pmicirq {
370 fsl,pins = < 369 fsl,pins = <
371 MX8MQ_IOMUXC_GPIO1_IO0 370 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
372 >; 371 >;
373 }; 372 };
374 373
375 pinctrl_uart1: uart1grp { 374 pinctrl_uart1: uart1grp {
376 fsl,pins = < 375 fsl,pins = <
377 MX8MQ_IOMUXC_UART1_RXD 376 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
378 MX8MQ_IOMUXC_UART1_TXD 377 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
379 >; 378 >;
380 }; 379 };
381 380
382 pinctrl_usdhc1: usdhc1grp { 381 pinctrl_usdhc1: usdhc1grp {
383 fsl,pins = < 382 fsl,pins = <
384 MX8MQ_IOMUXC_SD1_CLK_U 383 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
385 MX8MQ_IOMUXC_SD1_CMD_U 384 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
386 MX8MQ_IOMUXC_SD1_DATA0 385 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
387 MX8MQ_IOMUXC_SD1_DATA1 386 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
388 MX8MQ_IOMUXC_SD1_DATA2 387 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
389 MX8MQ_IOMUXC_SD1_DATA3 388 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
390 MX8MQ_IOMUXC_SD1_DATA4 389 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
391 MX8MQ_IOMUXC_SD1_DATA5 390 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
392 MX8MQ_IOMUXC_SD1_DATA6 391 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
393 MX8MQ_IOMUXC_SD1_DATA7 392 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
394 MX8MQ_IOMUXC_SD1_STROB 393 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
395 MX8MQ_IOMUXC_SD1_RESET 394 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
396 >; 395 >;
397 }; 396 };
398 397
399 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr !! 398 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
400 fsl,pins = < 399 fsl,pins = <
401 MX8MQ_IOMUXC_SD1_CLK_U 400 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
402 MX8MQ_IOMUXC_SD1_CMD_U 401 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
403 MX8MQ_IOMUXC_SD1_DATA0 402 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
404 MX8MQ_IOMUXC_SD1_DATA1 403 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
405 MX8MQ_IOMUXC_SD1_DATA2 404 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
406 MX8MQ_IOMUXC_SD1_DATA3 405 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
407 MX8MQ_IOMUXC_SD1_DATA4 406 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
408 MX8MQ_IOMUXC_SD1_DATA5 407 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
409 MX8MQ_IOMUXC_SD1_DATA6 408 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
410 MX8MQ_IOMUXC_SD1_DATA7 409 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
411 MX8MQ_IOMUXC_SD1_STROB 410 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
412 MX8MQ_IOMUXC_SD1_RESET 411 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
413 >; 412 >;
414 }; 413 };
415 414
416 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr !! 415 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
417 fsl,pins = < 416 fsl,pins = <
418 MX8MQ_IOMUXC_SD1_CLK_U 417 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
419 MX8MQ_IOMUXC_SD1_CMD_U 418 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
420 MX8MQ_IOMUXC_SD1_DATA0 419 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
421 MX8MQ_IOMUXC_SD1_DATA1 420 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
422 MX8MQ_IOMUXC_SD1_DATA2 421 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
423 MX8MQ_IOMUXC_SD1_DATA3 422 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
424 MX8MQ_IOMUXC_SD1_DATA4 423 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
425 MX8MQ_IOMUXC_SD1_DATA5 424 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
426 MX8MQ_IOMUXC_SD1_DATA6 425 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
427 MX8MQ_IOMUXC_SD1_DATA7 426 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
428 MX8MQ_IOMUXC_SD1_STROB 427 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
429 MX8MQ_IOMUXC_SD1_RESET 428 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
430 >; 429 >;
431 }; 430 };
432 431
433 pinctrl_usdhc2_gpio: usdhc2gpiogrp { !! 432 pinctrl_usdhc2_gpio: usdhc2grpgpio {
434 fsl,pins = < 433 fsl,pins = <
435 MX8MQ_IOMUXC_SD2_CD_B_ 434 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
436 MX8MQ_IOMUXC_SD2_RESET 435 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
437 >; 436 >;
438 }; 437 };
439 438
440 pinctrl_usdhc2: usdhc2grp { 439 pinctrl_usdhc2: usdhc2grp {
441 fsl,pins = < 440 fsl,pins = <
442 MX8MQ_IOMUXC_SD2_CLK_U 441 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
443 MX8MQ_IOMUXC_SD2_CMD_U 442 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
444 MX8MQ_IOMUXC_SD2_DATA0 443 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
445 MX8MQ_IOMUXC_SD2_DATA1 444 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
446 MX8MQ_IOMUXC_SD2_DATA2 445 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
447 MX8MQ_IOMUXC_SD2_DATA3 446 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
448 MX8MQ_IOMUXC_GPIO1_IO0 447 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
449 >; 448 >;
450 }; 449 };
451 450
452 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr !! 451 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
453 fsl,pins = < 452 fsl,pins = <
454 MX8MQ_IOMUXC_SD2_CLK_U 453 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
455 MX8MQ_IOMUXC_SD2_CMD_U 454 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
456 MX8MQ_IOMUXC_SD2_DATA0 455 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
457 MX8MQ_IOMUXC_SD2_DATA1 456 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
458 MX8MQ_IOMUXC_SD2_DATA2 457 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
459 MX8MQ_IOMUXC_SD2_DATA3 458 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
460 MX8MQ_IOMUXC_GPIO1_IO0 459 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
461 >; 460 >;
462 }; 461 };
463 462
464 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr !! 463 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
465 fsl,pins = < 464 fsl,pins = <
466 MX8MQ_IOMUXC_SD2_CLK_U 465 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
467 MX8MQ_IOMUXC_SD2_CMD_U 466 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
468 MX8MQ_IOMUXC_SD2_DATA0 467 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
469 MX8MQ_IOMUXC_SD2_DATA1 468 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
470 MX8MQ_IOMUXC_SD2_DATA2 469 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
471 MX8MQ_IOMUXC_SD2_DATA3 470 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
472 MX8MQ_IOMUXC_GPIO1_IO0 471 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
473 >; 472 >;
474 }; 473 };
475 474
476 pinctrl_wdog: wdoggrp { 475 pinctrl_wdog: wdoggrp {
477 fsl,pins = < 476 fsl,pins = <
478 MX8MQ_IOMUXC_GPIO1_IO0 477 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
479 >; 478 >;
480 }; 479 };
481 }; 480 };
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