1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* 2 /*
3 * Copyright 2017-2019 NXP 3 * Copyright 2017-2019 NXP
4 */ 4 */
5 5
6 /dts-v1/; 6 /dts-v1/;
7 7
8 #include "imx8mq.dtsi" 8 #include "imx8mq.dtsi"
9 #include <dt-bindings/interrupt-controller/irq 9 #include <dt-bindings/interrupt-controller/irq.h>
10 10
11 / { 11 / {
12 model = "Google i.MX8MQ Phanbell"; 12 model = "Google i.MX8MQ Phanbell";
13 compatible = "google,imx8mq-phanbell", 13 compatible = "google,imx8mq-phanbell", "fsl,imx8mq";
14 14
15 chosen { 15 chosen {
16 stdout-path = &uart1; 16 stdout-path = &uart1;
17 }; 17 };
18 18
19 memory@40000000 { 19 memory@40000000 {
20 device_type = "memory"; 20 device_type = "memory";
21 reg = <0x00000000 0x40000000 0 21 reg = <0x00000000 0x40000000 0 0x40000000>;
22 }; 22 };
23 23
24 pmic_osc: clock-pmic { 24 pmic_osc: clock-pmic {
25 compatible = "fixed-clock"; 25 compatible = "fixed-clock";
26 #clock-cells = <0>; 26 #clock-cells = <0>;
27 clock-frequency = <32768>; 27 clock-frequency = <32768>;
28 clock-output-names = "pmic_osc 28 clock-output-names = "pmic_osc";
29 }; 29 };
30 30
31 reg_usdhc2_vmmc: regulator-usdhc2-vmmc 31 reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
32 compatible = "regulator-fixed" 32 compatible = "regulator-fixed";
33 regulator-name = "VSD_3V3"; 33 regulator-name = "VSD_3V3";
34 regulator-min-microvolt = <330 34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <330 35 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio2 19 GPIO_ACTIVE_ 36 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
37 enable-active-high; 37 enable-active-high;
38 }; 38 };
39 39
40 fan: gpio-fan { 40 fan: gpio-fan {
41 compatible = "gpio-fan"; 41 compatible = "gpio-fan";
42 gpio-fan,speed-map = <0 0>, <8 42 gpio-fan,speed-map = <0 0>, <8600 1>;
43 gpios = <&gpio3 5 GPIO_ACTIVE_ 43 gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>;
44 #cooling-cells = <2>; 44 #cooling-cells = <2>;
45 pinctrl-names = "default"; 45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_gpio_fan 46 pinctrl-0 = <&pinctrl_gpio_fan>;
47 status = "okay"; 47 status = "okay";
48 }; 48 };
49 }; 49 };
50 50
51 &A53_0 { 51 &A53_0 {
52 cpu-supply = <&buck2>; 52 cpu-supply = <&buck2>;
53 }; 53 };
54 54
55 &A53_1 { 55 &A53_1 {
56 cpu-supply = <&buck2>; 56 cpu-supply = <&buck2>;
57 }; 57 };
58 58
59 &A53_2 { 59 &A53_2 {
60 cpu-supply = <&buck2>; 60 cpu-supply = <&buck2>;
61 }; 61 };
62 62
63 &A53_3 { 63 &A53_3 {
64 cpu-supply = <&buck2>; 64 cpu-supply = <&buck2>;
65 }; 65 };
66 66
67 &cpu_thermal { 67 &cpu_thermal {
68 trips { 68 trips {
69 cpu_alert0: trip0 { 69 cpu_alert0: trip0 {
70 temperature = <75000>; 70 temperature = <75000>;
71 hysteresis = <2000>; 71 hysteresis = <2000>;
72 type = "passive"; 72 type = "passive";
73 }; 73 };
74 74
75 cpu_alert1: trip1 { 75 cpu_alert1: trip1 {
76 temperature = <80000>; 76 temperature = <80000>;
77 hysteresis = <2000>; 77 hysteresis = <2000>;
78 type = "passive"; 78 type = "passive";
79 }; 79 };
80 80
81 cpu_crit0: trip3 { 81 cpu_crit0: trip3 {
82 temperature = <90000>; 82 temperature = <90000>;
83 hysteresis = <2000>; 83 hysteresis = <2000>;
84 type = "critical"; 84 type = "critical";
85 }; 85 };
86 86
87 fan_toggle0: trip4 { 87 fan_toggle0: trip4 {
88 temperature = <65000>; 88 temperature = <65000>;
89 hysteresis = <10000>; 89 hysteresis = <10000>;
90 type = "active"; 90 type = "active";
91 }; 91 };
92 }; 92 };
93 93
94 cooling-maps { 94 cooling-maps {
95 map0 { 95 map0 {
96 trip = <&cpu_alert0>; 96 trip = <&cpu_alert0>;
97 cooling-device = 97 cooling-device =
98 <&A53_0 0 1>; /* Exclu 98 <&A53_0 0 1>; /* Exclude highest OPP */
99 }; 99 };
100 100
101 map1 { 101 map1 {
102 trip = <&cpu_alert1>; 102 trip = <&cpu_alert1>;
103 cooling-device = 103 cooling-device =
104 <&A53_0 0 2>; /* Exclu 104 <&A53_0 0 2>; /* Exclude two highest OPPs */
105 }; 105 };
106 106
107 map4 { 107 map4 {
108 trip = <&fan_toggle0>; 108 trip = <&fan_toggle0>;
109 cooling-device = <&fan 109 cooling-device = <&fan 0 1>;
110 }; 110 };
111 }; 111 };
112 }; 112 };
113 113
114 &i2c1 { 114 &i2c1 {
115 clock-frequency = <400000>; 115 clock-frequency = <400000>;
116 pinctrl-names = "default"; 116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c1>; 117 pinctrl-0 = <&pinctrl_i2c1>;
118 status = "okay"; 118 status = "okay";
119 119
120 pmic: pmic@4b { 120 pmic: pmic@4b {
121 compatible = "rohm,bd71837"; 121 compatible = "rohm,bd71837";
122 reg = <0x4b>; 122 reg = <0x4b>;
123 pinctrl-names = "default"; 123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_pmic>; 124 pinctrl-0 = <&pinctrl_pmic>;
125 #clock-cells = <0>; 125 #clock-cells = <0>;
126 clocks = <&pmic_osc>; 126 clocks = <&pmic_osc>;
127 clock-output-names = "pmic_clk 127 clock-output-names = "pmic_clk";
128 interrupt-parent = <&gpio1>; 128 interrupt-parent = <&gpio1>;
129 interrupts = <3 IRQ_TYPE_LEVEL 129 interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
130 130
131 regulators { 131 regulators {
132 buck1: BUCK1 { 132 buck1: BUCK1 {
133 regulator-name 133 regulator-name = "buck1";
134 regulator-min- 134 regulator-min-microvolt = <700000>;
135 regulator-max- 135 regulator-max-microvolt = <1300000>;
136 regulator-boot 136 regulator-boot-on;
137 regulator-alwa 137 regulator-always-on;
138 regulator-ramp 138 regulator-ramp-delay = <1250>;
139 rohm,dvs-run-v 139 rohm,dvs-run-voltage = <900000>;
140 rohm,dvs-idle- 140 rohm,dvs-idle-voltage = <900000>;
141 rohm,dvs-suspe 141 rohm,dvs-suspend-voltage = <800000>;
142 }; 142 };
143 143
144 buck2: BUCK2 { 144 buck2: BUCK2 {
145 regulator-name 145 regulator-name = "buck2";
146 regulator-min- 146 regulator-min-microvolt = <850000>;
147 regulator-max- 147 regulator-max-microvolt = <1000000>;
148 regulator-boot 148 regulator-boot-on;
149 regulator-alwa 149 regulator-always-on;
150 rohm,dvs-run-v 150 rohm,dvs-run-voltage = <1000000>;
151 rohm,dvs-idle- 151 rohm,dvs-idle-voltage = <900000>;
152 }; 152 };
153 153
154 buck3: BUCK3 { 154 buck3: BUCK3 {
155 regulator-name 155 regulator-name = "buck3";
156 regulator-min- 156 regulator-min-microvolt = <700000>;
157 regulator-max- 157 regulator-max-microvolt = <1300000>;
158 regulator-boot 158 regulator-boot-on;
159 rohm,dvs-run-v 159 rohm,dvs-run-voltage = <900000>;
160 }; 160 };
161 161
162 buck4: BUCK4 { 162 buck4: BUCK4 {
163 regulator-name 163 regulator-name = "buck4";
164 regulator-min- 164 regulator-min-microvolt = <700000>;
165 regulator-max- 165 regulator-max-microvolt = <1300000>;
166 regulator-boot 166 regulator-boot-on;
167 regulator-alwa 167 regulator-always-on;
168 rohm,dvs-run-v 168 rohm,dvs-run-voltage = <900000>;
169 }; 169 };
170 170
171 buck5: BUCK5 { 171 buck5: BUCK5 {
172 regulator-name 172 regulator-name = "buck5";
173 regulator-min- 173 regulator-min-microvolt = <700000>;
174 regulator-max- 174 regulator-max-microvolt = <1350000>;
175 regulator-boot 175 regulator-boot-on;
176 regulator-alwa 176 regulator-always-on;
177 }; 177 };
178 178
179 buck6: BUCK6 { 179 buck6: BUCK6 {
180 regulator-name 180 regulator-name = "buck6";
181 regulator-min- 181 regulator-min-microvolt = <3000000>;
182 regulator-max- 182 regulator-max-microvolt = <3300000>;
183 regulator-boot 183 regulator-boot-on;
184 regulator-alwa 184 regulator-always-on;
185 }; 185 };
186 186
187 buck7: BUCK7 { 187 buck7: BUCK7 {
188 regulator-name 188 regulator-name = "buck7";
189 regulator-min- 189 regulator-min-microvolt = <1605000>;
190 regulator-max- 190 regulator-max-microvolt = <1995000>;
191 regulator-boot 191 regulator-boot-on;
192 regulator-alwa 192 regulator-always-on;
193 }; 193 };
194 194
195 buck8: BUCK8 { 195 buck8: BUCK8 {
196 regulator-name 196 regulator-name = "buck8";
197 regulator-min- 197 regulator-min-microvolt = <800000>;
198 regulator-max- 198 regulator-max-microvolt = <1400000>;
199 regulator-boot 199 regulator-boot-on;
200 regulator-alwa 200 regulator-always-on;
201 }; 201 };
202 202
203 ldo1: LDO1 { 203 ldo1: LDO1 {
204 regulator-name 204 regulator-name = "ldo1";
205 regulator-min- 205 regulator-min-microvolt = <3000000>;
206 regulator-max- 206 regulator-max-microvolt = <3300000>;
207 regulator-boot 207 regulator-boot-on;
208 regulator-alwa 208 regulator-always-on;
209 }; 209 };
210 210
211 ldo2: LDO2 { 211 ldo2: LDO2 {
212 regulator-name 212 regulator-name = "ldo2";
213 regulator-min- 213 regulator-min-microvolt = <900000>;
214 regulator-max- 214 regulator-max-microvolt = <900000>;
215 regulator-boot 215 regulator-boot-on;
216 regulator-alwa 216 regulator-always-on;
217 }; 217 };
218 218
219 ldo3: LDO3 { 219 ldo3: LDO3 {
220 regulator-name 220 regulator-name = "ldo3";
221 regulator-min- 221 regulator-min-microvolt = <1800000>;
222 regulator-max- 222 regulator-max-microvolt = <3300000>;
223 regulator-boot 223 regulator-boot-on;
224 regulator-alwa 224 regulator-always-on;
225 }; 225 };
226 226
227 ldo4: LDO4 { 227 ldo4: LDO4 {
228 regulator-name 228 regulator-name = "ldo4";
229 regulator-min- 229 regulator-min-microvolt = <900000>;
230 regulator-max- 230 regulator-max-microvolt = <1800000>;
231 regulator-boot 231 regulator-boot-on;
232 regulator-alwa 232 regulator-always-on;
233 }; 233 };
234 234
235 ldo5: LDO5 { 235 ldo5: LDO5 {
236 regulator-name 236 regulator-name = "ldo5";
237 regulator-min- 237 regulator-min-microvolt = <1800000>;
238 regulator-max- 238 regulator-max-microvolt = <3300000>;
239 regulator-boot 239 regulator-boot-on;
240 regulator-alwa 240 regulator-always-on;
241 }; 241 };
242 242
243 ldo6: LDO6 { 243 ldo6: LDO6 {
244 regulator-name 244 regulator-name = "ldo6";
245 regulator-min- 245 regulator-min-microvolt = <900000>;
246 regulator-max- 246 regulator-max-microvolt = <1800000>;
247 regulator-boot 247 regulator-boot-on;
248 regulator-alwa 248 regulator-always-on;
249 }; 249 };
250 250
251 ldo7: LDO7 { 251 ldo7: LDO7 {
252 regulator-name 252 regulator-name = "ldo7";
253 regulator-min- 253 regulator-min-microvolt = <1800000>;
254 regulator-max- 254 regulator-max-microvolt = <3300000>;
255 regulator-boot 255 regulator-boot-on;
256 regulator-alwa 256 regulator-always-on;
257 }; 257 };
258 }; 258 };
259 }; 259 };
260 }; 260 };
261 261
262 &fec1 { 262 &fec1 {
263 pinctrl-names = "default"; 263 pinctrl-names = "default";
264 pinctrl-0 = <&pinctrl_fec1>; 264 pinctrl-0 = <&pinctrl_fec1>;
265 phy-mode = "rgmii-id"; 265 phy-mode = "rgmii-id";
266 phy-handle = <ðphy0>; 266 phy-handle = <ðphy0>;
267 fsl,magic-packet; 267 fsl,magic-packet;
268 status = "okay"; 268 status = "okay";
269 269
270 mdio { 270 mdio {
271 #address-cells = <1>; 271 #address-cells = <1>;
272 #size-cells = <0>; 272 #size-cells = <0>;
273 ethphy0: ethernet-phy@0 { 273 ethphy0: ethernet-phy@0 {
274 compatible = "ethernet 274 compatible = "ethernet-phy-ieee802.3-c22";
275 reg = <0>; 275 reg = <0>;
276 reset-gpios = <&gpio1 276 reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
277 reset-assert-us = <100 277 reset-assert-us = <10000>;
278 reset-deassert-us = <5 278 reset-deassert-us = <50000>;
279 }; 279 };
280 }; 280 };
281 }; 281 };
282 282
283 &uart1 { 283 &uart1 {
284 pinctrl-names = "default"; 284 pinctrl-names = "default";
285 pinctrl-0 = <&pinctrl_uart1>; 285 pinctrl-0 = <&pinctrl_uart1>;
286 status = "okay"; 286 status = "okay";
287 }; 287 };
288 288
289 &usdhc1 { 289 &usdhc1 {
290 pinctrl-names = "default", "state_100m 290 pinctrl-names = "default", "state_100mhz", "state_200mhz";
291 pinctrl-0 = <&pinctrl_usdhc1>; 291 pinctrl-0 = <&pinctrl_usdhc1>;
292 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 292 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
293 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 293 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
294 bus-width = <8>; 294 bus-width = <8>;
295 non-removable; 295 non-removable;
296 status = "okay"; 296 status = "okay";
297 }; 297 };
298 298
299 &usdhc2 { 299 &usdhc2 {
300 pinctrl-names = "default", "state_100m 300 pinctrl-names = "default", "state_100mhz", "state_200mhz";
301 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 301 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
302 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 302 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
303 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 303 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
304 bus-width = <4>; 304 bus-width = <4>;
305 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 305 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
306 vmmc-supply = <®_usdhc2_vmmc>; 306 vmmc-supply = <®_usdhc2_vmmc>;
307 status = "okay"; 307 status = "okay";
308 }; 308 };
309 309
310 &usb3_phy0 { 310 &usb3_phy0 {
311 status = "okay"; 311 status = "okay";
312 }; 312 };
313 313
314 &usb_dwc3_0 { 314 &usb_dwc3_0 {
315 dr_mode = "otg"; 315 dr_mode = "otg";
316 status = "okay"; 316 status = "okay";
317 }; 317 };
318 318
319 &usb3_phy1 { 319 &usb3_phy1 {
320 status = "okay"; 320 status = "okay";
321 }; 321 };
322 322
323 &usb_dwc3_1 { 323 &usb_dwc3_1 {
324 dr_mode = "host"; 324 dr_mode = "host";
325 status = "okay"; 325 status = "okay";
326 }; 326 };
327 327
328 &wdog1 { 328 &wdog1 {
329 pinctrl-names = "default"; 329 pinctrl-names = "default";
330 pinctrl-0 = <&pinctrl_wdog>; 330 pinctrl-0 = <&pinctrl_wdog>;
331 fsl,ext-reset-output; 331 fsl,ext-reset-output;
332 status = "okay"; 332 status = "okay";
333 }; 333 };
334 334
335 &iomuxc { 335 &iomuxc {
336 pinctrl_fec1: fec1grp { 336 pinctrl_fec1: fec1grp {
337 fsl,pins = < 337 fsl,pins = <
338 MX8MQ_IOMUXC_ENET_MDC_ 338 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
339 MX8MQ_IOMUXC_ENET_MDIO 339 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
340 MX8MQ_IOMUXC_ENET_TD3_ 340 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
341 MX8MQ_IOMUXC_ENET_TD2_ 341 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
342 MX8MQ_IOMUXC_ENET_TD1_ 342 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
343 MX8MQ_IOMUXC_ENET_TD0_ 343 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
344 MX8MQ_IOMUXC_ENET_RD3_ 344 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
345 MX8MQ_IOMUXC_ENET_RD2_ 345 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
346 MX8MQ_IOMUXC_ENET_RD1_ 346 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
347 MX8MQ_IOMUXC_ENET_RD0_ 347 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
348 MX8MQ_IOMUXC_ENET_TXC_ 348 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
349 MX8MQ_IOMUXC_ENET_RXC_ 349 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
350 MX8MQ_IOMUXC_ENET_RX_C 350 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
351 MX8MQ_IOMUXC_ENET_TX_C 351 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
352 MX8MQ_IOMUXC_GPIO1_IO0 352 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
353 >; 353 >;
354 }; 354 };
355 355
356 pinctrl_gpio_fan: gpiofangrp { 356 pinctrl_gpio_fan: gpiofangrp {
357 fsl,pins = < 357 fsl,pins = <
358 MX8MQ_IOMUXC_NAND_CLE_ 358 MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x16
359 >; 359 >;
360 }; 360 };
361 361
362 pinctrl_i2c1: i2c1grp { 362 pinctrl_i2c1: i2c1grp {
363 fsl,pins = < 363 fsl,pins = <
364 MX8MQ_IOMUXC_I2C1_SCL_ 364 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
365 MX8MQ_IOMUXC_I2C1_SDA_ 365 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
366 >; 366 >;
367 }; 367 };
368 368
369 pinctrl_pmic: pmicirqgrp { 369 pinctrl_pmic: pmicirqgrp {
370 fsl,pins = < 370 fsl,pins = <
371 MX8MQ_IOMUXC_GPIO1_IO0 371 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
372 >; 372 >;
373 }; 373 };
374 374
375 pinctrl_uart1: uart1grp { 375 pinctrl_uart1: uart1grp {
376 fsl,pins = < 376 fsl,pins = <
377 MX8MQ_IOMUXC_UART1_RXD 377 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
378 MX8MQ_IOMUXC_UART1_TXD 378 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
379 >; 379 >;
380 }; 380 };
381 381
382 pinctrl_usdhc1: usdhc1grp { 382 pinctrl_usdhc1: usdhc1grp {
383 fsl,pins = < 383 fsl,pins = <
384 MX8MQ_IOMUXC_SD1_CLK_U 384 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
385 MX8MQ_IOMUXC_SD1_CMD_U 385 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
386 MX8MQ_IOMUXC_SD1_DATA0 386 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
387 MX8MQ_IOMUXC_SD1_DATA1 387 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
388 MX8MQ_IOMUXC_SD1_DATA2 388 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
389 MX8MQ_IOMUXC_SD1_DATA3 389 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
390 MX8MQ_IOMUXC_SD1_DATA4 390 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
391 MX8MQ_IOMUXC_SD1_DATA5 391 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
392 MX8MQ_IOMUXC_SD1_DATA6 392 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
393 MX8MQ_IOMUXC_SD1_DATA7 393 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
394 MX8MQ_IOMUXC_SD1_STROB 394 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
395 MX8MQ_IOMUXC_SD1_RESET 395 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
396 >; 396 >;
397 }; 397 };
398 398
399 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr 399 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
400 fsl,pins = < 400 fsl,pins = <
401 MX8MQ_IOMUXC_SD1_CLK_U 401 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
402 MX8MQ_IOMUXC_SD1_CMD_U 402 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
403 MX8MQ_IOMUXC_SD1_DATA0 403 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
404 MX8MQ_IOMUXC_SD1_DATA1 404 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
405 MX8MQ_IOMUXC_SD1_DATA2 405 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
406 MX8MQ_IOMUXC_SD1_DATA3 406 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
407 MX8MQ_IOMUXC_SD1_DATA4 407 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
408 MX8MQ_IOMUXC_SD1_DATA5 408 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
409 MX8MQ_IOMUXC_SD1_DATA6 409 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
410 MX8MQ_IOMUXC_SD1_DATA7 410 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
411 MX8MQ_IOMUXC_SD1_STROB 411 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
412 MX8MQ_IOMUXC_SD1_RESET 412 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
413 >; 413 >;
414 }; 414 };
415 415
416 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr 416 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
417 fsl,pins = < 417 fsl,pins = <
418 MX8MQ_IOMUXC_SD1_CLK_U 418 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
419 MX8MQ_IOMUXC_SD1_CMD_U 419 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
420 MX8MQ_IOMUXC_SD1_DATA0 420 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
421 MX8MQ_IOMUXC_SD1_DATA1 421 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
422 MX8MQ_IOMUXC_SD1_DATA2 422 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
423 MX8MQ_IOMUXC_SD1_DATA3 423 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
424 MX8MQ_IOMUXC_SD1_DATA4 424 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
425 MX8MQ_IOMUXC_SD1_DATA5 425 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
426 MX8MQ_IOMUXC_SD1_DATA6 426 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
427 MX8MQ_IOMUXC_SD1_DATA7 427 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
428 MX8MQ_IOMUXC_SD1_STROB 428 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
429 MX8MQ_IOMUXC_SD1_RESET 429 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
430 >; 430 >;
431 }; 431 };
432 432
433 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 433 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
434 fsl,pins = < 434 fsl,pins = <
435 MX8MQ_IOMUXC_SD2_CD_B_ 435 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
436 MX8MQ_IOMUXC_SD2_RESET 436 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
437 >; 437 >;
438 }; 438 };
439 439
440 pinctrl_usdhc2: usdhc2grp { 440 pinctrl_usdhc2: usdhc2grp {
441 fsl,pins = < 441 fsl,pins = <
442 MX8MQ_IOMUXC_SD2_CLK_U 442 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
443 MX8MQ_IOMUXC_SD2_CMD_U 443 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
444 MX8MQ_IOMUXC_SD2_DATA0 444 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
445 MX8MQ_IOMUXC_SD2_DATA1 445 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
446 MX8MQ_IOMUXC_SD2_DATA2 446 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
447 MX8MQ_IOMUXC_SD2_DATA3 447 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
448 MX8MQ_IOMUXC_GPIO1_IO0 448 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
449 >; 449 >;
450 }; 450 };
451 451
452 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr 452 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
453 fsl,pins = < 453 fsl,pins = <
454 MX8MQ_IOMUXC_SD2_CLK_U 454 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
455 MX8MQ_IOMUXC_SD2_CMD_U 455 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
456 MX8MQ_IOMUXC_SD2_DATA0 456 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
457 MX8MQ_IOMUXC_SD2_DATA1 457 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
458 MX8MQ_IOMUXC_SD2_DATA2 458 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
459 MX8MQ_IOMUXC_SD2_DATA3 459 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
460 MX8MQ_IOMUXC_GPIO1_IO0 460 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
461 >; 461 >;
462 }; 462 };
463 463
464 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr 464 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
465 fsl,pins = < 465 fsl,pins = <
466 MX8MQ_IOMUXC_SD2_CLK_U 466 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
467 MX8MQ_IOMUXC_SD2_CMD_U 467 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
468 MX8MQ_IOMUXC_SD2_DATA0 468 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
469 MX8MQ_IOMUXC_SD2_DATA1 469 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
470 MX8MQ_IOMUXC_SD2_DATA2 470 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
471 MX8MQ_IOMUXC_SD2_DATA3 471 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
472 MX8MQ_IOMUXC_GPIO1_IO0 472 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
473 >; 473 >;
474 }; 474 };
475 475
476 pinctrl_wdog: wdoggrp { 476 pinctrl_wdog: wdoggrp {
477 fsl,pins = < 477 fsl,pins = <
478 MX8MQ_IOMUXC_GPIO1_IO0 478 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
479 >; 479 >;
480 }; 480 };
481 }; 481 };
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