1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright 2018 Wandboard, Org.
4 * Copyright 2017 NXP
5 *
6 * Author: Richard Hu <hakahu@gmail.com>
7 */
8
9 /dts-v1/;
10
11 #include "imx8mq.dtsi"
12 #include <dt-bindings/interrupt-controller/irq
13
14 / {
15 model = "TechNexion PICO-PI-8M";
16 compatible = "technexion,pico-pi-imx8m
17
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 pmic_osc: clock-pmic {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <32768>;
26 clock-output-names = "pmic_osc
27 };
28
29 reg_usb_otg_vbus: regulator-usb-otg-vb
30 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_otg_vbus
32 compatible = "regulator-fixed"
33 regulator-name = "usb_otg_vbus
34 regulator-min-microvolt = <500
35 regulator-max-microvolt = <500
36 gpio = <&gpio3 14 GPIO_ACTIVE_
37 };
38 };
39
40 &fec1 {
41 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_fec1 &pinctrl_en
43 phy-mode = "rgmii-id";
44 phy-handle = <ðphy0>;
45 fsl,magic-packet;
46 status = "okay";
47
48 mdio {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ethphy0: ethernet-phy@1 {
53 compatible = "ethernet
54 reg = <1>;
55 };
56 };
57 };
58
59 &i2c1 {
60 clock-frequency = <100000>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_i2c1>;
63 status = "okay";
64
65 pmic: pmic@4b {
66 reg = <0x4b>;
67 compatible = "rohm,bd71837";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pmic>;
70 #clock-cells = <0>;
71 clocks = <&pmic_osc>;
72 clock-names = "osc";
73 clock-output-names = "pmic_clk
74 interrupt-parent = <&gpio1>;
75 interrupts = <3 IRQ_TYPE_LEVEL
76
77 regulators {
78 buck1: BUCK1 {
79 regulator-name
80 regulator-min-
81 regulator-max-
82 regulator-boot
83 regulator-ramp
84 rohm,dvs-run-v
85 rohm,dvs-idle-
86 rohm,dvs-suspe
87 };
88
89 buck2: BUCK2 {
90 regulator-name
91 regulator-min-
92 regulator-max-
93 regulator-boot
94 regulator-ramp
95 rohm,dvs-run-v
96 rohm,dvs-idle-
97 };
98
99 buck3: BUCK3 {
100 regulator-name
101 regulator-min-
102 regulator-max-
103 regulator-boot
104 rohm,dvs-run-v
105 };
106
107 buck4: BUCK4 {
108 regulator-name
109 regulator-min-
110 regulator-max-
111 regulator-boot
112 rohm,dvs-run-v
113 };
114
115 buck5: BUCK5 {
116 regulator-name
117 regulator-min-
118 regulator-max-
119 regulator-boot
120 };
121
122 buck6: BUCK6 {
123 regulator-name
124 regulator-min-
125 regulator-max-
126 regulator-boot
127 };
128
129 buck7: BUCK7 {
130 regulator-name
131 regulator-min-
132 regulator-max-
133 regulator-boot
134 };
135
136 buck8: BUCK8 {
137 regulator-name
138 regulator-min-
139 regulator-max-
140 regulator-boot
141 };
142
143 ldo1: LDO1 {
144 regulator-name
145 regulator-min-
146 regulator-max-
147 regulator-boot
148 regulator-alwa
149 };
150
151 ldo2: LDO2 {
152 regulator-name
153 regulator-min-
154 regulator-max-
155 regulator-boot
156 regulator-alwa
157 };
158
159 ldo3: LDO3 {
160 regulator-name
161 regulator-min-
162 regulator-max-
163 regulator-boot
164 };
165
166 ldo4: LDO4 {
167 regulator-name
168 regulator-min-
169 regulator-max-
170 regulator-boot
171 };
172
173 ldo5: LDO5 {
174 regulator-name
175 regulator-min-
176 regulator-max-
177 regulator-boot
178 };
179
180 ldo6: LDO6 {
181 regulator-name
182 regulator-min-
183 regulator-max-
184 regulator-boot
185 };
186
187 ldo7: LDO7 {
188 regulator-name
189 regulator-min-
190 regulator-max-
191 regulator-boot
192 };
193 };
194 };
195 };
196
197 &i2c2 {
198 clock-frequency = <100000>;
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_i2c2>;
201 status = "okay";
202 };
203
204 &uart1 { /* console */
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart1>;
207 status = "okay";
208 };
209
210 &usdhc1 {
211 assigned-clocks = <&clk IMX8MQ_CLK_USD
212 assigned-clock-rates = <400000000>;
213 pinctrl-names = "default", "state_100m
214 pinctrl-0 = <&pinctrl_usdhc1>;
215 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
216 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
217 bus-width = <8>;
218 non-removable;
219 status = "okay";
220 };
221
222 &usdhc2 {
223 assigned-clocks = <&clk IMX8MQ_CLK_USD
224 assigned-clock-rates = <200000000>;
225 pinctrl-names = "default", "state_100m
226 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct
227 pinctrl-1 = <&pinctrl_usdhc2_100mhz>,
228 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,
229 bus-width = <4>;
230 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>
231 status = "okay";
232 };
233
234 &usb3_phy0 {
235 status = "okay";
236 };
237
238 &usb3_phy1 {
239 status = "okay";
240 };
241
242 &usb_dwc3_1 {
243 dr_mode = "host";
244 status = "okay";
245 };
246
247 &wdog1 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_wdog>;
250 fsl,ext-reset-output;
251 status = "okay";
252 };
253
254 &iomuxc {
255 pinctrl_enet_3v3: enet3v3grp {
256 fsl,pins = <
257 MX8MQ_IOMUXC_GPIO1_IO0
258 >;
259 };
260
261 pinctrl_fec1: fec1grp {
262 fsl,pins = <
263 MX8MQ_IOMUXC_ENET_MDC_
264 MX8MQ_IOMUXC_ENET_MDIO
265 MX8MQ_IOMUXC_ENET_TD3_
266 MX8MQ_IOMUXC_ENET_TD2_
267 MX8MQ_IOMUXC_ENET_TD1_
268 MX8MQ_IOMUXC_ENET_TD0_
269 MX8MQ_IOMUXC_ENET_RD3_
270 MX8MQ_IOMUXC_ENET_RD2_
271 MX8MQ_IOMUXC_ENET_RD1_
272 MX8MQ_IOMUXC_ENET_RD0_
273 MX8MQ_IOMUXC_ENET_TXC_
274 MX8MQ_IOMUXC_ENET_RXC_
275 MX8MQ_IOMUXC_ENET_RX_C
276 MX8MQ_IOMUXC_ENET_TX_C
277 MX8MQ_IOMUXC_GPIO1_IO0
278 >;
279 };
280
281 pinctrl_i2c1: i2c1grp {
282 fsl,pins = <
283 MX8MQ_IOMUXC_I2C1_SCL_
284 MX8MQ_IOMUXC_I2C1_SDA_
285 >;
286 };
287
288 pinctrl_i2c2: i2c2grp {
289 fsl,pins = <
290 MX8MQ_IOMUXC_I2C2_SCL_
291 MX8MQ_IOMUXC_I2C2_SDA_
292 >;
293 };
294
295 pinctrl_otg_vbus: otgvbusgrp {
296 fsl,pins = <
297 MX8MQ_IOMUXC_NAND_DQS_
298 >;
299 };
300
301 pinctrl_pmic: pmicirqgrp {
302 fsl,pins = <
303 MX8MQ_IOMUXC_GPIO1_IO0
304 >;
305 };
306
307 pinctrl_uart1: uart1grp {
308 fsl,pins = <
309 MX8MQ_IOMUXC_UART1_RXD
310 MX8MQ_IOMUXC_UART1_TXD
311 >;
312 };
313
314 pinctrl_uart2: uart2grp {
315 fsl,pins = <
316 MX8MQ_IOMUXC_UART2_RXD
317 MX8MQ_IOMUXC_UART2_TXD
318 MX8MQ_IOMUXC_UART4_RXD
319 MX8MQ_IOMUXC_UART4_TXD
320 >;
321 };
322
323 pinctrl_usdhc1: usdhc1grp {
324 fsl,pins = <
325 MX8MQ_IOMUXC_SD1_CLK_U
326 MX8MQ_IOMUXC_SD1_CMD_U
327 MX8MQ_IOMUXC_SD1_DATA0
328 MX8MQ_IOMUXC_SD1_DATA1
329 MX8MQ_IOMUXC_SD1_DATA2
330 MX8MQ_IOMUXC_SD1_DATA3
331 MX8MQ_IOMUXC_SD1_DATA4
332 MX8MQ_IOMUXC_SD1_DATA5
333 MX8MQ_IOMUXC_SD1_DATA6
334 MX8MQ_IOMUXC_SD1_DATA7
335 MX8MQ_IOMUXC_SD1_STROB
336 >;
337 };
338
339 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr
340 fsl,pins = <
341 MX8MQ_IOMUXC_SD1_CLK_U
342 MX8MQ_IOMUXC_SD1_CMD_U
343 MX8MQ_IOMUXC_SD1_DATA0
344 MX8MQ_IOMUXC_SD1_DATA1
345 MX8MQ_IOMUXC_SD1_DATA2
346 MX8MQ_IOMUXC_SD1_DATA3
347 MX8MQ_IOMUXC_SD1_DATA4
348 MX8MQ_IOMUXC_SD1_DATA5
349 MX8MQ_IOMUXC_SD1_DATA6
350 MX8MQ_IOMUXC_SD1_DATA7
351 MX8MQ_IOMUXC_SD1_STROB
352 >;
353 };
354
355 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr
356 fsl,pins = <
357 MX8MQ_IOMUXC_SD1_CLK_U
358 MX8MQ_IOMUXC_SD1_CMD_U
359 MX8MQ_IOMUXC_SD1_DATA0
360 MX8MQ_IOMUXC_SD1_DATA1
361 MX8MQ_IOMUXC_SD1_DATA2
362 MX8MQ_IOMUXC_SD1_DATA3
363 MX8MQ_IOMUXC_SD1_DATA4
364 MX8MQ_IOMUXC_SD1_DATA5
365 MX8MQ_IOMUXC_SD1_DATA6
366 MX8MQ_IOMUXC_SD1_DATA7
367 MX8MQ_IOMUXC_SD1_STROB
368 >;
369 };
370
371 pinctrl_usdhc2_gpio: usdhc2gpiogrp {
372 fsl,pins = <
373 MX8MQ_IOMUXC_SD2_CD_B_
374 >;
375 };
376
377 pinctrl_usdhc2: usdhc2grp {
378 fsl,pins = <
379 MX8MQ_IOMUXC_SD2_CLK_U
380 MX8MQ_IOMUXC_SD2_CMD_U
381 MX8MQ_IOMUXC_SD2_DATA0
382 MX8MQ_IOMUXC_SD2_DATA1
383 MX8MQ_IOMUXC_SD2_DATA2
384 MX8MQ_IOMUXC_SD2_DATA3
385 MX8MQ_IOMUXC_GPIO1_IO0
386 >;
387 };
388
389 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr
390 fsl,pins = <
391 MX8MQ_IOMUXC_SD2_CLK_U
392 MX8MQ_IOMUXC_SD2_CMD_U
393 MX8MQ_IOMUXC_SD2_DATA0
394 MX8MQ_IOMUXC_SD2_DATA1
395 MX8MQ_IOMUXC_SD2_DATA2
396 MX8MQ_IOMUXC_SD2_DATA3
397 MX8MQ_IOMUXC_GPIO1_IO0
398 >;
399 };
400
401 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr
402 fsl,pins = <
403 MX8MQ_IOMUXC_SD2_CLK_U
404 MX8MQ_IOMUXC_SD2_CMD_U
405 MX8MQ_IOMUXC_SD2_DATA0
406 MX8MQ_IOMUXC_SD2_DATA1
407 MX8MQ_IOMUXC_SD2_DATA2
408 MX8MQ_IOMUXC_SD2_DATA3
409 MX8MQ_IOMUXC_GPIO1_IO0
410 >;
411 };
412
413 pinctrl_wdog: wdoggrp {
414 fsl,pins = <
415 MX8MQ_IOMUXC_GPIO1_IO0
416 >;
417 };
418 };
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