1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * Copyright 2018 Wandboard, Org. 3 * Copyright 2018 Wandboard, Org.
4 * Copyright 2017 NXP 4 * Copyright 2017 NXP
5 * 5 *
6 * Author: Richard Hu <hakahu@gmail.com> 6 * Author: Richard Hu <hakahu@gmail.com>
7 */ 7 */
8 8
9 /dts-v1/; 9 /dts-v1/;
10 10
11 #include "imx8mq.dtsi" 11 #include "imx8mq.dtsi"
12 #include <dt-bindings/interrupt-controller/irq <<
13 12
14 / { 13 / {
15 model = "TechNexion PICO-PI-8M"; 14 model = "TechNexion PICO-PI-8M";
16 compatible = "technexion,pico-pi-imx8m 15 compatible = "technexion,pico-pi-imx8m", "fsl,imx8mq";
17 16
18 chosen { 17 chosen {
19 stdout-path = &uart1; 18 stdout-path = &uart1;
20 }; 19 };
21 20
22 pmic_osc: clock-pmic { 21 pmic_osc: clock-pmic {
23 compatible = "fixed-clock"; 22 compatible = "fixed-clock";
24 #clock-cells = <0>; 23 #clock-cells = <0>;
25 clock-frequency = <32768>; 24 clock-frequency = <32768>;
26 clock-output-names = "pmic_osc 25 clock-output-names = "pmic_osc";
27 }; 26 };
28 27
29 reg_usb_otg_vbus: regulator-usb-otg-vb 28 reg_usb_otg_vbus: regulator-usb-otg-vbus {
30 pinctrl-names = "default"; 29 pinctrl-names = "default";
31 pinctrl-0 = <&pinctrl_otg_vbus 30 pinctrl-0 = <&pinctrl_otg_vbus>;
32 compatible = "regulator-fixed" 31 compatible = "regulator-fixed";
33 regulator-name = "usb_otg_vbus 32 regulator-name = "usb_otg_vbus";
34 regulator-min-microvolt = <500 33 regulator-min-microvolt = <5000000>;
35 regulator-max-microvolt = <500 34 regulator-max-microvolt = <5000000>;
36 gpio = <&gpio3 14 GPIO_ACTIVE_ 35 gpio = <&gpio3 14 GPIO_ACTIVE_LOW>;
37 }; 36 };
38 }; 37 };
39 38
40 &fec1 { 39 &fec1 {
41 pinctrl-names = "default"; 40 pinctrl-names = "default";
42 pinctrl-0 = <&pinctrl_fec1 &pinctrl_en 41 pinctrl-0 = <&pinctrl_fec1 &pinctrl_enet_3v3>;
43 phy-mode = "rgmii-id"; 42 phy-mode = "rgmii-id";
44 phy-handle = <ðphy0>; 43 phy-handle = <ðphy0>;
45 fsl,magic-packet; 44 fsl,magic-packet;
46 status = "okay"; 45 status = "okay";
47 46
48 mdio { 47 mdio {
49 #address-cells = <1>; 48 #address-cells = <1>;
50 #size-cells = <0>; 49 #size-cells = <0>;
51 50
52 ethphy0: ethernet-phy@1 { 51 ethphy0: ethernet-phy@1 {
53 compatible = "ethernet 52 compatible = "ethernet-phy-ieee802.3-c22";
54 reg = <1>; 53 reg = <1>;
55 }; 54 };
56 }; 55 };
57 }; 56 };
58 57
59 &i2c1 { 58 &i2c1 {
60 clock-frequency = <100000>; 59 clock-frequency = <100000>;
61 pinctrl-names = "default"; 60 pinctrl-names = "default";
62 pinctrl-0 = <&pinctrl_i2c1>; 61 pinctrl-0 = <&pinctrl_i2c1>;
63 status = "okay"; 62 status = "okay";
64 63
65 pmic: pmic@4b { 64 pmic: pmic@4b {
66 reg = <0x4b>; 65 reg = <0x4b>;
67 compatible = "rohm,bd71837"; 66 compatible = "rohm,bd71837";
68 pinctrl-names = "default"; 67 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pmic>; 68 pinctrl-0 = <&pinctrl_pmic>;
70 #clock-cells = <0>; <<
71 clocks = <&pmic_osc>; 69 clocks = <&pmic_osc>;
72 clock-names = "osc"; 70 clock-names = "osc";
73 clock-output-names = "pmic_clk 71 clock-output-names = "pmic_clk";
74 interrupt-parent = <&gpio1>; 72 interrupt-parent = <&gpio1>;
75 interrupts = <3 IRQ_TYPE_LEVEL !! 73 interrupts = <3 GPIO_ACTIVE_LOW>;
>> 74 interrupt-names = "irq";
76 75
77 regulators { 76 regulators {
78 buck1: BUCK1 { 77 buck1: BUCK1 {
79 regulator-name 78 regulator-name = "buck1";
80 regulator-min- 79 regulator-min-microvolt = <700000>;
81 regulator-max- 80 regulator-max-microvolt = <1300000>;
82 regulator-boot 81 regulator-boot-on;
83 regulator-ramp 82 regulator-ramp-delay = <1250>;
84 rohm,dvs-run-v 83 rohm,dvs-run-voltage = <900000>;
85 rohm,dvs-idle- 84 rohm,dvs-idle-voltage = <850000>;
86 rohm,dvs-suspe 85 rohm,dvs-suspend-voltage = <800000>;
87 }; 86 };
88 87
89 buck2: BUCK2 { 88 buck2: BUCK2 {
90 regulator-name 89 regulator-name = "buck2";
91 regulator-min- 90 regulator-min-microvolt = <700000>;
92 regulator-max- 91 regulator-max-microvolt = <1300000>;
93 regulator-boot 92 regulator-boot-on;
94 regulator-ramp 93 regulator-ramp-delay = <1250>;
95 rohm,dvs-run-v 94 rohm,dvs-run-voltage = <1000000>;
96 rohm,dvs-idle- 95 rohm,dvs-idle-voltage = <900000>;
97 }; 96 };
98 97
99 buck3: BUCK3 { 98 buck3: BUCK3 {
100 regulator-name 99 regulator-name = "buck3";
101 regulator-min- 100 regulator-min-microvolt = <700000>;
102 regulator-max- 101 regulator-max-microvolt = <1300000>;
103 regulator-boot 102 regulator-boot-on;
104 rohm,dvs-run-v 103 rohm,dvs-run-voltage = <1000000>;
105 }; 104 };
106 105
107 buck4: BUCK4 { 106 buck4: BUCK4 {
108 regulator-name 107 regulator-name = "buck4";
109 regulator-min- 108 regulator-min-microvolt = <700000>;
110 regulator-max- 109 regulator-max-microvolt = <1300000>;
111 regulator-boot 110 regulator-boot-on;
112 rohm,dvs-run-v 111 rohm,dvs-run-voltage = <1000000>;
113 }; 112 };
114 113
115 buck5: BUCK5 { 114 buck5: BUCK5 {
116 regulator-name 115 regulator-name = "buck5";
117 regulator-min- 116 regulator-min-microvolt = <700000>;
118 regulator-max- 117 regulator-max-microvolt = <1350000>;
119 regulator-boot 118 regulator-boot-on;
120 }; 119 };
121 120
122 buck6: BUCK6 { 121 buck6: BUCK6 {
123 regulator-name 122 regulator-name = "buck6";
124 regulator-min- 123 regulator-min-microvolt = <3000000>;
125 regulator-max- 124 regulator-max-microvolt = <3300000>;
126 regulator-boot 125 regulator-boot-on;
127 }; 126 };
128 127
129 buck7: BUCK7 { 128 buck7: BUCK7 {
130 regulator-name 129 regulator-name = "buck7";
131 regulator-min- 130 regulator-min-microvolt = <1605000>;
132 regulator-max- 131 regulator-max-microvolt = <1995000>;
133 regulator-boot 132 regulator-boot-on;
134 }; 133 };
135 134
136 buck8: BUCK8 { 135 buck8: BUCK8 {
137 regulator-name 136 regulator-name = "buck8";
138 regulator-min- 137 regulator-min-microvolt = <800000>;
139 regulator-max- 138 regulator-max-microvolt = <1400000>;
140 regulator-boot 139 regulator-boot-on;
141 }; 140 };
142 141
143 ldo1: LDO1 { 142 ldo1: LDO1 {
144 regulator-name 143 regulator-name = "ldo1";
145 regulator-min- 144 regulator-min-microvolt = <3000000>;
146 regulator-max- 145 regulator-max-microvolt = <3300000>;
147 regulator-boot 146 regulator-boot-on;
148 regulator-alwa 147 regulator-always-on;
149 }; 148 };
150 149
151 ldo2: LDO2 { 150 ldo2: LDO2 {
152 regulator-name 151 regulator-name = "ldo2";
153 regulator-min- 152 regulator-min-microvolt = <900000>;
154 regulator-max- 153 regulator-max-microvolt = <900000>;
155 regulator-boot 154 regulator-boot-on;
156 regulator-alwa 155 regulator-always-on;
157 }; 156 };
158 157
159 ldo3: LDO3 { 158 ldo3: LDO3 {
160 regulator-name 159 regulator-name = "ldo3";
161 regulator-min- 160 regulator-min-microvolt = <1800000>;
162 regulator-max- 161 regulator-max-microvolt = <3300000>;
163 regulator-boot 162 regulator-boot-on;
164 }; 163 };
165 164
166 ldo4: LDO4 { 165 ldo4: LDO4 {
167 regulator-name 166 regulator-name = "ldo4";
168 regulator-min- 167 regulator-min-microvolt = <900000>;
169 regulator-max- 168 regulator-max-microvolt = <1800000>;
170 regulator-boot 169 regulator-boot-on;
171 }; 170 };
172 171
173 ldo5: LDO5 { 172 ldo5: LDO5 {
174 regulator-name 173 regulator-name = "ldo5";
175 regulator-min- 174 regulator-min-microvolt = <1800000>;
176 regulator-max- 175 regulator-max-microvolt = <3300000>;
177 regulator-boot 176 regulator-boot-on;
178 }; 177 };
179 178
180 ldo6: LDO6 { 179 ldo6: LDO6 {
181 regulator-name 180 regulator-name = "ldo6";
182 regulator-min- 181 regulator-min-microvolt = <900000>;
183 regulator-max- 182 regulator-max-microvolt = <1800000>;
184 regulator-boot 183 regulator-boot-on;
185 }; 184 };
186 185
187 ldo7: LDO7 { 186 ldo7: LDO7 {
188 regulator-name 187 regulator-name = "ldo7";
189 regulator-min- 188 regulator-min-microvolt = <1800000>;
190 regulator-max- 189 regulator-max-microvolt = <3300000>;
191 regulator-boot 190 regulator-boot-on;
192 }; 191 };
193 }; 192 };
194 }; 193 };
195 }; 194 };
196 195
197 &i2c2 { 196 &i2c2 {
198 clock-frequency = <100000>; 197 clock-frequency = <100000>;
199 pinctrl-names = "default"; 198 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_i2c2>; 199 pinctrl-0 = <&pinctrl_i2c2>;
201 status = "okay"; 200 status = "okay";
202 }; 201 };
203 202
204 &uart1 { /* console */ 203 &uart1 { /* console */
205 pinctrl-names = "default"; 204 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_uart1>; 205 pinctrl-0 = <&pinctrl_uart1>;
207 status = "okay"; 206 status = "okay";
208 }; 207 };
209 208
210 &usdhc1 { 209 &usdhc1 {
211 assigned-clocks = <&clk IMX8MQ_CLK_USD 210 assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>;
212 assigned-clock-rates = <400000000>; 211 assigned-clock-rates = <400000000>;
213 pinctrl-names = "default", "state_100m 212 pinctrl-names = "default", "state_100mhz", "state_200mhz";
214 pinctrl-0 = <&pinctrl_usdhc1>; 213 pinctrl-0 = <&pinctrl_usdhc1>;
215 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 214 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
216 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 215 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
217 bus-width = <8>; 216 bus-width = <8>;
218 non-removable; 217 non-removable;
219 status = "okay"; 218 status = "okay";
220 }; 219 };
221 220
222 &usdhc2 { 221 &usdhc2 {
223 assigned-clocks = <&clk IMX8MQ_CLK_USD 222 assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>;
224 assigned-clock-rates = <200000000>; 223 assigned-clock-rates = <200000000>;
225 pinctrl-names = "default", "state_100m 224 pinctrl-names = "default", "state_100mhz", "state_200mhz";
226 pinctrl-0 = <&pinctrl_usdhc2>, <&pinct 225 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
227 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, 226 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
228 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, 227 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
229 bus-width = <4>; 228 bus-width = <4>;
230 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW> 229 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
231 status = "okay"; 230 status = "okay";
232 }; 231 };
233 232
234 &usb3_phy0 { 233 &usb3_phy0 {
235 status = "okay"; 234 status = "okay";
236 }; 235 };
237 236
238 &usb3_phy1 { 237 &usb3_phy1 {
239 status = "okay"; 238 status = "okay";
240 }; 239 };
241 240
242 &usb_dwc3_1 { 241 &usb_dwc3_1 {
243 dr_mode = "host"; 242 dr_mode = "host";
244 status = "okay"; 243 status = "okay";
245 }; 244 };
246 245
247 &wdog1 { 246 &wdog1 {
248 pinctrl-names = "default"; 247 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_wdog>; 248 pinctrl-0 = <&pinctrl_wdog>;
250 fsl,ext-reset-output; 249 fsl,ext-reset-output;
251 status = "okay"; 250 status = "okay";
252 }; 251 };
253 252
254 &iomuxc { 253 &iomuxc {
255 pinctrl_enet_3v3: enet3v3grp { 254 pinctrl_enet_3v3: enet3v3grp {
256 fsl,pins = < 255 fsl,pins = <
257 MX8MQ_IOMUXC_GPIO1_IO0 256 MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x19
258 >; 257 >;
259 }; 258 };
260 259
261 pinctrl_fec1: fec1grp { 260 pinctrl_fec1: fec1grp {
262 fsl,pins = < 261 fsl,pins = <
263 MX8MQ_IOMUXC_ENET_MDC_ 262 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
264 MX8MQ_IOMUXC_ENET_MDIO 263 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
265 MX8MQ_IOMUXC_ENET_TD3_ 264 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
266 MX8MQ_IOMUXC_ENET_TD2_ 265 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
267 MX8MQ_IOMUXC_ENET_TD1_ 266 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
268 MX8MQ_IOMUXC_ENET_TD0_ 267 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
269 MX8MQ_IOMUXC_ENET_RD3_ 268 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
270 MX8MQ_IOMUXC_ENET_RD2_ 269 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
271 MX8MQ_IOMUXC_ENET_RD1_ 270 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
272 MX8MQ_IOMUXC_ENET_RD0_ 271 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
273 MX8MQ_IOMUXC_ENET_TXC_ 272 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
274 MX8MQ_IOMUXC_ENET_RXC_ 273 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
275 MX8MQ_IOMUXC_ENET_RX_C 274 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
276 MX8MQ_IOMUXC_ENET_TX_C 275 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
277 MX8MQ_IOMUXC_GPIO1_IO0 276 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
278 >; 277 >;
279 }; 278 };
280 279
281 pinctrl_i2c1: i2c1grp { 280 pinctrl_i2c1: i2c1grp {
282 fsl,pins = < 281 fsl,pins = <
283 MX8MQ_IOMUXC_I2C1_SCL_ 282 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
284 MX8MQ_IOMUXC_I2C1_SDA_ 283 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
285 >; 284 >;
286 }; 285 };
287 286
288 pinctrl_i2c2: i2c2grp { 287 pinctrl_i2c2: i2c2grp {
289 fsl,pins = < 288 fsl,pins = <
290 MX8MQ_IOMUXC_I2C2_SCL_ 289 MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x4000007f
291 MX8MQ_IOMUXC_I2C2_SDA_ 290 MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x4000007f
292 >; 291 >;
293 }; 292 };
294 293
295 pinctrl_otg_vbus: otgvbusgrp { 294 pinctrl_otg_vbus: otgvbusgrp {
296 fsl,pins = < 295 fsl,pins = <
297 MX8MQ_IOMUXC_NAND_DQS_ 296 MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14 0x19 /* USB OTG VBUS Enable */
298 >; 297 >;
299 }; 298 };
300 299
301 pinctrl_pmic: pmicirqgrp { !! 300 pinctrl_pmic: pmicirq {
302 fsl,pins = < 301 fsl,pins = <
303 MX8MQ_IOMUXC_GPIO1_IO0 302 MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
304 >; 303 >;
305 }; 304 };
306 305
307 pinctrl_uart1: uart1grp { 306 pinctrl_uart1: uart1grp {
308 fsl,pins = < 307 fsl,pins = <
309 MX8MQ_IOMUXC_UART1_RXD 308 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
310 MX8MQ_IOMUXC_UART1_TXD 309 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
311 >; 310 >;
312 }; 311 };
313 312
314 pinctrl_uart2: uart2grp { 313 pinctrl_uart2: uart2grp {
315 fsl,pins = < 314 fsl,pins = <
316 MX8MQ_IOMUXC_UART2_RXD 315 MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x49
317 MX8MQ_IOMUXC_UART2_TXD 316 MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x49
318 MX8MQ_IOMUXC_UART4_RXD 317 MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B 0x49
319 MX8MQ_IOMUXC_UART4_TXD 318 MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B 0x49
320 >; 319 >;
321 }; 320 };
322 321
323 pinctrl_usdhc1: usdhc1grp { 322 pinctrl_usdhc1: usdhc1grp {
324 fsl,pins = < 323 fsl,pins = <
325 MX8MQ_IOMUXC_SD1_CLK_U 324 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
326 MX8MQ_IOMUXC_SD1_CMD_U 325 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
327 MX8MQ_IOMUXC_SD1_DATA0 326 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
328 MX8MQ_IOMUXC_SD1_DATA1 327 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
329 MX8MQ_IOMUXC_SD1_DATA2 328 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
330 MX8MQ_IOMUXC_SD1_DATA3 329 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
331 MX8MQ_IOMUXC_SD1_DATA4 330 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
332 MX8MQ_IOMUXC_SD1_DATA5 331 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
333 MX8MQ_IOMUXC_SD1_DATA6 332 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
334 MX8MQ_IOMUXC_SD1_DATA7 333 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
335 MX8MQ_IOMUXC_SD1_STROB 334 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
336 >; 335 >;
337 }; 336 };
338 337
339 pinctrl_usdhc1_100mhz: usdhc1-100mhzgr !! 338 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
340 fsl,pins = < 339 fsl,pins = <
341 MX8MQ_IOMUXC_SD1_CLK_U 340 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
342 MX8MQ_IOMUXC_SD1_CMD_U 341 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
343 MX8MQ_IOMUXC_SD1_DATA0 342 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc5
344 MX8MQ_IOMUXC_SD1_DATA1 343 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc5
345 MX8MQ_IOMUXC_SD1_DATA2 344 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc5
346 MX8MQ_IOMUXC_SD1_DATA3 345 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc5
347 MX8MQ_IOMUXC_SD1_DATA4 346 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc5
348 MX8MQ_IOMUXC_SD1_DATA5 347 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc5
349 MX8MQ_IOMUXC_SD1_DATA6 348 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc5
350 MX8MQ_IOMUXC_SD1_DATA7 349 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc5
351 MX8MQ_IOMUXC_SD1_STROB 350 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x85
352 >; 351 >;
353 }; 352 };
354 353
355 pinctrl_usdhc1_200mhz: usdhc1-200mhzgr !! 354 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
356 fsl,pins = < 355 fsl,pins = <
357 MX8MQ_IOMUXC_SD1_CLK_U 356 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
358 MX8MQ_IOMUXC_SD1_CMD_U 357 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
359 MX8MQ_IOMUXC_SD1_DATA0 358 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc7
360 MX8MQ_IOMUXC_SD1_DATA1 359 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc7
361 MX8MQ_IOMUXC_SD1_DATA2 360 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc7
362 MX8MQ_IOMUXC_SD1_DATA3 361 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc7
363 MX8MQ_IOMUXC_SD1_DATA4 362 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc7
364 MX8MQ_IOMUXC_SD1_DATA5 363 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc7
365 MX8MQ_IOMUXC_SD1_DATA6 364 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc7
366 MX8MQ_IOMUXC_SD1_DATA7 365 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc7
367 MX8MQ_IOMUXC_SD1_STROB 366 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x87
368 >; 367 >;
369 }; 368 };
370 369
371 pinctrl_usdhc2_gpio: usdhc2gpiogrp { !! 370 pinctrl_usdhc2_gpio: usdhc2grpgpio {
372 fsl,pins = < 371 fsl,pins = <
373 MX8MQ_IOMUXC_SD2_CD_B_ 372 MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
374 >; 373 >;
375 }; 374 };
376 375
377 pinctrl_usdhc2: usdhc2grp { 376 pinctrl_usdhc2: usdhc2grp {
378 fsl,pins = < 377 fsl,pins = <
379 MX8MQ_IOMUXC_SD2_CLK_U 378 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
380 MX8MQ_IOMUXC_SD2_CMD_U 379 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
381 MX8MQ_IOMUXC_SD2_DATA0 380 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
382 MX8MQ_IOMUXC_SD2_DATA1 381 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
383 MX8MQ_IOMUXC_SD2_DATA2 382 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
384 MX8MQ_IOMUXC_SD2_DATA3 383 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
385 MX8MQ_IOMUXC_GPIO1_IO0 384 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
386 >; 385 >;
387 }; 386 };
388 387
389 pinctrl_usdhc2_100mhz: usdhc2-100mhzgr !! 388 pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
390 fsl,pins = < 389 fsl,pins = <
391 MX8MQ_IOMUXC_SD2_CLK_U 390 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
392 MX8MQ_IOMUXC_SD2_CMD_U 391 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
393 MX8MQ_IOMUXC_SD2_DATA0 392 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
394 MX8MQ_IOMUXC_SD2_DATA1 393 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
395 MX8MQ_IOMUXC_SD2_DATA2 394 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
396 MX8MQ_IOMUXC_SD2_DATA3 395 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
397 MX8MQ_IOMUXC_GPIO1_IO0 396 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
398 >; 397 >;
399 }; 398 };
400 399
401 pinctrl_usdhc2_200mhz: usdhc2-200mhzgr !! 400 pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
402 fsl,pins = < 401 fsl,pins = <
403 MX8MQ_IOMUXC_SD2_CLK_U 402 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
404 MX8MQ_IOMUXC_SD2_CMD_U 403 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
405 MX8MQ_IOMUXC_SD2_DATA0 404 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
406 MX8MQ_IOMUXC_SD2_DATA1 405 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
407 MX8MQ_IOMUXC_SD2_DATA2 406 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
408 MX8MQ_IOMUXC_SD2_DATA3 407 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
409 MX8MQ_IOMUXC_GPIO1_IO0 408 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
410 >; 409 >;
411 }; 410 };
412 411
413 pinctrl_wdog: wdoggrp { 412 pinctrl_wdog: wdoggrp {
414 fsl,pins = < 413 fsl,pins = <
415 MX8MQ_IOMUXC_GPIO1_IO0 414 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
416 >; 415 >;
417 }; 416 };
418 }; 417 };
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